From d0af2cd974d606f151996c7375aa4fbbd7cda368 Mon Sep 17 00:00:00 2001 From: Dreaded_X Date: Wed, 6 Jan 2021 03:20:13 +0100 Subject: [PATCH] Updated HAL Firmware Package --- .mxproject | 12 +- .../DspLibTest_FVP/ARMCM23_config.txt | 163 ++++++++++ .../DspLibTest_FVP/ARMCM33_DSP_FP_config.txt | 183 +++++++++++ .../DspLibTest_FVP/ARMCM33_DSP_config.txt | 183 +++++++++++ .../DspLibTest_FVP/ARMCM33_FP_config.txt | 183 +++++++++++ .../DspLibTest_FVP/ARMCM33_config.txt | 183 +++++++++++ .../DspLibTest_MPS2/HowTo.txt | 29 ++ Drivers/CMSIS/DSP/DSP_Lib_TestSuite/HowTo.txt | 144 +++++++++ .../ARM/arm_class_marks_example/Abstract.txt | 4 + .../ARM/arm_convolution_example/Abstract.txt | 4 + .../ARM/arm_dotproduct_example/Abstract.txt | 4 + .../ARM/arm_fft_bin_example/Abstract.txt | 4 + .../Examples/ARM/arm_fir_example/Abstract.txt | 4 + .../Abstract.txt | 4 + .../arm_linear_interp_example/Abstract.txt | 4 + .../ARM/arm_matrix_example/Abstract.txt | 4 + .../arm_signal_converge_example/Abstract.txt | 4 + .../ARM/arm_sin_cos_example/Abstract.txt | 4 + .../ARM/arm_variance_example/Abstract.txt | 4 + Drivers/CMSIS/LICENSE.txt | 201 ++++++++++++ .../ARM/arm_nn_examples/cifar10/readme.txt | 4 + .../ARM/arm_nn_examples/gru/readme.txt | 4 + .../CMSIS/NN/NN_Lib_Tests/nn_test/readme.txt | 4 + Drivers/CMSIS/docs/General/html/LICENSE.txt | 201 ++++++++++++ .../Inc/stm32f4xx_hal_fmpsmbus.h | 8 +- .../Inc/stm32f4xx_hal_hcd.h | 37 +-- .../Inc/stm32f4xx_hal_i2c.h | 4 + .../Inc/stm32f4xx_hal_pcd.h | 82 +++-- .../Inc/stm32f4xx_ll_fmpi2c.h | 74 ++--- .../Inc/stm32f4xx_ll_i2c.h | 4 +- .../Inc/stm32f4xx_ll_usb.h | 29 +- .../STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c | 4 +- .../Src/stm32f4xx_hal_fmpi2c.c | 17 +- .../Src/stm32f4xx_hal_fmpsmbus.c | 32 +- .../Src/stm32f4xx_hal_hcd.c | 35 ++- .../Src/stm32f4xx_hal_i2c.c | 255 ++++++++++++---- .../Src/stm32f4xx_hal_pcd.c | 131 +++++--- .../Src/stm32f4xx_hal_pcd_ex.c | 4 +- .../Src/stm32f4xx_ll_usb.c | 143 +++++---- Inc/bsp_driver_sd.h | 28 +- Inc/fatfs.h | 2 +- Inc/fatfs_platform.h | 4 +- Inc/ffconf.h | 8 +- Inc/sd_diskio.h | 4 +- Inc/stm32f4xx_hal_conf.h | 131 +++++--- Inc/stm32f4xx_it.h | 2 +- Inc/usbd_desc.h | 4 +- Makefile | 2 +- .../Third_Party/FatFs/src/00history.txt | 288 ++++++++++++++++++ .../Third_Party/FatFs/src/00readme.txt | 21 ++ .../Third_Party/FatFs/src/st_readme.txt | 221 ++++++++++++++ Src/bsp_driver_sd.c | 34 +-- Src/fatfs.c | 10 +- Src/fatfs_platform.c | 6 +- Src/main.c | 34 +-- Src/sd_diskio.c | 12 +- Src/stm32f4xx_hal_msp.c | 44 +-- Src/stm32f4xx_it.c | 2 +- Src/usb_device.c | 2 +- Src/usbd_conf.c | 104 +++---- Src/usbd_desc.c | 19 +- z80-stm32-v2.ioc | 8 +- 62 files changed, 2864 insertions(+), 523 deletions(-) create mode 100644 Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMCM23_config.txt create mode 100644 Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMCM33_DSP_FP_config.txt create mode 100644 Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMCM33_DSP_config.txt create mode 100644 Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMCM33_FP_config.txt create mode 100644 Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMCM33_config.txt create mode 100644 Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_MPS2/HowTo.txt create mode 100644 Drivers/CMSIS/DSP/DSP_Lib_TestSuite/HowTo.txt create mode 100644 Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/Abstract.txt create mode 100644 Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/Abstract.txt create mode 100644 Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/Abstract.txt create mode 100644 Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/Abstract.txt create mode 100644 Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/Abstract.txt create mode 100644 Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/Abstract.txt create mode 100644 Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/Abstract.txt create mode 100644 Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/Abstract.txt create mode 100644 Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/Abstract.txt create mode 100644 Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/Abstract.txt create mode 100644 Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/Abstract.txt create mode 100644 Drivers/CMSIS/LICENSE.txt create mode 100644 Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/readme.txt create mode 100644 Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/readme.txt create mode 100644 Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/readme.txt create mode 100644 Drivers/CMSIS/docs/General/html/LICENSE.txt create mode 100644 Middlewares/Third_Party/FatFs/src/00history.txt create mode 100644 Middlewares/Third_Party/FatFs/src/00readme.txt create mode 100644 Middlewares/Third_Party/FatFs/src/st_readme.txt diff --git a/.mxproject b/.mxproject index ea6734d..1faf35f 100644 --- a/.mxproject +++ b/.mxproject @@ -1,9 +1,3 @@ -[PreviousGenFiles] -HeaderPath=/home/tim/Projects/z80/stm32/Inc -HeaderFiles=ffconf.h;bsp_driver_sd.h;sd_diskio.h;fatfs.h;fatfs_platform.h;usb_device.h;usbd_conf.h;usbd_desc.h;usbd_storage_if.h;stm32f4xx_it.h;stm32f4xx_hal_conf.h;main.h; -SourcePath=/home/tim/Projects/z80/stm32/Src -SourceFiles=bsp_driver_sd.c;sd_diskio.c;fatfs.c;fatfs_platform.c;usb_device.c;usbd_conf.c;usbd_desc.c;usbd_storage_if.c;stm32f4xx_it.c;stm32f4xx_hal_msp.c;main.c; - [PreviousLibFiles] LibFiles=Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h;Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_sdmmc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sd.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h;Middlewares/Third_Party/FatFs/src/diskio.h;Middlewares/Third_Party/FatFs/src/ff.h;Middlewares/Third_Party/FatFs/src/ff_gen_drv.h;Middlewares/Third_Party/FatFs/src/integer.h;Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h;Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h;Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h;Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h;Middlewares/ST/STM32_USB_Device_Library/Class/MSC/Inc/usbd_msc.h;Middlewares/ST/STM32_USB_Device_Library/Class/MSC/Inc/usbd_msc_bot.h;Middlewares/ST/STM32_USB_Device_Library/Class/MSC/Inc/usbd_msc_data.h;Middlewares/ST/STM32_USB_Device_Library/Class/MSC/Inc/usbd_msc_scsi.h;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c;Middlewares/Third_Party/FatFs/src/diskio.c;Middlewares/Third_Party/FatFs/src/ff.c;Middlewares/Third_Party/FatFs/src/ff_gen_drv.c;Middlewares/Third_Party/FatFs/src/option/syscall.c;Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c;Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c;Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c;Middlewares/ST/STM32_USB_Device_Library/Class/MSC/Src/usbd_msc.c;Middlewares/ST/STM32_USB_Device_Library/Class/MSC/Src/usbd_msc_bot.c;Middlewares/ST/STM32_USB_Device_Library/Class/MSC/Src/usbd_msc_data.c;Middlewares/ST/STM32_USB_Device_Library/Class/MSC/Src/usbd_msc_scsi.c;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h;Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_sdmmc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sd.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h;Middlewares/Third_Party/FatFs/src/diskio.h;Middlewares/Third_Party/FatFs/src/ff.h;Middlewares/Third_Party/FatFs/src/ff_gen_drv.h;Middlewares/Third_Party/FatFs/src/integer.h;Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h;Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h;Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h;Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h;Middlewares/ST/STM32_USB_Device_Library/Class/MSC/Inc/usbd_msc.h;Middlewares/ST/STM32_USB_Device_Library/Class/MSC/Inc/usbd_msc_bot.h;Middlewares/ST/STM32_USB_Device_Library/Class/MSC/Inc/usbd_msc_data.h;Middlewares/ST/STM32_USB_Device_Library/Class/MSC/Inc/usbd_msc_scsi.h;Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f407xx.h;Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h;Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h;Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c;Drivers/CMSIS/Include/core_sc000.h;Drivers/CMSIS/Include/core_armv8mml.h;Drivers/CMSIS/Include/core_cm7.h;Drivers/CMSIS/Include/core_sc300.h;Drivers/CMSIS/Include/core_cm0.h;Drivers/CMSIS/Include/core_cm33.h;Drivers/CMSIS/Include/mpu_armv8.h;Drivers/CMSIS/Include/core_cm1.h;Drivers/CMSIS/Include/core_cm3.h;Drivers/CMSIS/Include/cmsis_armclang.h;Drivers/CMSIS/Include/mpu_armv7.h;Drivers/CMSIS/Include/cmsis_armcc.h;Drivers/CMSIS/Include/tz_context.h;Drivers/CMSIS/Include/core_armv8mbl.h;Drivers/CMSIS/Include/cmsis_gcc.h;Drivers/CMSIS/Include/cmsis_compiler.h;Drivers/CMSIS/Include/core_cm0plus.h;Drivers/CMSIS/Include/core_cm4.h;Drivers/CMSIS/Include/cmsis_iccarm.h;Drivers/CMSIS/Include/core_cm23.h;Drivers/CMSIS/Include/cmsis_version.h; @@ -12,3 +6,9 @@ SourceFiles=Src/main.c;Src/bsp_driver_sd.c;Src/sd_diskio.c;Src/fatfs.c;Src/fatfs HeaderPath=Drivers/STM32F4xx_HAL_Driver/Inc;Drivers/STM32F4xx_HAL_Driver/Inc/Legacy;Middlewares/Third_Party/FatFs/src;Middlewares/ST/STM32_USB_Device_Library/Core/Inc;Middlewares/ST/STM32_USB_Device_Library/Class/MSC/Inc;Drivers/CMSIS/Device/ST/STM32F4xx/Include;Drivers/CMSIS/Include;Inc; CDefines=USE_HAL_DRIVER;STM32F407xx;USE_HAL_DRIVER;USE_HAL_DRIVER; +[PreviousGenFiles] +HeaderPath=/home/tim/Projects/z80/stm32/Inc +HeaderFiles=ffconf.h;bsp_driver_sd.h;sd_diskio.h;fatfs.h;fatfs_platform.h;usb_device.h;usbd_conf.h;usbd_desc.h;usbd_storage_if.h;stm32f4xx_it.h;stm32f4xx_hal_conf.h;main.h; +SourcePath=/home/tim/Projects/z80/stm32/Src +SourceFiles=bsp_driver_sd.c;sd_diskio.c;fatfs.c;fatfs_platform.c;usb_device.c;usbd_conf.c;usbd_desc.c;usbd_storage_if.c;stm32f4xx_it.c;stm32f4xx_hal_msp.c;main.c; + diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMCM23_config.txt b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMCM23_config.txt new file mode 100644 index 0000000..eeb9c59 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMCM23_config.txt @@ -0,0 +1,163 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#---------------------------------------------------------------------------------------------- +cpu0.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +cpu0.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' : +cpu0.SECEXT=0 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included +fvp_mps2.platform_type=0x0 # (int , init-time) default = '0x0' : 0:MPS2 ; 1:IoT Kit ; 2:Castor : [0x0..0x2] +fvp_mps2.extra_psram=0 # (bool , init-time) default = '0' : Increases PSRAM to 32Mb +fvp_mps2.DISABLE_GATING=1 # (bool , init-time) default = '0' : Disable Memory gating logic +fvp_mps2.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' : +fvp_mps2.UART2.out_file="" # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout) +fvp_mps2.UART2.in_file="" # (string, init-time) default = '' : Input file for data to be read by the UART +fvp_mps2.UART2.unbuffered_output=0 # (bool , init-time) default = '0' : Unbuffered output +fvp_mps2.UART2.in_file_escape_sequence="##" # (string, init-time) default = '##' : Input file escape sequence +fvp_mps2.UART2.shutdown_on_eot=0 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available) +fvp_mps2.UART2.shutdown_tag="" # (string, run-time ) default = '' : Shutdown simulation when a string is transmitted +fvp_mps2.UART1.out_file="" # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout) +fvp_mps2.UART1.in_file="" # (string, init-time) default = '' : Input file for data to be read by the UART +fvp_mps2.UART1.unbuffered_output=0 # (bool , init-time) default = '0' : Unbuffered output +fvp_mps2.UART1.in_file_escape_sequence="##" # (string, init-time) default = '##' : Input file escape sequence +fvp_mps2.UART1.shutdown_on_eot=0 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available) +fvp_mps2.UART1.shutdown_tag="" # (string, run-time ) default = '' : Shutdown simulation when a string is transmitted +fvp_mps2.mps2_visualisation.rate_limit-enable=1 # (bool , init-time) default = '1' : Rate limit simulation. +fvp_mps2.mps2_visualisation.disable-visualisation=0 # (bool , init-time) default = '0' : Enable/disable visualisation +fvp_mps2.mps2_visualisation.window_title="CLCD %cpu%" # (string, init-time) default = 'CLCD %cpu%' : Window title (%cpu% is replaced by cpu_name) +fvp_mps2.mps2_visualisation.idler.delay_ms=0x32 # (int , init-time) default = '0x32' : Determines the period, in milliseconds of real time, between gui_callback() calls. +fvp_mps2.telnetterminal0.mode="telnet" # (string, init-time) default = 'telnet' : Terminal initialisation mode +fvp_mps2.telnetterminal0.start_telnet=1 # (bool , init-time) default = '1' : Start telnet if nothing connected +fvp_mps2.telnetterminal0.start_port=0x1388 # (int , init-time) default = '0x1388' : Telnet TCP Port Number : [0x0..0xFFFFFFFF] +fvp_mps2.telnetterminal0.quiet=0 # (bool , init-time) default = '0' : Avoid output on stdout/stderr +fvp_mps2.telnetterminal0.terminal_command="" # (string, init-time) default = '' : Commandline to launch a terminal application and connect to the opened TCP port. Keywords %port and %title will be replaced with the opened port number and component name respectively. An empty string (default behaviour) will launch xterm (Linux) or telnet.exe (Windows) +fvp_mps2.telnetterminal1.mode="telnet" # (string, init-time) default = 'telnet' : Terminal initialisation mode +fvp_mps2.telnetterminal1.start_telnet=1 # (bool , init-time) default = '1' : Start telnet if nothing connected +fvp_mps2.telnetterminal1.start_port=0x1388 # (int , init-time) default = '0x1388' : Telnet TCP Port Number : [0x0..0xFFFFFFFF] +fvp_mps2.telnetterminal1.quiet=0 # (bool , init-time) default = '0' : Avoid output on stdout/stderr +fvp_mps2.telnetterminal1.terminal_command="" # (string, init-time) default = '' : Commandline to launch a terminal application and connect to the opened TCP port. Keywords %port and %title will be replaced with the opened port number and component name respectively. An empty string (default behaviour) will launch xterm (Linux) or telnet.exe (Windows) +fvp_mps2.telnetterminal2.mode="telnet" # (string, init-time) default = 'telnet' : Terminal initialisation mode +fvp_mps2.telnetterminal2.start_telnet=1 # (bool , init-time) default = '1' : Start telnet if nothing connected +fvp_mps2.telnetterminal2.start_port=0x1388 # (int , init-time) default = '0x1388' : Telnet TCP Port Number : [0x0..0xFFFFFFFF] +fvp_mps2.telnetterminal2.quiet=0 # (bool , init-time) default = '0' : Avoid output on stdout/stderr +fvp_mps2.telnetterminal2.terminal_command="" # (string, init-time) default = '' : Commandline to launch a terminal application and connect to the opened TCP port. Keywords %port and %title will be replaced with the opened port number and component name respectively. An empty string (default behaviour) will launch xterm (Linux) or telnet.exe (Windows) +fvp_mps2.PSRAM_M7.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size +fvp_mps2.PSRAM_M7.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.PSRAM_M7.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.UART0.out_file="" # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout) +fvp_mps2.UART0.in_file="" # (string, init-time) default = '' : Input file for data to be read by the UART +fvp_mps2.UART0.unbuffered_output=0 # (bool , init-time) default = '0' : Unbuffered output +fvp_mps2.UART0.in_file_escape_sequence="##" # (string, init-time) default = '##' : Input file escape sequence +fvp_mps2.UART0.shutdown_on_eot=0 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available) +fvp_mps2.UART0.shutdown_tag="" # (string, run-time ) default = '' : Shutdown simulation when a string is transmitted +fvp_mps2.cmsdk_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset. +fvp_mps2.s32k_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset. +fvp_mps2.secure_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset. +fvp_mps2.nonsecure_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset. +fvp_mps2.PSRAM.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size +fvp_mps2.PSRAM.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.PSRAM.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.ssram2.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size +fvp_mps2.ssram2.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.ssram2.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.ssram1.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size +fvp_mps2.ssram1.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.ssram1.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.stub.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size +fvp_mps2.iotss_internal_sram0.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size +fvp_mps2.iotss_internal_sram0.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.iotss_internal_sram0.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.iotss_internal_sram1.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size +fvp_mps2.iotss_internal_sram1.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.iotss_internal_sram1.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.iotss_internal_sram2.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size +fvp_mps2.iotss_internal_sram2.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.iotss_internal_sram2.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.iotss_internal_sram3.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size +fvp_mps2.iotss_internal_sram3.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.iotss_internal_sram3.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.sys_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.sys_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.cpu0core_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.cpu0dbg_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.cpu1core_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.cpu1core_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.cpu1dbg_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.cpu1dbg_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.crypto_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.crypto_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.cordio_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.cordio_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.dbg_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.dbg_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.ram0_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.ram0_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.ram1_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.ram1_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.ram2_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.ram2_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.ram3_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.ram3_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.smsc_91c111.enabled=0 # (bool , init-time) default = '0' : Host interface connection enabled +fvp_mps2.smsc_91c111.mac_address="00:02:f7:ef:5d:a2" # (string, init-time) default = '00:02:f7:ef:5d:a2' : Host/model MAC address +fvp_mps2.smsc_91c111.promiscuous=1 # (bool , init-time) default = '1' : Put host into promiscuous mode +fvp_mps2.hostbridge.interfaceName="ARM0" # (string, init-time) default = 'ARM0' : Host Interface +fvp_mps2.hostbridge.userNetworking=0 # (bool , init-time) default = '0' : Enable user-mode networking +fvp_mps2.hostbridge.userNetSubnet="172.20.51.0/24" # (string, init-time) default = '172.20.51.0/24' : Virtual subnet for user-mode networking +fvp_mps2.hostbridge.userNetPorts="" # (string, init-time) default = '' : Listening ports to expose in user-mode networking +fvp_mps2.secure_control_register_block.FLASH_BLOCK_CFG=0x3 # (int , init-time) default = '0x3' : Flash Block size configuration : [0x0..0x31] +fvp_mps2.secure_control_register_block.SRAM_BLOCK_CFG=0x3 # (int , init-time) default = '0x3' : SRAM Block size configuration : [0x0..0x31] +fvp_mps2.secure_control_register_block.FLASH_WATERMARK_SUPPORTED=1 # (bool , init-time) default = '1' : Flash Watermark supported +fvp_mps2.secure_control_register_block.SRAM_WATERMARK_SUPPORTED=1 # (bool , init-time) default = '1' : SRAM Watermark supported +fvp_mps2.exclusive_monitor_psram.enable_component=1 # (bool , init-time) default = '1' : Enable component +fvp_mps2.exclusive_monitor_psram.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF] +fvp_mps2.exclusive_monitor_psram.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB] +fvp_mps2.exclusive_monitor_psram.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master +fvp_mps2.exclusive_monitor_psram.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit +fvp_mps2.exclusive_monitor_psram.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3] +fvp_mps2.exclusive_monitor_psram.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores +fvp_mps2.exclusive_monitor_zbtsram1.enable_component=1 # (bool , init-time) default = '1' : Enable component +fvp_mps2.exclusive_monitor_zbtsram1.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF] +fvp_mps2.exclusive_monitor_zbtsram1.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB] +fvp_mps2.exclusive_monitor_zbtsram1.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master +fvp_mps2.exclusive_monitor_zbtsram1.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit +fvp_mps2.exclusive_monitor_zbtsram1.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3] +fvp_mps2.exclusive_monitor_zbtsram1.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores +fvp_mps2.exclusive_monitor_zbtsram2.enable_component=1 # (bool , init-time) default = '1' : Enable component +fvp_mps2.exclusive_monitor_zbtsram2.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF] +fvp_mps2.exclusive_monitor_zbtsram2.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB] +fvp_mps2.exclusive_monitor_zbtsram2.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master +fvp_mps2.exclusive_monitor_zbtsram2.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit +fvp_mps2.exclusive_monitor_zbtsram2.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3] +fvp_mps2.exclusive_monitor_zbtsram2.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores +fvp_mps2.exclusive_monitor_iotss_internal_sram.enable_component=1 # (bool , init-time) default = '1' : Enable component +fvp_mps2.exclusive_monitor_iotss_internal_sram.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF] +fvp_mps2.exclusive_monitor_iotss_internal_sram.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB] +fvp_mps2.exclusive_monitor_iotss_internal_sram.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master +fvp_mps2.exclusive_monitor_iotss_internal_sram.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit +fvp_mps2.exclusive_monitor_iotss_internal_sram.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3] +fvp_mps2.exclusive_monitor_iotss_internal_sram.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores +fvp_mps2.dma0_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S +fvp_mps2.dma0_securitymodifier.behaviour_s_to_ns=0x0 # (int , init-time) default = '0x0' : Behaviour for S transactions to NS space : 0:block 1:transmit 2:convert to NS +fvp_mps2.dma1_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S +fvp_mps2.dma1_securitymodifier.behaviour_s_to_ns=0x0 # (int , init-time) default = '0x0' : Behaviour for S transactions to NS space : 0:block 1:transmit 2:convert to NS +fvp_mps2.dma2_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S +fvp_mps2.dma2_securitymodifier.behaviour_s_to_ns=0x0 # (int , init-time) default = '0x0' : Behaviour for S transactions to NS space : 0:block 1:transmit 2:convert to NS +fvp_mps2.dma3_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S +fvp_mps2.dma3_securitymodifier.behaviour_s_to_ns=0x0 # (int , init-time) default = '0x0' : Behaviour for S transactions to NS space : 0:block 1:transmit 2:convert to NS +fvp_mps2.dma0.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes +fvp_mps2.dma0.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer +fvp_mps2.dma0.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response +fvp_mps2.dma0.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay +fvp_mps2.dma1.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes +fvp_mps2.dma1.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer +fvp_mps2.dma1.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response +fvp_mps2.dma1.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay +fvp_mps2.dma2.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes +fvp_mps2.dma2.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer +fvp_mps2.dma2.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response +fvp_mps2.dma2.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay +fvp_mps2.dma3.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes +fvp_mps2.dma3.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer +fvp_mps2.dma3.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response +fvp_mps2.dma3.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay +fvp_mps2.iotss_cpuidentity.debugger_master_id=0xFFFFFFFF # (int , init-time) default = '0xFFFFFFFF' : : [0x0..0xFFFFFFFF] +#---------------------------------------------------------------------------------------------- diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMCM33_DSP_FP_config.txt b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMCM33_DSP_FP_config.txt new file mode 100644 index 0000000..4438b2e --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMCM33_DSP_FP_config.txt @@ -0,0 +1,183 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#---------------------------------------------------------------------------------------------- +cpu0.FPU=1 # (bool , init-time) default = '1' : Set whether the model has VFP support +cpu0.DSP=1 # (bool , init-time) default = '1' : Set whether the model has the DSP extension +cpu0.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +cpu0.MPU_S=0x8 # (int , init-time) default = '0x8' : Number of regions in the Secure MPU. If Security Extentions are absent, this is ignored : [0x0..0x10] +cpu0.MPU_NS=0x8 # (int , init-time) default = '0x8' : Number of regions in the Non-Secure MPU. If Security Extentions are absent, this is the total number of MPU regions : [0x0..0x10] +cpu0.ITM=0 # (bool , init-time) default = '1' : Level of instrumentation trace supported. false : No ITM trace included, true: ITM trace included +cpu0.IRQLVL=0x3 # (int , init-time) default = '0x3' : Number of bits of interrupt priority : [0x3..0x8] +cpu0.BIGENDINIT=0 # (bool , init-time) default = '0' : Initialize processor to big endian mode +cpu0.INITSVTOR=0x00000000 # (int , init-time) default = '0x10000000' : Secure vector-table offset at reset : [0x0..0xFFFFFF80] +cpu0.INITNSVTOR=0x0 # (int , init-time) default = '0x0' : Non-Secure vector-table offset at reset : [0x0..0xFFFFFF80] +cpu0.SAU=0x0 # (int , init-time) default = '0x4' : Number of SAU regions (0 => no SAU) : [0x0..0x8] +cpu0.SAU_CTRL.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU at reset +cpu0.SAU_CTRL.ALLNS=0 # (bool , init-time) default = '0' : At reset, the SAU treats entire memory space as NS when the SAU is disabled if this is set +cpu0.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' : +cpu0.LOCK_SAU=0 # (bool , init-time) default = '0' : Lock down of SAU registers write +cpu0.LOCK_S_MPU=0 # (bool , init-time) default = '0' : Lock down of Secure MPU registers write +cpu0.LOCK_NS_MPU=0 # (bool , init-time) default = '0' : Lock down of Non-Secure MPU registers write +cpu0.CPIF=1 # (bool , init-time) default = '1' : Specifies whether the external coprocessor interface is included +cpu0.SECEXT=0 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included +fvp_mps2.DISABLE_GATING=1 # (bool , init-time) default = '0' : Disable Memory gating logic +fvp_mps2.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' : +fvp_mps2.SCC_ID.Variant=0x0 # (int , init-time) default = '0x0' : SCC_ID[23:20], X in the FGPA version 'rXpY' : [0x0..0xF] +fvp_mps2.SCC_ID.Revision=0x1 # (int , init-time) default = '0x1' : SCC_ID[3:0], Y in the FGPA version 'rXpY' : [0x0..0xF] +fvp_mps2.platform_type=0x0 # (int , init-time) default = '0x0' : 0:MPS2 ; 1:IoT Kit ; 2:Castor : [0x0..0x2] +fvp_mps2.extra_psram=0 # (bool , init-time) default = '0' : Increases PSRAM to 32Mb +fvp_mps2.UART2.out_file="" # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout) +fvp_mps2.UART2.in_file="" # (string, init-time) default = '' : Input file for data to be read by the UART +fvp_mps2.UART2.unbuffered_output=0 # (bool , init-time) default = '0' : Unbuffered output +fvp_mps2.UART2.in_file_escape_sequence="##" # (string, init-time) default = '##' : Input file escape sequence +fvp_mps2.UART2.shutdown_on_eot=0 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available) +fvp_mps2.UART2.shutdown_tag="" # (string, run-time ) default = '' : Shutdown simulation when a string is transmitted +fvp_mps2.UART1.out_file="" # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout) +fvp_mps2.UART1.in_file="" # (string, init-time) default = '' : Input file for data to be read by the UART +fvp_mps2.UART1.unbuffered_output=0 # (bool , init-time) default = '0' : Unbuffered output +fvp_mps2.UART1.in_file_escape_sequence="##" # (string, init-time) default = '##' : Input file escape sequence +fvp_mps2.UART1.shutdown_on_eot=0 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available) +fvp_mps2.UART1.shutdown_tag="" # (string, run-time ) default = '' : Shutdown simulation when a string is transmitted +fvp_mps2.mps2_visualisation.rate_limit-enable=1 # (bool , init-time) default = '1' : Rate limit simulation. +fvp_mps2.mps2_visualisation.disable-visualisation=0 # (bool , init-time) default = '0' : Enable/disable visualisation +fvp_mps2.mps2_visualisation.window_title="CLCD %cpu%" # (string, init-time) default = 'CLCD %cpu%' : Window title (%cpu% is replaced by cpu_name) +fvp_mps2.mps2_visualisation.idler.delay_ms=0x32 # (int , init-time) default = '0x32' : Determines the period, in milliseconds of real time, between gui_callback() calls. +fvp_mps2.telnetterminal0.mode="telnet" # (string, init-time) default = 'telnet' : Terminal initialisation mode +fvp_mps2.telnetterminal0.start_telnet=1 # (bool , init-time) default = '1' : Start telnet if nothing connected +fvp_mps2.telnetterminal0.start_port=0x1388 # (int , init-time) default = '0x1388' : Telnet TCP Port Number : [0x0..0xFFFFFFFF] +fvp_mps2.telnetterminal0.quiet=0 # (bool , init-time) default = '0' : Avoid output on stdout/stderr +fvp_mps2.telnetterminal0.terminal_command="" # (string, init-time) default = '' : Commandline to launch a terminal application and connect to the opened TCP port. Keywords %port and %title will be replaced with the opened port number and component name respectively. An empty string (default behaviour) will launch xterm (Linux) or telnet.exe (Windows) +fvp_mps2.telnetterminal1.mode="telnet" # (string, init-time) default = 'telnet' : Terminal initialisation mode +fvp_mps2.telnetterminal1.start_telnet=1 # (bool , init-time) default = '1' : Start telnet if nothing connected +fvp_mps2.telnetterminal1.start_port=0x1388 # (int , init-time) default = '0x1388' : Telnet TCP Port Number : [0x0..0xFFFFFFFF] +fvp_mps2.telnetterminal1.quiet=0 # (bool , init-time) default = '0' : Avoid output on stdout/stderr +fvp_mps2.telnetterminal1.terminal_command="" # (string, init-time) default = '' : Commandline to launch a terminal application and connect to the opened TCP port. Keywords %port and %title will be replaced with the opened port number and component name respectively. An empty string (default behaviour) will launch xterm (Linux) or telnet.exe (Windows) +fvp_mps2.telnetterminal2.mode="telnet" # (string, init-time) default = 'telnet' : Terminal initialisation mode +fvp_mps2.telnetterminal2.start_telnet=1 # (bool , init-time) default = '1' : Start telnet if nothing connected +fvp_mps2.telnetterminal2.start_port=0x1388 # (int , init-time) default = '0x1388' : Telnet TCP Port Number : [0x0..0xFFFFFFFF] +fvp_mps2.telnetterminal2.quiet=0 # (bool , init-time) default = '0' : Avoid output on stdout/stderr +fvp_mps2.telnetterminal2.terminal_command="" # (string, init-time) default = '' : Commandline to launch a terminal application and connect to the opened TCP port. Keywords %port and %title will be replaced with the opened port number and component name respectively. An empty string (default behaviour) will launch xterm (Linux) or telnet.exe (Windows) +fvp_mps2.PSRAM_M7.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size +fvp_mps2.PSRAM_M7.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.PSRAM_M7.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.UART0.out_file="" # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout) +fvp_mps2.UART0.in_file="" # (string, init-time) default = '' : Input file for data to be read by the UART +fvp_mps2.UART0.unbuffered_output=0 # (bool , init-time) default = '0' : Unbuffered output +fvp_mps2.UART0.in_file_escape_sequence="##" # (string, init-time) default = '##' : Input file escape sequence +fvp_mps2.UART0.shutdown_on_eot=0 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available) +fvp_mps2.UART0.shutdown_tag="" # (string, run-time ) default = '' : Shutdown simulation when a string is transmitted +fvp_mps2.cmsdk_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset. +fvp_mps2.s32k_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset. +fvp_mps2.secure_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset. +fvp_mps2.nonsecure_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset. +fvp_mps2.PSRAM.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size +fvp_mps2.PSRAM.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.PSRAM.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.ssram2.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size +fvp_mps2.ssram2.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.ssram2.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.ssram1.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size +fvp_mps2.ssram1.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.ssram1.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.stub.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size +fvp_mps2.iotss_internal_sram0.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size +fvp_mps2.iotss_internal_sram0.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.iotss_internal_sram0.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.iotss_internal_sram1.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size +fvp_mps2.iotss_internal_sram1.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.iotss_internal_sram1.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.iotss_internal_sram2.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size +fvp_mps2.iotss_internal_sram2.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.iotss_internal_sram2.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.iotss_internal_sram3.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size +fvp_mps2.iotss_internal_sram3.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.iotss_internal_sram3.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.sys_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.sys_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.cpu0core_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.cpu0dbg_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.cpu1core_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.cpu1core_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.cpu1dbg_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.cpu1dbg_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.crypto_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.crypto_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.cordio_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.cordio_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.dbg_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.dbg_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.ram0_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.ram0_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.ram1_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.ram1_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.ram2_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.ram2_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.ram3_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.ram3_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.smsc_91c111.enabled=0 # (bool , init-time) default = '0' : Host interface connection enabled +fvp_mps2.smsc_91c111.mac_address="00:02:f7:ef:5d:a2" # (string, init-time) default = '00:02:f7:ef:5d:a2' : Host/model MAC address +fvp_mps2.smsc_91c111.promiscuous=1 # (bool , init-time) default = '1' : Put host into promiscuous mode +fvp_mps2.hostbridge.interfaceName="ARM0" # (string, init-time) default = 'ARM0' : Host Interface +fvp_mps2.hostbridge.userNetworking=0 # (bool , init-time) default = '0' : Enable user-mode networking +fvp_mps2.hostbridge.userNetSubnet="172.20.51.0/24" # (string, init-time) default = '172.20.51.0/24' : Virtual subnet for user-mode networking +fvp_mps2.hostbridge.userNetPorts="" # (string, init-time) default = '' : Listening ports to expose in user-mode networking +fvp_mps2.secure_control_register_block.FLASH_BLOCK_CFG=0x3 # (int , init-time) default = '0x3' : Flash Block size configuration : [0x0..0x31] +fvp_mps2.secure_control_register_block.SRAM_BLOCK_CFG=0x3 # (int , init-time) default = '0x3' : SRAM Block size configuration : [0x0..0x31] +fvp_mps2.secure_control_register_block.FLASH_WATERMARK_SUPPORTED=1 # (bool , init-time) default = '1' : Flash Watermark supported +fvp_mps2.secure_control_register_block.SRAM_WATERMARK_SUPPORTED=1 # (bool , init-time) default = '1' : SRAM Watermark supported +fvp_mps2.exclusive_monitor_psram.enable_component=1 # (bool , init-time) default = '1' : Enable component +fvp_mps2.exclusive_monitor_psram.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF] +fvp_mps2.exclusive_monitor_psram.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB] +fvp_mps2.exclusive_monitor_psram.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master +fvp_mps2.exclusive_monitor_psram.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit +fvp_mps2.exclusive_monitor_psram.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3] +fvp_mps2.exclusive_monitor_psram.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores +fvp_mps2.exclusive_monitor_zbtsram1.enable_component=1 # (bool , init-time) default = '1' : Enable component +fvp_mps2.exclusive_monitor_zbtsram1.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF] +fvp_mps2.exclusive_monitor_zbtsram1.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB] +fvp_mps2.exclusive_monitor_zbtsram1.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master +fvp_mps2.exclusive_monitor_zbtsram1.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit +fvp_mps2.exclusive_monitor_zbtsram1.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3] +fvp_mps2.exclusive_monitor_zbtsram1.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores +fvp_mps2.exclusive_monitor_zbtsram2.enable_component=1 # (bool , init-time) default = '1' : Enable component +fvp_mps2.exclusive_monitor_zbtsram2.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF] +fvp_mps2.exclusive_monitor_zbtsram2.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB] +fvp_mps2.exclusive_monitor_zbtsram2.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master +fvp_mps2.exclusive_monitor_zbtsram2.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit +fvp_mps2.exclusive_monitor_zbtsram2.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3] +fvp_mps2.exclusive_monitor_zbtsram2.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores +fvp_mps2.exclusive_monitor_iotss_internal_sram.enable_component=1 # (bool , init-time) default = '1' : Enable component +fvp_mps2.exclusive_monitor_iotss_internal_sram.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF] +fvp_mps2.exclusive_monitor_iotss_internal_sram.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB] +fvp_mps2.exclusive_monitor_iotss_internal_sram.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master +fvp_mps2.exclusive_monitor_iotss_internal_sram.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit +fvp_mps2.exclusive_monitor_iotss_internal_sram.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3] +fvp_mps2.exclusive_monitor_iotss_internal_sram.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores +fvp_mps2.dma0_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S +fvp_mps2.dma0_securitymodifier.behaviour_s_to_ns=0x0 # (int , init-time) default = '0x0' : Behaviour for S transactions to NS space : 0:block 1:transmit 2:convert to NS +fvp_mps2.dma1_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S +fvp_mps2.dma1_securitymodifier.behaviour_s_to_ns=0x0 # (int , init-time) default = '0x0' : Behaviour for S transactions to NS space : 0:block 1:transmit 2:convert to NS +fvp_mps2.dma2_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S +fvp_mps2.dma2_securitymodifier.behaviour_s_to_ns=0x0 # (int , init-time) default = '0x0' : Behaviour for S transactions to NS space : 0:block 1:transmit 2:convert to NS +fvp_mps2.dma3_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S +fvp_mps2.dma3_securitymodifier.behaviour_s_to_ns=0x0 # (int , init-time) default = '0x0' : Behaviour for S transactions to NS space : 0:block 1:transmit 2:convert to NS +fvp_mps2.dma0.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes +fvp_mps2.dma0.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer +fvp_mps2.dma0.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response +fvp_mps2.dma0.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay +fvp_mps2.dma1.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes +fvp_mps2.dma1.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer +fvp_mps2.dma1.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response +fvp_mps2.dma1.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay +fvp_mps2.dma2.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes +fvp_mps2.dma2.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer +fvp_mps2.dma2.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response +fvp_mps2.dma2.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay +fvp_mps2.dma3.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes +fvp_mps2.dma3.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer +fvp_mps2.dma3.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response +fvp_mps2.dma3.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay +fvp_mps2.iotss_systemcontrol.cpu0wait=0 # (bool , init-time) default = '0' : Whether to hold cpu1 in reset at boot +fvp_mps2.iotss_systemcontrol.cpu1wait=1 # (bool , init-time) default = '1' : Whether to hold cpu1 in reset at boot +fvp_mps2.iotss_cpuidentity.debugger_master_id=0xFFFFFFFF # (int , init-time) default = '0xFFFFFFFF' : : [0x0..0xFFFFFFFF] +#---------------------------------------------------------------------------------------------- diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMCM33_DSP_config.txt b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMCM33_DSP_config.txt new file mode 100644 index 0000000..cb9fd3d --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMCM33_DSP_config.txt @@ -0,0 +1,183 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#---------------------------------------------------------------------------------------------- +cpu0.FPU=0 # (bool , init-time) default = '1' : Set whether the model has VFP support +cpu0.DSP=1 # (bool , init-time) default = '1' : Set whether the model has the DSP extension +cpu0.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +cpu0.MPU_S=0x8 # (int , init-time) default = '0x8' : Number of regions in the Secure MPU. If Security Extentions are absent, this is ignored : [0x0..0x10] +cpu0.MPU_NS=0x8 # (int , init-time) default = '0x8' : Number of regions in the Non-Secure MPU. If Security Extentions are absent, this is the total number of MPU regions : [0x0..0x10] +cpu0.ITM=0 # (bool , init-time) default = '1' : Level of instrumentation trace supported. false : No ITM trace included, true: ITM trace included +cpu0.IRQLVL=0x3 # (int , init-time) default = '0x3' : Number of bits of interrupt priority : [0x3..0x8] +cpu0.BIGENDINIT=0 # (bool , init-time) default = '0' : Initialize processor to big endian mode +cpu0.INITSVTOR=0x00000000 # (int , init-time) default = '0x10000000' : Secure vector-table offset at reset : [0x0..0xFFFFFF80] +cpu0.INITNSVTOR=0x0 # (int , init-time) default = '0x0' : Non-Secure vector-table offset at reset : [0x0..0xFFFFFF80] +cpu0.SAU=0x0 # (int , init-time) default = '0x4' : Number of SAU regions (0 => no SAU) : [0x0..0x8] +cpu0.SAU_CTRL.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU at reset +cpu0.SAU_CTRL.ALLNS=0 # (bool , init-time) default = '0' : At reset, the SAU treats entire memory space as NS when the SAU is disabled if this is set +cpu0.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' : +cpu0.LOCK_SAU=0 # (bool , init-time) default = '0' : Lock down of SAU registers write +cpu0.LOCK_S_MPU=0 # (bool , init-time) default = '0' : Lock down of Secure MPU registers write +cpu0.LOCK_NS_MPU=0 # (bool , init-time) default = '0' : Lock down of Non-Secure MPU registers write +cpu0.CPIF=1 # (bool , init-time) default = '1' : Specifies whether the external coprocessor interface is included +cpu0.SECEXT=0 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included +fvp_mps2.DISABLE_GATING=1 # (bool , init-time) default = '0' : Disable Memory gating logic +fvp_mps2.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' : +fvp_mps2.SCC_ID.Variant=0x0 # (int , init-time) default = '0x0' : SCC_ID[23:20], X in the FGPA version 'rXpY' : [0x0..0xF] +fvp_mps2.SCC_ID.Revision=0x1 # (int , init-time) default = '0x1' : SCC_ID[3:0], Y in the FGPA version 'rXpY' : [0x0..0xF] +fvp_mps2.platform_type=0x0 # (int , init-time) default = '0x0' : 0:MPS2 ; 1:IoT Kit ; 2:Castor : [0x0..0x2] +fvp_mps2.extra_psram=0 # (bool , init-time) default = '0' : Increases PSRAM to 32Mb +fvp_mps2.UART2.out_file="" # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout) +fvp_mps2.UART2.in_file="" # (string, init-time) default = '' : Input file for data to be read by the UART +fvp_mps2.UART2.unbuffered_output=0 # (bool , init-time) default = '0' : Unbuffered output +fvp_mps2.UART2.in_file_escape_sequence="##" # (string, init-time) default = '##' : Input file escape sequence +fvp_mps2.UART2.shutdown_on_eot=0 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available) +fvp_mps2.UART2.shutdown_tag="" # (string, run-time ) default = '' : Shutdown simulation when a string is transmitted +fvp_mps2.UART1.out_file="" # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout) +fvp_mps2.UART1.in_file="" # (string, init-time) default = '' : Input file for data to be read by the UART +fvp_mps2.UART1.unbuffered_output=0 # (bool , init-time) default = '0' : Unbuffered output +fvp_mps2.UART1.in_file_escape_sequence="##" # (string, init-time) default = '##' : Input file escape sequence +fvp_mps2.UART1.shutdown_on_eot=0 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available) +fvp_mps2.UART1.shutdown_tag="" # (string, run-time ) default = '' : Shutdown simulation when a string is transmitted +fvp_mps2.mps2_visualisation.rate_limit-enable=1 # (bool , init-time) default = '1' : Rate limit simulation. +fvp_mps2.mps2_visualisation.disable-visualisation=0 # (bool , init-time) default = '0' : Enable/disable visualisation +fvp_mps2.mps2_visualisation.window_title="CLCD %cpu%" # (string, init-time) default = 'CLCD %cpu%' : Window title (%cpu% is replaced by cpu_name) +fvp_mps2.mps2_visualisation.idler.delay_ms=0x32 # (int , init-time) default = '0x32' : Determines the period, in milliseconds of real time, between gui_callback() calls. +fvp_mps2.telnetterminal0.mode="telnet" # (string, init-time) default = 'telnet' : Terminal initialisation mode +fvp_mps2.telnetterminal0.start_telnet=1 # (bool , init-time) default = '1' : Start telnet if nothing connected +fvp_mps2.telnetterminal0.start_port=0x1388 # (int , init-time) default = '0x1388' : Telnet TCP Port Number : [0x0..0xFFFFFFFF] +fvp_mps2.telnetterminal0.quiet=0 # (bool , init-time) default = '0' : Avoid output on stdout/stderr +fvp_mps2.telnetterminal0.terminal_command="" # (string, init-time) default = '' : Commandline to launch a terminal application and connect to the opened TCP port. Keywords %port and %title will be replaced with the opened port number and component name respectively. An empty string (default behaviour) will launch xterm (Linux) or telnet.exe (Windows) +fvp_mps2.telnetterminal1.mode="telnet" # (string, init-time) default = 'telnet' : Terminal initialisation mode +fvp_mps2.telnetterminal1.start_telnet=1 # (bool , init-time) default = '1' : Start telnet if nothing connected +fvp_mps2.telnetterminal1.start_port=0x1388 # (int , init-time) default = '0x1388' : Telnet TCP Port Number : [0x0..0xFFFFFFFF] +fvp_mps2.telnetterminal1.quiet=0 # (bool , init-time) default = '0' : Avoid output on stdout/stderr +fvp_mps2.telnetterminal1.terminal_command="" # (string, init-time) default = '' : Commandline to launch a terminal application and connect to the opened TCP port. Keywords %port and %title will be replaced with the opened port number and component name respectively. An empty string (default behaviour) will launch xterm (Linux) or telnet.exe (Windows) +fvp_mps2.telnetterminal2.mode="telnet" # (string, init-time) default = 'telnet' : Terminal initialisation mode +fvp_mps2.telnetterminal2.start_telnet=1 # (bool , init-time) default = '1' : Start telnet if nothing connected +fvp_mps2.telnetterminal2.start_port=0x1388 # (int , init-time) default = '0x1388' : Telnet TCP Port Number : [0x0..0xFFFFFFFF] +fvp_mps2.telnetterminal2.quiet=0 # (bool , init-time) default = '0' : Avoid output on stdout/stderr +fvp_mps2.telnetterminal2.terminal_command="" # (string, init-time) default = '' : Commandline to launch a terminal application and connect to the opened TCP port. Keywords %port and %title will be replaced with the opened port number and component name respectively. An empty string (default behaviour) will launch xterm (Linux) or telnet.exe (Windows) +fvp_mps2.PSRAM_M7.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size +fvp_mps2.PSRAM_M7.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.PSRAM_M7.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.UART0.out_file="" # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout) +fvp_mps2.UART0.in_file="" # (string, init-time) default = '' : Input file for data to be read by the UART +fvp_mps2.UART0.unbuffered_output=0 # (bool , init-time) default = '0' : Unbuffered output +fvp_mps2.UART0.in_file_escape_sequence="##" # (string, init-time) default = '##' : Input file escape sequence +fvp_mps2.UART0.shutdown_on_eot=0 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available) +fvp_mps2.UART0.shutdown_tag="" # (string, run-time ) default = '' : Shutdown simulation when a string is transmitted +fvp_mps2.cmsdk_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset. +fvp_mps2.s32k_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset. +fvp_mps2.secure_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset. +fvp_mps2.nonsecure_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset. +fvp_mps2.PSRAM.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size +fvp_mps2.PSRAM.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.PSRAM.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.ssram2.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size +fvp_mps2.ssram2.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.ssram2.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.ssram1.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size +fvp_mps2.ssram1.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.ssram1.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.stub.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size +fvp_mps2.iotss_internal_sram0.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size +fvp_mps2.iotss_internal_sram0.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.iotss_internal_sram0.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.iotss_internal_sram1.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size +fvp_mps2.iotss_internal_sram1.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.iotss_internal_sram1.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.iotss_internal_sram2.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size +fvp_mps2.iotss_internal_sram2.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.iotss_internal_sram2.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.iotss_internal_sram3.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size +fvp_mps2.iotss_internal_sram3.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.iotss_internal_sram3.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.sys_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.sys_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.cpu0core_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.cpu0dbg_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.cpu1core_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.cpu1core_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.cpu1dbg_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.cpu1dbg_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.crypto_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.crypto_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.cordio_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.cordio_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.dbg_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.dbg_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.ram0_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.ram0_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.ram1_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.ram1_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.ram2_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.ram2_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.ram3_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.ram3_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.smsc_91c111.enabled=0 # (bool , init-time) default = '0' : Host interface connection enabled +fvp_mps2.smsc_91c111.mac_address="00:02:f7:ef:5d:a2" # (string, init-time) default = '00:02:f7:ef:5d:a2' : Host/model MAC address +fvp_mps2.smsc_91c111.promiscuous=1 # (bool , init-time) default = '1' : Put host into promiscuous mode +fvp_mps2.hostbridge.interfaceName="ARM0" # (string, init-time) default = 'ARM0' : Host Interface +fvp_mps2.hostbridge.userNetworking=0 # (bool , init-time) default = '0' : Enable user-mode networking +fvp_mps2.hostbridge.userNetSubnet="172.20.51.0/24" # (string, init-time) default = '172.20.51.0/24' : Virtual subnet for user-mode networking +fvp_mps2.hostbridge.userNetPorts="" # (string, init-time) default = '' : Listening ports to expose in user-mode networking +fvp_mps2.secure_control_register_block.FLASH_BLOCK_CFG=0x3 # (int , init-time) default = '0x3' : Flash Block size configuration : [0x0..0x31] +fvp_mps2.secure_control_register_block.SRAM_BLOCK_CFG=0x3 # (int , init-time) default = '0x3' : SRAM Block size configuration : [0x0..0x31] +fvp_mps2.secure_control_register_block.FLASH_WATERMARK_SUPPORTED=1 # (bool , init-time) default = '1' : Flash Watermark supported +fvp_mps2.secure_control_register_block.SRAM_WATERMARK_SUPPORTED=1 # (bool , init-time) default = '1' : SRAM Watermark supported +fvp_mps2.exclusive_monitor_psram.enable_component=1 # (bool , init-time) default = '1' : Enable component +fvp_mps2.exclusive_monitor_psram.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF] +fvp_mps2.exclusive_monitor_psram.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB] +fvp_mps2.exclusive_monitor_psram.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master +fvp_mps2.exclusive_monitor_psram.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit +fvp_mps2.exclusive_monitor_psram.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3] +fvp_mps2.exclusive_monitor_psram.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores +fvp_mps2.exclusive_monitor_zbtsram1.enable_component=1 # (bool , init-time) default = '1' : Enable component +fvp_mps2.exclusive_monitor_zbtsram1.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF] +fvp_mps2.exclusive_monitor_zbtsram1.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB] +fvp_mps2.exclusive_monitor_zbtsram1.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master +fvp_mps2.exclusive_monitor_zbtsram1.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit +fvp_mps2.exclusive_monitor_zbtsram1.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3] +fvp_mps2.exclusive_monitor_zbtsram1.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores +fvp_mps2.exclusive_monitor_zbtsram2.enable_component=1 # (bool , init-time) default = '1' : Enable component +fvp_mps2.exclusive_monitor_zbtsram2.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF] +fvp_mps2.exclusive_monitor_zbtsram2.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB] +fvp_mps2.exclusive_monitor_zbtsram2.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master +fvp_mps2.exclusive_monitor_zbtsram2.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit +fvp_mps2.exclusive_monitor_zbtsram2.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3] +fvp_mps2.exclusive_monitor_zbtsram2.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores +fvp_mps2.exclusive_monitor_iotss_internal_sram.enable_component=1 # (bool , init-time) default = '1' : Enable component +fvp_mps2.exclusive_monitor_iotss_internal_sram.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF] +fvp_mps2.exclusive_monitor_iotss_internal_sram.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB] +fvp_mps2.exclusive_monitor_iotss_internal_sram.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master +fvp_mps2.exclusive_monitor_iotss_internal_sram.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit +fvp_mps2.exclusive_monitor_iotss_internal_sram.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3] +fvp_mps2.exclusive_monitor_iotss_internal_sram.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores +fvp_mps2.dma0_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S +fvp_mps2.dma0_securitymodifier.behaviour_s_to_ns=0x0 # (int , init-time) default = '0x0' : Behaviour for S transactions to NS space : 0:block 1:transmit 2:convert to NS +fvp_mps2.dma1_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S +fvp_mps2.dma1_securitymodifier.behaviour_s_to_ns=0x0 # (int , init-time) default = '0x0' : Behaviour for S transactions to NS space : 0:block 1:transmit 2:convert to NS +fvp_mps2.dma2_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S +fvp_mps2.dma2_securitymodifier.behaviour_s_to_ns=0x0 # (int , init-time) default = '0x0' : Behaviour for S transactions to NS space : 0:block 1:transmit 2:convert to NS +fvp_mps2.dma3_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S +fvp_mps2.dma3_securitymodifier.behaviour_s_to_ns=0x0 # (int , init-time) default = '0x0' : Behaviour for S transactions to NS space : 0:block 1:transmit 2:convert to NS +fvp_mps2.dma0.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes +fvp_mps2.dma0.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer +fvp_mps2.dma0.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response +fvp_mps2.dma0.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay +fvp_mps2.dma1.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes +fvp_mps2.dma1.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer +fvp_mps2.dma1.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response +fvp_mps2.dma1.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay +fvp_mps2.dma2.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes +fvp_mps2.dma2.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer +fvp_mps2.dma2.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response +fvp_mps2.dma2.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay +fvp_mps2.dma3.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes +fvp_mps2.dma3.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer +fvp_mps2.dma3.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response +fvp_mps2.dma3.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay +fvp_mps2.iotss_systemcontrol.cpu0wait=0 # (bool , init-time) default = '0' : Whether to hold cpu1 in reset at boot +fvp_mps2.iotss_systemcontrol.cpu1wait=1 # (bool , init-time) default = '1' : Whether to hold cpu1 in reset at boot +fvp_mps2.iotss_cpuidentity.debugger_master_id=0xFFFFFFFF # (int , init-time) default = '0xFFFFFFFF' : : [0x0..0xFFFFFFFF] +#---------------------------------------------------------------------------------------------- diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMCM33_FP_config.txt b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMCM33_FP_config.txt new file mode 100644 index 0000000..6812151 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMCM33_FP_config.txt @@ -0,0 +1,183 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#---------------------------------------------------------------------------------------------- +cpu0.FPU=1 # (bool , init-time) default = '1' : Set whether the model has VFP support +cpu0.DSP=0 # (bool , init-time) default = '1' : Set whether the model has the DSP extension +cpu0.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +cpu0.MPU_S=0x8 # (int , init-time) default = '0x8' : Number of regions in the Secure MPU. If Security Extentions are absent, this is ignored : [0x0..0x10] +cpu0.MPU_NS=0x8 # (int , init-time) default = '0x8' : Number of regions in the Non-Secure MPU. If Security Extentions are absent, this is the total number of MPU regions : [0x0..0x10] +cpu0.ITM=0 # (bool , init-time) default = '1' : Level of instrumentation trace supported. false : No ITM trace included, true: ITM trace included +cpu0.IRQLVL=0x3 # (int , init-time) default = '0x3' : Number of bits of interrupt priority : [0x3..0x8] +cpu0.BIGENDINIT=0 # (bool , init-time) default = '0' : Initialize processor to big endian mode +cpu0.INITSVTOR=0x00000000 # (int , init-time) default = '0x10000000' : Secure vector-table offset at reset : [0x0..0xFFFFFF80] +cpu0.INITNSVTOR=0x0 # (int , init-time) default = '0x0' : Non-Secure vector-table offset at reset : [0x0..0xFFFFFF80] +cpu0.SAU=0x0 # (int , init-time) default = '0x4' : Number of SAU regions (0 => no SAU) : [0x0..0x8] +cpu0.SAU_CTRL.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU at reset +cpu0.SAU_CTRL.ALLNS=0 # (bool , init-time) default = '0' : At reset, the SAU treats entire memory space as NS when the SAU is disabled if this is set +cpu0.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' : +cpu0.LOCK_SAU=0 # (bool , init-time) default = '0' : Lock down of SAU registers write +cpu0.LOCK_S_MPU=0 # (bool , init-time) default = '0' : Lock down of Secure MPU registers write +cpu0.LOCK_NS_MPU=0 # (bool , init-time) default = '0' : Lock down of Non-Secure MPU registers write +cpu0.CPIF=1 # (bool , init-time) default = '1' : Specifies whether the external coprocessor interface is included +cpu0.SECEXT=0 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included +fvp_mps2.DISABLE_GATING=1 # (bool , init-time) default = '0' : Disable Memory gating logic +fvp_mps2.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' : +fvp_mps2.SCC_ID.Variant=0x0 # (int , init-time) default = '0x0' : SCC_ID[23:20], X in the FGPA version 'rXpY' : [0x0..0xF] +fvp_mps2.SCC_ID.Revision=0x1 # (int , init-time) default = '0x1' : SCC_ID[3:0], Y in the FGPA version 'rXpY' : [0x0..0xF] +fvp_mps2.platform_type=0x0 # (int , init-time) default = '0x0' : 0:MPS2 ; 1:IoT Kit ; 2:Castor : [0x0..0x2] +fvp_mps2.extra_psram=0 # (bool , init-time) default = '0' : Increases PSRAM to 32Mb +fvp_mps2.UART2.out_file="" # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout) +fvp_mps2.UART2.in_file="" # (string, init-time) default = '' : Input file for data to be read by the UART +fvp_mps2.UART2.unbuffered_output=0 # (bool , init-time) default = '0' : Unbuffered output +fvp_mps2.UART2.in_file_escape_sequence="##" # (string, init-time) default = '##' : Input file escape sequence +fvp_mps2.UART2.shutdown_on_eot=0 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available) +fvp_mps2.UART2.shutdown_tag="" # (string, run-time ) default = '' : Shutdown simulation when a string is transmitted +fvp_mps2.UART1.out_file="" # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout) +fvp_mps2.UART1.in_file="" # (string, init-time) default = '' : Input file for data to be read by the UART +fvp_mps2.UART1.unbuffered_output=0 # (bool , init-time) default = '0' : Unbuffered output +fvp_mps2.UART1.in_file_escape_sequence="##" # (string, init-time) default = '##' : Input file escape sequence +fvp_mps2.UART1.shutdown_on_eot=0 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available) +fvp_mps2.UART1.shutdown_tag="" # (string, run-time ) default = '' : Shutdown simulation when a string is transmitted +fvp_mps2.mps2_visualisation.rate_limit-enable=1 # (bool , init-time) default = '1' : Rate limit simulation. +fvp_mps2.mps2_visualisation.disable-visualisation=0 # (bool , init-time) default = '0' : Enable/disable visualisation +fvp_mps2.mps2_visualisation.window_title="CLCD %cpu%" # (string, init-time) default = 'CLCD %cpu%' : Window title (%cpu% is replaced by cpu_name) +fvp_mps2.mps2_visualisation.idler.delay_ms=0x32 # (int , init-time) default = '0x32' : Determines the period, in milliseconds of real time, between gui_callback() calls. +fvp_mps2.telnetterminal0.mode="telnet" # (string, init-time) default = 'telnet' : Terminal initialisation mode +fvp_mps2.telnetterminal0.start_telnet=1 # (bool , init-time) default = '1' : Start telnet if nothing connected +fvp_mps2.telnetterminal0.start_port=0x1388 # (int , init-time) default = '0x1388' : Telnet TCP Port Number : [0x0..0xFFFFFFFF] +fvp_mps2.telnetterminal0.quiet=0 # (bool , init-time) default = '0' : Avoid output on stdout/stderr +fvp_mps2.telnetterminal0.terminal_command="" # (string, init-time) default = '' : Commandline to launch a terminal application and connect to the opened TCP port. Keywords %port and %title will be replaced with the opened port number and component name respectively. An empty string (default behaviour) will launch xterm (Linux) or telnet.exe (Windows) +fvp_mps2.telnetterminal1.mode="telnet" # (string, init-time) default = 'telnet' : Terminal initialisation mode +fvp_mps2.telnetterminal1.start_telnet=1 # (bool , init-time) default = '1' : Start telnet if nothing connected +fvp_mps2.telnetterminal1.start_port=0x1388 # (int , init-time) default = '0x1388' : Telnet TCP Port Number : [0x0..0xFFFFFFFF] +fvp_mps2.telnetterminal1.quiet=0 # (bool , init-time) default = '0' : Avoid output on stdout/stderr +fvp_mps2.telnetterminal1.terminal_command="" # (string, init-time) default = '' : Commandline to launch a terminal application and connect to the opened TCP port. Keywords %port and %title will be replaced with the opened port number and component name respectively. An empty string (default behaviour) will launch xterm (Linux) or telnet.exe (Windows) +fvp_mps2.telnetterminal2.mode="telnet" # (string, init-time) default = 'telnet' : Terminal initialisation mode +fvp_mps2.telnetterminal2.start_telnet=1 # (bool , init-time) default = '1' : Start telnet if nothing connected +fvp_mps2.telnetterminal2.start_port=0x1388 # (int , init-time) default = '0x1388' : Telnet TCP Port Number : [0x0..0xFFFFFFFF] +fvp_mps2.telnetterminal2.quiet=0 # (bool , init-time) default = '0' : Avoid output on stdout/stderr +fvp_mps2.telnetterminal2.terminal_command="" # (string, init-time) default = '' : Commandline to launch a terminal application and connect to the opened TCP port. Keywords %port and %title will be replaced with the opened port number and component name respectively. An empty string (default behaviour) will launch xterm (Linux) or telnet.exe (Windows) +fvp_mps2.PSRAM_M7.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size +fvp_mps2.PSRAM_M7.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.PSRAM_M7.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.UART0.out_file="" # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout) +fvp_mps2.UART0.in_file="" # (string, init-time) default = '' : Input file for data to be read by the UART +fvp_mps2.UART0.unbuffered_output=0 # (bool , init-time) default = '0' : Unbuffered output +fvp_mps2.UART0.in_file_escape_sequence="##" # (string, init-time) default = '##' : Input file escape sequence +fvp_mps2.UART0.shutdown_on_eot=0 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available) +fvp_mps2.UART0.shutdown_tag="" # (string, run-time ) default = '' : Shutdown simulation when a string is transmitted +fvp_mps2.cmsdk_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset. +fvp_mps2.s32k_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset. +fvp_mps2.secure_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset. +fvp_mps2.nonsecure_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset. +fvp_mps2.PSRAM.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size +fvp_mps2.PSRAM.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.PSRAM.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.ssram2.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size +fvp_mps2.ssram2.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.ssram2.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.ssram1.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size +fvp_mps2.ssram1.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.ssram1.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.stub.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size +fvp_mps2.iotss_internal_sram0.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size +fvp_mps2.iotss_internal_sram0.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.iotss_internal_sram0.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.iotss_internal_sram1.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size +fvp_mps2.iotss_internal_sram1.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.iotss_internal_sram1.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.iotss_internal_sram2.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size +fvp_mps2.iotss_internal_sram2.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.iotss_internal_sram2.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.iotss_internal_sram3.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size +fvp_mps2.iotss_internal_sram3.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.iotss_internal_sram3.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.sys_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.sys_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.cpu0core_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.cpu0dbg_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.cpu1core_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.cpu1core_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.cpu1dbg_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.cpu1dbg_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.crypto_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.crypto_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.cordio_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.cordio_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.dbg_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.dbg_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.ram0_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.ram0_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.ram1_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.ram1_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.ram2_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.ram2_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.ram3_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.ram3_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.smsc_91c111.enabled=0 # (bool , init-time) default = '0' : Host interface connection enabled +fvp_mps2.smsc_91c111.mac_address="00:02:f7:ef:5d:a2" # (string, init-time) default = '00:02:f7:ef:5d:a2' : Host/model MAC address +fvp_mps2.smsc_91c111.promiscuous=1 # (bool , init-time) default = '1' : Put host into promiscuous mode +fvp_mps2.hostbridge.interfaceName="ARM0" # (string, init-time) default = 'ARM0' : Host Interface +fvp_mps2.hostbridge.userNetworking=0 # (bool , init-time) default = '0' : Enable user-mode networking +fvp_mps2.hostbridge.userNetSubnet="172.20.51.0/24" # (string, init-time) default = '172.20.51.0/24' : Virtual subnet for user-mode networking +fvp_mps2.hostbridge.userNetPorts="" # (string, init-time) default = '' : Listening ports to expose in user-mode networking +fvp_mps2.secure_control_register_block.FLASH_BLOCK_CFG=0x3 # (int , init-time) default = '0x3' : Flash Block size configuration : [0x0..0x31] +fvp_mps2.secure_control_register_block.SRAM_BLOCK_CFG=0x3 # (int , init-time) default = '0x3' : SRAM Block size configuration : [0x0..0x31] +fvp_mps2.secure_control_register_block.FLASH_WATERMARK_SUPPORTED=1 # (bool , init-time) default = '1' : Flash Watermark supported +fvp_mps2.secure_control_register_block.SRAM_WATERMARK_SUPPORTED=1 # (bool , init-time) default = '1' : SRAM Watermark supported +fvp_mps2.exclusive_monitor_psram.enable_component=1 # (bool , init-time) default = '1' : Enable component +fvp_mps2.exclusive_monitor_psram.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF] +fvp_mps2.exclusive_monitor_psram.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB] +fvp_mps2.exclusive_monitor_psram.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master +fvp_mps2.exclusive_monitor_psram.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit +fvp_mps2.exclusive_monitor_psram.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3] +fvp_mps2.exclusive_monitor_psram.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores +fvp_mps2.exclusive_monitor_zbtsram1.enable_component=1 # (bool , init-time) default = '1' : Enable component +fvp_mps2.exclusive_monitor_zbtsram1.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF] +fvp_mps2.exclusive_monitor_zbtsram1.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB] +fvp_mps2.exclusive_monitor_zbtsram1.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master +fvp_mps2.exclusive_monitor_zbtsram1.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit +fvp_mps2.exclusive_monitor_zbtsram1.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3] +fvp_mps2.exclusive_monitor_zbtsram1.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores +fvp_mps2.exclusive_monitor_zbtsram2.enable_component=1 # (bool , init-time) default = '1' : Enable component +fvp_mps2.exclusive_monitor_zbtsram2.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF] +fvp_mps2.exclusive_monitor_zbtsram2.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB] +fvp_mps2.exclusive_monitor_zbtsram2.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master +fvp_mps2.exclusive_monitor_zbtsram2.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit +fvp_mps2.exclusive_monitor_zbtsram2.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3] +fvp_mps2.exclusive_monitor_zbtsram2.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores +fvp_mps2.exclusive_monitor_iotss_internal_sram.enable_component=1 # (bool , init-time) default = '1' : Enable component +fvp_mps2.exclusive_monitor_iotss_internal_sram.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF] +fvp_mps2.exclusive_monitor_iotss_internal_sram.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB] +fvp_mps2.exclusive_monitor_iotss_internal_sram.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master +fvp_mps2.exclusive_monitor_iotss_internal_sram.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit +fvp_mps2.exclusive_monitor_iotss_internal_sram.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3] +fvp_mps2.exclusive_monitor_iotss_internal_sram.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores +fvp_mps2.dma0_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S +fvp_mps2.dma0_securitymodifier.behaviour_s_to_ns=0x0 # (int , init-time) default = '0x0' : Behaviour for S transactions to NS space : 0:block 1:transmit 2:convert to NS +fvp_mps2.dma1_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S +fvp_mps2.dma1_securitymodifier.behaviour_s_to_ns=0x0 # (int , init-time) default = '0x0' : Behaviour for S transactions to NS space : 0:block 1:transmit 2:convert to NS +fvp_mps2.dma2_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S +fvp_mps2.dma2_securitymodifier.behaviour_s_to_ns=0x0 # (int , init-time) default = '0x0' : Behaviour for S transactions to NS space : 0:block 1:transmit 2:convert to NS +fvp_mps2.dma3_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S +fvp_mps2.dma3_securitymodifier.behaviour_s_to_ns=0x0 # (int , init-time) default = '0x0' : Behaviour for S transactions to NS space : 0:block 1:transmit 2:convert to NS +fvp_mps2.dma0.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes +fvp_mps2.dma0.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer +fvp_mps2.dma0.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response +fvp_mps2.dma0.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay +fvp_mps2.dma1.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes +fvp_mps2.dma1.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer +fvp_mps2.dma1.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response +fvp_mps2.dma1.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay +fvp_mps2.dma2.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes +fvp_mps2.dma2.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer +fvp_mps2.dma2.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response +fvp_mps2.dma2.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay +fvp_mps2.dma3.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes +fvp_mps2.dma3.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer +fvp_mps2.dma3.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response +fvp_mps2.dma3.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay +fvp_mps2.iotss_systemcontrol.cpu0wait=0 # (bool , init-time) default = '0' : Whether to hold cpu1 in reset at boot +fvp_mps2.iotss_systemcontrol.cpu1wait=1 # (bool , init-time) default = '1' : Whether to hold cpu1 in reset at boot +fvp_mps2.iotss_cpuidentity.debugger_master_id=0xFFFFFFFF # (int , init-time) default = '0xFFFFFFFF' : : [0x0..0xFFFFFFFF] +#---------------------------------------------------------------------------------------------- diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMCM33_config.txt b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMCM33_config.txt new file mode 100644 index 0000000..a2d1052 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMCM33_config.txt @@ -0,0 +1,183 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#---------------------------------------------------------------------------------------------- +cpu0.FPU=0 # (bool , init-time) default = '1' : Set whether the model has VFP support +cpu0.DSP=0 # (bool , init-time) default = '1' : Set whether the model has the DSP extension +cpu0.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +cpu0.MPU_S=0x8 # (int , init-time) default = '0x8' : Number of regions in the Secure MPU. If Security Extentions are absent, this is ignored : [0x0..0x10] +cpu0.MPU_NS=0x8 # (int , init-time) default = '0x8' : Number of regions in the Non-Secure MPU. If Security Extentions are absent, this is the total number of MPU regions : [0x0..0x10] +cpu0.ITM=0 # (bool , init-time) default = '1' : Level of instrumentation trace supported. false : No ITM trace included, true: ITM trace included +cpu0.IRQLVL=0x3 # (int , init-time) default = '0x3' : Number of bits of interrupt priority : [0x3..0x8] +cpu0.BIGENDINIT=0 # (bool , init-time) default = '0' : Initialize processor to big endian mode +cpu0.INITSVTOR=0x00000000 # (int , init-time) default = '0x10000000' : Secure vector-table offset at reset : [0x0..0xFFFFFF80] +cpu0.INITNSVTOR=0x0 # (int , init-time) default = '0x0' : Non-Secure vector-table offset at reset : [0x0..0xFFFFFF80] +cpu0.SAU=0x0 # (int , init-time) default = '0x4' : Number of SAU regions (0 => no SAU) : [0x0..0x8] +cpu0.SAU_CTRL.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU at reset +cpu0.SAU_CTRL.ALLNS=0 # (bool , init-time) default = '0' : At reset, the SAU treats entire memory space as NS when the SAU is disabled if this is set +cpu0.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' : +cpu0.LOCK_SAU=0 # (bool , init-time) default = '0' : Lock down of SAU registers write +cpu0.LOCK_S_MPU=0 # (bool , init-time) default = '0' : Lock down of Secure MPU registers write +cpu0.LOCK_NS_MPU=0 # (bool , init-time) default = '0' : Lock down of Non-Secure MPU registers write +cpu0.CPIF=1 # (bool , init-time) default = '1' : Specifies whether the external coprocessor interface is included +cpu0.SECEXT=0 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included +fvp_mps2.DISABLE_GATING=1 # (bool , init-time) default = '0' : Disable Memory gating logic +fvp_mps2.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' : +fvp_mps2.SCC_ID.Variant=0x0 # (int , init-time) default = '0x0' : SCC_ID[23:20], X in the FGPA version 'rXpY' : [0x0..0xF] +fvp_mps2.SCC_ID.Revision=0x1 # (int , init-time) default = '0x1' : SCC_ID[3:0], Y in the FGPA version 'rXpY' : [0x0..0xF] +fvp_mps2.platform_type=0x0 # (int , init-time) default = '0x0' : 0:MPS2 ; 1:IoT Kit ; 2:Castor : [0x0..0x2] +fvp_mps2.extra_psram=0 # (bool , init-time) default = '0' : Increases PSRAM to 32Mb +fvp_mps2.UART2.out_file="" # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout) +fvp_mps2.UART2.in_file="" # (string, init-time) default = '' : Input file for data to be read by the UART +fvp_mps2.UART2.unbuffered_output=0 # (bool , init-time) default = '0' : Unbuffered output +fvp_mps2.UART2.in_file_escape_sequence="##" # (string, init-time) default = '##' : Input file escape sequence +fvp_mps2.UART2.shutdown_on_eot=0 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available) +fvp_mps2.UART2.shutdown_tag="" # (string, run-time ) default = '' : Shutdown simulation when a string is transmitted +fvp_mps2.UART1.out_file="" # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout) +fvp_mps2.UART1.in_file="" # (string, init-time) default = '' : Input file for data to be read by the UART +fvp_mps2.UART1.unbuffered_output=0 # (bool , init-time) default = '0' : Unbuffered output +fvp_mps2.UART1.in_file_escape_sequence="##" # (string, init-time) default = '##' : Input file escape sequence +fvp_mps2.UART1.shutdown_on_eot=0 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available) +fvp_mps2.UART1.shutdown_tag="" # (string, run-time ) default = '' : Shutdown simulation when a string is transmitted +fvp_mps2.mps2_visualisation.rate_limit-enable=1 # (bool , init-time) default = '1' : Rate limit simulation. +fvp_mps2.mps2_visualisation.disable-visualisation=0 # (bool , init-time) default = '0' : Enable/disable visualisation +fvp_mps2.mps2_visualisation.window_title="CLCD %cpu%" # (string, init-time) default = 'CLCD %cpu%' : Window title (%cpu% is replaced by cpu_name) +fvp_mps2.mps2_visualisation.idler.delay_ms=0x32 # (int , init-time) default = '0x32' : Determines the period, in milliseconds of real time, between gui_callback() calls. +fvp_mps2.telnetterminal0.mode="telnet" # (string, init-time) default = 'telnet' : Terminal initialisation mode +fvp_mps2.telnetterminal0.start_telnet=1 # (bool , init-time) default = '1' : Start telnet if nothing connected +fvp_mps2.telnetterminal0.start_port=0x1388 # (int , init-time) default = '0x1388' : Telnet TCP Port Number : [0x0..0xFFFFFFFF] +fvp_mps2.telnetterminal0.quiet=0 # (bool , init-time) default = '0' : Avoid output on stdout/stderr +fvp_mps2.telnetterminal0.terminal_command="" # (string, init-time) default = '' : Commandline to launch a terminal application and connect to the opened TCP port. Keywords %port and %title will be replaced with the opened port number and component name respectively. An empty string (default behaviour) will launch xterm (Linux) or telnet.exe (Windows) +fvp_mps2.telnetterminal1.mode="telnet" # (string, init-time) default = 'telnet' : Terminal initialisation mode +fvp_mps2.telnetterminal1.start_telnet=1 # (bool , init-time) default = '1' : Start telnet if nothing connected +fvp_mps2.telnetterminal1.start_port=0x1388 # (int , init-time) default = '0x1388' : Telnet TCP Port Number : [0x0..0xFFFFFFFF] +fvp_mps2.telnetterminal1.quiet=0 # (bool , init-time) default = '0' : Avoid output on stdout/stderr +fvp_mps2.telnetterminal1.terminal_command="" # (string, init-time) default = '' : Commandline to launch a terminal application and connect to the opened TCP port. Keywords %port and %title will be replaced with the opened port number and component name respectively. An empty string (default behaviour) will launch xterm (Linux) or telnet.exe (Windows) +fvp_mps2.telnetterminal2.mode="telnet" # (string, init-time) default = 'telnet' : Terminal initialisation mode +fvp_mps2.telnetterminal2.start_telnet=1 # (bool , init-time) default = '1' : Start telnet if nothing connected +fvp_mps2.telnetterminal2.start_port=0x1388 # (int , init-time) default = '0x1388' : Telnet TCP Port Number : [0x0..0xFFFFFFFF] +fvp_mps2.telnetterminal2.quiet=0 # (bool , init-time) default = '0' : Avoid output on stdout/stderr +fvp_mps2.telnetterminal2.terminal_command="" # (string, init-time) default = '' : Commandline to launch a terminal application and connect to the opened TCP port. Keywords %port and %title will be replaced with the opened port number and component name respectively. An empty string (default behaviour) will launch xterm (Linux) or telnet.exe (Windows) +fvp_mps2.PSRAM_M7.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size +fvp_mps2.PSRAM_M7.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.PSRAM_M7.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.UART0.out_file="" # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout) +fvp_mps2.UART0.in_file="" # (string, init-time) default = '' : Input file for data to be read by the UART +fvp_mps2.UART0.unbuffered_output=0 # (bool , init-time) default = '0' : Unbuffered output +fvp_mps2.UART0.in_file_escape_sequence="##" # (string, init-time) default = '##' : Input file escape sequence +fvp_mps2.UART0.shutdown_on_eot=0 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available) +fvp_mps2.UART0.shutdown_tag="" # (string, run-time ) default = '' : Shutdown simulation when a string is transmitted +fvp_mps2.cmsdk_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset. +fvp_mps2.s32k_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset. +fvp_mps2.secure_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset. +fvp_mps2.nonsecure_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset. +fvp_mps2.PSRAM.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size +fvp_mps2.PSRAM.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.PSRAM.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.ssram2.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size +fvp_mps2.ssram2.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.ssram2.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.ssram1.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size +fvp_mps2.ssram1.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.ssram1.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.stub.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size +fvp_mps2.iotss_internal_sram0.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size +fvp_mps2.iotss_internal_sram0.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.iotss_internal_sram0.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.iotss_internal_sram1.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size +fvp_mps2.iotss_internal_sram1.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.iotss_internal_sram1.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.iotss_internal_sram2.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size +fvp_mps2.iotss_internal_sram2.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.iotss_internal_sram2.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.iotss_internal_sram3.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size +fvp_mps2.iotss_internal_sram3.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.iotss_internal_sram3.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.sys_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.sys_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.cpu0core_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.cpu0dbg_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.cpu1core_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.cpu1core_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.cpu1dbg_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.cpu1dbg_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.crypto_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.crypto_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.cordio_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.cordio_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.dbg_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.dbg_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.ram0_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.ram0_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.ram1_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.ram1_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.ram2_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.ram2_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.ram3_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.ram3_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.smsc_91c111.enabled=0 # (bool , init-time) default = '0' : Host interface connection enabled +fvp_mps2.smsc_91c111.mac_address="00:02:f7:ef:5d:a2" # (string, init-time) default = '00:02:f7:ef:5d:a2' : Host/model MAC address +fvp_mps2.smsc_91c111.promiscuous=1 # (bool , init-time) default = '1' : Put host into promiscuous mode +fvp_mps2.hostbridge.interfaceName="ARM0" # (string, init-time) default = 'ARM0' : Host Interface +fvp_mps2.hostbridge.userNetworking=0 # (bool , init-time) default = '0' : Enable user-mode networking +fvp_mps2.hostbridge.userNetSubnet="172.20.51.0/24" # (string, init-time) default = '172.20.51.0/24' : Virtual subnet for user-mode networking +fvp_mps2.hostbridge.userNetPorts="" # (string, init-time) default = '' : Listening ports to expose in user-mode networking +fvp_mps2.secure_control_register_block.FLASH_BLOCK_CFG=0x3 # (int , init-time) default = '0x3' : Flash Block size configuration : [0x0..0x31] +fvp_mps2.secure_control_register_block.SRAM_BLOCK_CFG=0x3 # (int , init-time) default = '0x3' : SRAM Block size configuration : [0x0..0x31] +fvp_mps2.secure_control_register_block.FLASH_WATERMARK_SUPPORTED=1 # (bool , init-time) default = '1' : Flash Watermark supported +fvp_mps2.secure_control_register_block.SRAM_WATERMARK_SUPPORTED=1 # (bool , init-time) default = '1' : SRAM Watermark supported +fvp_mps2.exclusive_monitor_psram.enable_component=1 # (bool , init-time) default = '1' : Enable component +fvp_mps2.exclusive_monitor_psram.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF] +fvp_mps2.exclusive_monitor_psram.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB] +fvp_mps2.exclusive_monitor_psram.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master +fvp_mps2.exclusive_monitor_psram.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit +fvp_mps2.exclusive_monitor_psram.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3] +fvp_mps2.exclusive_monitor_psram.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores +fvp_mps2.exclusive_monitor_zbtsram1.enable_component=1 # (bool , init-time) default = '1' : Enable component +fvp_mps2.exclusive_monitor_zbtsram1.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF] +fvp_mps2.exclusive_monitor_zbtsram1.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB] +fvp_mps2.exclusive_monitor_zbtsram1.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master +fvp_mps2.exclusive_monitor_zbtsram1.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit +fvp_mps2.exclusive_monitor_zbtsram1.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3] +fvp_mps2.exclusive_monitor_zbtsram1.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores +fvp_mps2.exclusive_monitor_zbtsram2.enable_component=1 # (bool , init-time) default = '1' : Enable component +fvp_mps2.exclusive_monitor_zbtsram2.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF] +fvp_mps2.exclusive_monitor_zbtsram2.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB] +fvp_mps2.exclusive_monitor_zbtsram2.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master +fvp_mps2.exclusive_monitor_zbtsram2.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit +fvp_mps2.exclusive_monitor_zbtsram2.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3] +fvp_mps2.exclusive_monitor_zbtsram2.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores +fvp_mps2.exclusive_monitor_iotss_internal_sram.enable_component=1 # (bool , init-time) default = '1' : Enable component +fvp_mps2.exclusive_monitor_iotss_internal_sram.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF] +fvp_mps2.exclusive_monitor_iotss_internal_sram.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB] +fvp_mps2.exclusive_monitor_iotss_internal_sram.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master +fvp_mps2.exclusive_monitor_iotss_internal_sram.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit +fvp_mps2.exclusive_monitor_iotss_internal_sram.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3] +fvp_mps2.exclusive_monitor_iotss_internal_sram.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores +fvp_mps2.dma0_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S +fvp_mps2.dma0_securitymodifier.behaviour_s_to_ns=0x0 # (int , init-time) default = '0x0' : Behaviour for S transactions to NS space : 0:block 1:transmit 2:convert to NS +fvp_mps2.dma1_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S +fvp_mps2.dma1_securitymodifier.behaviour_s_to_ns=0x0 # (int , init-time) default = '0x0' : Behaviour for S transactions to NS space : 0:block 1:transmit 2:convert to NS +fvp_mps2.dma2_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S +fvp_mps2.dma2_securitymodifier.behaviour_s_to_ns=0x0 # (int , init-time) default = '0x0' : Behaviour for S transactions to NS space : 0:block 1:transmit 2:convert to NS +fvp_mps2.dma3_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S +fvp_mps2.dma3_securitymodifier.behaviour_s_to_ns=0x0 # (int , init-time) default = '0x0' : Behaviour for S transactions to NS space : 0:block 1:transmit 2:convert to NS +fvp_mps2.dma0.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes +fvp_mps2.dma0.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer +fvp_mps2.dma0.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response +fvp_mps2.dma0.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay +fvp_mps2.dma1.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes +fvp_mps2.dma1.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer +fvp_mps2.dma1.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response +fvp_mps2.dma1.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay +fvp_mps2.dma2.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes +fvp_mps2.dma2.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer +fvp_mps2.dma2.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response +fvp_mps2.dma2.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay +fvp_mps2.dma3.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes +fvp_mps2.dma3.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer +fvp_mps2.dma3.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response +fvp_mps2.dma3.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay +fvp_mps2.iotss_systemcontrol.cpu0wait=0 # (bool , init-time) default = '0' : Whether to hold cpu1 in reset at boot +fvp_mps2.iotss_systemcontrol.cpu1wait=1 # (bool , init-time) default = '1' : Whether to hold cpu1 in reset at boot +fvp_mps2.iotss_cpuidentity.debugger_master_id=0xFFFFFFFF # (int , init-time) default = '0xFFFFFFFF' : : [0x0..0xFFFFFFFF] +#---------------------------------------------------------------------------------------------- diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_MPS2/HowTo.txt b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_MPS2/HowTo.txt new file mode 100644 index 0000000..865ac15 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_MPS2/HowTo.txt @@ -0,0 +1,29 @@ + +Used board: + MPS2+. + +Used BIOS: + mbb_v121.ebf ; use this for ULINKpro + mbb_v220.ebf ; CMSIS-DAP + +Used Images: + AN382\an382_v3.txt ; Cortex-M0 + AN385\an385_v3.txt ; Cortex-M3 + AN386\an386_v3.txt ; Cortex-M4 + AN500\an500_v1.txt ; Cortex-M7 + AN505\an505_v2.txt ; Cortex-M33 (IoT Kit) + AN519\an519_v1.txt ; Cortex-M23 (IoT Kit) + +Used Debugger: + IoT Kit: + ULINKpro, JTAG, 25MHz, HW Reset + other: + ULINKpro, JTAG, 25MHz, Autodetect + +Memory Settings: + IoT Kit: + ROM: 0x10000000 + RAM: 0x38000000 + other: + ROM: 0x00000000 + RAM: 0x20000000 \ No newline at end of file diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/HowTo.txt b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/HowTo.txt new file mode 100644 index 0000000..39147ab --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/HowTo.txt @@ -0,0 +1,144 @@ +HowTo DSP_Lib_TestSuite 16.12.2016 +======================================= + +This file describes the folder structure, content, prerequisites and instructions to validate the +build of the CMSIS-DSP library. This is done by processing input data sets using the DSP Library +functions executing on a target simulator or hardware. The output data sets are then compared +with the reference data set produced by unoptimized DSP functions and a Signal to Noise Ratio (SNR) +is computed. If the SNR is below a defined threshold the test is considered "passed". + + +Folder structure +---------------- + .\DSP_Lib_TestSuite Batch files for building the reference libraries and running the tests. + .\DSP_Lib_TestSuite\Common + .\DSP_Lib_TestSuite\Common\inc DSP_Lib test include files + .\DSP_Lib_TestSuite\Common\JTest JTEST Test Framework + INI files for uVision + .\DSP_Lib_TestSuite\Common\platform ARM/GCC device startup/system files + .\DSP_Lib_TestSuite\Common\src DSP_Lib test source files + .\DSP_Lib_TestSuite\DspLibTest_FVP ARM/GCC DSP_Lib test projects for Fixed Virtual Platforms + .\DSP_Lib_TestSuite\DspLibTest_MPS2 ARM/GCC DSP_Lib test projects for MPS2 + .\DSP_Lib_TestSuite\DspLibTest_Simulator ARM/GCC DSP_Lib test projects for uVision simulator + .\DSP_Lib_TestSuite\RefLibs ARM/GCC DSP_Lib reference libraries (and projects) + + + +Prerequisites +-------------- + - Python (running on Windows). Tested with ActivePython 2.7.8.10. + - Keil MDK-ARM (tested with MDK-ARM 5.22: http://www2.keil.com/mdk5) + - ULINKpro debug adapter (http://www2.keil.com/mdk5/ulink) + - MPS2 (Cortex-M Prototyping System:https://www.arm.com/products/tools/development-boards/versatile-express/cortex-m-prototyping-system.php) + - CMSIS 5.0.0 (https://github.com/ARM-software/CMSIS_5/releases/tag/5.0.0) + + +Setup +------ + - Copy DSP_Lib_TestSuite to the CMSIS installation/pack folder. + ... + .\Keil_v5\ARM\PACK\ARM\CMSIS\DSP_Lib + .\Keil_v5\ARM\PACK\ARM\CMSIS\DSP_Lib_TestSuite <- location of DSP_Lib_TestSuite + .\Keil_v5\ARM\PACK\ARM\CMSIS\Include + ... + + - remove 'read-only' tag from folder ./CMSIS/Lib + (required for rebuild of the DSP_Lib libraries) + + - open a Windows command window in folder .\CMSIS\DSP_Lib_TestSuite. + + + +How to run the tests +--------------------- + +a) build the DSP_Lib libraries: + - batch file: buildDspLibs.bat + Note: only require if the DSP_Lib source code got updated or the desired configuration is missing + buildDspLibs.bat overwrites the prebuild libraries in .\CMSIS\Lib. + Log files of the build process are generated in folder .\CMSIS\DSP_Lib/[ARM|GCC] + - run: buildDspLibs.bat in a Windows command window in folder ./CMSIS/DSP_Lib_TestSuite + buildDspLibs ARM -> builds the ARMCC libraries + buildDspLibs GCC -> builds the GCC libraries + +b) build the reference libraries: + - batch file: buildRefLibs.bat + + Log files of the build process are generated in folder .\CMSIS\DSP_Lib_TestSuite\RefLibs/[ARM|GCC] + - run: buildRefLibs.bat in a Windows command window in folder .\CMSIS\DSP_Lib_TestSuite + buildRefLibs ARM -> builds the ARMCC reference libraries + buildRefLibs GCC -> builds the GCC reference libraries + +c) running an individual test using uVision (MDK-ARM): + - batch file: runTest.bat + - run: runTest.bat in a Windows command window in folder .\CMSIS\DSP_Lib_TestSuite + runTest -> prints usage information + e.g. runTest ARM cortexM4lf Simulator -> runs the test for toolchain ARM, Cortex-M4 littel endian with FPU, uVision Simulator. + + Tests running on MPS2 requires additional steps to setup. See section 'MPS2'. + +d) parsing the test output log file + - script: parseLog.py + - run: parseLog.py python script in a Windows command window in folder .\CMSIS\DSP_Lib_TestSuite + command line options should match the invocation of the runTest executed before. + e.g: runTest ARM cortexM4lf Simulator -> python parseLog.py ARM cortexM4lf Simulator + + - check the test log + depending on your test parameters change into the required folder + .\DSP_Lib_TestSuite\DspLibTest_[FVP|MPS2|Simulator]\[ARM|GCC]\Logs + the folder will contain the following files (e.g. for a 'runTest') : + DspLibTest_Simulator.log raw result of the last test run. + DspLibTest_Simulator_cortexM4lf.log raw result of a cortexM4lf test run + DspLibTest_Simulator_cortexM4lf_build.log build result of cortexM4lf test + DspLibTest_Simulator_cortexM4lf_parsed.log parsed log of raw result of a cortexM4lf test run + DspLibTest_Simulator_cortexM4lf_time.log log how long the test took (some tests e.g. M0 take really a long time!). + 'runTest' produces files of the format: DspLibTest__... + + +Differences between the tests for FVP, MPS2, Simulator +------------------------------------------------------ + - all tests are identical except for: + 'Simulator' uses uVision with uVision simulator and generates also code coverage information + can be used for little/big endian tests + ! do not use 'Simulator' for M7 with FPU -> no uVision simulation available. + ! do not use 'Simulator' for ARMv8-M devices -> no uVision simulation available. + 'MPS2' uses uVision with ULINKpro debugger and MPS2. No code coverage information is generated. + can be used for little endian only (because of the lack of MPS2 FPGA images). + 'FVP' uses uVision with Models debugger. No code coverage information is generated. + can be used for little/big endian tests. + ! config files must be prepared. + ! uVision target for big endianess are not yet prepared. + + +Setup 'MPS2' +------------- + - load the appropriate FPGA image to the MPS2 board matching the CPU of the test builds prior to running the test + - check if ULINKpro can connect with the configured debug connection (JTAG or SWD) as this must + match the protocol implemented in the FPGA image. + + +How to select tests for "run all tests" +---------------------------------------- + - edit .\CMSIS\DSP_Lib_TestSuite\Common\src\all_tests.c + comment out all unwanted test groups. + e.g. // JTEST_GROUP_CALL(complex_math_tests); + + - edit .\CMSIS\DSP_Lib_TestSuite\Common\src\/_group.c + comment out all unwanted sub test groups. + e.g. file .\DSP_Lib_TestSuite\Common\src\basic_math_tests\basic_math_test_group.c -> // JTEST_GROUP_CALL(abs_tests); + + - edit .\CMSIS\DSP_Lib_TestSuite\Common\src\/_tests.c + comment out all unwanted tests. + e.g. file .\DSP_Lib_TestSuite\Common\src\basic_math_tests\abs_tests.c -> // JTEST_TEST_CALL(arm_abs_f32_test); + + +Notes +----- + - How to use ARM Clang (ARM Compiler 6): + in uVision 'Options for Target' tab you can select which compiler to use + by default uVision uses ARMCC V5 for Cortex-M devices and ARMCLANG V6 only for ARMv8M. + Only ARMv8M cores have been tested using ARMCLANG + + - test data used for the tests is used as provided by DSP Concepts. + + - some tests run for a very long time before they finish. This is expected + diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/Abstract.txt b/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/Abstract.txt new file mode 100644 index 0000000..7ac021f --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/Abstract.txt @@ -0,0 +1,4 @@ +CMSIS DSP_Lib example arm_class_marks_example for + Cortex-M0, Cortex-M3, Cortex-M4 with FPU and Cortex-M7 with single precision FPU. + +The example is configured for uVision Simulator diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/Abstract.txt b/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/Abstract.txt new file mode 100644 index 0000000..7ef79e2 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/Abstract.txt @@ -0,0 +1,4 @@ +CMSIS DSP_Lib example arm_convolution_example for + Cortex-M0, Cortex-M3, Cortex-M4 with FPU and Cortex-M7 with single precision FPU. + +The example is configured for uVision Simulator. diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/Abstract.txt b/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/Abstract.txt new file mode 100644 index 0000000..f889251 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/Abstract.txt @@ -0,0 +1,4 @@ +CMSIS DSP_Lib example arm_dotproduct_example for + Cortex-M0, Cortex-M3, Cortex-M4 with FPU and Cortex-M7 with single precision FPU. + +The example is configured for uVision Simulator. diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/Abstract.txt b/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/Abstract.txt new file mode 100644 index 0000000..37bea21 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/Abstract.txt @@ -0,0 +1,4 @@ +CMSIS DSP_Lib example arm_fft_bin_example for + Cortex-M0, Cortex-M3, Cortex-M4 with FPU and Cortex-M7 with single precision FPU. + +The example is configured for uVision Simulator. diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/Abstract.txt b/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/Abstract.txt new file mode 100644 index 0000000..9189b7c --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/Abstract.txt @@ -0,0 +1,4 @@ +CMSIS DSP_Lib example arm_fir_example for + Cortex-M0, Cortex-M3, Cortex-M4 with FPU and Cortex-M7 with single precision FPU. + +The example is configured for uVision Simulator. diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/Abstract.txt b/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/Abstract.txt new file mode 100644 index 0000000..c2452b6 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/Abstract.txt @@ -0,0 +1,4 @@ +CMSIS DSP_Lib example arm_graphic_equalizer_example for + Cortex-M0, Cortex-M3, Cortex-M4 with FPU and Cortex-M7 with single precision FPU. + +The example is configured for uVision Simulator. diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/Abstract.txt b/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/Abstract.txt new file mode 100644 index 0000000..9062c48 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/Abstract.txt @@ -0,0 +1,4 @@ +CMSIS DSP_Lib example arm_linear_interp_example for + Cortex-M0, Cortex-M3, Cortex-M4 with FPU and Cortex-M7 with single precision FPU. + +The example is configured for uVision Simulator. diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/Abstract.txt b/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/Abstract.txt new file mode 100644 index 0000000..f45b0e0 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/Abstract.txt @@ -0,0 +1,4 @@ +CMSIS DSP_Lib example arm_matrix_example for + Cortex-M0, Cortex-M3, Cortex-M4 with FPU and Cortex-M7 with single precision FPU. + +The example is configured for uVision Simulator. diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/Abstract.txt b/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/Abstract.txt new file mode 100644 index 0000000..d202e78 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/Abstract.txt @@ -0,0 +1,4 @@ +CMSIS DSP_Lib example arm_signal_converge_example for + Cortex-M0, Cortex-M3, Cortex-M4 with FPU and Cortex-M7 with single precision FPU. + +The example is configured for uVision Simulator. diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/Abstract.txt b/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/Abstract.txt new file mode 100644 index 0000000..84bd3fd --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/Abstract.txt @@ -0,0 +1,4 @@ +CMSIS DSP_Lib example arm_sin_cos_example for + Cortex-M0, Cortex-M3, Cortex-M4 with FPU and Cortex-M7 with single precision FPU. + +The example is configured for uVision Simulator. diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/Abstract.txt b/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/Abstract.txt new file mode 100644 index 0000000..4dc03b8 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/Abstract.txt @@ -0,0 +1,4 @@ +CMSIS DSP_Lib example arm_variance_example for + Cortex-M0, Cortex-M3, Cortex-M4 with FPU and Cortex-M7 with single precision FPU. + +The example is configured for uVision Simulator. diff --git a/Drivers/CMSIS/LICENSE.txt b/Drivers/CMSIS/LICENSE.txt new file mode 100644 index 0000000..c0ee812 --- /dev/null +++ b/Drivers/CMSIS/LICENSE.txt @@ -0,0 +1,201 @@ + Apache License + Version 2.0, January 2004 + http://www.apache.org/licenses/ + + TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION + + 1. Definitions. + + "License" shall mean the terms and conditions for use, reproduction, + and distribution as defined by Sections 1 through 9 of this document. + + "Licensor" shall mean the copyright owner or entity authorized by + the copyright owner that is granting the License. + + "Legal Entity" shall mean the union of the acting entity and all + other entities that control, are controlled by, or are under common + control with that entity. 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In no event and under no legal theory, + whether in tort (including negligence), contract, or otherwise, + unless required by applicable law (such as deliberate and grossly + negligent acts) or agreed to in writing, shall any Contributor be + liable to You for damages, including any direct, indirect, special, + incidental, or consequential damages of any character arising as a + result of this License or out of the use or inability to use the + Work (including but not limited to damages for loss of goodwill, + work stoppage, computer failure or malfunction, or any and all + other commercial damages or losses), even if such Contributor + has been advised of the possibility of such damages. + + 9. Accepting Warranty or Additional Liability. While redistributing + the Work or Derivative Works thereof, You may choose to offer, + and charge a fee for, acceptance of support, warranty, indemnity, + or other liability obligations and/or rights consistent with this + License. However, in accepting such obligations, You may act only + on Your own behalf and on Your sole responsibility, not on behalf + of any other Contributor, and only if You agree to indemnify, + defend, and hold each Contributor harmless for any liability + incurred by, or claims asserted against, such Contributor by reason + of your accepting any such warranty or additional liability. + + END OF TERMS AND CONDITIONS + + APPENDIX: How to apply the Apache License to your work. + + To apply the Apache License to your work, attach the following + boilerplate notice, with the fields enclosed by brackets "{}" + replaced with your own identifying information. (Don't include + the brackets!) The text should be enclosed in the appropriate + comment syntax for the file format. We also recommend that a + file or class name and description of purpose be included on the + same "printed page" as the copyright notice for easier + identification within third-party archives. + + Copyright {yyyy} {name of copyright owner} + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. diff --git a/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/readme.txt b/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/readme.txt new file mode 100644 index 0000000..75b6e01 --- /dev/null +++ b/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/readme.txt @@ -0,0 +1,4 @@ +CMSIS NN Lib example arm_nnexample_cifar10 for + Cortex-M4 and Cortex-M7. + +The example is configured for uVision Simulator. diff --git a/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/readme.txt b/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/readme.txt new file mode 100644 index 0000000..99cf676 --- /dev/null +++ b/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/readme.txt @@ -0,0 +1,4 @@ +CMSIS NN Lib example arm_nnexample_gru0 for + Cortex-M4 and Cortex-M7. + +The example is configured for uVision Simulator. diff --git a/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/readme.txt b/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/readme.txt new file mode 100644 index 0000000..0ea82e7 --- /dev/null +++ b/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/readme.txt @@ -0,0 +1,4 @@ +CMSIS DSP_Lib example arm_nnexample_nn_test for + Cortex-M3, Cortex-M4 and Cortex-M7. + +The example is configured for uVision Simulator. diff --git a/Drivers/CMSIS/docs/General/html/LICENSE.txt b/Drivers/CMSIS/docs/General/html/LICENSE.txt new file mode 100644 index 0000000..c0ee812 --- /dev/null +++ b/Drivers/CMSIS/docs/General/html/LICENSE.txt @@ -0,0 +1,201 @@ + Apache License + Version 2.0, January 2004 + http://www.apache.org/licenses/ + + TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION + + 1. Definitions. + + "License" shall mean the terms and conditions for use, reproduction, + and distribution as defined by Sections 1 through 9 of this document. + + "Licensor" shall mean the copyright owner or entity authorized by + the copyright owner that is granting the License. + + "Legal Entity" shall mean the union of the acting entity and all + other entities that control, are controlled by, or are under common + control with that entity. For the purposes of this definition, + "control" means (i) the power, direct or indirect, to cause the + direction or management of such entity, whether by contract or + otherwise, or (ii) ownership of fifty percent (50%) or more of the + outstanding shares, or (iii) beneficial ownership of such entity. + + "You" (or "Your") shall mean an individual or Legal Entity + exercising permissions granted by this License. + + "Source" form shall mean the preferred form for making modifications, + including but not limited to software source code, documentation + source, and configuration files. + + "Object" form shall mean any form resulting from mechanical + transformation or translation of a Source form, including but + not limited to compiled object code, generated documentation, + and conversions to other media types. + + "Work" shall mean the work of authorship, whether in Source or + Object form, made available under the License, as indicated by a + copyright notice that is included in or attached to the work + (an example is provided in the Appendix below). + + "Derivative Works" shall mean any work, whether in Source or Object + form, that is based on (or derived from) the Work and for which the + editorial revisions, annotations, elaborations, or other modifications + represent, as a whole, an original work of authorship. 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Unless required by applicable law or + agreed to in writing, Licensor provides the Work (and each + Contributor provides its Contributions) on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied, including, without limitation, any warranties or conditions + of TITLE, NON-INFRINGEMENT, MERCHANTABILITY, or FITNESS FOR A + PARTICULAR PURPOSE. You are solely responsible for determining the + appropriateness of using or redistributing the Work and assume any + risks associated with Your exercise of permissions under this License. + + 8. Limitation of Liability. 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However, in accepting such obligations, You may act only + on Your own behalf and on Your sole responsibility, not on behalf + of any other Contributor, and only if You agree to indemnify, + defend, and hold each Contributor harmless for any liability + incurred by, or claims asserted against, such Contributor by reason + of your accepting any such warranty or additional liability. + + END OF TERMS AND CONDITIONS + + APPENDIX: How to apply the Apache License to your work. + + To apply the Apache License to your work, attach the following + boilerplate notice, with the fields enclosed by brackets "{}" + replaced with your own identifying information. (Don't include + the brackets!) The text should be enclosed in the appropriate + comment syntax for the file format. We also recommend that a + file or class name and description of purpose be included on the + same "printed page" as the copyright notice for easier + identification within third-party archives. + + Copyright {yyyy} {name of copyright owner} + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_fmpsmbus.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_fmpsmbus.h index e75b522..0118a46 100644 --- a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_fmpsmbus.h +++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_fmpsmbus.h @@ -133,7 +133,11 @@ typedef struct * @brief FMPSMBUS handle Structure definition * @{ */ +#if (USE_HAL_FMPSMBUS_REGISTER_CALLBACKS == 1) typedef struct __FMPSMBUS_HandleTypeDef +#else +typedef struct +#endif /* USE_HAL_FMPSMBUS_REGISTER_CALLBACKS */ { FMPI2C_TypeDef *Instance; /*!< FMPSMBUS registers base address */ @@ -327,6 +331,7 @@ typedef void (*pFMPSMBUS_AddrCallbackTypeDef)(FMPSMBUS_HandleTypeDef *hfmpsmbus #define FMPSMBUS_NEXT_FRAME ((uint32_t)(FMPSMBUS_RELOAD_MODE | FMPSMBUS_SOFTEND_MODE)) #define FMPSMBUS_FIRST_AND_LAST_FRAME_NO_PEC FMPSMBUS_AUTOEND_MODE #define FMPSMBUS_LAST_FRAME_NO_PEC FMPSMBUS_AUTOEND_MODE +#define FMPSMBUS_FIRST_FRAME_WITH_PEC ((uint32_t)(FMPSMBUS_SOFTEND_MODE | FMPSMBUS_SENDPEC_MODE)) #define FMPSMBUS_FIRST_AND_LAST_FRAME_WITH_PEC ((uint32_t)(FMPSMBUS_AUTOEND_MODE | FMPSMBUS_SENDPEC_MODE)) #define FMPSMBUS_LAST_FRAME_WITH_PEC ((uint32_t)(FMPSMBUS_AUTOEND_MODE | FMPSMBUS_SENDPEC_MODE)) @@ -583,11 +588,12 @@ typedef void (*pFMPSMBUS_AddrCallbackTypeDef)(FMPSMBUS_HandleTypeDef *hfmpsmbus ((REQUEST) == FMPSMBUS_NO_STARTSTOP)) -#define IS_FMPSMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST) (IS_FMPSMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) || \ +#define IS_FMPSMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST) (IS_FMPSMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) || \ ((REQUEST) == FMPSMBUS_FIRST_FRAME) || \ ((REQUEST) == FMPSMBUS_NEXT_FRAME) || \ ((REQUEST) == FMPSMBUS_FIRST_AND_LAST_FRAME_NO_PEC) || \ ((REQUEST) == FMPSMBUS_LAST_FRAME_NO_PEC) || \ + ((REQUEST) == FMPSMBUS_FIRST_FRAME_WITH_PEC) || \ ((REQUEST) == FMPSMBUS_FIRST_AND_LAST_FRAME_WITH_PEC) || \ ((REQUEST) == FMPSMBUS_LAST_FRAME_WITH_PEC)) diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_hcd.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_hcd.h index 95715df..8771ae3 100644 --- a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_hcd.h +++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_hcd.h @@ -143,9 +143,9 @@ typedef struct /* Exported macro ------------------------------------------------------------*/ /** @defgroup HCD_Exported_Macros HCD Exported Macros - * @brief macros to handle interrupts and specific clock configurations - * @{ - */ + * @brief macros to handle interrupts and specific clock configurations + * @{ + */ #define __HAL_HCD_ENABLE(__HANDLE__) (void)USB_EnableGlobalInt ((__HANDLE__)->Instance) #define __HAL_HCD_DISABLE(__HANDLE__) (void)USB_DisableGlobalInt ((__HANDLE__)->Instance) @@ -214,10 +214,16 @@ typedef void (*pHCD_HC_NotifyURBChangeCallbackTypeDef)(HCD_HandleTypeDef *hhcd, * @} */ -HAL_StatusTypeDef HAL_HCD_RegisterCallback(HCD_HandleTypeDef *hhcd, HAL_HCD_CallbackIDTypeDef CallbackID, pHCD_CallbackTypeDef pCallback); -HAL_StatusTypeDef HAL_HCD_UnRegisterCallback(HCD_HandleTypeDef *hhcd, HAL_HCD_CallbackIDTypeDef CallbackID); +HAL_StatusTypeDef HAL_HCD_RegisterCallback(HCD_HandleTypeDef *hhcd, + HAL_HCD_CallbackIDTypeDef CallbackID, + pHCD_CallbackTypeDef pCallback); + +HAL_StatusTypeDef HAL_HCD_UnRegisterCallback(HCD_HandleTypeDef *hhcd, + HAL_HCD_CallbackIDTypeDef CallbackID); + +HAL_StatusTypeDef HAL_HCD_RegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef *hhcd, + pHCD_HC_NotifyURBChangeCallbackTypeDef pCallback); -HAL_StatusTypeDef HAL_HCD_RegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef *hhcd, pHCD_HC_NotifyURBChangeCallbackTypeDef pCallback); HAL_StatusTypeDef HAL_HCD_UnRegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef *hhcd); #endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ /** @@ -235,6 +241,7 @@ HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd, uint8_t ch_n /* Non-Blocking mode: Interrupt */ void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd); +void HAL_HCD_WKUP_IRQHandler(HCD_HandleTypeDef *hhcd); void HAL_HCD_SOF_Callback(HCD_HandleTypeDef *hhcd); void HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd); void HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd); @@ -256,6 +263,9 @@ HAL_StatusTypeDef HAL_HCD_Stop(HCD_HandleTypeDef *hhcd); /** * @} */ +/** + * @} + */ /* Peripheral State functions ************************************************/ /** @addtogroup HCD_Exported_Functions_Group4 Peripheral State functions @@ -267,6 +277,7 @@ HCD_HCStateTypeDef HAL_HCD_HC_GetState(HCD_HandleTypeDef *hhcd, uint8_t chn uint32_t HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef *hhcd, uint8_t chnum); uint32_t HAL_HCD_GetCurrentFrame(HCD_HandleTypeDef *hhcd); uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd); + /** * @} */ @@ -277,13 +288,11 @@ uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd); /* Private macros ------------------------------------------------------------*/ /** @defgroup HCD_Private_Macros HCD Private Macros - * @{ - */ - + * @{ + */ /** * @} */ - /* Private functions prototypes ----------------------------------------------*/ /** @defgroup HCD_Private_Functions_Prototypes HCD Private Functions Prototypes * @{ @@ -298,14 +307,6 @@ uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd); * @{ */ -/** - * @} - */ - -/** - * @} - */ - /** * @} */ diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h index a6f00ae..3b9fca8 100644 --- a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h +++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h @@ -182,7 +182,11 @@ typedef enum * @brief I2C handle Structure definition * @{ */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) typedef struct __I2C_HandleTypeDef +#else +typedef struct +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ { I2C_TypeDef *Instance; /*!< I2C registers base address */ diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h index f57f021..7fa3184 100644 --- a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h +++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h @@ -187,9 +187,9 @@ typedef struct /* Exported macros -----------------------------------------------------------*/ /** @defgroup PCD_Exported_Macros PCD Exported Macros - * @brief macros to handle interrupts and specific clock configurations - * @{ - */ + * @brief macros to handle interrupts and specific clock configurations + * @{ + */ #if defined (USB_OTG_FS) || defined (USB_OTG_HS) #define __HAL_PCD_ENABLE(__HANDLE__) (void)USB_EnableGlobalInt ((__HANDLE__)->Instance) #define __HAL_PCD_DISABLE(__HANDLE__) (void)USB_DisableGlobalInt ((__HANDLE__)->Instance) @@ -199,12 +199,11 @@ typedef struct #define __HAL_PCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0U) -#define __HAL_PCD_UNGATE_PHYCLOCK(__HANDLE__) *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) &= \ - ~(USB_OTG_PCGCCTL_STOPCLK) +#define __HAL_PCD_UNGATE_PHYCLOCK(__HANDLE__) *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) &= ~(USB_OTG_PCGCCTL_STOPCLK) -#define __HAL_PCD_GATE_PHYCLOCK(__HANDLE__) *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) |= USB_OTG_PCGCCTL_STOPCLK +#define __HAL_PCD_GATE_PHYCLOCK(__HANDLE__) *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) |= USB_OTG_PCGCCTL_STOPCLK -#define __HAL_PCD_IS_PHY_SUSPENDED(__HANDLE__) ((*(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE)) & 0x10U) +#define __HAL_PCD_IS_PHY_SUSPENDED(__HANDLE__) ((*(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE)) & 0x10U) #define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= (USB_OTG_HS_WAKEUP_EXTI_LINE) #define __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE) @@ -212,20 +211,20 @@ typedef struct #define __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = (USB_OTG_HS_WAKEUP_EXTI_LINE) #define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE() \ - do { \ - EXTI->FTSR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE); \ - EXTI->RTSR |= USB_OTG_HS_WAKEUP_EXTI_LINE; \ - } while(0U) + do { \ + EXTI->FTSR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE); \ + EXTI->RTSR |= USB_OTG_HS_WAKEUP_EXTI_LINE; \ + } while(0U) #define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= USB_OTG_FS_WAKEUP_EXTI_LINE #define __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE) #define __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (USB_OTG_FS_WAKEUP_EXTI_LINE) #define __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = USB_OTG_FS_WAKEUP_EXTI_LINE #define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE() \ - do { \ - EXTI->FTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE); \ - EXTI->RTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE; \ - } while(0U) + do { \ + EXTI->FTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE); \ + EXTI->RTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE; \ + } while(0U) #endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ @@ -287,25 +286,41 @@ typedef void (*pPCD_BcdCallbackTypeDef)(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgType * @} */ -HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID, pPCD_CallbackTypeDef pCallback); -HAL_StatusTypeDef HAL_PCD_UnRegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID); +HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd, + HAL_PCD_CallbackIDTypeDef CallbackID, + pPCD_CallbackTypeDef pCallback); + +HAL_StatusTypeDef HAL_PCD_UnRegisterCallback(PCD_HandleTypeDef *hpcd, + HAL_PCD_CallbackIDTypeDef CallbackID); + +HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd, + pPCD_DataOutStageCallbackTypeDef pCallback); -HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd, pPCD_DataOutStageCallbackTypeDef pCallback); HAL_StatusTypeDef HAL_PCD_UnRegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd); -HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(PCD_HandleTypeDef *hpcd, pPCD_DataInStageCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(PCD_HandleTypeDef *hpcd, + pPCD_DataInStageCallbackTypeDef pCallback); + HAL_StatusTypeDef HAL_PCD_UnRegisterDataInStageCallback(PCD_HandleTypeDef *hpcd); -HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd, pPCD_IsoOutIncpltCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd, + pPCD_IsoOutIncpltCallbackTypeDef pCallback); + HAL_StatusTypeDef HAL_PCD_UnRegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd); -HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd, pPCD_IsoInIncpltCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd, + pPCD_IsoInIncpltCallbackTypeDef pCallback); + HAL_StatusTypeDef HAL_PCD_UnRegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd); -HAL_StatusTypeDef HAL_PCD_RegisterBcdCallback(PCD_HandleTypeDef *hpcd, pPCD_BcdCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_PCD_RegisterBcdCallback(PCD_HandleTypeDef *hpcd, + pPCD_BcdCallbackTypeDef pCallback); + HAL_StatusTypeDef HAL_PCD_UnRegisterBcdCallback(PCD_HandleTypeDef *hpcd); -HAL_StatusTypeDef HAL_PCD_RegisterLpmCallback(PCD_HandleTypeDef *hpcd, pPCD_LpmCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_PCD_RegisterLpmCallback(PCD_HandleTypeDef *hpcd, + pPCD_LpmCallbackTypeDef pCallback); + HAL_StatusTypeDef HAL_PCD_UnRegisterLpmCallback(PCD_HandleTypeDef *hpcd); #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ /** @@ -320,6 +335,7 @@ HAL_StatusTypeDef HAL_PCD_UnRegisterLpmCallback(PCD_HandleTypeDef *hpcd); HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd); HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd); void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd); +void HAL_PCD_WKUP_IRQHandler(PCD_HandleTypeDef *hpcd); void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd); void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd); @@ -344,16 +360,24 @@ void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum); HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd); HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd); HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address); -HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type); +HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, + uint16_t ep_mps, uint8_t ep_type); + HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); -HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len); -HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len); -uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); +HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, + uint8_t *pBuf, uint32_t len); + +HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, + uint8_t *pBuf, uint32_t len); + + HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd); HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd); + +uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); /** * @} */ @@ -419,8 +443,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); /* Private macros ------------------------------------------------------------*/ /** @defgroup PCD_Private_Macros PCD Private Macros - * @{ - */ + * @{ + */ /** * @} diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_fmpi2c.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_fmpi2c.h index 9a6640f..03f59ae 100644 --- a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_fmpi2c.h +++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_fmpi2c.h @@ -68,38 +68,38 @@ extern "C" { typedef struct { uint32_t PeripheralMode; /*!< Specifies the peripheral mode. - This parameter can be a value of @ref FMPI2C_LL_EC_PERIPHERAL_MODE + This parameter can be a value of @ref FMPI2C_LL_EC_PERIPHERAL_MODE. This feature can be modified afterwards using unitary function @ref LL_FMPI2C_SetMode(). */ uint32_t Timing; /*!< Specifies the SDA setup, hold time and the SCL high, low period values. This parameter must be set by referring to the STM32CubeMX Tool and - the helper macro @ref __LL_FMPI2C_CONVERT_TIMINGS() + the helper macro @ref __LL_FMPI2C_CONVERT_TIMINGS(). This feature can be modified afterwards using unitary function @ref LL_FMPI2C_SetTiming(). */ uint32_t AnalogFilter; /*!< Enables or disables analog noise filter. - This parameter can be a value of @ref FMPI2C_LL_EC_ANALOGFILTER_SELECTION + This parameter can be a value of @ref FMPI2C_LL_EC_ANALOGFILTER_SELECTION. This feature can be modified afterwards using unitary functions @ref LL_FMPI2C_EnableAnalogFilter() or LL_FMPI2C_DisableAnalogFilter(). */ uint32_t DigitalFilter; /*!< Configures the digital noise filter. - This parameter can be a number between Min_Data = 0x00 and Max_Data = 0x0F + This parameter can be a number between Min_Data = 0x00 and Max_Data = 0x0F. This feature can be modified afterwards using unitary function @ref LL_FMPI2C_SetDigitalFilter(). */ uint32_t OwnAddress1; /*!< Specifies the device own address 1. - This parameter must be a value between Min_Data = 0x00 and Max_Data = 0x3FF + This parameter must be a value between Min_Data = 0x00 and Max_Data = 0x3FF. This feature can be modified afterwards using unitary function @ref LL_FMPI2C_SetOwnAddress1(). */ uint32_t TypeAcknowledge; /*!< Specifies the ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte. - This parameter can be a value of @ref FMPI2C_LL_EC_I2C_ACKNOWLEDGE + This parameter can be a value of @ref FMPI2C_LL_EC_I2C_ACKNOWLEDGE. This feature can be modified afterwards using unitary function @ref LL_FMPI2C_AcknowledgeNextData(). */ uint32_t OwnAddrSize; /*!< Specifies the device own address 1 size (7-bit or 10-bit). - This parameter can be a value of @ref FMPI2C_LL_EC_OWNADDRESS1 + This parameter can be a value of @ref FMPI2C_LL_EC_OWNADDRESS1. This feature can be modified afterwards using unitary function @ref LL_FMPI2C_SetOwnAddress1(). */ } LL_FMPI2C_InitTypeDef; @@ -579,7 +579,7 @@ __STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledDMAReq_RX(FMPI2C_TypeDef *FMPI2Cx) */ __STATIC_INLINE uint32_t LL_FMPI2C_DMA_GetRegAddr(FMPI2C_TypeDef *FMPI2Cx, uint32_t Direction) { - register uint32_t data_reg_addr; + uint32_t data_reg_addr; if (Direction == LL_FMPI2C_DMA_REG_DATA_TRANSMIT) { @@ -903,7 +903,7 @@ __STATIC_INLINE uint32_t LL_FMPI2C_GetDataSetupTime(FMPI2C_TypeDef *FMPI2Cx) /** * @brief Configure peripheral mode. - * @note Macro @ref IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not + * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not * SMBus feature is supported by the FMPI2Cx Instance. * @rmtoll CR1 SMBHEN LL_FMPI2C_SetMode\n * CR1 SMBDEN LL_FMPI2C_SetMode @@ -922,7 +922,7 @@ __STATIC_INLINE void LL_FMPI2C_SetMode(FMPI2C_TypeDef *FMPI2Cx, uint32_t Periphe /** * @brief Get peripheral mode. - * @note Macro @ref IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not + * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not * SMBus feature is supported by the FMPI2Cx Instance. * @rmtoll CR1 SMBHEN LL_FMPI2C_GetMode\n * CR1 SMBDEN LL_FMPI2C_GetMode @@ -940,7 +940,7 @@ __STATIC_INLINE uint32_t LL_FMPI2C_GetMode(FMPI2C_TypeDef *FMPI2Cx) /** * @brief Enable SMBus alert (Host or Device mode) - * @note Macro @ref IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not + * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not * SMBus feature is supported by the FMPI2Cx Instance. * @note SMBus Device mode: * - SMBus Alert pin is drived low and @@ -958,7 +958,7 @@ __STATIC_INLINE void LL_FMPI2C_EnableSMBusAlert(FMPI2C_TypeDef *FMPI2Cx) /** * @brief Disable SMBus alert (Host or Device mode) - * @note Macro @ref IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not + * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not * SMBus feature is supported by the FMPI2Cx Instance. * @note SMBus Device mode: * - SMBus Alert pin is not drived (can be used as a standard GPIO) and @@ -976,7 +976,7 @@ __STATIC_INLINE void LL_FMPI2C_DisableSMBusAlert(FMPI2C_TypeDef *FMPI2Cx) /** * @brief Check if SMBus alert (Host or Device mode) is enabled or disabled. - * @note Macro @ref IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not + * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not * SMBus feature is supported by the FMPI2Cx Instance. * @rmtoll CR1 ALERTEN LL_FMPI2C_IsEnabledSMBusAlert * @param FMPI2Cx FMPI2C Instance. @@ -989,7 +989,7 @@ __STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledSMBusAlert(FMPI2C_TypeDef *FMPI2Cx) /** * @brief Enable SMBus Packet Error Calculation (PEC). - * @note Macro @ref IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not + * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not * SMBus feature is supported by the FMPI2Cx Instance. * @rmtoll CR1 PECEN LL_FMPI2C_EnableSMBusPEC * @param FMPI2Cx FMPI2C Instance. @@ -1002,7 +1002,7 @@ __STATIC_INLINE void LL_FMPI2C_EnableSMBusPEC(FMPI2C_TypeDef *FMPI2Cx) /** * @brief Disable SMBus Packet Error Calculation (PEC). - * @note Macro @ref IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not + * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not * SMBus feature is supported by the FMPI2Cx Instance. * @rmtoll CR1 PECEN LL_FMPI2C_DisableSMBusPEC * @param FMPI2Cx FMPI2C Instance. @@ -1015,7 +1015,7 @@ __STATIC_INLINE void LL_FMPI2C_DisableSMBusPEC(FMPI2C_TypeDef *FMPI2Cx) /** * @brief Check if SMBus Packet Error Calculation (PEC) is enabled or disabled. - * @note Macro @ref IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not + * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not * SMBus feature is supported by the FMPI2Cx Instance. * @rmtoll CR1 PECEN LL_FMPI2C_IsEnabledSMBusPEC * @param FMPI2Cx FMPI2C Instance. @@ -1028,7 +1028,7 @@ __STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledSMBusPEC(FMPI2C_TypeDef *FMPI2Cx) /** * @brief Configure the SMBus Clock Timeout. - * @note Macro @ref IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not + * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not * SMBus feature is supported by the FMPI2Cx Instance. * @note This configuration can only be programmed when associated Timeout is disabled (TimeoutA and/orTimeoutB). * @rmtoll TIMEOUTR TIMEOUTA LL_FMPI2C_ConfigSMBusTimeout\n @@ -1051,7 +1051,7 @@ __STATIC_INLINE void LL_FMPI2C_ConfigSMBusTimeout(FMPI2C_TypeDef *FMPI2Cx, uint3 /** * @brief Configure the SMBus Clock TimeoutA (SCL low timeout or SCL and SDA high timeout depends on TimeoutA mode). - * @note Macro @ref IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not + * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not * SMBus feature is supported by the FMPI2Cx Instance. * @note These bits can only be programmed when TimeoutA is disabled. * @rmtoll TIMEOUTR TIMEOUTA LL_FMPI2C_SetSMBusTimeoutA @@ -1066,7 +1066,7 @@ __STATIC_INLINE void LL_FMPI2C_SetSMBusTimeoutA(FMPI2C_TypeDef *FMPI2Cx, uint32_ /** * @brief Get the SMBus Clock TimeoutA setting. - * @note Macro @ref IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not + * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not * SMBus feature is supported by the FMPI2Cx Instance. * @rmtoll TIMEOUTR TIMEOUTA LL_FMPI2C_GetSMBusTimeoutA * @param FMPI2Cx FMPI2C Instance. @@ -1079,7 +1079,7 @@ __STATIC_INLINE uint32_t LL_FMPI2C_GetSMBusTimeoutA(FMPI2C_TypeDef *FMPI2Cx) /** * @brief Set the SMBus Clock TimeoutA mode. - * @note Macro @ref IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not + * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not * SMBus feature is supported by the FMPI2Cx Instance. * @note This bit can only be programmed when TimeoutA is disabled. * @rmtoll TIMEOUTR TIDLE LL_FMPI2C_SetSMBusTimeoutAMode @@ -1096,7 +1096,7 @@ __STATIC_INLINE void LL_FMPI2C_SetSMBusTimeoutAMode(FMPI2C_TypeDef *FMPI2Cx, uin /** * @brief Get the SMBus Clock TimeoutA mode. - * @note Macro @ref IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not + * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not * SMBus feature is supported by the FMPI2Cx Instance. * @rmtoll TIMEOUTR TIDLE LL_FMPI2C_GetSMBusTimeoutAMode * @param FMPI2Cx FMPI2C Instance. @@ -1111,7 +1111,7 @@ __STATIC_INLINE uint32_t LL_FMPI2C_GetSMBusTimeoutAMode(FMPI2C_TypeDef *FMPI2Cx) /** * @brief Configure the SMBus Extended Cumulative Clock TimeoutB (Master or Slave mode). - * @note Macro @ref IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not + * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not * SMBus feature is supported by the FMPI2Cx Instance. * @note These bits can only be programmed when TimeoutB is disabled. * @rmtoll TIMEOUTR TIMEOUTB LL_FMPI2C_SetSMBusTimeoutB @@ -1126,7 +1126,7 @@ __STATIC_INLINE void LL_FMPI2C_SetSMBusTimeoutB(FMPI2C_TypeDef *FMPI2Cx, uint32_ /** * @brief Get the SMBus Extented Cumulative Clock TimeoutB setting. - * @note Macro @ref IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not + * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not * SMBus feature is supported by the FMPI2Cx Instance. * @rmtoll TIMEOUTR TIMEOUTB LL_FMPI2C_GetSMBusTimeoutB * @param FMPI2Cx FMPI2C Instance. @@ -1139,7 +1139,7 @@ __STATIC_INLINE uint32_t LL_FMPI2C_GetSMBusTimeoutB(FMPI2C_TypeDef *FMPI2Cx) /** * @brief Enable the SMBus Clock Timeout. - * @note Macro @ref IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not + * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not * SMBus feature is supported by the FMPI2Cx Instance. * @rmtoll TIMEOUTR TIMOUTEN LL_FMPI2C_EnableSMBusTimeout\n * TIMEOUTR TEXTEN LL_FMPI2C_EnableSMBusTimeout @@ -1157,7 +1157,7 @@ __STATIC_INLINE void LL_FMPI2C_EnableSMBusTimeout(FMPI2C_TypeDef *FMPI2Cx, uint3 /** * @brief Disable the SMBus Clock Timeout. - * @note Macro @ref IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not + * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not * SMBus feature is supported by the FMPI2Cx Instance. * @rmtoll TIMEOUTR TIMOUTEN LL_FMPI2C_DisableSMBusTimeout\n * TIMEOUTR TEXTEN LL_FMPI2C_DisableSMBusTimeout @@ -1175,7 +1175,7 @@ __STATIC_INLINE void LL_FMPI2C_DisableSMBusTimeout(FMPI2C_TypeDef *FMPI2Cx, uint /** * @brief Check if the SMBus Clock Timeout is enabled or disabled. - * @note Macro @ref IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not + * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not * SMBus feature is supported by the FMPI2Cx Instance. * @rmtoll TIMEOUTR TIMOUTEN LL_FMPI2C_IsEnabledSMBusTimeout\n * TIMEOUTR TEXTEN LL_FMPI2C_IsEnabledSMBusTimeout @@ -1405,7 +1405,7 @@ __STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledIT_TC(FMPI2C_TypeDef *FMPI2Cx) /** * @brief Enable Error interrupts. - * @note Macro @ref IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not + * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not * SMBus feature is supported by the FMPI2Cx Instance. * @note Any of these errors will generate interrupt : * Arbitration Loss (ARLO) @@ -1425,7 +1425,7 @@ __STATIC_INLINE void LL_FMPI2C_EnableIT_ERR(FMPI2C_TypeDef *FMPI2Cx) /** * @brief Disable Error interrupts. - * @note Macro @ref IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not + * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not * SMBus feature is supported by the FMPI2Cx Instance. * @note Any of these errors will generate interrupt : * Arbitration Loss (ARLO) @@ -1607,7 +1607,7 @@ __STATIC_INLINE uint32_t LL_FMPI2C_IsActiveFlag_OVR(FMPI2C_TypeDef *FMPI2Cx) /** * @brief Indicate the status of SMBus PEC error flag in reception. - * @note Macro @ref IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not + * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not * SMBus feature is supported by the FMPI2Cx Instance. * @note RESET: Clear default value. * SET: When the received PEC does not match with the PEC register content. @@ -1622,7 +1622,7 @@ __STATIC_INLINE uint32_t LL_FMPI2C_IsActiveSMBusFlag_PECERR(FMPI2C_TypeDef *FMPI /** * @brief Indicate the status of SMBus Timeout detection flag. - * @note Macro @ref IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not + * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not * SMBus feature is supported by the FMPI2Cx Instance. * @note RESET: Clear default value. * SET: When a timeout or extended clock timeout occurs. @@ -1637,7 +1637,7 @@ __STATIC_INLINE uint32_t LL_FMPI2C_IsActiveSMBusFlag_TIMEOUT(FMPI2C_TypeDef *FMP /** * @brief Indicate the status of SMBus alert flag. - * @note Macro @ref IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not + * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not * SMBus feature is supported by the FMPI2Cx Instance. * @note RESET: Clear default value. * SET: When SMBus host configuration, SMBus alert enabled and @@ -1744,7 +1744,7 @@ __STATIC_INLINE void LL_FMPI2C_ClearFlag_OVR(FMPI2C_TypeDef *FMPI2Cx) /** * @brief Clear SMBus PEC error flag. - * @note Macro @ref IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not + * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not * SMBus feature is supported by the FMPI2Cx Instance. * @rmtoll ICR PECCF LL_FMPI2C_ClearSMBusFlag_PECERR * @param FMPI2Cx FMPI2C Instance. @@ -1757,7 +1757,7 @@ __STATIC_INLINE void LL_FMPI2C_ClearSMBusFlag_PECERR(FMPI2C_TypeDef *FMPI2Cx) /** * @brief Clear SMBus Timeout detection flag. - * @note Macro @ref IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not + * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not * SMBus feature is supported by the FMPI2Cx Instance. * @rmtoll ICR TIMOUTCF LL_FMPI2C_ClearSMBusFlag_TIMEOUT * @param FMPI2Cx FMPI2C Instance. @@ -1770,7 +1770,7 @@ __STATIC_INLINE void LL_FMPI2C_ClearSMBusFlag_TIMEOUT(FMPI2C_TypeDef *FMPI2Cx) /** * @brief Clear SMBus Alert flag. - * @note Macro @ref IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not + * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not * SMBus feature is supported by the FMPI2Cx Instance. * @rmtoll ICR ALERTCF LL_FMPI2C_ClearSMBusFlag_ALERT * @param FMPI2Cx FMPI2C Instance. @@ -2085,7 +2085,7 @@ __STATIC_INLINE uint32_t LL_FMPI2C_GetAddressMatchCode(FMPI2C_TypeDef *FMPI2Cx) /** * @brief Enable internal comparison of the SMBus Packet Error byte (transmission or reception mode). - * @note Macro @ref IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not + * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not * SMBus feature is supported by the FMPI2Cx Instance. * @note This feature is cleared by hardware when the PEC byte is transferred, or when a STOP condition or an Address Matched is received. * This bit has no effect when RELOAD bit is set. @@ -2101,7 +2101,7 @@ __STATIC_INLINE void LL_FMPI2C_EnableSMBusPECCompare(FMPI2C_TypeDef *FMPI2Cx) /** * @brief Check if the SMBus Packet Error byte internal comparison is requested or not. - * @note Macro @ref IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not + * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not * SMBus feature is supported by the FMPI2Cx Instance. * @rmtoll CR2 PECBYTE LL_FMPI2C_IsEnabledSMBusPECCompare * @param FMPI2Cx FMPI2C Instance. @@ -2114,7 +2114,7 @@ __STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledSMBusPECCompare(FMPI2C_TypeDef *FMPI /** * @brief Get the SMBus Packet Error byte calculated. - * @note Macro @ref IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not + * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not * SMBus feature is supported by the FMPI2Cx Instance. * @rmtoll PECR PEC LL_FMPI2C_GetSMBusPEC * @param FMPI2Cx FMPI2C Instance. diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_i2c.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_i2c.h index bc865ec..909f33c 100644 --- a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_i2c.h +++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_i2c.h @@ -837,8 +837,8 @@ __STATIC_INLINE uint32_t LL_I2C_GetClockPeriod(I2C_TypeDef *I2Cx) __STATIC_INLINE void LL_I2C_ConfigSpeed(I2C_TypeDef *I2Cx, uint32_t PeriphClock, uint32_t ClockSpeed, uint32_t DutyCycle) { - register uint32_t freqrange = 0x0U; - register uint32_t clockconfig = 0x0U; + uint32_t freqrange = 0x0U; + uint32_t clockconfig = 0x0U; /* Compute frequency range */ freqrange = __LL_I2C_FREQ_HZ_TO_MHZ(PeriphClock); diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h index b202528..c558cb5 100644 --- a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h +++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h @@ -81,7 +81,7 @@ typedef enum } USB_OTG_HCStateTypeDef; /** - * @brief USB OTG Initialization Structure definition + * @brief USB Instance Initialization Structure definition */ typedef struct { @@ -94,14 +94,14 @@ typedef struct This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ uint32_t speed; /*!< USB Core speed. - This parameter can be any value of @ref USB_Core_Speed_ */ + This parameter can be any value of @ref USB_Core_Speed */ uint32_t dma_enable; /*!< Enable or disable of the USB embedded DMA used only for OTG HS. */ uint32_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size. */ uint32_t phy_itface; /*!< Select the used PHY interface. - This parameter can be any value of @ref USB_Core_PHY_ */ + This parameter can be any value of @ref USB_Core_PHY */ uint32_t Sof_enable; /*!< Enable or disable the output of the SOF signal. */ @@ -116,6 +116,7 @@ typedef struct uint32_t use_dedicated_ep1; /*!< Enable or disable the use of the dedicated EP1 interrupt. */ uint32_t use_external_vbus; /*!< Enable or disable the use of the external VBUS. */ + } USB_OTG_CfgTypeDef; typedef struct @@ -197,13 +198,13 @@ typedef struct uint32_t dma_addr; /*!< 32 bits aligned transfer buffer address. */ - uint32_t ErrCnt; /*!< Host channel error count.*/ + uint32_t ErrCnt; /*!< Host channel error count. */ USB_OTG_URBStateTypeDef urb_state; /*!< URB state. This parameter can be any value of @ref USB_OTG_URBStateTypeDef */ USB_OTG_HCStateTypeDef state; /*!< Host Channel state. - This parameter can be any value of @ref USB_OTG_HCStateTypeDef */ + This parameter can be any value of @ref USB_OTG_HCStateTypeDef */ } USB_OTG_HCTypeDef; #endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ @@ -313,10 +314,10 @@ typedef struct /** @defgroup USB_LL_EP0_MPS USB Low Layer EP0 MPS * @{ */ -#define DEP0CTL_MPS_64 0U -#define DEP0CTL_MPS_32 1U -#define DEP0CTL_MPS_16 2U -#define DEP0CTL_MPS_8 3U +#define EP_MPS_64 0U +#define EP_MPS_32 1U +#define EP_MPS_16 2U +#define EP_MPS_8 3U /** * @} */ @@ -402,7 +403,7 @@ typedef struct #define USBx_HC(i) ((USB_OTG_HostChannelTypeDef *)(USBx_BASE + USB_OTG_HOST_CHANNEL_BASE + ((i) * USB_OTG_HOST_CHANNEL_SIZE))) #endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ -#define EP_ADDR_MSK 0xFU +#define EP_ADDR_MSK 0xFU /** * @} */ @@ -442,7 +443,9 @@ HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep); HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep, uint8_t dma); HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep, uint8_t dma); -HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len, uint8_t dma); +HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, + uint8_t ch_ep_num, uint16_t len, uint8_t dma); + void *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len); HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep); HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep); @@ -470,7 +473,9 @@ uint32_t USB_GetCurrentFrame(USB_OTG_GlobalTypeDef *USBx); HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num, uint8_t epnum, uint8_t dev_address, uint8_t speed, uint8_t ep_type, uint16_t mps); -HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDef *hc, uint8_t dma); +HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, + USB_OTG_HCTypeDef *hc, uint8_t dma); + uint32_t USB_HC_ReadInterrupt(USB_OTG_GlobalTypeDef *USBx); HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num); HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num); diff --git a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c index a27c14c..b9a4546 100644 --- a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c +++ b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c @@ -50,11 +50,11 @@ * @{ */ /** - * @brief STM32F4xx HAL Driver version number V1.7.8 + * @brief STM32F4xx HAL Driver version number V1.7.10 */ #define __STM32F4xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */ #define __STM32F4xx_HAL_VERSION_SUB1 (0x07U) /*!< [23:16] sub1 version */ -#define __STM32F4xx_HAL_VERSION_SUB2 (0x08U) /*!< [15:8] sub2 version */ +#define __STM32F4xx_HAL_VERSION_SUB2 (0x0AU) /*!< [15:8] sub2 version */ #define __STM32F4xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */ #define __STM32F4xx_HAL_VERSION ((__STM32F4xx_HAL_VERSION_MAIN << 24U)\ |(__STM32F4xx_HAL_VERSION_SUB1 << 16U)\ diff --git a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_fmpi2c.c b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_fmpi2c.c index 276bb57..2f88dba 100644 --- a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_fmpi2c.c +++ b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_fmpi2c.c @@ -5478,7 +5478,7 @@ static void FMPI2C_ITMasterCplt(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags) { uint32_t tmperror; uint32_t tmpITFlags = ITFlags; - uint32_t tmp; + __IO uint32_t tmpreg; /* Clear STOP Flag */ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF); @@ -5519,9 +5519,8 @@ static void FMPI2C_ITMasterCplt(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags) if ((hfmpi2c->State == HAL_FMPI2C_STATE_ABORT) && (FMPI2C_CHECK_FLAG(tmpITFlags, FMPI2C_FLAG_RXNE) != RESET)) { /* Read data from RXDR */ - tmp = (uint8_t)hfmpi2c->Instance->RXDR; - - UNUSED(tmp); + tmpreg = (uint8_t)hfmpi2c->Instance->RXDR; + UNUSED(tmpreg); } /* Flush TX register */ @@ -6190,8 +6189,14 @@ static void FMPI2C_DMAAbort(DMA_HandleTypeDef *hdma) FMPI2C_HandleTypeDef *hfmpi2c = (FMPI2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ /* Reset AbortCpltCallback */ - hfmpi2c->hdmatx->XferAbortCallback = NULL; - hfmpi2c->hdmarx->XferAbortCallback = NULL; + if (hfmpi2c->hdmatx != NULL) + { + hfmpi2c->hdmatx->XferAbortCallback = NULL; + } + if (hfmpi2c->hdmarx != NULL) + { + hfmpi2c->hdmarx->XferAbortCallback = NULL; + } FMPI2C_TreatErrorCallback(hfmpi2c); } diff --git a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_fmpsmbus.c b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_fmpsmbus.c index 9305aba..5274bf9 100644 --- a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_fmpsmbus.c +++ b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_fmpsmbus.c @@ -204,18 +204,18 @@ /** @addtogroup FMPSMBUS_Private_Functions FMPSMBUS Private Functions * @{ */ -static HAL_StatusTypeDef FMPSMBUS_WaitOnFlagUntilTimeout(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus, uint32_t Flag, FlagStatus Status, uint32_t Timeout); +static HAL_StatusTypeDef FMPSMBUS_WaitOnFlagUntilTimeout(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint32_t Flag, FlagStatus Status, uint32_t Timeout); -static void FMPSMBUS_Enable_IRQ(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus, uint32_t InterruptRequest); -static void FMPSMBUS_Disable_IRQ(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus, uint32_t InterruptRequest); -static HAL_StatusTypeDef FMPSMBUS_Master_ISR(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus, uint32_t StatusFlags); -static HAL_StatusTypeDef FMPSMBUS_Slave_ISR(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus, uint32_t StatusFlags); +static void FMPSMBUS_Enable_IRQ(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint32_t InterruptRequest); +static void FMPSMBUS_Disable_IRQ(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint32_t InterruptRequest); +static HAL_StatusTypeDef FMPSMBUS_Master_ISR(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint32_t StatusFlags); +static HAL_StatusTypeDef FMPSMBUS_Slave_ISR(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint32_t StatusFlags); -static void FMPSMBUS_ConvertOtherXferOptions(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus); +static void FMPSMBUS_ConvertOtherXferOptions(FMPSMBUS_HandleTypeDef *hfmpsmbus); -static void FMPSMBUS_ITErrorHandler(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus); +static void FMPSMBUS_ITErrorHandler(FMPSMBUS_HandleTypeDef *hfmpsmbus); -static void FMPSMBUS_TransferConfig(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request); +static void FMPSMBUS_TransferConfig(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request); /** * @} */ @@ -1802,7 +1802,7 @@ uint32_t HAL_FMPSMBUS_GetError(FMPSMBUS_HandleTypeDef *hfmpsmbus) * @param StatusFlags Value of Interrupt Flags. * @retval HAL status */ -static HAL_StatusTypeDef FMPSMBUS_Master_ISR(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus, uint32_t StatusFlags) +static HAL_StatusTypeDef FMPSMBUS_Master_ISR(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint32_t StatusFlags) { uint16_t DevAddress; @@ -2086,7 +2086,7 @@ static HAL_StatusTypeDef FMPSMBUS_Master_ISR(struct __FMPSMBUS_HandleTypeDef *hf * @param StatusFlags Value of Interrupt Flags. * @retval HAL status */ -static HAL_StatusTypeDef FMPSMBUS_Slave_ISR(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus, uint32_t StatusFlags) +static HAL_StatusTypeDef FMPSMBUS_Slave_ISR(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint32_t StatusFlags) { uint8_t TransferDirection; uint16_t SlaveAddrCode; @@ -2342,7 +2342,7 @@ static HAL_StatusTypeDef FMPSMBUS_Slave_ISR(struct __FMPSMBUS_HandleTypeDef *hfm * @param InterruptRequest Value of @ref FMPSMBUS_Interrupt_configuration_definition. * @retval HAL status */ -static void FMPSMBUS_Enable_IRQ(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus, uint32_t InterruptRequest) +static void FMPSMBUS_Enable_IRQ(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint32_t InterruptRequest) { uint32_t tmpisr = 0UL; @@ -2382,7 +2382,7 @@ static void FMPSMBUS_Enable_IRQ(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus, uint * @param InterruptRequest Value of @ref FMPSMBUS_Interrupt_configuration_definition. * @retval HAL status */ -static void FMPSMBUS_Disable_IRQ(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus, uint32_t InterruptRequest) +static void FMPSMBUS_Disable_IRQ(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint32_t InterruptRequest) { uint32_t tmpisr = 0UL; uint32_t tmpstate = hfmpsmbus->State; @@ -2454,7 +2454,7 @@ static void FMPSMBUS_Disable_IRQ(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus, uin * @param hfmpsmbus FMPSMBUS handle. * @retval None */ -static void FMPSMBUS_ITErrorHandler(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus) +static void FMPSMBUS_ITErrorHandler(FMPSMBUS_HandleTypeDef *hfmpsmbus) { uint32_t itflags = READ_REG(hfmpsmbus->Instance->ISR); uint32_t itsources = READ_REG(hfmpsmbus->Instance->CR1); @@ -2555,7 +2555,7 @@ static void FMPSMBUS_ITErrorHandler(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus) * @param Timeout Timeout duration * @retval HAL status */ -static HAL_StatusTypeDef FMPSMBUS_WaitOnFlagUntilTimeout(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus, uint32_t Flag, FlagStatus Status, uint32_t Timeout) +static HAL_StatusTypeDef FMPSMBUS_WaitOnFlagUntilTimeout(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint32_t Flag, FlagStatus Status, uint32_t Timeout) { uint32_t tickstart = HAL_GetTick(); @@ -2604,7 +2604,7 @@ static HAL_StatusTypeDef FMPSMBUS_WaitOnFlagUntilTimeout(struct __FMPSMBUS_Handl * @arg @ref FMPSMBUS_GENERATE_START_WRITE Generate Restart for write request. * @retval None */ -static void FMPSMBUS_TransferConfig(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request) +static void FMPSMBUS_TransferConfig(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request) { /* Check the parameters */ assert_param(IS_FMPSMBUS_ALL_INSTANCE(hfmpsmbus->Instance)); @@ -2621,7 +2621,7 @@ static void FMPSMBUS_TransferConfig(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus, * @param hfmpsmbus FMPSMBUS handle. * @retval None */ -static void FMPSMBUS_ConvertOtherXferOptions(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus) +static void FMPSMBUS_ConvertOtherXferOptions(FMPSMBUS_HandleTypeDef *hfmpsmbus) { /* if user set XferOptions to FMPSMBUS_OTHER_FRAME_NO_PEC */ /* it request implicitly to generate a restart condition */ diff --git a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_hcd.c b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_hcd.c index aee8ac7..29b0c0a 100644 --- a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_hcd.c +++ b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_hcd.c @@ -91,8 +91,8 @@ static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd); */ /** @defgroup HCD_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * + * @brief Initialization and Configuration functions + * @verbatim =============================================================================== ##### Initialization and de-initialization functions ##### @@ -599,6 +599,18 @@ void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd) } } + +/** + * @brief Handles HCD Wakeup interrupt request. + * @param hhcd HCD handle + * @retval HAL status + */ +void HAL_HCD_WKUP_IRQHandler(HCD_HandleTypeDef *hhcd) +{ + UNUSED(hhcd); +} + + /** * @brief SOF callback. * @param hhcd HCD handle @@ -718,7 +730,9 @@ __weak void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd, uint8_t * @param pCallback pointer to the Callback function * @retval HAL status */ -HAL_StatusTypeDef HAL_HCD_RegisterCallback(HCD_HandleTypeDef *hhcd, HAL_HCD_CallbackIDTypeDef CallbackID, pHCD_CallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_HCD_RegisterCallback(HCD_HandleTypeDef *hhcd, + HAL_HCD_CallbackIDTypeDef CallbackID, + pHCD_CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; @@ -806,7 +820,7 @@ HAL_StatusTypeDef HAL_HCD_RegisterCallback(HCD_HandleTypeDef *hhcd, HAL_HCD_Call /** * @brief Unregister an USB HCD Callback - * USB HCD callabck is redirected to the weak predefined callback + * USB HCD callback is redirected to the weak predefined callback * @param hhcd USB HCD handle * @param CallbackID ID of the callback to be unregistered * This parameter can be one of the following values: @@ -910,7 +924,8 @@ HAL_StatusTypeDef HAL_HCD_UnRegisterCallback(HCD_HandleTypeDef *hhcd, HAL_HCD_Ca * @param pCallback pointer to the USB HCD Host Channel Notify URB Change Callback function * @retval HAL status */ -HAL_StatusTypeDef HAL_HCD_RegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef *hhcd, pHCD_HC_NotifyURBChangeCallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_HCD_RegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef *hhcd, + pHCD_HC_NotifyURBChangeCallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; @@ -945,7 +960,7 @@ HAL_StatusTypeDef HAL_HCD_RegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef * } /** - * @brief UnRegister the USB HCD Host Channel Notify URB Change Callback + * @brief Unregister the USB HCD Host Channel Notify URB Change Callback * USB HCD Host Channel Notify URB Change Callback is redirected to the weak HAL_HCD_HC_NotifyURBChange_Callback() predefined callback * @param hhcd HCD handle * @retval HAL status @@ -982,8 +997,8 @@ HAL_StatusTypeDef HAL_HCD_UnRegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef */ /** @defgroup HCD_Exported_Functions_Group3 Peripheral Control functions - * @brief Management functions - * + * @brief Management functions + * @verbatim =============================================================================== ##### Peripheral Control functions ##### @@ -1041,8 +1056,8 @@ HAL_StatusTypeDef HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd) */ /** @defgroup HCD_Exported_Functions_Group4 Peripheral State functions - * @brief Peripheral State functions - * + * @brief Peripheral State functions + * @verbatim =============================================================================== ##### Peripheral State functions ##### diff --git a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c index 8bb8416..5c6932b 100644 --- a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c +++ b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c @@ -319,6 +319,7 @@ */ #define I2C_TIMEOUT_FLAG 35U /*!< Timeout 35 ms */ #define I2C_TIMEOUT_BUSY_FLAG 25U /*!< Timeout 25 ms */ +#define I2C_TIMEOUT_STOP_FLAG 5U /*!< Timeout 5 ms */ #define I2C_NO_OPTION_FRAME 0xFFFF0000U /*!< XferOptions default value */ /* Private define for @ref PreviousState usage */ @@ -359,6 +360,7 @@ static HAL_StatusTypeDef I2C_WaitOnTXEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, static HAL_StatusTypeDef I2C_WaitOnBTFFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef I2C_WaitOnSTOPRequestThroughIT(I2C_HandleTypeDef *hi2c); static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c); /* Private functions for I2C transfer IRQ handler */ @@ -3040,6 +3042,27 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd /* Send Slave Address and Memory Address */ if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) { + /* Abort the ongoing DMA */ + dmaxferstatus = HAL_DMA_Abort_IT(hi2c->hdmatx); + + /* Prevent unused argument(s) compilation and MISRA warning */ + UNUSED(dmaxferstatus); + + /* Clear directly Complete callback as no XferAbortCallback is used to finalize Abort treatment */ + if (hi2c->hdmatx != NULL) + { + hi2c->hdmatx->XferCpltCallback = NULL; + } + + /* Disable Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + hi2c->XferSize = 0U; + hi2c->XferCount = 0U; + + /* Disable I2C peripheral to prevent dummy data in buffer */ + __HAL_I2C_DISABLE(hi2c); + return HAL_ERROR; } @@ -3185,6 +3208,27 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr /* Send Slave Address and Memory Address */ if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) { + /* Abort the ongoing DMA */ + dmaxferstatus = HAL_DMA_Abort_IT(hi2c->hdmarx); + + /* Prevent unused argument(s) compilation and MISRA warning */ + UNUSED(dmaxferstatus); + + /* Clear directly Complete callback as no XferAbortCallback is used to finalize Abort treatment */ + if (hi2c->hdmarx != NULL) + { + hi2c->hdmarx->XferCpltCallback = NULL; + } + + /* Disable Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + hi2c->XferSize = 0U; + hi2c->XferCount = 0U; + + /* Disable I2C peripheral to prevent dummy data in buffer */ + __HAL_I2C_DISABLE(hi2c); + return HAL_ERROR; } @@ -3309,7 +3353,7 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd /* Wait until SB flag is set */ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, tickstart) != HAL_OK) { - if (hi2c->Instance->CR1 & I2C_CR1_START) + if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START) { hi2c->ErrorCode = HAL_I2C_WRONG_START; } @@ -3415,7 +3459,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16 if (hi2c->State == HAL_I2C_STATE_READY) { /* Check Busy Flag only if FIRST call of Master interface */ - if ((XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME)) + if ((READ_BIT(hi2c->Instance->CR1, I2C_CR1_STOP) == I2C_CR1_STOP) || (XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME)) { /* Wait until BUSY flag is reset */ count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U); @@ -3514,7 +3558,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint1 if (hi2c->State == HAL_I2C_STATE_READY) { /* Check Busy Flag only if FIRST call of Master interface */ - if ((XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME)) + if ((READ_BIT(hi2c->Instance->CR1, I2C_CR1_STOP) == I2C_CR1_STOP) || (XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME)) { /* Wait until BUSY flag is reset */ count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U); @@ -3680,7 +3724,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_ if (hi2c->State == HAL_I2C_STATE_READY) { /* Check Busy Flag only if FIRST call of Master interface */ - if ((XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME)) + if ((READ_BIT(hi2c->Instance->CR1, I2C_CR1_STOP) == I2C_CR1_STOP) || (XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME)) { /* Wait until BUSY flag is reset */ count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U); @@ -3805,7 +3849,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16 if (hi2c->State == HAL_I2C_STATE_READY) { /* Check Busy Flag only if FIRST call of Master interface */ - if ((XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME)) + if ((READ_BIT(hi2c->Instance->CR1, I2C_CR1_STOP) == I2C_CR1_STOP) || (XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME)) { /* Wait until BUSY flag is reset */ count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U); @@ -4507,11 +4551,14 @@ HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c) */ HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress) { + /* Declaration of temporary variables to prevent undefined behavior of volatile usage */ + HAL_I2C_ModeTypeDef CurrentMode = hi2c->Mode; + /* Prevent unused argument(s) compilation warning */ UNUSED(DevAddress); /* Abort Master transfer during Receive or Transmit process */ - if (hi2c->Mode == HAL_I2C_MODE_MASTER) + if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET) && (CurrentMode == HAL_I2C_MODE_MASTER)) { /* Process Locked */ __HAL_LOCK(hi2c); @@ -4542,6 +4589,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevA { /* Wrong usage of abort function */ /* This function should be used only in case of abort monitored by master device */ + /* Or periphal is not in busy state, mean there is no active sequence to be abort */ return HAL_ERROR; } } @@ -4613,7 +4661,14 @@ void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c) /* BTF set -------------------------------------------------------------*/ else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET)) { - I2C_MasterTransmit_BTF(hi2c); + if (CurrentMode == HAL_I2C_MODE_MASTER) + { + I2C_MasterTransmit_BTF(hi2c); + } + else /* HAL_I2C_MODE_MEM */ + { + I2C_MemoryTransmit_TXE_BTF(hi2c); + } } else { @@ -5166,33 +5221,16 @@ static void I2C_MasterTransmit_BTF(I2C_HandleTypeDef *hi2c) hi2c->PreviousState = I2C_STATE_NONE; hi2c->State = HAL_I2C_STATE_READY; - - if (hi2c->Mode == HAL_I2C_MODE_MEM) - { - hi2c->Mode = HAL_I2C_MODE_NONE; -#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) - hi2c->MemTxCpltCallback(hi2c); -#else - HAL_I2C_MemTxCpltCallback(hi2c); -#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ - } - else - { - hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->Mode = HAL_I2C_MODE_NONE; #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) - hi2c->MasterTxCpltCallback(hi2c); + hi2c->MasterTxCpltCallback(hi2c); #else - HAL_I2C_MasterTxCpltCallback(hi2c); + HAL_I2C_MasterTxCpltCallback(hi2c); #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ - } } } } - else if (hi2c->Mode == HAL_I2C_MODE_MEM) - { - I2C_MemoryTransmit_TXE_BTF(hi2c); - } else { /* Do nothing */ @@ -5207,6 +5245,9 @@ static void I2C_MasterTransmit_BTF(I2C_HandleTypeDef *hi2c) */ static void I2C_MemoryTransmit_TXE_BTF(I2C_HandleTypeDef *hi2c) { + /* Declaration of temporary variables to prevent undefined behavior of volatile usage */ + HAL_I2C_StateTypeDef CurrentState = hi2c->State; + if (hi2c->EventCount == 0U) { /* If Memory address size is 8Bit */ @@ -5235,12 +5276,12 @@ static void I2C_MemoryTransmit_TXE_BTF(I2C_HandleTypeDef *hi2c) } else if (hi2c->EventCount == 2U) { - if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + if (CurrentState == HAL_I2C_STATE_BUSY_RX) { /* Generate Restart */ hi2c->Instance->CR1 |= I2C_CR1_START; } - else if (hi2c->State == HAL_I2C_STATE_BUSY_TX) + else if ((hi2c->XferCount > 0U) && (CurrentState == HAL_I2C_STATE_BUSY_TX)) { /* Write data to DR */ hi2c->Instance->DR = *hi2c->pBuffPtr; @@ -5251,6 +5292,24 @@ static void I2C_MemoryTransmit_TXE_BTF(I2C_HandleTypeDef *hi2c) /* Update counter */ hi2c->XferCount--; } + else if ((hi2c->XferCount == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_TX)) + { + /* Generate Stop condition then Call TxCpltCallback() */ + /* Disable EVT, BUF and ERR interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->MemTxCpltCallback(hi2c); +#else + HAL_I2C_MemTxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } else { /* Do nothing */ @@ -5296,43 +5355,70 @@ static void I2C_MasterReceive_RXNE(I2C_HandleTypeDef *hi2c) } else if ((hi2c->XferOptions != I2C_FIRST_AND_NEXT_FRAME) && ((tmp == 1U) || (tmp == 0U))) { - /* Disable Acknowledge */ - CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); - - /* Disable EVT, BUF and ERR interrupt */ - __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); - - /* Read data from DR */ - *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; - - /* Increment Buffer pointer */ - hi2c->pBuffPtr++; - - /* Update counter */ - hi2c->XferCount--; - - hi2c->State = HAL_I2C_STATE_READY; - - if (hi2c->Mode == HAL_I2C_MODE_MEM) + if (I2C_WaitOnSTOPRequestThroughIT(hi2c) == HAL_OK) { - hi2c->Mode = HAL_I2C_MODE_NONE; - hi2c->PreviousState = I2C_STATE_NONE; + /* Disable Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Disable EVT, BUF and ERR interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + /* Read data from DR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferCount--; + + hi2c->State = HAL_I2C_STATE_READY; + + if (hi2c->Mode == HAL_I2C_MODE_MEM) + { + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->PreviousState = I2C_STATE_NONE; #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) - hi2c->MemRxCpltCallback(hi2c); + hi2c->MemRxCpltCallback(hi2c); #else - HAL_I2C_MemRxCpltCallback(hi2c); + HAL_I2C_MemRxCpltCallback(hi2c); #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + else + { + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; + +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->MasterRxCpltCallback(hi2c); +#else + HAL_I2C_MasterRxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } } else { - hi2c->Mode = HAL_I2C_MODE_NONE; - hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; + /* Disable EVT, BUF and ERR interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + /* Read data from DR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferCount--; + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Call user error callback */ #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) - hi2c->MasterRxCpltCallback(hi2c); + hi2c->ErrorCallback(hi2c); #else - HAL_I2C_MasterRxCpltCallback(hi2c); + HAL_I2C_ErrorCallback(hi2c); #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ } } @@ -6117,9 +6203,10 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c) { /* Declaration of temporary variable to prevent undefined behavior of volatile usage */ HAL_I2C_StateTypeDef CurrentState = hi2c->State; + HAL_I2C_ModeTypeDef CurrentMode = hi2c->Mode; uint32_t CurrentError; - if ((hi2c->Mode == HAL_I2C_MODE_MASTER) && (CurrentState == HAL_I2C_STATE_BUSY_RX)) + if (((CurrentMode == HAL_I2C_MODE_MASTER) || (CurrentMode == HAL_I2C_MODE_MEM)) && (CurrentState == HAL_I2C_STATE_BUSY_RX)) { /* Disable Pos bit in I2C CR1 when error occurred in Master/Mem Receive IT Process */ hi2c->Instance->CR1 &= ~I2C_CR1_POS; @@ -6138,9 +6225,9 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c) if ((READ_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN) != I2C_CR2_DMAEN) && (CurrentState != HAL_I2C_STATE_ABORT)) { hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; } hi2c->PreviousState = I2C_STATE_NONE; - hi2c->Mode = HAL_I2C_MODE_NONE; } /* Abort DMA transfer */ @@ -6302,7 +6389,7 @@ static HAL_StatusTypeDef I2C_MasterRequestWrite(I2C_HandleTypeDef *hi2c, uint16_ /* Wait until SB flag is set */ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK) { - if (hi2c->Instance->CR1 & I2C_CR1_START) + if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START) { hi2c->ErrorCode = HAL_I2C_WRONG_START; } @@ -6375,7 +6462,7 @@ static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t /* Wait until SB flag is set */ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK) { - if (hi2c->Instance->CR1 & I2C_CR1_START) + if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START) { hi2c->ErrorCode = HAL_I2C_WRONG_START; } @@ -6416,7 +6503,7 @@ static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t /* Wait until SB flag is set */ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK) { - if (hi2c->Instance->CR1 & I2C_CR1_START) + if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START) { hi2c->ErrorCode = HAL_I2C_WRONG_START; } @@ -6456,7 +6543,7 @@ static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_ /* Wait until SB flag is set */ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK) { - if (hi2c->Instance->CR1 & I2C_CR1_START) + if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START) { hi2c->ErrorCode = HAL_I2C_WRONG_START; } @@ -6539,7 +6626,7 @@ static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t /* Wait until SB flag is set */ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK) { - if (hi2c->Instance->CR1 & I2C_CR1_START) + if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START) { hi2c->ErrorCode = HAL_I2C_WRONG_START; } @@ -6613,7 +6700,7 @@ static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t /* Wait until SB flag is set */ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK) { - if (hi2c->Instance->CR1 & I2C_CR1_START) + if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START) { hi2c->ErrorCode = HAL_I2C_WRONG_START; } @@ -6818,11 +6905,26 @@ static void I2C_DMAError(DMA_HandleTypeDef *hdma) */ static void I2C_DMAAbort(DMA_HandleTypeDef *hdma) { + __IO uint32_t count = 0U; I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */ /* Declaration of temporary variable to prevent undefined behavior of volatile usage */ HAL_I2C_StateTypeDef CurrentState = hi2c->State; + /* During abort treatment, check that there is no pending STOP request */ + /* Wait until STOP flag is reset */ + count = I2C_TIMEOUT_FLAG * (SystemCoreClock / 25U / 1000U); + do + { + if (count == 0U) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + break; + } + count--; + } + while (READ_BIT(hi2c->Instance->CR1, I2C_CR1_STOP) == I2C_CR1_STOP); + /* Clear Complete callback */ if (hi2c->hdmatx != NULL) { @@ -7092,6 +7194,33 @@ static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, return HAL_OK; } +/** + * @brief This function handles I2C Communication Timeout for specific usage of STOP request through Interrupt. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_WaitOnSTOPRequestThroughIT(I2C_HandleTypeDef *hi2c) +{ + __IO uint32_t count = 0U; + + /* Wait until STOP flag is reset */ + count = I2C_TIMEOUT_STOP_FLAG * (SystemCoreClock / 25U / 1000U); + do + { + count--; + if (count == 0U) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + + return HAL_ERROR; + } + } + while (READ_BIT(hi2c->Instance->CR1, I2C_CR1_STOP) == I2C_CR1_STOP); + + return HAL_OK; +} + /** * @brief This function handles I2C Communication Timeout for specific usage of RXNE flag. * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains diff --git a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c index 0725f4c..b3eaf4b 100644 --- a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c +++ b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c @@ -102,8 +102,8 @@ static HAL_StatusTypeDef PCD_EP_OutSetupPacket_int(PCD_HandleTypeDef *hpcd, uint */ /** @defgroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * + * @brief Initialization and Configuration functions + * @verbatim =============================================================================== ##### Initialization and de-initialization functions ##### @@ -230,7 +230,7 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd) { (void)HAL_PCDEx_ActivateLPM(hpcd); } - #endif /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) */ +#endif /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) */ (void)USB_DevDisconnect(hpcd->Instance); return HAL_OK; @@ -252,7 +252,10 @@ HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd) hpcd->State = HAL_PCD_STATE_BUSY; /* Stop Device */ - (void)HAL_PCD_Stop(hpcd); + if (USB_StopDevice(hpcd->Instance) != HAL_OK) + { + return HAL_ERROR; + } #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) if (hpcd->MspDeInitCallback == NULL) @@ -321,7 +324,9 @@ __weak void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd) * @param pCallback pointer to the Callback function * @retval HAL status */ -HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID, pPCD_CallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd, + HAL_PCD_CallbackIDTypeDef CallbackID, + pPCD_CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; @@ -531,7 +536,8 @@ HAL_StatusTypeDef HAL_PCD_UnRegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_Ca * @param pCallback pointer to the USB PCD Data OUT Stage Callback function * @retval HAL status */ -HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd, pPCD_DataOutStageCallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd, + pPCD_DataOutStageCallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; @@ -566,7 +572,7 @@ HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd, } /** - * @brief UnRegister the USB PCD Data OUT Stage Callback + * @brief Unregister the USB PCD Data OUT Stage Callback * USB PCD Data OUT Stage Callback is redirected to the weak HAL_PCD_DataOutStageCallback() predefined callback * @param hpcd PCD handle * @retval HAL status @@ -604,7 +610,8 @@ HAL_StatusTypeDef HAL_PCD_UnRegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd * @param pCallback pointer to the USB PCD Data IN Stage Callback function * @retval HAL status */ -HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(PCD_HandleTypeDef *hpcd, pPCD_DataInStageCallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(PCD_HandleTypeDef *hpcd, + pPCD_DataInStageCallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; @@ -639,7 +646,7 @@ HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(PCD_HandleTypeDef *hpcd, p } /** - * @brief UnRegister the USB PCD Data IN Stage Callback + * @brief Unregister the USB PCD Data IN Stage Callback * USB PCD Data OUT Stage Callback is redirected to the weak HAL_PCD_DataInStageCallback() predefined callback * @param hpcd PCD handle * @retval HAL status @@ -677,7 +684,8 @@ HAL_StatusTypeDef HAL_PCD_UnRegisterDataInStageCallback(PCD_HandleTypeDef *hpcd) * @param pCallback pointer to the USB PCD Iso OUT incomplete Callback function * @retval HAL status */ -HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd, pPCD_IsoOutIncpltCallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd, + pPCD_IsoOutIncpltCallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; @@ -712,7 +720,7 @@ HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd, } /** - * @brief UnRegister the USB PCD Iso OUT incomplete Callback + * @brief Unregister the USB PCD Iso OUT incomplete Callback * USB PCD Iso OUT incomplete Callback is redirected to the weak HAL_PCD_ISOOUTIncompleteCallback() predefined callback * @param hpcd PCD handle * @retval HAL status @@ -750,7 +758,8 @@ HAL_StatusTypeDef HAL_PCD_UnRegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd * @param pCallback pointer to the USB PCD Iso IN incomplete Callback function * @retval HAL status */ -HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd, pPCD_IsoInIncpltCallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd, + pPCD_IsoInIncpltCallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; @@ -785,7 +794,7 @@ HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd, p } /** - * @brief UnRegister the USB PCD Iso IN incomplete Callback + * @brief Unregister the USB PCD Iso IN incomplete Callback * USB PCD Iso IN incomplete Callback is redirected to the weak HAL_PCD_ISOINIncompleteCallback() predefined callback * @param hpcd PCD handle * @retval HAL status @@ -858,7 +867,7 @@ HAL_StatusTypeDef HAL_PCD_RegisterBcdCallback(PCD_HandleTypeDef *hpcd, pPCD_BcdC } /** - * @brief UnRegister the USB PCD BCD Callback + * @brief Unregister the USB PCD BCD Callback * USB BCD Callback is redirected to the weak HAL_PCDEx_BCD_Callback() predefined callback * @param hpcd PCD handle * @retval HAL status @@ -931,7 +940,7 @@ HAL_StatusTypeDef HAL_PCD_RegisterLpmCallback(PCD_HandleTypeDef *hpcd, pPCD_LpmC } /** - * @brief UnRegister the USB PCD LPM Callback + * @brief Unregister the USB PCD LPM Callback * USB LPM Callback is redirected to the weak HAL_PCDEx_LPM_Callback() predefined callback * @param hpcd PCD handle * @retval HAL status @@ -968,8 +977,8 @@ HAL_StatusTypeDef HAL_PCD_UnRegisterLpmCallback(PCD_HandleTypeDef *hpcd) */ /** @defgroup PCD_Exported_Functions_Group2 Input and Output operation functions - * @brief Data transfers functions - * + * @brief Data transfers functions + * @verbatim =============================================================================== ##### IO operation functions ##### @@ -989,22 +998,21 @@ HAL_StatusTypeDef HAL_PCD_UnRegisterLpmCallback(PCD_HandleTypeDef *hpcd) */ HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd) { -#if defined (USB_OTG_FS) || defined (USB_OTG_HS) USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; -#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ __HAL_LOCK(hpcd); -#if defined (USB_OTG_FS) || defined (USB_OTG_HS) + if ((hpcd->Init.battery_charging_enable == 1U) && (hpcd->Init.phy_itface != USB_OTG_ULPI_PHY)) { /* Enable USB Transceiver */ USBx->GCCFG |= USB_OTG_GCCFG_PWRDWN; } -#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ - (void)USB_DevConnect(hpcd->Instance); + __HAL_PCD_ENABLE(hpcd); + (void)USB_DevConnect(hpcd->Instance); __HAL_UNLOCK(hpcd); + return HAL_OK; } @@ -1015,20 +1023,25 @@ HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd) */ HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd) { + USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; + __HAL_LOCK(hpcd); __HAL_PCD_DISABLE(hpcd); - - if (USB_StopDevice(hpcd->Instance) != HAL_OK) - { - __HAL_UNLOCK(hpcd); - return HAL_ERROR; - } - (void)USB_DevDisconnect(hpcd->Instance); + + (void)USB_FlushTxFifo(hpcd->Instance, 0x10U); + + if ((hpcd->Init.battery_charging_enable == 1U) && + (hpcd->Init.phy_itface != USB_OTG_ULPI_PHY)) + { + /* Disable USB Transceiver */ + USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN); + } __HAL_UNLOCK(hpcd); return HAL_OK; } + #if defined (USB_OTG_FS) || defined (USB_OTG_HS) /** * @brief Handles PCD interrupt request. @@ -1058,7 +1071,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_MMIS); } - /* Handle RxQLevel Interrupt */ + /* Handle RxQLevel Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_RXFLVL)) { USB_MASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL); @@ -1243,7 +1256,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) } __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP); } - #if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) +#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) /* Handle LPM Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_LPMINT)) { @@ -1269,7 +1282,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } } - #endif /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) */ +#endif /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) */ /* Handle Reset Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBRST)) { @@ -1413,6 +1426,30 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) } } } + + +/** + * @brief Handles PCD Wakeup interrupt request. + * @param hpcd PCD handle + * @retval HAL status + */ +void HAL_PCD_WKUP_IRQHandler(PCD_HandleTypeDef *hpcd) +{ + USB_OTG_GlobalTypeDef *USBx; + + USBx = hpcd->Instance; + + if ((USBx->CID & (0x1U << 8)) == 0U) + { + /* Clear EXTI pending Bit */ + __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG(); + } + else + { + /* Clear EXTI pending Bit */ + __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG(); + } +} #endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ @@ -1593,8 +1630,8 @@ __weak void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd) */ /** @defgroup PCD_Exported_Functions_Group3 Peripheral Control functions - * @brief management functions - * + * @brief management functions + * @verbatim =============================================================================== ##### Peripheral Control functions ##### @@ -1629,6 +1666,7 @@ HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd) #endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ (void)USB_DevConnect(hpcd->Instance); __HAL_UNLOCK(hpcd); + return HAL_OK; } @@ -1639,9 +1677,24 @@ HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd) */ HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd) { +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) + USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ + __HAL_LOCK(hpcd); (void)USB_DevDisconnect(hpcd->Instance); + +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) + if ((hpcd->Init.battery_charging_enable == 1U) && + (hpcd->Init.phy_itface != USB_OTG_ULPI_PHY)) + { + /* Disable USB Transceiver */ + USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN); + } +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ + __HAL_UNLOCK(hpcd); + return HAL_OK; } @@ -1657,6 +1710,7 @@ HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address) hpcd->USB_Address = address; (void)USB_SetDevAddress(hpcd->Instance, address); __HAL_UNLOCK(hpcd); + return HAL_OK; } /** @@ -1667,7 +1721,8 @@ HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address) * @param ep_type endpoint type * @retval HAL status */ -HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type) +HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, + uint16_t ep_mps, uint8_t ep_type) { HAL_StatusTypeDef ret = HAL_OK; PCD_EPTypeDef *ep; @@ -1852,10 +1907,12 @@ HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) __HAL_LOCK(hpcd); (void)USB_EPSetStall(hpcd->Instance, ep); + if ((ep_addr & EP_ADDR_MSK) == 0U) { (void)USB_EP0_OutStart(hpcd->Instance, (uint8_t)hpcd->Init.dma_enable, (uint8_t *)hpcd->Setup); } + __HAL_UNLOCK(hpcd); return HAL_OK; @@ -1946,8 +2003,8 @@ HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd) */ /** @defgroup PCD_Exported_Functions_Group4 Peripheral State functions - * @brief Peripheral State functions - * + * @brief Peripheral State functions + * @verbatim =============================================================================== ##### Peripheral State functions ##### diff --git a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.c b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.c index 269fce7..56e1d3b 100644 --- a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.c +++ b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.c @@ -49,7 +49,7 @@ /** @defgroup PCDEx_Exported_Functions_Group1 Peripheral Control functions * @brief PCDEx control functions - * + * @verbatim =============================================================================== ##### Extended features functions ##### @@ -260,7 +260,7 @@ HAL_StatusTypeDef HAL_PCDEx_ActivateBCD(PCD_HandleTypeDef *hpcd) USBx->GCCFG &= ~(USB_OTG_GCCFG_PDEN); USBx->GCCFG &= ~(USB_OTG_GCCFG_SDEN); - /* Power Down USB tranceiver */ + /* Power Down USB transceiver */ USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN); /* Enable Battery charging */ diff --git a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c index 5c6205c..23fa64b 100644 --- a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c +++ b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c @@ -61,8 +61,8 @@ static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx); */ /** @defgroup USB_LL_Exported_Functions_Group1 Initialization/de-initialization functions - * @brief Initialization and Configuration functions - * + * @brief Initialization and Configuration functions + * @verbatim =============================================================================== ##### Initialization/de-initialization functions ##### @@ -104,7 +104,7 @@ HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef c /* Select FS Embedded PHY */ USBx->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL; - /* Reset after a PHY select and set Host mode */ + /* Reset after a PHY select */ ret = USB_CoreReset(USBx); if (cfg.battery_charging_enable == 0U) @@ -229,7 +229,7 @@ HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx) * Disable the controller's Global Int in the AHB Config reg * @param USBx Selected device * @retval HAL status -*/ + */ HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx) { USBx->GAHBCFG &= ~USB_OTG_GAHBCFG_GINT; @@ -237,13 +237,12 @@ HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx) } /** - * @brief USB_SetCurrentMode : Set functional mode + * @brief USB_SetCurrentMode Set functional mode * @param USBx Selected device - * @param mode current core mode + * @param mode current core mode * This parameter can be one of these values: - * @arg USB_DEVICE_MODE: Peripheral mode - * @arg USB_HOST_MODE: Host mode - * @arg USB_DRD_MODE: Dual Role Device mode + * @arg USB_DEVICE_MODE Peripheral mode + * @arg USB_HOST_MODE Host mode * @retval HAL status */ HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx, USB_OTG_ModeTypeDef mode) @@ -268,7 +267,7 @@ HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx, USB_OTG_ModeTy } /** - * @brief USB_DevInit : Initializes the USB_OTG controller registers + * @brief USB_DevInit Initializes the USB_OTG controller registers * for device mode * @param USBx Selected device * @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains @@ -463,8 +462,7 @@ HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num) { return HAL_TIMEOUT; } - } - while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_TXFFLSH) == USB_OTG_GRSTCTL_TXFFLSH); + } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_TXFFLSH) == USB_OTG_GRSTCTL_TXFFLSH); return HAL_OK; } @@ -486,8 +484,7 @@ HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx) { return HAL_TIMEOUT; } - } - while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_RXFFLSH) == USB_OTG_GRSTCTL_RXFFLSH); + } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_RXFFLSH) == USB_OTG_GRSTCTL_RXFFLSH); return HAL_OK; } @@ -956,7 +953,8 @@ HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDe * 1 : DMA feature used * @retval HAL status */ -HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len, uint8_t dma) +HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, + uint8_t ch_ep_num, uint16_t len, uint8_t dma) { uint32_t USBx_BASE = (uint32_t)USBx; uint32_t *pSrc = (uint32_t *)src; @@ -1116,7 +1114,7 @@ HAL_StatusTypeDef USB_SetDevAddress(USB_OTG_GlobalTypeDef *USBx, uint8_t addres } /** - * @brief USB_DevConnect : Connect the USB device by enabling the pull-up/pull-down + * @brief USB_DevConnect : Connect the USB device by enabling Rpu * @param USBx Selected device * @retval HAL status */ @@ -1124,14 +1122,16 @@ HAL_StatusTypeDef USB_DevConnect(USB_OTG_GlobalTypeDef *USBx) { uint32_t USBx_BASE = (uint32_t)USBx; + /* In case phy is stopped, ensure to ungate and restore the phy CLK */ + USBx_PCGCCTL &= ~(USB_OTG_PCGCCTL_STOPCLK | USB_OTG_PCGCCTL_GATECLK); + USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_SDIS; - HAL_Delay(3U); return HAL_OK; } /** - * @brief USB_DevDisconnect : Disconnect the USB device by disabling the pull-up/pull-down + * @brief USB_DevDisconnect : Disconnect the USB device by disabling Rpu * @param USBx Selected device * @retval HAL status */ @@ -1139,8 +1139,10 @@ HAL_StatusTypeDef USB_DevDisconnect(USB_OTG_GlobalTypeDef *USBx) { uint32_t USBx_BASE = (uint32_t)USBx; + /* In case phy is stopped, ensure to ungate and restore the phy CLK */ + USBx_PCGCCTL &= ~(USB_OTG_PCGCCTL_STOPCLK | USB_OTG_PCGCCTL_GATECLK); + USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS; - HAL_Delay(3U); return HAL_OK; } @@ -1233,7 +1235,7 @@ uint32_t USB_ReadDevInEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum) /** * @brief USB_ClearInterrupts: clear a USB interrupt * @param USBx Selected device - * @param interrupt interrupt flag + * @param interrupt flag * @retval None */ void USB_ClearInterrupts(USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt) @@ -1325,8 +1327,7 @@ static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx) { return HAL_TIMEOUT; } - } - while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U); + } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U); /* Core Soft Reset */ count = 0U; @@ -1338,8 +1339,7 @@ static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx) { return HAL_TIMEOUT; } - } - while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_CSRST) == USB_OTG_GRSTCTL_CSRST); + } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_CSRST) == USB_OTG_GRSTCTL_CSRST); return HAL_OK; } @@ -1481,7 +1481,7 @@ HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx, uint8_t freq) } /** -* @brief USB_OTG_ResetPort : Reset Host Port + * @brief USB_OTG_ResetPort : Reset Host Port * @param USBx Selected device * @retval HAL status * @note (1)The application must wait at least 10 ms @@ -1510,10 +1510,10 @@ HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx) * @brief USB_DriveVbus : activate or de-activate vbus * @param state VBUS state * This parameter can be one of these values: - * 0 : VBUS Active - * 1 : VBUS Inactive + * 0 : Deactivate VBUS + * 1 : Activate VBUS * @retval HAL status -*/ + */ HAL_StatusTypeDef USB_DriveVbus(USB_OTG_GlobalTypeDef *USBx, uint8_t state) { uint32_t USBx_BASE = (uint32_t)USBx; @@ -1557,7 +1557,7 @@ uint32_t USB_GetHostSpeed(USB_OTG_GlobalTypeDef *USBx) * @brief Return Host Current Frame number * @param USBx Selected device * @retval current frame number -*/ + */ uint32_t USB_GetCurrentFrame(USB_OTG_GlobalTypeDef *USBx) { uint32_t USBx_BASE = (uint32_t)USBx; @@ -1589,13 +1589,9 @@ uint32_t USB_GetCurrentFrame(USB_OTG_GlobalTypeDef *USBx) * This parameter can be a value from 0 to32K * @retval HAL state */ -HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, - uint8_t ch_num, - uint8_t epnum, - uint8_t dev_address, - uint8_t speed, - uint8_t ep_type, - uint16_t mps) +HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num, + uint8_t epnum, uint8_t dev_address, uint8_t speed, + uint8_t ep_type, uint16_t mps) { HAL_StatusTypeDef ret = HAL_OK; uint32_t USBx_BASE = (uint32_t)USBx; @@ -1789,45 +1785,47 @@ HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDe tmpreg |= USB_OTG_HCCHAR_CHENA; USBx_HC(ch_num)->HCCHAR = tmpreg; - if (dma == 0U) /* Slave mode */ + if (dma != 0U) /* dma mode */ { - if ((hc->ep_is_in == 0U) && (hc->xfer_len > 0U)) + return HAL_OK; + } + + if ((hc->ep_is_in == 0U) && (hc->xfer_len > 0U)) + { + switch (hc->ep_type) { - switch (hc->ep_type) - { - /* Non periodic transfer */ - case EP_TYPE_CTRL: - case EP_TYPE_BULK: + /* Non periodic transfer */ + case EP_TYPE_CTRL: + case EP_TYPE_BULK: - len_words = (uint16_t)((hc->xfer_len + 3U) / 4U); + len_words = (uint16_t)((hc->xfer_len + 3U) / 4U); - /* check if there is enough space in FIFO space */ - if (len_words > (USBx->HNPTXSTS & 0xFFFFU)) - { - /* need to process data in nptxfempty interrupt */ - USBx->GINTMSK |= USB_OTG_GINTMSK_NPTXFEM; - } - break; + /* check if there is enough space in FIFO space */ + if (len_words > (USBx->HNPTXSTS & 0xFFFFU)) + { + /* need to process data in nptxfempty interrupt */ + USBx->GINTMSK |= USB_OTG_GINTMSK_NPTXFEM; + } + break; - /* Periodic transfer */ - case EP_TYPE_INTR: - case EP_TYPE_ISOC: - len_words = (uint16_t)((hc->xfer_len + 3U) / 4U); - /* check if there is enough space in FIFO space */ - if (len_words > (USBx_HOST->HPTXSTS & 0xFFFFU)) /* split the transfer */ - { - /* need to process data in ptxfempty interrupt */ - USBx->GINTMSK |= USB_OTG_GINTMSK_PTXFEM; - } - break; + /* Periodic transfer */ + case EP_TYPE_INTR: + case EP_TYPE_ISOC: + len_words = (uint16_t)((hc->xfer_len + 3U) / 4U); + /* check if there is enough space in FIFO space */ + if (len_words > (USBx_HOST->HPTXSTS & 0xFFFFU)) /* split the transfer */ + { + /* need to process data in ptxfempty interrupt */ + USBx->GINTMSK |= USB_OTG_GINTMSK_PTXFEM; + } + break; - default: - break; - } - - /* Write packet into the Tx FIFO. */ - (void)USB_WritePacket(USBx, hc->xfer_buff, hc->ch_num, (uint16_t)hc->xfer_len, 0); + default: + break; } + + /* Write packet into the Tx FIFO. */ + (void)USB_WritePacket(USBx, hc->xfer_buff, hc->ch_num, (uint16_t)hc->xfer_len, 0); } return HAL_OK; @@ -1875,8 +1873,7 @@ HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num) { break; } - } - while ((USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA); + } while ((USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA); } else { @@ -1898,8 +1895,7 @@ HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num) { break; } - } - while ((USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA); + } while ((USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA); } else { @@ -1979,8 +1975,7 @@ HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx) { break; } - } - while ((USBx_HC(i)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA); + } while ((USBx_HC(i)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA); } /* Clear any pending Host interrupts */ diff --git a/Inc/bsp_driver_sd.h b/Inc/bsp_driver_sd.h index 801343b..cd882be 100644 --- a/Inc/bsp_driver_sd.h +++ b/Inc/bsp_driver_sd.h @@ -1,12 +1,12 @@ /** ****************************************************************************** * @file bsp_driver_sd.h for F4 (based on stm324x9i_eval_sd.h) - * @brief This file contains the common defines and functions prototypes for + * @brief This file contains the common defines and functions prototypes for * the bsp_driver_sd.c driver. ****************************************************************************** * @attention * - *

© Copyright (c) 2020 STMicroelectronics. + *

© Copyright (c) 2021 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under Ultimate Liberty license @@ -23,28 +23,28 @@ #ifdef __cplusplus extern "C" { -#endif +#endif /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx_hal.h" #include "fatfs_platform.h" -/* Exported types --------------------------------------------------------*/ -/** - * @brief SD Card information structure +/* Exported types --------------------------------------------------------*/ +/** + * @brief SD Card information structure */ #define BSP_SD_CardInfo HAL_SD_CardInfoTypeDef -/* Exported constants --------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ /** - * @brief SD status structure definition - */ + * @brief SD status structure definition + */ #define MSD_OK ((uint8_t)0x00) #define MSD_ERROR ((uint8_t)0x01) -/** - * @brief SD transfer state definition - */ +/** + * @brief SD transfer state definition + */ #define SD_TRANSFER_OK ((uint8_t)0x00) #define SD_TRANSFER_BUSY ((uint8_t)0x01) @@ -56,7 +56,7 @@ /* kept to avoid issue when migrating old projects. */ /* USER CODE BEGIN 0 */ -/* USER CODE END 0 */ +/* USER CODE END 0 */ #else /* USER CODE BEGIN BSP_H_CODE */ /* Exported functions --------------------------------------------------------*/ @@ -83,7 +83,7 @@ void BSP_SD_WriteCpltCallback(void); void BSP_SD_ReadCpltCallback(void); /* USER CODE END BSP_H_CODE */ #endif - + #ifdef __cplusplus } #endif diff --git a/Inc/fatfs.h b/Inc/fatfs.h index fdc4fcb..0f8a12e 100644 --- a/Inc/fatfs.h +++ b/Inc/fatfs.h @@ -5,7 +5,7 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2020 STMicroelectronics. + *

© Copyright (c) 2021 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under Ultimate Liberty license diff --git a/Inc/fatfs_platform.h b/Inc/fatfs_platform.h index 92dcffe..17649fb 100644 --- a/Inc/fatfs_platform.h +++ b/Inc/fatfs_platform.h @@ -5,7 +5,7 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2020 STMicroelectronics. + *

© Copyright (c) 2021 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under Ultimate Liberty license @@ -16,7 +16,7 @@ ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_hal.h" +#include "stm32f4xx_hal.h" /* Defines ------------------------------------------------------------------*/ #define SD_PRESENT ((uint8_t)0x01) /* also in bsp_driver_sd.h */ #define SD_NOT_PRESENT ((uint8_t)0x00) /* also in bsp_driver_sd.h */ diff --git a/Inc/ffconf.h b/Inc/ffconf.h index 5c67f10..06ab95f 100644 --- a/Inc/ffconf.h +++ b/Inc/ffconf.h @@ -21,7 +21,7 @@ #define _FFCONF 68300 /* Revision ID */ /*-----------------------------------------------------------------------------/ -/ Additional user header to be used +/ Additional user header to be used /-----------------------------------------------------------------------------*/ #include "main.h" #include "stm32f4xx_hal.h" @@ -158,7 +158,7 @@ #define _VOLUMES 1 /* Number of volumes (logical drives) to be used. */ -/* USER CODE BEGIN Volumes */ +/* USER CODE BEGIN Volumes */ #define _STR_VOLUME_ID 0 /* 0:Use only 0-9 for drive ID, 1:Use strings for drive ID */ #define _VOLUME_STRS "RAM","NAND","CF","SD1","SD2","USB1","USB2","USB3" /* _STR_VOLUME_ID switches string support of volume ID. @@ -166,7 +166,7 @@ / number in the path name. _VOLUME_STRS defines the drive ID strings for each / logical drives. Number of items must be equal to _VOLUMES. Valid characters for / the drive ID strings are: A-Z and 0-9. */ -/* USER CODE END Volumes */ +/* USER CODE END Volumes */ #define _MULTI_PARTITION 0 /* 0:Single partition, 1:Multiple partition */ /* This option switches support of multi-partition on a physical drive. @@ -225,7 +225,7 @@ / defined by _NORTC_MON, _NORTC_MDAY and _NORTC_YEAR in local time. / To enable timestamp function (_FS_NORTC = 0), get_fattime() function need to be / added to the project to get current time form real-time clock. _NORTC_MON, -/ _NORTC_MDAY and _NORTC_YEAR have no effect. +/ _NORTC_MDAY and _NORTC_YEAR have no effect. / These options have no effect at read-only configuration (_FS_READONLY = 1). */ #define _FS_LOCK 2 /* 0:Disable or >=1:Enable */ diff --git a/Inc/sd_diskio.h b/Inc/sd_diskio.h index 6cb5fb5..fce427f 100644 --- a/Inc/sd_diskio.h +++ b/Inc/sd_diskio.h @@ -24,7 +24,7 @@ #ifndef __SD_DISKIO_H #define __SD_DISKIO_H -/* USER CODE BEGIN firstSection */ +/* USER CODE BEGIN firstSection */ /* can be used to modify / undefine following code or add new definitions */ /* USER CODE END firstSection */ @@ -35,7 +35,7 @@ /* Exported functions ------------------------------------------------------- */ extern const Diskio_drvTypeDef SD_Driver; -/* USER CODE BEGIN lastSection */ +/* USER CODE BEGIN lastSection */ /* can be used to modify / undefine previous code or add new definitions */ /* USER CODE END lastSection */ diff --git a/Inc/stm32f4xx_hal_conf.h b/Inc/stm32f4xx_hal_conf.h index a358457..33764b2 100644 --- a/Inc/stm32f4xx_hal_conf.h +++ b/Inc/stm32f4xx_hal_conf.h @@ -2,7 +2,7 @@ ****************************************************************************** * @file stm32f4xx_hal_conf_template.h * @author MCD Application Team - * @brief HAL configuration template file. + * @brief HAL configuration template file. * This file should be copied to the application folder and renamed * to stm32f4xx_hal_conf.h. ****************************************************************************** @@ -17,7 +17,7 @@ * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** - */ + */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F4xx_HAL_CONF_H @@ -32,14 +32,15 @@ /* ########################## Module Selection ############################## */ /** - * @brief This is the list of modules to be used in the HAL driver + * @brief This is the list of modules to be used in the HAL driver */ -#define HAL_MODULE_ENABLED +#define HAL_MODULE_ENABLED /* #define HAL_ADC_MODULE_ENABLED */ /* #define HAL_CRYP_MODULE_ENABLED */ /* #define HAL_CAN_MODULE_ENABLED */ /* #define HAL_CRC_MODULE_ENABLED */ +/* #define HAL_CAN_LEGACY_MODULE_ENABLED */ /* #define HAL_CRYP_MODULE_ENABLED */ /* #define HAL_DAC_MODULE_ENABLED */ /* #define HAL_DCMI_MODULE_ENABLED */ @@ -90,9 +91,9 @@ /** * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. * This value is used by the RCC HAL module to compute the system frequency - * (when HSE is used as system clock source, directly or through the PLL). + * (when HSE is used as system clock source, directly or through the PLL). */ -#if !defined (HSE_VALUE) +#if !defined (HSE_VALUE) #define HSE_VALUE ((uint32_t)25000000U) /*!< Value of the External oscillator in Hz */ #endif /* HSE_VALUE */ @@ -103,7 +104,7 @@ /** * @brief Internal High Speed oscillator (HSI) value. * This value is used by the RCC HAL module to compute the system frequency - * (when HSI is used as system clock source, directly or through the PLL). + * (when HSI is used as system clock source, directly or through the PLL). */ #if !defined (HSI_VALUE) #define HSI_VALUE ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/ @@ -112,7 +113,7 @@ /** * @brief Internal Low Speed oscillator (LSI) value. */ -#if !defined (LSI_VALUE) +#if !defined (LSI_VALUE) #define LSI_VALUE ((uint32_t)32000U) /*!< LSI Typical Value in Hz*/ #endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz The real value may vary depending on the variations @@ -130,8 +131,8 @@ /** * @brief External clock source for I2S peripheral - * This value is used by the I2S HAL module to compute the I2S clock source - * frequency, this source is inserted directly through I2S_CKIN pad. + * This value is used by the I2S HAL module to compute the I2S clock source + * frequency, this source is inserted directly through I2S_CKIN pad. */ #if !defined (EXTERNAL_CLOCK_VALUE) #define EXTERNAL_CLOCK_VALUE ((uint32_t)12288000U) /*!< Value of the External audio frequency in Hz*/ @@ -144,16 +145,55 @@ /** * @brief This is the HAL system configuration section */ -#define VDD_VALUE ((uint32_t)3300U) /*!< Value of VDD in mv */ -#define TICK_INT_PRIORITY ((uint32_t)0U) /*!< tick interrupt priority */ -#define USE_RTOS 0U +#define VDD_VALUE ((uint32_t)3300U) /*!< Value of VDD in mv */ +#define TICK_INT_PRIORITY ((uint32_t)0U) /*!< tick interrupt priority */ +#define USE_RTOS 0U #define PREFETCH_ENABLE 1U #define INSTRUCTION_CACHE_ENABLE 1U #define DATA_CACHE_ENABLE 1U +#define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */ +#define USE_HAL_CAN_REGISTER_CALLBACKS 0U /* CAN register callback disabled */ +#define USE_HAL_CEC_REGISTER_CALLBACKS 0U /* CEC register callback disabled */ +#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U /* CRYP register callback disabled */ +#define USE_HAL_DAC_REGISTER_CALLBACKS 0U /* DAC register callback disabled */ +#define USE_HAL_DCMI_REGISTER_CALLBACKS 0U /* DCMI register callback disabled */ +#define USE_HAL_DFSDM_REGISTER_CALLBACKS 0U /* DFSDM register callback disabled */ +#define USE_HAL_DMA2D_REGISTER_CALLBACKS 0U /* DMA2D register callback disabled */ +#define USE_HAL_DSI_REGISTER_CALLBACKS 0U /* DSI register callback disabled */ +#define USE_HAL_ETH_REGISTER_CALLBACKS 0U /* ETH register callback disabled */ +#define USE_HAL_HASH_REGISTER_CALLBACKS 0U /* HASH register callback disabled */ +#define USE_HAL_HCD_REGISTER_CALLBACKS 0U /* HCD register callback disabled */ +#define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */ +#define USE_HAL_FMPI2C_REGISTER_CALLBACKS 0U /* FMPI2C register callback disabled */ +#define USE_HAL_I2S_REGISTER_CALLBACKS 0U /* I2S register callback disabled */ +#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U /* IRDA register callback disabled */ +#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U /* LPTIM register callback disabled */ +#define USE_HAL_LTDC_REGISTER_CALLBACKS 0U /* LTDC register callback disabled */ +#define USE_HAL_MMC_REGISTER_CALLBACKS 0U /* MMC register callback disabled */ +#define USE_HAL_NAND_REGISTER_CALLBACKS 0U /* NAND register callback disabled */ +#define USE_HAL_NOR_REGISTER_CALLBACKS 0U /* NOR register callback disabled */ +#define USE_HAL_PCCARD_REGISTER_CALLBACKS 0U /* PCCARD register callback disabled */ +#define USE_HAL_PCD_REGISTER_CALLBACKS 0U /* PCD register callback disabled */ +#define USE_HAL_QSPI_REGISTER_CALLBACKS 0U /* QSPI register callback disabled */ +#define USE_HAL_RNG_REGISTER_CALLBACKS 0U /* RNG register callback disabled */ +#define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */ +#define USE_HAL_SAI_REGISTER_CALLBACKS 0U /* SAI register callback disabled */ +#define USE_HAL_SD_REGISTER_CALLBACKS 0U /* SD register callback disabled */ +#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U /* SMARTCARD register callback disabled */ +#define USE_HAL_SDRAM_REGISTER_CALLBACKS 0U /* SDRAM register callback disabled */ +#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U /* SRAM register callback disabled */ +#define USE_HAL_SPDIFRX_REGISTER_CALLBACKS 0U /* SPDIFRX register callback disabled */ +#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U /* SMBUS register callback disabled */ +#define USE_HAL_SPI_REGISTER_CALLBACKS 0U /* SPI register callback disabled */ +#define USE_HAL_TIM_REGISTER_CALLBACKS 0U /* TIM register callback disabled */ +#define USE_HAL_UART_REGISTER_CALLBACKS 0U /* UART register callback disabled */ +#define USE_HAL_USART_REGISTER_CALLBACKS 0U /* USART register callback disabled */ +#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */ + /* ########################## Assert Selection ############################## */ /** - * @brief Uncomment the line below to expanse the "assert_param" macro in the + * @brief Uncomment the line below to expanse the "assert_param" macro in the * HAL drivers code */ /* #define USE_FULL_ASSERT 1U */ @@ -170,7 +210,7 @@ #define MAC_ADDR4 0U #define MAC_ADDR5 0U -/* Definition of the Ethernet driver buffers size and count */ +/* Definition of the Ethernet driver buffers size and count */ #define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */ #define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */ #define ETH_RXBUFNB ((uint32_t)4U) /* 4 Rx buffers of size ETH_RX_BUF_SIZE */ @@ -178,9 +218,9 @@ /* Section 2: PHY configuration section */ -/* DP83848_PHY_ADDRESS Address*/ +/* DP83848_PHY_ADDRESS Address*/ #define DP83848_PHY_ADDRESS 0x01U -/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ +/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ #define PHY_RESET_DELAY ((uint32_t)0x000000FFU) /* PHY Configuration delay */ #define PHY_CONFIG_DELAY ((uint32_t)0x00000FFFU) @@ -192,7 +232,7 @@ #define PHY_BCR ((uint16_t)0x0000U) /*!< Transceiver Basic Control Register */ #define PHY_BSR ((uint16_t)0x0001U) /*!< Transceiver Basic Status Register */ - + #define PHY_RESET ((uint16_t)0x8000U) /*!< PHY Reset */ #define PHY_LOOPBACK ((uint16_t)0x4000U) /*!< Select loop-back mode */ #define PHY_FULLDUPLEX_100M ((uint16_t)0x2100U) /*!< Set the full-duplex mode at 100 Mb/s */ @@ -207,7 +247,7 @@ #define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020U) /*!< Auto-Negotiation process completed */ #define PHY_LINKED_STATUS ((uint16_t)0x0004U) /*!< Valid link established */ #define PHY_JABBER_DETECTION ((uint16_t)0x0002U) /*!< Jabber condition detected */ - + /* Section 4: Extended PHY Registers */ #define PHY_SR ((uint16_t)0x10U) /*!< PHY status register Offset */ @@ -225,25 +265,25 @@ /* Includes ------------------------------------------------------------------*/ /** - * @brief Include module's header file + * @brief Include module's header file */ #ifdef HAL_RCC_MODULE_ENABLED #include "stm32f4xx_hal_rcc.h" #endif /* HAL_RCC_MODULE_ENABLED */ -#ifdef HAL_EXTI_MODULE_ENABLED - #include "stm32f4xx_hal_exti.h" -#endif /* HAL_EXTI_MODULE_ENABLED */ - #ifdef HAL_GPIO_MODULE_ENABLED #include "stm32f4xx_hal_gpio.h" #endif /* HAL_GPIO_MODULE_ENABLED */ +#ifdef HAL_EXTI_MODULE_ENABLED + #include "stm32f4xx_hal_exti.h" +#endif /* HAL_EXTI_MODULE_ENABLED */ + #ifdef HAL_DMA_MODULE_ENABLED #include "stm32f4xx_hal_dma.h" #endif /* HAL_DMA_MODULE_ENABLED */ - + #ifdef HAL_CORTEX_MODULE_ENABLED #include "stm32f4xx_hal_cortex.h" #endif /* HAL_CORTEX_MODULE_ENABLED */ @@ -256,18 +296,18 @@ #include "stm32f4xx_hal_can.h" #endif /* HAL_CAN_MODULE_ENABLED */ +#ifdef HAL_CAN_LEGACY_MODULE_ENABLED + #include "stm32f4xx_hal_can_legacy.h" +#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */ + #ifdef HAL_CRC_MODULE_ENABLED #include "stm32f4xx_hal_crc.h" #endif /* HAL_CRC_MODULE_ENABLED */ #ifdef HAL_CRYP_MODULE_ENABLED - #include "stm32f4xx_hal_cryp.h" + #include "stm32f4xx_hal_cryp.h" #endif /* HAL_CRYP_MODULE_ENABLED */ -#ifdef HAL_SMBUS_MODULE_ENABLED -#include "stm32f4xx_hal_smbus.h" -#endif /* HAL_SMBUS_MODULE_ENABLED */ - #ifdef HAL_DMA2D_MODULE_ENABLED #include "stm32f4xx_hal_dma2d.h" #endif /* HAL_DMA2D_MODULE_ENABLED */ @@ -287,7 +327,7 @@ #ifdef HAL_FLASH_MODULE_ENABLED #include "stm32f4xx_hal_flash.h" #endif /* HAL_FLASH_MODULE_ENABLED */ - + #ifdef HAL_SRAM_MODULE_ENABLED #include "stm32f4xx_hal_sram.h" #endif /* HAL_SRAM_MODULE_ENABLED */ @@ -302,11 +342,11 @@ #ifdef HAL_PCCARD_MODULE_ENABLED #include "stm32f4xx_hal_pccard.h" -#endif /* HAL_PCCARD_MODULE_ENABLED */ - +#endif /* HAL_PCCARD_MODULE_ENABLED */ + #ifdef HAL_SDRAM_MODULE_ENABLED #include "stm32f4xx_hal_sdram.h" -#endif /* HAL_SDRAM_MODULE_ENABLED */ +#endif /* HAL_SDRAM_MODULE_ENABLED */ #ifdef HAL_HASH_MODULE_ENABLED #include "stm32f4xx_hal_hash.h" @@ -316,6 +356,10 @@ #include "stm32f4xx_hal_i2c.h" #endif /* HAL_I2C_MODULE_ENABLED */ +#ifdef HAL_SMBUS_MODULE_ENABLED + #include "stm32f4xx_hal_smbus.h" +#endif /* HAL_SMBUS_MODULE_ENABLED */ + #ifdef HAL_I2S_MODULE_ENABLED #include "stm32f4xx_hal_i2s.h" #endif /* HAL_I2S_MODULE_ENABLED */ @@ -348,10 +392,6 @@ #include "stm32f4xx_hal_sd.h" #endif /* HAL_SD_MODULE_ENABLED */ -#ifdef HAL_MMC_MODULE_ENABLED - #include "stm32f4xx_hal_mmc.h" -#endif /* HAL_MMC_MODULE_ENABLED */ - #ifdef HAL_SPI_MODULE_ENABLED #include "stm32f4xx_hal_spi.h" #endif /* HAL_SPI_MODULE_ENABLED */ @@ -387,7 +427,7 @@ #ifdef HAL_HCD_MODULE_ENABLED #include "stm32f4xx_hal_hcd.h" #endif /* HAL_HCD_MODULE_ENABLED */ - + #ifdef HAL_DSI_MODULE_ENABLED #include "stm32f4xx_hal_dsi.h" #endif /* HAL_DSI_MODULE_ENABLED */ @@ -415,14 +455,18 @@ #ifdef HAL_LPTIM_MODULE_ENABLED #include "stm32f4xx_hal_lptim.h" #endif /* HAL_LPTIM_MODULE_ENABLED */ - + +#ifdef HAL_MMC_MODULE_ENABLED + #include "stm32f4xx_hal_mmc.h" +#endif /* HAL_MMC_MODULE_ENABLED */ + /* Exported macro ------------------------------------------------------------*/ #ifdef USE_FULL_ASSERT /** * @brief The assert_param macro is used for function's parameters check. - * @param expr: If expr is false, it calls assert_failed function + * @param expr If expr is false, it calls assert_failed function * which reports the name of the source file and the source - * line number of the call that failed. + * line number of the call that failed. * If expr is true, it returns no value. * @retval None */ @@ -431,13 +475,12 @@ void assert_failed(uint8_t* file, uint32_t line); #else #define assert_param(expr) ((void)0U) -#endif /* USE_FULL_ASSERT */ +#endif /* USE_FULL_ASSERT */ #ifdef __cplusplus } #endif #endif /* __STM32F4xx_HAL_CONF_H */ - /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Inc/stm32f4xx_it.h b/Inc/stm32f4xx_it.h index 05b79a5..6af70b9 100644 --- a/Inc/stm32f4xx_it.h +++ b/Inc/stm32f4xx_it.h @@ -24,7 +24,7 @@ #ifdef __cplusplus extern "C" { -#endif +#endif /* Private includes ----------------------------------------------------------*/ /* USER CODE BEGIN Includes */ diff --git a/Inc/usbd_desc.h b/Inc/usbd_desc.h index 0c6619f..43e7922 100644 --- a/Inc/usbd_desc.h +++ b/Inc/usbd_desc.h @@ -17,7 +17,7 @@ * ****************************************************************************** */ -/* USER CODE END Header */ +/* USER CODE END Header */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __USBD_DESC__C__ #define __USBD_DESC__C__ @@ -41,7 +41,7 @@ * @brief Usb device descriptors module. * @{ */ - + /** @defgroup USBD_DESC_Exported_Constants USBD_DESC_Exported_Constants * @brief Constants. * @{ diff --git a/Makefile b/Makefile index ab2b63a..1db5e0f 100644 --- a/Makefile +++ b/Makefile @@ -1,5 +1,5 @@ ########################################################################################################################## -# File automatically-generated by tool: [projectgenerator] version: [3.7.1] date: [Thu Oct 01 22:37:12 CEST 2020] +# File automatically-generated by tool: [projectgenerator] version: [3.11.0-B13] date: [Wed Jan 06 03:17:31 CET 2021] ########################################################################################################################## # ------------------------------------------------ diff --git a/Middlewares/Third_Party/FatFs/src/00history.txt b/Middlewares/Third_Party/FatFs/src/00history.txt new file mode 100644 index 0000000..fa73638 --- /dev/null +++ b/Middlewares/Third_Party/FatFs/src/00history.txt @@ -0,0 +1,288 @@ +---------------------------------------------------------------------------- + Revision history of FatFs module +---------------------------------------------------------------------------- + +R0.00 (February 26, 2006) + + Prototype. + + + +R0.01 (April 29, 2006) + + The first release. + + + +R0.02 (June 01, 2006) + + Added FAT12 support. + Removed unbuffered mode. + Fixed a problem on small (<32M) partition. + + + +R0.02a (June 10, 2006) + + Added a configuration option (_FS_MINIMUM). + + + +R0.03 (September 22, 2006) + + Added f_rename(). + Changed option _FS_MINIMUM to _FS_MINIMIZE. + + + +R0.03a (December 11, 2006) + + Improved cluster scan algorithm to write files fast. + Fixed f_mkdir() creates incorrect directory on FAT32. + + + +R0.04 (February 04, 2007) + + Added f_mkfs(). + Supported multiple drive system. + Changed some interfaces for multiple drive system. + Changed f_mountdrv() to f_mount(). + + + +R0.04a (April 01, 2007) + + Supported multiple partitions on a physical drive. + Added a capability of extending file size to f_lseek(). + Added minimization level 3. + Fixed an endian sensitive code in f_mkfs(). + + + +R0.04b (May 05, 2007) + + Added a configuration option _USE_NTFLAG. + Added FSINFO support. + Fixed DBCS name can result FR_INVALID_NAME. + Fixed short seek (<= csize) collapses the file object. + + + +R0.05 (August 25, 2007) + + Changed arguments of f_read(), f_write() and f_mkfs(). + Fixed f_mkfs() on FAT32 creates incorrect FSINFO. + Fixed f_mkdir() on FAT32 creates incorrect directory. + + + +R0.05a (February 03, 2008) + + Added f_truncate() and f_utime(). + Fixed off by one error at FAT sub-type determination. + Fixed btr in f_read() can be mistruncated. + Fixed cached sector is not flushed when create and close without write. + + + +R0.06 (April 01, 2008) + + Added fputc(), fputs(), fprintf() and fgets(). + Improved performance of f_lseek() on moving to the same or following cluster. + + + +R0.07 (April 01, 2009) + + Merged Tiny-FatFs as a configuration option. (_FS_TINY) + Added long file name feature. (_USE_LFN) + Added multiple code page feature. (_CODE_PAGE) + Added re-entrancy for multitask operation. (_FS_REENTRANT) + Added auto cluster size selection to f_mkfs(). + Added rewind option to f_readdir(). + Changed result code of critical errors. + Renamed string functions to avoid name collision. + + + +R0.07a (April 14, 2009) + + Septemberarated out OS dependent code on reentrant cfg. + Added multiple sector size feature. + + + +R0.07c (June 21, 2009) + + Fixed f_unlink() can return FR_OK on error. + Fixed wrong cache control in f_lseek(). + Added relative path feature. + Added f_chdir() and f_chdrive(). + Added proper case conversion to extended character. + + + +R0.07e (November 03, 2009) + + Septemberarated out configuration options from ff.h to ffconf.h. + Fixed f_unlink() fails to remove a sub-directory on _FS_RPATH. + Fixed name matching error on the 13 character boundary. + Added a configuration option, _LFN_UNICODE. + Changed f_readdir() to return the SFN with always upper case on non-LFN cfg. + + + +R0.08 (May 15, 2010) + + Added a memory configuration option. (_USE_LFN = 3) + Added file lock feature. (_FS_SHARE) + Added fast seek feature. (_USE_FASTSEEK) + Changed some types on the API, XCHAR->TCHAR. + Changed .fname in the FILINFO structure on Unicode cfg. + String functions support UTF-8 encoding files on Unicode cfg. + + + +R0.08a (August 16, 2010) + + Added f_getcwd(). (_FS_RPATH = 2) + Added sector erase feature. (_USE_ERASE) + Moved file lock semaphore table from fs object to the bss. + Fixed f_mkfs() creates wrong FAT32 volume. + + + +R0.08b (January 15, 2011) + + Fast seek feature is also applied to f_read() and f_write(). + f_lseek() reports required table size on creating CLMP. + Extended format syntax of f_printf(). + Ignores duplicated directory separators in given path name. + + + +R0.09 (September 06, 2011) + + f_mkfs() supports multiple partition to complete the multiple partition feature. + Added f_fdisk(). + + + +R0.09a (August 27, 2012) + + Changed f_open() and f_opendir() reject null object pointer to avoid crash. + Changed option name _FS_SHARE to _FS_LOCK. + Fixed assertion failure due to OS/2 EA on FAT12/16 volume. + + + +R0.09b (January 24, 2013) + + Added f_setlabel() and f_getlabel(). + + + +R0.10 (October 02, 2013) + + Added selection of character encoding on the file. (_STRF_ENCODE) + Added f_closedir(). + Added forced full FAT scan for f_getfree(). (_FS_NOFSINFO) + Added forced mount feature with changes of f_mount(). + Improved behavior of volume auto detection. + Improved write throughput of f_puts() and f_printf(). + Changed argument of f_chdrive(), f_mkfs(), disk_read() and disk_write(). + Fixed f_write() can be truncated when the file size is close to 4GB. + Fixed f_open(), f_mkdir() and f_setlabel() can return incorrect value on error. + + + +R0.10a (January 15, 2014) + + Added arbitrary strings as drive number in the path name. (_STR_VOLUME_ID) + Added a configuration option of minimum sector size. (_MIN_SS) + 2nd argument of f_rename() can have a drive number and it will be ignored. + Fixed f_mount() with forced mount fails when drive number is >= 1. (appeared at R0.10) + Fixed f_close() invalidates the file object without volume lock. + Fixed f_closedir() returns but the volume lock is left acquired. (appeared at R0.10) + Fixed creation of an entry with LFN fails on too many SFN collisions. (appeared at R0.07) + + + +R0.10b (May 19, 2014) + + Fixed a hard error in the disk I/O layer can collapse the directory entry. + Fixed LFN entry is not deleted when delete/rename an object with lossy converted SFN. (appeared at R0.07) + + + +R0.10c (November 09, 2014) + + Added a configuration option for the platforms without RTC. (_FS_NORTC) + Changed option name _USE_ERASE to _USE_TRIM. + Fixed volume label created by Mac OS X cannot be retrieved with f_getlabel(). (appeared at R0.09b) + Fixed a potential problem of FAT access that can appear on disk error. + Fixed null pointer dereference on attempting to delete the root direcotry. (appeared at R0.08) + + + +R0.11 (February 09, 2015) + + Added f_findfirst(), f_findnext() and f_findclose(). (_USE_FIND) + Fixed f_unlink() does not remove cluster chain of the file. (appeared at R0.10c) + Fixed _FS_NORTC option does not work properly. (appeared at R0.10c) + + + +R0.11a (September 05, 2015) + + Fixed wrong media change can lead a deadlock at thread-safe configuration. + Added code page 771, 860, 861, 863, 864, 865 and 869. (_CODE_PAGE) + Removed some code pages actually not exist on the standard systems. (_CODE_PAGE) + Fixed errors in the case conversion teble of code page 437 and 850 (ff.c). + Fixed errors in the case conversion teble of Unicode (cc*.c). + + + +R0.12 (April 12, 2016) + + Added support for exFAT file system. (_FS_EXFAT) + Added f_expand(). (_USE_EXPAND) + Changed some members in FINFO structure and behavior of f_readdir(). + Added an option _USE_CHMOD. + Removed an option _WORD_ACCESS. + Fixed errors in the case conversion table of Unicode (cc*.c). + + + +R0.12a (July 10, 2016) + + Added support for creating exFAT volume with some changes of f_mkfs(). + Added a file open method FA_OPEN_APPEND. An f_lseek() following f_open() is no longer needed. + f_forward() is available regardless of _FS_TINY. + Fixed f_mkfs() creates wrong volume. (appeared at R0.12) + Fixed wrong memory read in create_name(). (appeared at R0.12) + Fixed compilation fails at some configurations, _USE_FASTSEEK and _USE_FORWARD. + + + +R0.12b (September 04, 2016) + + Made f_rename() be able to rename objects with the same name but case. + Fixed an error in the case conversion teble of code page 866. (ff.c) + Fixed writing data is truncated at the file offset 4GiB on the exFAT volume. (appeared at R0.12) + Fixed creating a file in the root directory of exFAT volume can fail. (appeared at R0.12) + Fixed f_mkfs() creating exFAT volume with too small cluster size can collapse unallocated memory. (appeared at R0.12) + Fixed wrong object name can be returned when read directory at Unicode cfg. (appeared at R0.12) + Fixed large file allocation/removing on the exFAT volume collapses allocation bitmap. (appeared at R0.12) + Fixed some internal errors in f_expand() and f_lseek(). (appeared at R0.12) + + + +R0.12c (March 04, 2017) + + Improved write throughput at the fragmented file on the exFAT volume. + Made memory usage for exFAT be able to be reduced as decreasing _MAX_LFN. + Fixed successive f_getfree() can return wrong count on the FAT12/16 volume. (appeared at R0.12) + Fixed configuration option _VOLUMES cannot be set 10. (appeared at R0.10c) + diff --git a/Middlewares/Third_Party/FatFs/src/00readme.txt b/Middlewares/Third_Party/FatFs/src/00readme.txt new file mode 100644 index 0000000..2b7cc76 --- /dev/null +++ b/Middlewares/Third_Party/FatFs/src/00readme.txt @@ -0,0 +1,21 @@ +FatFs Module Source Files R0.12c + + +FILES + + 00readme.txt This file. + 00history.txt Revision history. + ff.c FatFs module. + ffconf.h Configuration file of FatFs module. + ff.h Common include file for FatFs and application module. + diskio.h Common include file for FatFs and disk I/O module. + diskio.c An example of glue function to attach existing disk I/O module to FatFs. + integer.h Integer type definitions for FatFs. + option Optional external modules. + + + Low level disk I/O module is not included in this archive because the FatFs + module is only a generic file system layer and it does not depend on any specific + storage device. You have to provide a low level disk I/O module written to + control the storage device that attached to the target system. + diff --git a/Middlewares/Third_Party/FatFs/src/st_readme.txt b/Middlewares/Third_Party/FatFs/src/st_readme.txt new file mode 100644 index 0000000..d8b31de --- /dev/null +++ b/Middlewares/Third_Party/FatFs/src/st_readme.txt @@ -0,0 +1,221 @@ + @verbatim + ****************************************************************************** + * @file st_readme.txt + * @author MCD Application Team + * @brief This file lists the main modification done by STMicroelectronics on + * FatFs for integration with STM32Cube solution. + * For more details on FatFs implementation on STM32Cube, please refer + * to UM1721 "Developing Applications on STM32Cube with FatFs" + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + @endverbatim + +### V2.1.4/18-10-2019 ### +============================ ++ Fix wrong usage of the "memcpy" in the SD_Write() function + - drivers/sd_diskio_dma_template_bspv1.c + - drivers/sd_diskio_dma_template_bspv2.c + - drivers/sd_diskio_dma_rtos_template_bspv1.c + - drivers/sd_diskio_dma_rtos_template_bspv2.c + ++ correct the usage of the "_USE_MUTEX" config flag + - syscall.c + +### V2.1.3/26-07-2019 ### +============================ ++ add new BSPv2 templates: + - drivers/sd_diskio_dma_rtos_template_bspv2.c + - drivers/sd_diskio_dma_template_bspv2.c + - drivers/sd_diskio_template_bspv2.c + - drivers/sdram_diskio_template_bspv2.c + ++ rename old template to "xxxx_diskio_template_bspv1.c": + - drivers/sd_diskio_dma_rtos_template_bspv1.c + - drivers/sd_diskio_dma_template_bspv1.c + - drivers/sd_diskio_template_bspv1.c + - drivers/sdram_diskio_template_bspv1.c + ++ Add CMSIS-OSv2 support in templates, syscall.c and ff_conf_template.h + - syscall.c + - ff_conf_template.h + - drivers/sd_diskio_dma_rtos_template_bspv2.c + ++ support usage of "osMutex" alongside "osSemaphore" as _SYNC_t type in fatfs + - syscall.c + - ff_conf_template.h + + +### V2.1.2/29-03-2019 ### +============================ ++ add st_license.txt in the root directory ++ src/drivers/xxx_diskio_template.[c/h], src/ff_gen_drv.[c/h], src/option/syscall.c: update the license terms to BSD-3-Clause + +### V2.1.1/25-01-2019 ### +============================ ++ sd_diskio_dma_rtos_template.c + - Fix memory leak in the SD_Initialize() + - Disable the ENABLE_SD_DMA_CACHE_MAINTENANCE flag by default to fix a build error for CM4 + - include correct diskio header file + ++ sd_diskio_dma_template.c + - Correct the SD_read() function when enabling the ENABLE_SCRATCH_BUFFER flag + ++ sd_diskio_dma_rtos_template.c sd_diskio_dma_template.c + - fix potential overflow when using SysTick. + + +### V2.1.0/21-09-2018 ### +============================ ++ ff.c + - back-port a fix from 0.13, to correct an issue when using multi-threading + access in the same device due to a missing semaphore lock when calling + disk_status() API. + ++ sd_diskio_dma_rtos_template.c + - Add support to CMSIS-RTOS V2 API + ++ sd_diskio_dma_rtos_template.c sd_diskio_dma_template.c + - Add a compile flag "ENABLE_SCRATCH_BUFFER" to avoid misaligned access + caused buffer alignment constraint in some DMA versions. + - Add BSP_SD_ErrorCallback() and BSP_SD_AbortCallback() template functions. + +### V2.0.2/17-November-2017 ### +============================ ++ sdram_diskio_template.c sram_diskio_template.c + Fix wrong buffer size in the (SRAM/SDRAM)DISK_read(), (SRAM/SDRAM)DISK_write() + ++ sd_diskio_template.c + - define a generic 'SD_TIMEOUT' based on the BSP drivers defines. This fixes + a build issue when using this driver with the Adafruit shield. + ++ sd_diskio_dma_rtos_template.c + - add a check via osKernelRunning(), to avoid runtime errors due to + osMessageXXX calls that needs the "osKernelStart()" call done first. + ++ sd_diskio_dma_template.c, sd_diskio_dma_rtos_template.c + - fix wrong address alignment when calling SCB_InvalidateDCache_by_Addr() and + SCB_CleanDCache_by_Addr(), the address has to be 32-Byte and not + 32-bit aligned. + + - fix BSP_SD_ReadCpltCallback() and BSP_SD_WriteCpltCallback() prototypes by + adding 'void' as argument to avoid IAR compiler errors + + ++ sd_diskio_template.c sd_diskio_dma_template.c, sd_diskio_dma_rtos_template.c + - add the flag "DISABLE_SD_INIT" to give the user the choice to initialize the SD + either in the application or in the FatFs diskio driver. + ++ all xxx_diskio_template.c + - fix GET_BLOCK_SIZE ioctl call; the return value is in unit of sectors. + + +### V2.0.1/10-July-2017 ### +============================ ++ sd_diskio_dma_template.c, sd_diskio_dma_rtos_template.c + - add the flag "ENABLE_SD_DMA_CACHE_MAINTENANCE", to enable cache maintenance at each read write operation. + This is useful for STM32F7/STM32H7 based platforms when using a cachable memory region. + - add timeout checks in SD_Read() and SD_Write() to give the control back to the application to decide in case of errors. + ++ ff_gen_drv.c: fix a wrong check that causes an out of bound array access. + + +### V2.0.0/07-March-2017 ### +============================ + + Upgrade to use FatFS R0.12c. The R0.12c breaks the API compatibility with R0.11b. + - f_mkfs() API has a new signature. + - The _CODE_PAGE got new values. + - For more details check the files (doc/updates.txt) and the following urls: + http://elm-chan.org/fsw/ff/en/mkfs.html + http://elm-chan.org/fsw/ff/en/config.html + + + Add USB, RAMDISK and uSD template drivers under src/drivers. + - The diskio drivers aren't part of fatfs anymore, they are just templates instead. + - User has to copy the suitable template .c/.h file under the project, rename them by + removing the "_template" suffix then link them into the final application. + - The diskio driver .c/.h files have to be edited according to the used platform. + + + Define the macros "ff_malloc" and "ff_free" in the ff_conf_template.h and use + them in the syscall.c instead of direct calls to stdlib malloc and free functions. + + Define the "__weak" attribute in diskio.c for the GNU GCC compiler + + +### V1.4.0/09-September-2016 ### +================================ + + Upgrade to use FatFs R0.12b. + + ff_conf.h: remove the use of define "_USE_BUFF_WO_ALIGNMENT". + + +### V1.3.0/08-May-2015 ### +========================== + + Upgrade to use FatFs R0.11. + + Add new APIs FATFS_LinkDriverEx() and FATFS_UnLinkDriverEx() to manage USB Key Disk having + multi-lun capability. These APIs are equivalent to FATFS_LinkDriver() and FATFS_UnLinkDriver() + with "lun" parameter set to 0. + + ff_conf.h: add new define "_USE_BUFF_WO_ALIGNMENT". + This option is available only for usbh diskio interface and allow to disable + the management of the unaligned buffer. + When STM32 USB OTG HS or FS IP is used with internal DMA enabled, this define + must be set to 0 to align data into 32bits through an internal scratch buffer + before being processed by the DMA . Otherwise (DMA not used), this define must + be set to 1 to avoid Data alignment and improve the performance. + Please note that if _USE_BUFF_WO_ALIGNMENT is set to 1 and an unaligned 32bits + buffer is forwarded to the FatFs Write/Read functions, an error will be returned. + (0: default value or 1: unaligned buffer return an error). + + + + Important note: + For application code based on previous FatFs version; when moving to R0.11 + the changes that need to be done is to update ffconf.h file, taking + ffconf_template.h file as reference. + + +### V1.2.1/20-November-2014 ### +=============================== + + Disk I/O drivers; change count argument type from BYTE to UINT + + + Important note: + For application code based on previous FatFs version; when moving to R0.10b + the only change that need to be done is to update ffconf.h file, taking + ffconf_template.h file as reference. + + +### V1.2.0/04-November-2014 ### +=============================== + + Upgrade to use FatFs R0.10b. + + diskio.c: update disk_read() and disk_write() argument's type. + + + Important note: + For application code based on previous FatFs version; when moving to R0.10b + the only change that need to be done is to update ffconf.h file, taking + ffconf_template.h file as reference. + + +### V1.1.1/12-September-2014 ### +================================ + + ff_gen_drv.c: Update the Disk_drvTypeDef disk variable initialization to avoid + warnings detected with Atollic TrueSTUDIO Complier. + + +### V1.1.0/22-April-2014 ### +============================ + + Update sd_diskio to use SD BSP in polling mode instead of DMA mode (the scratch + buffer needed for DMA alignment is removed as well). + + diskio.c and ff_gen_drv.c/.h: update to prevent multiple initialization. + + +### V1.0.0/18-February-2014 ### +=============================== + + First R0.10 customized version for STM32Cube solution. + + + *

© COPYRIGHT STMicroelectronics

+ */ diff --git a/Src/bsp_driver_sd.c b/Src/bsp_driver_sd.c index 720faf7..7638f8d 100644 --- a/Src/bsp_driver_sd.c +++ b/Src/bsp_driver_sd.c @@ -10,7 +10,7 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2020 STMicroelectronics. + *

© Copyright (c) 2021 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under Ultimate Liberty license @@ -33,7 +33,7 @@ /* Includes ------------------------------------------------------------------*/ #include "bsp_driver_sd.h" -/* Extern variables ---------------------------------------------------------*/ +/* Extern variables ---------------------------------------------------------*/ extern SD_HandleTypeDef hsd; @@ -110,7 +110,7 @@ __weak uint8_t BSP_SD_ReadBlocks(uint32_t *pData, uint32_t ReadAddr, uint32_t Nu sd_state = MSD_ERROR; } - return sd_state; + return sd_state; } /* USER CODE BEGIN BeforeWriteBlocksSection */ @@ -128,12 +128,12 @@ __weak uint8_t BSP_SD_WriteBlocks(uint32_t *pData, uint32_t WriteAddr, uint32_t { uint8_t sd_state = MSD_OK; - if (HAL_SD_WriteBlocks(&hsd, (uint8_t *)pData, WriteAddr, NumOfBlocks, Timeout) != HAL_OK) + if (HAL_SD_WriteBlocks(&hsd, (uint8_t *)pData, WriteAddr, NumOfBlocks, Timeout) != HAL_OK) { sd_state = MSD_ERROR; } - return sd_state; + return sd_state; } /* USER CODE BEGIN BeforeReadDMABlocksSection */ @@ -143,20 +143,20 @@ __weak uint8_t BSP_SD_WriteBlocks(uint32_t *pData, uint32_t WriteAddr, uint32_t * @brief Reads block(s) from a specified address in an SD card, in DMA mode. * @param pData: Pointer to the buffer that will contain the data to transmit * @param ReadAddr: Address from where data is to be read - * @param NumOfBlocks: Number of SD blocks to read + * @param NumOfBlocks: Number of SD blocks to read * @retval SD status */ __weak uint8_t BSP_SD_ReadBlocks_DMA(uint32_t *pData, uint32_t ReadAddr, uint32_t NumOfBlocks) { uint8_t sd_state = MSD_OK; - + /* Read block(s) in DMA transfer mode */ if (HAL_SD_ReadBlocks_DMA(&hsd, (uint8_t *)pData, ReadAddr, NumOfBlocks) != HAL_OK) { sd_state = MSD_ERROR; } - - return sd_state; + + return sd_state; } /* USER CODE BEGIN BeforeWriteDMABlocksSection */ @@ -166,27 +166,27 @@ __weak uint8_t BSP_SD_ReadBlocks_DMA(uint32_t *pData, uint32_t ReadAddr, uint32_ * @brief Writes block(s) to a specified address in an SD card, in DMA mode. * @param pData: Pointer to the buffer that will contain the data to transmit * @param WriteAddr: Address from where data is to be written - * @param NumOfBlocks: Number of SD blocks to write + * @param NumOfBlocks: Number of SD blocks to write * @retval SD status */ __weak uint8_t BSP_SD_WriteBlocks_DMA(uint32_t *pData, uint32_t WriteAddr, uint32_t NumOfBlocks) { uint8_t sd_state = MSD_OK; - + /* Write block(s) in DMA transfer mode */ if (HAL_SD_WriteBlocks_DMA(&hsd, (uint8_t *)pData, WriteAddr, NumOfBlocks) != HAL_OK) { sd_state = MSD_ERROR; } - - return sd_state; + + return sd_state; } /* USER CODE BEGIN BeforeEraseSection */ /* can be used to modify previous code / undefine following code / add code */ /* USER CODE END BeforeEraseSection */ /** - * @brief Erases the specified memory area of the given SD card. + * @brief Erases the specified memory area of the given SD card. * @param StartAddr: Start byte address * @param EndAddr: End byte address * @retval SD status @@ -195,7 +195,7 @@ __weak uint8_t BSP_SD_Erase(uint32_t StartAddr, uint32_t EndAddr) { uint8_t sd_state = MSD_OK; - if (HAL_SD_Erase(&hsd, StartAddr, EndAddr) != HAL_OK) + if (HAL_SD_Erase(&hsd, StartAddr, EndAddr) != HAL_OK) { sd_state = MSD_ERROR; } @@ -219,7 +219,7 @@ __weak uint8_t BSP_SD_GetCardState(void) /** * @brief Get SD information about specific SD card. * @param CardInfo: Pointer to HAL_SD_CardInfoTypedef structure - * @retval None + * @retval None */ __weak void BSP_SD_GetCardInfo(HAL_SD_CardInfoTypeDef *CardInfo) { @@ -302,7 +302,7 @@ __weak uint8_t BSP_SD_IsDetected(void) { __IO uint8_t status = SD_PRESENT; - if (BSP_PlatformIsDetected() == 0x0) + if (BSP_PlatformIsDetected() == 0x0) { status = SD_NOT_PRESENT; } diff --git a/Src/fatfs.c b/Src/fatfs.c index c0808d2..7de69ab 100644 --- a/Src/fatfs.c +++ b/Src/fatfs.c @@ -5,7 +5,7 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2020 STMicroelectronics. + *

© Copyright (c) 2021 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under Ultimate Liberty license @@ -25,9 +25,9 @@ FIL SDFile; /* File object for SD */ /* USER CODE BEGIN Variables */ -/* USER CODE END Variables */ +/* USER CODE END Variables */ -void MX_FATFS_Init(void) +void MX_FATFS_Init(void) { /*## FatFS: Link the SD driver ###########################*/ retSD = FATFS_LinkDriver(&SD_Driver, SDPath); @@ -38,7 +38,7 @@ void MX_FATFS_Init(void) } /** - * @brief Gets Time from RTC + * @brief Gets Time from RTC * @param None * @retval Time in DWORD */ @@ -46,7 +46,7 @@ DWORD get_fattime(void) { /* USER CODE BEGIN get_fattime */ return 0; - /* USER CODE END get_fattime */ + /* USER CODE END get_fattime */ } /* USER CODE BEGIN Application */ diff --git a/Src/fatfs_platform.c b/Src/fatfs_platform.c index c5076a9..354bca9 100644 --- a/Src/fatfs_platform.c +++ b/Src/fatfs_platform.c @@ -5,7 +5,7 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2020 STMicroelectronics. + *

© Copyright (c) 2021 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under Ultimate Liberty license @@ -26,6 +26,6 @@ uint8_t BSP_PlatformIsDetected(void) { } /* USER CODE BEGIN 1 */ /* user code can be inserted here */ - /* USER CODE END 1 */ + /* USER CODE END 1 */ return status; -} +} diff --git a/Src/main.c b/Src/main.c index 81b5447..288d562 100644 --- a/Src/main.c +++ b/Src/main.c @@ -17,7 +17,6 @@ ****************************************************************************** */ /* USER CODE END Header */ - /* Includes ------------------------------------------------------------------*/ #include "main.h" #include "fatfs.h" @@ -278,12 +277,13 @@ void SystemClock_Config(void) RCC_OscInitTypeDef RCC_OscInitStruct = {0}; RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; - /** Configure the main internal regulator output voltage + /** Configure the main internal regulator output voltage */ __HAL_RCC_PWR_CLK_ENABLE(); __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); - /** Initializes the CPU, AHB and APB busses clocks - */ + /** Initializes the RCC Oscillators according to the specified parameters + * in the RCC_OscInitTypeDef structure. + */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; RCC_OscInitStruct.HSEState = RCC_HSE_ON; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; @@ -296,7 +296,7 @@ void SystemClock_Config(void) { Error_Handler(); } - /** Initializes the CPU, AHB and APB busses clocks + /** Initializes the CPU, AHB and APB buses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; @@ -439,7 +439,7 @@ static void MX_GPIO_Init(void) HAL_GPIO_WritePin(GPIOC, GPIO_PIN_4|GPIO_PIN_5, GPIO_PIN_RESET); /*Configure GPIO pin Output Level */ - HAL_GPIO_WritePin(GPIOB, GPIO_PIN_11|GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14 + HAL_GPIO_WritePin(GPIOB, GPIO_PIN_11|GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14 |GPIO_PIN_15, GPIO_PIN_RESET); /*Configure GPIO pin Output Level */ @@ -477,17 +477,17 @@ static void MX_GPIO_Init(void) GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); - /*Configure GPIO pins : PA0 PA1 PA8 PA14 + /*Configure GPIO pins : PA0 PA1 PA8 PA14 PA15 */ - GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_8|GPIO_PIN_14 + GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_8|GPIO_PIN_14 |GPIO_PIN_15; GPIO_InitStruct.Mode = GPIO_MODE_INPUT; GPIO_InitStruct.Pull = GPIO_NOPULL; HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); - /*Configure GPIO pins : PA4 PA5 PA6 PA9 + /*Configure GPIO pins : PA4 PA5 PA6 PA9 PA10 */ - GPIO_InitStruct.Pin = GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_9 + GPIO_InitStruct.Pin = GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_9 |GPIO_PIN_10; GPIO_InitStruct.Mode = GPIO_MODE_INPUT; GPIO_InitStruct.Pull = GPIO_PULLDOWN; @@ -500,9 +500,9 @@ static void MX_GPIO_Init(void) GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); - /*Configure GPIO pins : PB11 PB12 PB13 PB14 + /*Configure GPIO pins : PB11 PB12 PB13 PB14 PB15 */ - GPIO_InitStruct.Pin = GPIO_PIN_11|GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14 + GPIO_InitStruct.Pin = GPIO_PIN_11|GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14 |GPIO_PIN_15; GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; GPIO_InitStruct.Pull = GPIO_NOPULL; @@ -528,17 +528,17 @@ static void MX_GPIO_Init(void) GPIO_InitStruct.Pull = GPIO_PULLDOWN; HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); - /*Configure GPIO pins : PD0 PD1 PD3 PD4 + /*Configure GPIO pins : PD0 PD1 PD3 PD4 PD5 PD6 PD7 */ - GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_3|GPIO_PIN_4 + GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_3|GPIO_PIN_4 |GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7; GPIO_InitStruct.Mode = GPIO_MODE_INPUT; GPIO_InitStruct.Pull = GPIO_NOPULL; HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); - /*Configure GPIO pins : PB3 PB4 PB5 PB8 + /*Configure GPIO pins : PB3 PB4 PB5 PB8 PB9 */ - GPIO_InitStruct.Pin = GPIO_PIN_3|GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_8 + GPIO_InitStruct.Pin = GPIO_PIN_3|GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_8 |GPIO_PIN_9; GPIO_InitStruct.Mode = GPIO_MODE_INPUT; GPIO_InitStruct.Pull = GPIO_NOPULL; @@ -570,7 +570,7 @@ void Error_Handler(void) * @retval None */ void assert_failed(uint8_t *file, uint32_t line) -{ +{ /* USER CODE BEGIN 6 */ /* User can add his own implementation to report the file name and line number, tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ diff --git a/Src/sd_diskio.c b/Src/sd_diskio.c index 8ae2755..40424fc 100644 --- a/Src/sd_diskio.c +++ b/Src/sd_diskio.c @@ -18,7 +18,7 @@ */ /* USER CODE END Header */ -/* Note: code generation based on sd_diskio_template_bspv1.c v2.1.4 +/* Note: code generation based on sd_diskio_template_bspv1.c v2.1.4 as "Use dma template" is disabled. */ /* USER CODE BEGIN firstSection */ @@ -45,7 +45,7 @@ /* * Depending on the use case, the SD card initialization could be done at the * application level: if it is the case define the flag below to disable - * the BSP_SD_Init() call in the SD_Initialize() and add a call to + * the BSP_SD_Init() call in the SD_Initialize() and add a call to * BSP_SD_Init() elsewhere in the application. */ /* USER CODE BEGIN disableSDInit */ @@ -107,7 +107,7 @@ static DSTATUS SD_CheckStatus(BYTE lun) */ DSTATUS SD_initialize(BYTE lun) { -Stat = STA_NOINIT; +Stat = STA_NOINIT; #if !defined(DISABLE_SD_INIT) @@ -144,7 +144,7 @@ DSTATUS SD_status(BYTE lun) * @param count: Number of sectors to read (1..128) * @retval DRESULT: Operation result */ - + DRESULT SD_read(BYTE lun, BYTE *buff, DWORD sector, UINT count) { DRESULT res = RES_ERROR; @@ -175,7 +175,7 @@ DRESULT SD_read(BYTE lun, BYTE *buff, DWORD sector, UINT count) * @retval DRESULT: Operation result */ #if _USE_WRITE == 1 - + DRESULT SD_write(BYTE lun, const BYTE *buff, DWORD sector, UINT count) { DRESULT res = RES_ERROR; @@ -253,7 +253,7 @@ DRESULT SD_ioctl(BYTE lun, BYTE cmd, void *buff) /* can be used to modify previous code / undefine following code / add new code */ /* USER CODE END afterIoctlSection */ -/* USER CODE BEGIN lastSection */ +/* USER CODE BEGIN lastSection */ /* can be used to modify / undefine previous code or add new code */ /* USER CODE END lastSection */ diff --git a/Src/stm32f4xx_hal_msp.c b/Src/stm32f4xx_hal_msp.c index 27c7fff..46c7a97 100644 --- a/Src/stm32f4xx_hal_msp.c +++ b/Src/stm32f4xx_hal_msp.c @@ -91,11 +91,11 @@ void HAL_I2C_MspInit(I2C_HandleTypeDef* hi2c) /* USER CODE BEGIN I2C1_MspInit 0 */ /* USER CODE END I2C1_MspInit 0 */ - + __HAL_RCC_GPIOB_CLK_ENABLE(); - /**I2C1 GPIO Configuration + /**I2C1 GPIO Configuration PB6 ------> I2C1_SCL - PB7 ------> I2C1_SDA + PB7 ------> I2C1_SDA */ GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7; GPIO_InitStruct.Mode = GPIO_MODE_AF_OD; @@ -128,12 +128,14 @@ void HAL_I2C_MspDeInit(I2C_HandleTypeDef* hi2c) /* USER CODE END I2C1_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_I2C1_CLK_DISABLE(); - - /**I2C1 GPIO Configuration + + /**I2C1 GPIO Configuration PB6 ------> I2C1_SCL - PB7 ------> I2C1_SDA + PB7 ------> I2C1_SDA */ - HAL_GPIO_DeInit(GPIOB, GPIO_PIN_6|GPIO_PIN_7); + HAL_GPIO_DeInit(GPIOB, GPIO_PIN_6); + + HAL_GPIO_DeInit(GPIOB, GPIO_PIN_7); /* USER CODE BEGIN I2C1_MspDeInit 1 */ @@ -158,18 +160,18 @@ void HAL_SD_MspInit(SD_HandleTypeDef* hsd) /* USER CODE END SDIO_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_SDIO_CLK_ENABLE(); - + __HAL_RCC_GPIOC_CLK_ENABLE(); __HAL_RCC_GPIOD_CLK_ENABLE(); - /**SDIO GPIO Configuration + /**SDIO GPIO Configuration PC8 ------> SDIO_D0 PC9 ------> SDIO_D1 PC10 ------> SDIO_D2 PC11 ------> SDIO_D3 PC12 ------> SDIO_CK - PD2 ------> SDIO_CMD + PD2 ------> SDIO_CMD */ - GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11 + GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11 |GPIO_PIN_12; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; GPIO_InitStruct.Pull = GPIO_NOPULL; @@ -206,16 +208,16 @@ void HAL_SD_MspDeInit(SD_HandleTypeDef* hsd) /* USER CODE END SDIO_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_SDIO_CLK_DISABLE(); - - /**SDIO GPIO Configuration + + /**SDIO GPIO Configuration PC8 ------> SDIO_D0 PC9 ------> SDIO_D1 PC10 ------> SDIO_D2 PC11 ------> SDIO_D3 PC12 ------> SDIO_CK - PD2 ------> SDIO_CMD + PD2 ------> SDIO_CMD */ - HAL_GPIO_DeInit(GPIOC, GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11 + HAL_GPIO_DeInit(GPIOC, GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11 |GPIO_PIN_12); HAL_GPIO_DeInit(GPIOD, GPIO_PIN_2); @@ -243,11 +245,11 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) /* USER CODE END USART2_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_USART2_CLK_ENABLE(); - + __HAL_RCC_GPIOA_CLK_ENABLE(); - /**USART2 GPIO Configuration + /**USART2 GPIO Configuration PA2 ------> USART2_TX - PA3 ------> USART2_RX + PA3 ------> USART2_RX */ GPIO_InitStruct.Pin = GPIO_PIN_2|GPIO_PIN_3; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -281,10 +283,10 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) /* USER CODE END USART2_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_USART2_CLK_DISABLE(); - - /**USART2 GPIO Configuration + + /**USART2 GPIO Configuration PA2 ------> USART2_TX - PA3 ------> USART2_RX + PA3 ------> USART2_RX */ HAL_GPIO_DeInit(GPIOA, GPIO_PIN_2|GPIO_PIN_3); diff --git a/Src/stm32f4xx_it.c b/Src/stm32f4xx_it.c index 1b15265..25d7c63 100644 --- a/Src/stm32f4xx_it.c +++ b/Src/stm32f4xx_it.c @@ -63,7 +63,7 @@ extern UART_HandleTypeDef huart2; /* USER CODE END EV */ /******************************************************************************/ -/* Cortex-M4 Processor Interruption and Exception Handlers */ +/* Cortex-M4 Processor Interruption and Exception Handlers */ /******************************************************************************/ /** * @brief This function handles Non maskable interrupt. diff --git a/Src/usb_device.c b/Src/usb_device.c index 61b2e52..c72a1c4 100644 --- a/Src/usb_device.c +++ b/Src/usb_device.c @@ -67,7 +67,7 @@ void MX_USB_DEVICE_Init(void) /* USER CODE BEGIN USB_DEVICE_Init_PreTreatment */ /* USER CODE END USB_DEVICE_Init_PreTreatment */ - + /* Init Device Library, add supported class and start the library. */ if (USBD_Init(&hUsbDeviceFS, &FS_Desc, DEVICE_FS) != USBD_OK) { diff --git a/Src/usbd_conf.c b/Src/usbd_conf.c index da9f789..c4a4b22 100644 --- a/Src/usbd_conf.c +++ b/Src/usbd_conf.c @@ -73,11 +73,11 @@ void HAL_PCD_MspInit(PCD_HandleTypeDef* pcdHandle) /* USER CODE BEGIN USB_OTG_FS_MspInit 0 */ /* USER CODE END USB_OTG_FS_MspInit 0 */ - + __HAL_RCC_GPIOA_CLK_ENABLE(); - /**USB_OTG_FS GPIO Configuration + /**USB_OTG_FS GPIO Configuration PA11 ------> USB_OTG_FS_DM - PA12 ------> USB_OTG_FS_DP + PA12 ------> USB_OTG_FS_DP */ GPIO_InitStruct.Pin = GPIO_PIN_11|GPIO_PIN_12; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -107,10 +107,10 @@ void HAL_PCD_MspDeInit(PCD_HandleTypeDef* pcdHandle) /* USER CODE END USB_OTG_FS_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_USB_OTG_FS_CLK_DISABLE(); - - /**USB_OTG_FS GPIO Configuration + + /**USB_OTG_FS GPIO Configuration PA11 ------> USB_OTG_FS_DM - PA12 ------> USB_OTG_FS_DP + PA12 ------> USB_OTG_FS_DP */ HAL_GPIO_DeInit(GPIOA, GPIO_PIN_11|GPIO_PIN_12); @@ -191,7 +191,7 @@ static void PCD_ResetCallback(PCD_HandleTypeDef *hpcd) #else void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ -{ +{ USBD_SpeedTypeDef speed = USBD_SPEED_FULL; if ( hpcd->Init.speed == PCD_SPEED_HIGH) @@ -330,7 +330,7 @@ USBD_StatusTypeDef USBD_LL_Init(USBD_HandleTypeDef *pdev) /* Link the driver to the stack. */ hpcd_USB_OTG_FS.pData = pdev; pdev->pData = &hpcd_USB_OTG_FS; - + hpcd_USB_OTG_FS.Instance = USB_OTG_FS; hpcd_USB_OTG_FS.Init.dev_endpoints = 4; hpcd_USB_OTG_FS.Init.speed = PCD_SPEED_FULL; @@ -381,12 +381,12 @@ USBD_StatusTypeDef USBD_LL_DeInit(USBD_HandleTypeDef *pdev) hal_status = HAL_PCD_DeInit(pdev->pData); usb_status = USBD_Get_USB_Status(hal_status); - - return usb_status; + + return usb_status; } /** - * @brief Starts the low level portion of the device driver. + * @brief Starts the low level portion of the device driver. * @param pdev: Device handle * @retval USBD status */ @@ -394,11 +394,11 @@ USBD_StatusTypeDef USBD_LL_Start(USBD_HandleTypeDef *pdev) { HAL_StatusTypeDef hal_status = HAL_OK; USBD_StatusTypeDef usb_status = USBD_OK; - + hal_status = HAL_PCD_Start(pdev->pData); - - usb_status = USBD_Get_USB_Status(hal_status); - + + usb_status = USBD_Get_USB_Status(hal_status); + return usb_status; } @@ -413,9 +413,9 @@ USBD_StatusTypeDef USBD_LL_Stop(USBD_HandleTypeDef *pdev) USBD_StatusTypeDef usb_status = USBD_OK; hal_status = HAL_PCD_Stop(pdev->pData); - + usb_status = USBD_Get_USB_Status(hal_status); - + return usb_status; } @@ -435,7 +435,7 @@ USBD_StatusTypeDef USBD_LL_OpenEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uin hal_status = HAL_PCD_EP_Open(pdev->pData, ep_addr, ep_mps, ep_type); usb_status = USBD_Get_USB_Status(hal_status); - + return usb_status; } @@ -449,12 +449,12 @@ USBD_StatusTypeDef USBD_LL_CloseEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr) { HAL_StatusTypeDef hal_status = HAL_OK; USBD_StatusTypeDef usb_status = USBD_OK; - + hal_status = HAL_PCD_EP_Close(pdev->pData, ep_addr); - - usb_status = USBD_Get_USB_Status(hal_status); - - return usb_status; + + usb_status = USBD_Get_USB_Status(hal_status); + + return usb_status; } /** @@ -467,12 +467,12 @@ USBD_StatusTypeDef USBD_LL_FlushEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr) { HAL_StatusTypeDef hal_status = HAL_OK; USBD_StatusTypeDef usb_status = USBD_OK; - + hal_status = HAL_PCD_EP_Flush(pdev->pData, ep_addr); - - usb_status = USBD_Get_USB_Status(hal_status); - - return usb_status; + + usb_status = USBD_Get_USB_Status(hal_status); + + return usb_status; } /** @@ -485,12 +485,12 @@ USBD_StatusTypeDef USBD_LL_StallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr) { HAL_StatusTypeDef hal_status = HAL_OK; USBD_StatusTypeDef usb_status = USBD_OK; - + hal_status = HAL_PCD_EP_SetStall(pdev->pData, ep_addr); usb_status = USBD_Get_USB_Status(hal_status); - - return usb_status; + + return usb_status; } /** @@ -503,12 +503,12 @@ USBD_StatusTypeDef USBD_LL_ClearStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_add { HAL_StatusTypeDef hal_status = HAL_OK; USBD_StatusTypeDef usb_status = USBD_OK; - + hal_status = HAL_PCD_EP_ClrStall(pdev->pData, ep_addr); - - usb_status = USBD_Get_USB_Status(hal_status); - - return usb_status; + + usb_status = USBD_Get_USB_Status(hal_status); + + return usb_status; } /** @@ -520,14 +520,14 @@ USBD_StatusTypeDef USBD_LL_ClearStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_add uint8_t USBD_LL_IsStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr) { PCD_HandleTypeDef *hpcd = (PCD_HandleTypeDef*) pdev->pData; - + if((ep_addr & 0x80) == 0x80) { - return hpcd->IN_ep[ep_addr & 0x7F].is_stall; + return hpcd->IN_ep[ep_addr & 0x7F].is_stall; } else { - return hpcd->OUT_ep[ep_addr & 0x7F].is_stall; + return hpcd->OUT_ep[ep_addr & 0x7F].is_stall; } } @@ -541,12 +541,12 @@ USBD_StatusTypeDef USBD_LL_SetUSBAddress(USBD_HandleTypeDef *pdev, uint8_t dev_a { HAL_StatusTypeDef hal_status = HAL_OK; USBD_StatusTypeDef usb_status = USBD_OK; - + hal_status = HAL_PCD_SetAddress(pdev->pData, dev_addr); - + usb_status = USBD_Get_USB_Status(hal_status); - - return usb_status; + + return usb_status; } /** @@ -554,7 +554,7 @@ USBD_StatusTypeDef USBD_LL_SetUSBAddress(USBD_HandleTypeDef *pdev, uint8_t dev_a * @param pdev: Device handle * @param ep_addr: Endpoint number * @param pbuf: Pointer to data to be sent - * @param size: Data size + * @param size: Data size * @retval USBD status */ USBD_StatusTypeDef USBD_LL_Transmit(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t *pbuf, uint32_t size) @@ -563,10 +563,10 @@ USBD_StatusTypeDef USBD_LL_Transmit(USBD_HandleTypeDef *pdev, uint8_t ep_addr, u USBD_StatusTypeDef usb_status = USBD_OK; hal_status = HAL_PCD_EP_Transmit(pdev->pData, ep_addr, pbuf, size); - - usb_status = USBD_Get_USB_Status(hal_status); - - return usb_status; + + usb_status = USBD_Get_USB_Status(hal_status); + + return usb_status; } /** @@ -583,10 +583,10 @@ USBD_StatusTypeDef USBD_LL_PrepareReceive(USBD_HandleTypeDef *pdev, uint8_t ep_a USBD_StatusTypeDef usb_status = USBD_OK; hal_status = HAL_PCD_EP_Receive(pdev->pData, ep_addr, pbuf, size); - - usb_status = USBD_Get_USB_Status(hal_status); - - return usb_status; + + usb_status = USBD_Get_USB_Status(hal_status); + + return usb_status; } /** diff --git a/Src/usbd_desc.c b/Src/usbd_desc.c index 6abe38a..6214f50 100644 --- a/Src/usbd_desc.c +++ b/Src/usbd_desc.c @@ -97,19 +97,18 @@ /** * @} */ - + /** @defgroup USBD_DESC_Private_FunctionPrototypes USBD_DESC_Private_FunctionPrototypes * @brief Private functions declaration. * @{ */ - + static void Get_SerialNum(void); static void IntToUnicode(uint32_t value, uint8_t * pbuf, uint8_t len); - + /** * @} - */ - + */ /** @defgroup USBD_DESC_Private_FunctionPrototypes USBD_DESC_Private_FunctionPrototypes * @brief Private functions declaration for FS. @@ -235,7 +234,7 @@ __ALIGN_BEGIN uint8_t USBD_LangIDDesc[USB_LEN_LANGID_STR_DESC] __ALIGN_END = __ALIGN_BEGIN uint8_t USBD_StrDesc[USBD_MAX_STR_DESC_SIZ] __ALIGN_END; #if defined ( __ICCARM__ ) /*!< IAR Compiler */ - #pragma data_alignment=4 + #pragma data_alignment=4 #endif __ALIGN_BEGIN uint8_t USBD_StringSerial[USB_SIZ_STRING_SERIAL] __ALIGN_END = { USB_SIZ_STRING_SERIAL, @@ -383,8 +382,8 @@ uint8_t * USBD_FS_USR_BOSDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) #endif /* (USBD_LPM_ENABLED == 1) */ /** - * @brief Create the serial number string descriptor - * @param None + * @brief Create the serial number string descriptor + * @param None * @retval None */ static void Get_SerialNum(void) @@ -405,9 +404,9 @@ static void Get_SerialNum(void) } /** - * @brief Convert Hex 32Bits value into char + * @brief Convert Hex 32Bits value into char * @param value: value to convert - * @param pbuf: pointer to the buffer + * @param pbuf: pointer to the buffer * @param len: buffer length * @retval None */ diff --git a/z80-stm32-v2.ioc b/z80-stm32-v2.ioc index 0ff53a1..4875ac3 100644 --- a/z80-stm32-v2.ioc +++ b/z80-stm32-v2.ioc @@ -41,8 +41,8 @@ PA8.Locked=true FATFS0.BSP.i2caddr=0 PA4.Locked=true PC13-ANTI_TAMP.Signal=GPIO_Input -ProjectManager.FirmwarePackage=STM32Cube FW_F4 V1.25.0 -MxDb.Version=DB.5.0.60 +ProjectManager.FirmwarePackage=STM32Cube FW_F4 V1.25.2 +MxDb.Version=DB.6.0.10 ProjectManager.BackupPrevious=false PA5.GPIO_PuPd=GPIO_PULLDOWN PC9.Mode=SD_4_bits_Wide_bus @@ -350,7 +350,7 @@ RCC.VCOOutputFreq_Value=336000000 PC13-ANTI_TAMP.Locked=true PD11.GPIOParameters=GPIO_Speed RCC.APB2Freq_Value=84000000 -MxCube.Version=5.6.0 +MxCube.Version=6.1.0 VP_SYS_VS_Systick.Mode=SysTick PA10.GPIOParameters=GPIO_PuPd PH1-OSC_OUT.Signal=RCC_OSC_OUT @@ -359,7 +359,7 @@ PA4.GPIOParameters=GPIO_PuPd PE5.Locked=true PE6.Signal=GPIO_Input RCC.IPParameters=48MHZClocksFreq_Value,AHBFreq_Value,APB1CLKDivider,APB1Freq_Value,APB1TimFreq_Value,APB2CLKDivider,APB2Freq_Value,APB2TimFreq_Value,CortexFreq_Value,EthernetFreq_Value,FCLKCortexFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,HSI_VALUE,I2SClocksFreq_Value,LSI_VALUE,MCO2PinFreq_Value,PLLCLKFreq_Value,PLLM,PLLN,PLLQ,PLLQCLKFreq_Value,RTCFreq_Value,RTCHSEDivFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,VCOI2SOutputFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value,VcooutputI2S -ProjectManager.AskForMigrate=true +ProjectManager.AskForMigrate=false Mcu.Name=STM32F407V(E-G)Tx PE0.Signal=GPIO_Input PA2.Signal=USART2_TX