//
// Copyright (c) 2002 Xilinx, Inc.  All rights reserved. 
// Xilinx, Inc. 
//
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A 
// COURTESY TO YOU.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS 
// ONE POSSIBLE   IMPLEMENTATION OF THIS FEATURE, APPLICATION OR 
// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION 
// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE 
// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. 
// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO 
// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO 
// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE 
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY 
// AND FITNESS FOR A PARTICULAR PURPOSE. 
//
// $Id: profile_mcount_mb.S,v 1.1.2.1 2011/05/17 04:37:58 sadanan Exp $
//
	.globl _mcount 
	.text 
	.align 2
	.ent _mcount

	#ifndef PROFILE_NO_GRAPH
	
_mcount:
	addi r1, r1, -48
	swi r11, r1, 44
	swi r12, r1, 40
	swi r5, r1, 36
	swi r6, r1, 32
	swi r7, r1, 28
	swi r8, r1, 24
	swi r9, r1, 20
	swi r10, r1, 16
	swi r16, r1, 12
	add r5, r0, r15
	brlid r15, mcount
	add r6, r0, r16

	lwi r11, r1, 44
	lwi r12, r1, 40	
	lwi r5, r1, 36
	lwi r6, r1, 32
	lwi r7, r1, 28
	lwi r8, r1, 24
	lwi r9, r1, 20
	lwi r10, r1, 16
	lwi r16, r1, 12
	rtbd r16, 4
	addi r1, r1, 48

	#endif	/* PROFILE_NO_GRAPH */
	
	.end _mcount 
