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Reorganized files and updated gitignore

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Dreaded_X
2020-09-20 21:11:33 +02:00
parent 03b78a078e
commit 0f312b8085
15 changed files with 103 additions and 352 deletions
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117
src/async_fifo.v Normal file
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`timescale 1ns / 1ps
/*
This file was generated automatically by Alchitry Labs version 1.2.0.
Do not edit this file directly. Instead edit the original Lucid source.
This is a temporary file and any changes made to it will be destroyed.
*/
/*
Parameters:
SIZE = DATA_IN_SIZE
DEPTH = 16
*/
module async_fifo (
input wclk,
input wrst,
input [29:0] din,
input wput,
output reg full,
input rclk,
input rrst,
output reg [29:0] dout,
input rget,
output reg empty
);
localparam SIZE = 5'h1e;
localparam DEPTH = 5'h10;
localparam ADDR_SIZE = 3'h4;
reg [3:0] M_waddr_d, M_waddr_q = 1'h0;
reg [7:0] M_wsync_d, M_wsync_q = 1'h0;
reg [3:0] M_raddr_d, M_raddr_q = 1'h0;
reg [7:0] M_rsync_d, M_rsync_q = 1'h0;
wire [30-1:0] M_ram_read_data;
reg [1-1:0] M_ram_wclk;
reg [4-1:0] M_ram_waddr;
reg [30-1:0] M_ram_write_data;
reg [1-1:0] M_ram_write_en;
reg [1-1:0] M_ram_rclk;
reg [4-1:0] M_ram_raddr;
simple_dual_ram #(.SIZE(5'h1e), .DEPTH(5'h10)) ram (
.wclk(M_ram_wclk),
.waddr(M_ram_waddr),
.write_data(M_ram_write_data),
.write_en(M_ram_write_en),
.rclk(M_ram_rclk),
.raddr(M_ram_raddr),
.read_data(M_ram_read_data)
);
reg [3:0] waddr_gray;
reg [3:0] wnext_gray;
reg [3:0] raddr_gray;
reg wrdy;
reg rrdy;
always @* begin
M_rsync_d = M_rsync_q;
M_wsync_d = M_wsync_q;
M_waddr_d = M_waddr_q;
M_raddr_d = M_raddr_q;
M_ram_wclk = wclk;
M_ram_rclk = rclk;
M_ram_write_en = 1'h0;
waddr_gray = (M_waddr_q >> 1'h1) ^ M_waddr_q;
wnext_gray = ((M_waddr_q + 1'h1) >> 1'h1) ^ (M_waddr_q + 1'h1);
raddr_gray = (M_raddr_q >> 1'h1) ^ M_raddr_q;
M_rsync_d = {M_rsync_q[0+3-:4], waddr_gray};
M_wsync_d = {M_wsync_q[0+3-:4], raddr_gray};
wrdy = wnext_gray != M_wsync_q[4+3-:4];
rrdy = raddr_gray != M_rsync_q[4+3-:4];
full = !wrdy;
empty = !rrdy;
M_ram_waddr = M_waddr_q;
M_ram_raddr = M_raddr_q;
M_ram_write_data = din;
if (wput && wrdy) begin
M_waddr_d = M_waddr_q + 1'h1;
M_ram_write_en = 1'h1;
end
if (rget && rrdy) begin
M_raddr_d = M_raddr_q + 1'h1;
M_ram_raddr = M_raddr_q + 1'h1;
end
dout = M_ram_read_data;
end
always @(posedge rclk) begin
if (rrst == 1'b1) begin
M_raddr_q <= 1'h0;
M_rsync_q <= 1'h0;
end else begin
M_raddr_q <= M_raddr_d;
M_rsync_q <= M_rsync_d;
end
end
always @(posedge wclk) begin
if (wrst == 1'b1) begin
M_waddr_q <= 1'h0;
M_wsync_q <= 1'h0;
end else begin
M_waddr_q <= M_waddr_d;
M_wsync_q <= M_wsync_d;
end
end
endmodule

226
src/char_map.v Normal file
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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 20:18:41 09/13/2020
// Design Name:
// Module Name: char_map
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module char_map(
input clk,
input [7:0] index,
output reg [255:0] char
);
wire [255:0] char_data [94:0];
always @(posedge clk) begin
char <= char_data[index];
end
assign char_data[ 0] = 256'h0000000000000000000000000000000000000000000000000000000000000000; //
assign char_data[ 1] = 256'h0000000007000f800f800f800f800f8007000700000000000700070007000000; // !
assign char_data[ 2] = 256'h00000e380e380e380e3806300000000000000000000000000000000000000000; // "
assign char_data[ 3] = 256'h00000c300c300c307ffe7ffe0c300c300c300c307ffe7ffe0c300c300c300000; // #
assign char_data[ 4] = 256'h0000024002400ff81ff81a401a401ff00ff8025802581ff81ff0024002400000; // $
assign char_data[ 5] = 256'h0000000000000e100e300e7000e001c0038007000e700c700870000000000000; // %
assign char_data[ 6] = 256'h000000000f001980198019800f000f080f9819f818f018e019f00f9800000000; // &
assign char_data[ 7] = 256'h000000000700070007000e000000000000000000000000000000000000000000; // '
assign char_data[ 8] = 256'h0000000000f001c0038007000e000e000e000e000700038001c000f000000000; // (
assign char_data[ 9] = 256'h000000000f00038001c000e0007000700070007000e001c003800f0000000000; // )
assign char_data[10] = 256'h0000000001801188099007e007e03ffc3ffc07e007e009901188018000000000; // *
assign char_data[11] = 256'h00000000000001800180018001801ff81ff80180018001800180000000000000; // +
assign char_data[12] = 256'h000000000000000000000000000000000000000000000700070007000e000000; // ,
assign char_data[13] = 256'h00000000000000000000000000001ff81ff80000000000000000000000000000; // -
assign char_data[14] = 256'h0000000000000000000000000000000000000000000007000700070000000000; // .
assign char_data[15] = 256'h0000000000020006000e001c0038007000e001c0038007000e001c0000000000; // /
assign char_data[16] = 256'h000000000ff01c381c781cf81cf81db81db81f381f381e381c380ff000000000; // 0
assign char_data[17] = 256'h000000000180018003801f801f800380038003800380038003801ff000000000; // 1
assign char_data[18] = 256'h000000000fe01c701c380038007000e001c0038007000e381c381ff800000000; // 2
assign char_data[19] = 256'h000000000fe01c701c380038007003e003e0007000381c381c700fe000000000; // 3
assign char_data[20] = 256'h0000000000e001e003e006e00ce018e01ff81ff800e000e000e003f800000000; // 4
assign char_data[21] = 256'h000000001ff81c001c001c001c001fe01ff0007800381c381c700fe000000000; // 5
assign char_data[22] = 256'h0000000003e007000e001c001c001ff01ff81c381c381c381c380ff000000000; // 6
assign char_data[23] = 256'h000000001ffc1c1c1c1c1c1c001c0038007000e001c003800380038000000000; // 7
assign char_data[24] = 256'h000000000ff01c381c381c381f3807e007e01cf81c381c381c380ff000000000; // 8
assign char_data[25] = 256'h000000000ff01c381c381c381c381ff80ff800380038007000e007c000000000; // 9
assign char_data[26] = 256'h0000000000000000038003800380000000000380038003800000000000000000; // :
assign char_data[27] = 256'h0000000000000000070007000700000000000700070007000e00000000000000; // ;
assign char_data[28] = 256'h0000007000e001c0038007000e001c001c000e000700038001c000e000700000; // <
assign char_data[29] = 256'h000000000000000000003ffc3ffc000000003ffc3ffc00000000000000000000; // =
assign char_data[30] = 256'h00001c000e000700038001c000e00070007000e001c0038007000e001c000000; // >
assign char_data[31] = 256'h000003c00ff01e7818380038007000e001c001c00000000001c001c001c00000; // ?
assign char_data[32] = 256'h000007f81c1c1c1c1c1c1c1c1cfc1cfc1cfc1cfc1c001c001c001c0007f80000; // @
assign char_data[33] = 256'h0000000003c007e00e701c381c381c381c381ff81c381c381c381c3800000000; // A
assign char_data[34] = 256'h000000001ff00e380e380e380e380ff00ff00e380e380e380e381ff000000000; // B
assign char_data[35] = 256'h0000000007f00e381c381c001c001c001c001c001c001c380e3807f000000000; // C
assign char_data[36] = 256'h000000001fe00e700e380e380e380e380e380e380e380e380e701fe000000000; // D
assign char_data[37] = 256'h000000001ff80e180e080e000e300ff00ff00e300e000e080e181ff800000000; // E
assign char_data[38] = 256'h000000001ff80e180e080e000e300ff00ff00e300e000e000e001f0000000000; // F
assign char_data[39] = 256'h0000000007f00e381c381c381c001c001c001cf81c381c380e3807f800000000; // G
assign char_data[40] = 256'h000000001c701c701c701c701c701ff01ff01c701c701c701c701c7000000000; // H
assign char_data[41] = 256'h000000001fc007000700070007000700070007000700070007001fc000000000; // I
assign char_data[42] = 256'h0000000001fc0070007000700070007000701c701c701c701c700fe000000000; // J
assign char_data[43] = 256'h000000001e380e380e700ee00fc00f800f800fc00ee00e700e381e3800000000; // K
assign char_data[44] = 256'h000000001f000e000e000e000e000e000e000e000e080e180e381ff800000000; // L
assign char_data[45] = 256'h000000001c1c1e3c1f7c1ffc1ffc1ddc1c9c1c1c1c1c1c1c1c1c1c1c00000000; // M
assign char_data[46] = 256'h000000001c1c1c1c1e1c1f1c1f9c1ddc1cfc1c7c1c3c1c1c1c1c1c1c00000000; // N
assign char_data[47] = 256'h0000000003e007700e381c1c1c1c1c1c1c1c1c1c1c1c0e38077003e000000000; // O
assign char_data[48] = 256'h000000001ff00e380e380e380e380ff00ff00e000e000e000e001f0000000000; // P
assign char_data[49] = 256'h0000000003e00f780e381c1c1c1c1c1c1c1c1c7c1cfc0ff80ff8003800fc0000; // Q
assign char_data[50] = 256'h000000001ff00e380e380e380e380ff00ff00e700e380e380e381e3800000000; // R
assign char_data[51] = 256'h000000000ff01c381c381c381c000fe007f000381c381c381c380ff000000000; // S
assign char_data[52] = 256'h000000001ffc19cc11c401c001c001c001c001c001c001c001c007f000000000; // T
assign char_data[53] = 256'h000000001c701c701c701c701c701c701c701c701c701c701c700fe000000000; // U
assign char_data[54] = 256'h000000001c701c701c701c701c701c701c701c701c700ee007c0038000000000; // V
assign char_data[55] = 256'h000000001c1c1c1c1c1c1c1c1c1c1c9c1c9c1c9c0ff80f780770077000000000; // W
assign char_data[56] = 256'h000000001c701c701c700ee007c00380038007c00ee01c701c701c7000000000; // X
assign char_data[57] = 256'h000000001c701c701c701c701c700ee007c003800380038003800fe000000000; // Y
assign char_data[58] = 256'h000000001ff81c381838107000e001c0038007000e081c181c381ff800000000; // Z
assign char_data[59] = 256'h0000000007f0070007000700070007000700070007000700070007f000000000; // [
assign char_data[60] = 256'h00000000100018001c000e000700038001c000e000700038001c000e00000000; // \
assign char_data[61] = 256'h0000000007f0007000700070007000700070007000700070007007f000000000; // ]
assign char_data[62] = 256'h0000018003c007e00e701c380000000000000000000000000000000000000000; // ^
assign char_data[63] = 256'h00000000000000000000000000000000000000000000000000000000ffffffff; // _
assign char_data[64] = 256'h000000001c001c00070007000000000000000000000000000000000000000000; // `
assign char_data[65] = 256'h0000000000000000000000000fe0007000700ff01c701c701c700f9800000000; // a
assign char_data[66] = 256'h000000001e000e000e000e000ff00e380e380e380e380e380e3819f000000000; // b
assign char_data[67] = 256'h0000000000000000000000000fe01c701c701c001c001c701c700fe000000000; // c
assign char_data[68] = 256'h0000000000f80070007000700ff01c701c701c701c701c701c700f9800000000; // d
assign char_data[69] = 256'h0000000000000000000000000fe01c701c701ff01c001c701c700fe000000000; // e
assign char_data[70] = 256'h0000000003e007700770070007001fe01fe007000700070007001fc000000000; // f
assign char_data[71] = 256'h0000000000000000000000000f981c701c701c701c700ff007f000701c700fe0; // g
assign char_data[72] = 256'h000000001e000e000e000e000ef00f380f380e380e380e380e381e3800000000; // h
assign char_data[73] = 256'h0000000001c001c001c000000fc001c001c001c001c001c001c00ff800000000; // i
assign char_data[74] = 256'h00000000007000700070000003f00070007000700070007000701c701c7007e0; // j
assign char_data[75] = 256'h000000001e000e000e000e000e380e700ee00fc00ee00e700e381e3800000000; // k
assign char_data[76] = 256'h000000000fc001c001c001c001c001c001c001c001c001c001c00ff800000000; // l
assign char_data[77] = 256'h0000000000000000000000001ff81c9c1c9c1c9c1c9c1c9c1c9c1c1c00000000; // m
assign char_data[78] = 256'h0000000000000000000000001fe01c701c701c701c701c701c701c7000000000; // n
assign char_data[79] = 256'h0000000000000000000000000fe01c701c701c701c701c701c700fe000000000; // o
assign char_data[80] = 256'h00000000000000000000000019f00e380e380e380e380e380ff00e000e001f00; // p
assign char_data[81] = 256'h0000000000000000000000001f3038e038e038e038e038e01fe000e000e001f0; // q
assign char_data[82] = 256'h0000000000000000000000001e700ff80f380e000e000e000e001f0000000000; // r
assign char_data[83] = 256'h0000000000000000000000000fe01c301c300f8003e0187018700fe000000000; // s
assign char_data[84] = 256'h0000000000000100030007001ff007000700070007000770077003e000000000; // t
assign char_data[85] = 256'h0000000000000000000000001c701c701c701c701c701c701c700f9800000000; // u
assign char_data[86] = 256'h0000000000000000000000001c701c701c701c701c700ee007c0038000000000; // v
assign char_data[87] = 256'h0000000000000000000000001c1c1c1c1c1c1c9c1c9c0f780770077000000000; // w
assign char_data[88] = 256'h0000000000000000000000001ce01ce00fc0078007800fc01ce01ce000000000; // x
assign char_data[89] = 256'h0000000000000000000000000e380e380e380e380e3807f003e000e001c01f80; // y
assign char_data[90] = 256'h0000000000000000000000001fe018e011c0038007000e201c601fe000000000; // z
assign char_data[91] = 256'h0000000001f803800380038007001c001c00070003800380038001f800000000; // {
assign char_data[92] = 256'h0000000003c003c003c003c003c00000000003c003c003c003c003c000000000; // |
assign char_data[93] = 256'h000000001f8001c001c001c000e00038003800e001c001c001c01f8000000000; // }
assign char_data[94] = 256'h000000001f1c3b9c39dc38f80000000000000000000000000000000000000000; // ~
//assign char_data[0] = 30'h00000000; //
//assign char_data[1] = 30'h1CE7380E; // !
//assign char_data[2] = 30'h14A00000; // "
//assign char_data[3] = 30'hAFABEA; // #
//assign char_data[4] = 30'h8FA38BE; // $
//assign char_data[5] = 30'h19D1173; // %
//assign char_data[6] = 30'h1905324D; // &
//assign char_data[7] = 30'h8400000; // '
//assign char_data[8] = 30'hCC63186; // (
//assign char_data[9] = 30'h186318CC; // )
//assign char_data[10] = 30'h4ABAA4; // *
//assign char_data[11] = 30'h427C84; // +
//assign char_data[12] = 30'h0x8C; // ,
//assign char_data[13] = 30'h3800; // -
//assign char_data[14] = 30'hC; // .
//assign char_data[15] = 30'hC663318; // /
//assign char_data[16] = 30'h3FBDEF7F; // 0
//assign char_data[17] = 30'h3C6318DF; // 1
//assign char_data[18] = 30'h3E3FE31F; // 2
//assign char_data[19] = 30'h3E378C7F; // 3
//assign char_data[20] = 30'h37BF8C63; // 4
//assign char_data[21] = 30'h3F8F8C7F; // 5
//assign char_data[22] = 30'h3F8FEF7F; // 6
//assign char_data[23] = 30'h3E33318C; // 7
//assign char_data[24] = 30'h3FBFEF7F; // 8
//assign char_data[25] = 30'h3FBF8C7F; // 9
//assign char_data[26] = 30'hC00180; // :
//assign char_data[27] = 30'hC00198; // ;
//assign char_data[28] = 30'h666186; // <
//assign char_data[29] = 30'h701C0; // =
//assign char_data[30] = 30'hC30CCC; // >
//assign char_data[31] = 30'h3C31B80C; // ?
//assign char_data[32] = 30'h1D1BDE0F; // @
//assign char_data[33] = 30'h1DBDFF7B; // A
//assign char_data[34] = 30'h3DBF6F7E; // B
//assign char_data[35] = 30'h1DBC636E; // C
//assign char_data[36] = 30'h3DBDEF7E; // D
//assign char_data[37] = 30'h1F8F630F; // E
//assign char_data[38] = 30'h1F8F6318; // F
//assign char_data[39] = 30'h1F8C6F6F; // G
//assign char_data[40] = 30'h37BFEF7B; // H
//assign char_data[41] = 30'h3CC6319E; // I
//assign char_data[42] = 30'h3E6318DC; // J
//assign char_data[43] = 30'h37BE6F7B; // K
//assign char_data[44] = 30'h318C631F; // L
//assign char_data[45] = 30'h37FFEF7B; // M
//assign char_data[46] = 30'h3DBDEF7B; // N
//assign char_data[47] = 30'h1DBDEF6E; // O
//assign char_data[48] = 30'h3DBDFB18; // P
//assign char_data[49] = 30'h1DBDEFCF; // Q
//assign char_data[50] = 30'h3DBDF37B; // R
//assign char_data[51] = 30'h1F870C7E; // S
//assign char_data[52] = 30'h3EC6318C; // T
//assign char_data[53] = 30'h37BDEF6E; // U
//assign char_data[54] = 30'h37BDEDC4; // V
//assign char_data[55] = 30'h37BDFFFB; // W
//assign char_data[56] = 30'h37B26F7B; // X
//assign char_data[57] = 30'h37BF8C7E; // Y
//assign char_data[58] = 30'h3E33331F; // Z
//assign char_data[59] = 30'h1CC6318E; // [
//assign char_data[60] = 30'h18C31863; // \
//assign char_data[61] = 30'h1C6318CE; // ]
//assign char_data[62] = 30'h8A00000; // ^
//assign char_data[63] = 30'h1F; // _
//assign char_data[64] = 30'h10400000; // `
//assign char_data[65] = 30'h7EF7D; // a
//assign char_data[66] = 30'h318F6F7F; // b
//assign char_data[67] = 30'h7E30F; // c
//assign char_data[68] = 30'h637EF6F; // d
//assign char_data[69] = 30'h76F8F; // e
//assign char_data[70] = 30'hEC67D8C; // f
//assign char_data[71] = 30'h1FBDBC7E; // g
//assign char_data[72] = 30'h318F6F7B; // h
//assign char_data[73] = 30'h18063186; // i
//assign char_data[74] = 30'hC6318DC; // j
//assign char_data[75] = 30'h31BD735B; // k
//assign char_data[76] = 30'h18C63186; // l
//assign char_data[77] = 30'h57F7B; // m
//assign char_data[78] = 30'hF6F7B; // n
//assign char_data[79] = 30'h7EF7E; // o
//assign char_data[80] = 30'h3DBDFB18; // p
//assign char_data[81] = 30'h1FBDBC63; // q
//assign char_data[82] = 30'h76F18; // r
//assign char_data[83] = 30'h7F0FE; // s
//assign char_data[84] = 30'h18CF3186; // t
//assign char_data[85] = 30'hDEF6F; // u
//assign char_data[86] = 30'hDED44; // v
//assign char_data[87] = 30'hDEFEA; // w
//assign char_data[88] = 30'hDBB7B; // x
//assign char_data[89] = 30'h37BDBC6E; // y
//assign char_data[90] = 30'hF999F; // z
//assign char_data[91] = 30'h623086; // {
//assign char_data[92] = 30'h421084; // |
//assign char_data[93] = 30'h610C46; // }
//assign char_data[94] = 30'hAA0000; // ~
endmodule

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src/color_map.v Normal file
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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 22:16:37 09/18/2020
// Design Name:
// Module Name: color_map
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module color_map(
input clk,
input[3:0] colorcode,
output reg[23:0] color
);
wire [23:0] colors [15:0];
always @(posedge clk) begin
color <= colors[colorcode];
end
// VGA Colors
// Normal colors
assign colors[0] = 24'h000000;
assign colors[1] = 24'hAA0000;
assign colors[2] = 24'h00AA00;
assign colors[3] = 24'hAA5500;
assign colors[4] = 24'h0000AA;
assign colors[5] = 24'hAA00AA;
assign colors[6] = 24'h00AAAA;
assign colors[7] = 24'hAAAAAA;
// Bright colors
assign colors[8] = 24'h555555;
assign colors[9] = 24'hFF5555;
assign colors[10] = 24'h55FF55;
assign colors[11] = 24'hFFFF55;
assign colors[12] = 24'h5555FF;
assign colors[13] = 24'hFF55FF;
assign colors[14] = 24'h55FFFF;
assign colors[15] = 24'hFFFFFF;
endmodule

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src/dvi_encoder.v Normal file
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`timescale 1ns / 1ps
/*
This file was generated automatically by Alchitry Labs version 1.2.0.
Do not edit this file directly. Instead edit the original Lucid source.
This is a temporary file and any changes made to it will be destroyed.
*/
module dvi_encoder (
input pclk,
input pclkx2,
input pclkx10,
input strobe,
input rst,
input [7:0] red,
input [7:0] green,
input [7:0] blue,
input hsync,
input vsync,
input de,
output reg [3:0] tmds,
output reg [3:0] tmdsb
);
reg M_toggle_d, M_toggle_q = 1'h0;
wire [1-1:0] M_clkser_iob_out;
reg [5-1:0] M_clkser_data;
serdes_n_to_1 clkser (
.ioclk(pclkx10),
.strobe(strobe),
.gclk(pclkx2),
.rst(rst),
.data(M_clkser_data),
.iob_out(M_clkser_iob_out)
);
wire [1-1:0] M_clkbuf_O;
wire [1-1:0] M_clkbuf_OB;
OBUFDS clkbuf (
.I(M_clkser_iob_out),
.O(M_clkbuf_O),
.OB(M_clkbuf_OB)
);
wire [10-1:0] M_enc_blue_data_out;
reg [8-1:0] M_enc_blue_data_in;
reg [1-1:0] M_enc_blue_c0;
reg [1-1:0] M_enc_blue_c1;
reg [1-1:0] M_enc_blue_de;
tmds_encoder enc_blue (
.clk(pclk),
.rst(rst),
.data_in(M_enc_blue_data_in),
.c0(M_enc_blue_c0),
.c1(M_enc_blue_c1),
.de(M_enc_blue_de),
.data_out(M_enc_blue_data_out)
);
wire [10-1:0] M_enc_green_data_out;
reg [8-1:0] M_enc_green_data_in;
reg [1-1:0] M_enc_green_c0;
reg [1-1:0] M_enc_green_c1;
reg [1-1:0] M_enc_green_de;
tmds_encoder enc_green (
.clk(pclk),
.rst(rst),
.data_in(M_enc_green_data_in),
.c0(M_enc_green_c0),
.c1(M_enc_green_c1),
.de(M_enc_green_de),
.data_out(M_enc_green_data_out)
);
wire [10-1:0] M_enc_red_data_out;
reg [8-1:0] M_enc_red_data_in;
reg [1-1:0] M_enc_red_c0;
reg [1-1:0] M_enc_red_c1;
reg [1-1:0] M_enc_red_de;
tmds_encoder enc_red (
.clk(pclk),
.rst(rst),
.data_in(M_enc_red_data_in),
.c0(M_enc_red_c0),
.c1(M_enc_red_c1),
.de(M_enc_red_de),
.data_out(M_enc_red_data_out)
);
wire [15-1:0] M_fifo_data_out;
reg [30-1:0] M_fifo_data_in;
fifo_2x_reducer fifo (
.rst(rst),
.clk(pclk),
.clkx2(pclkx2),
.data_in(M_fifo_data_in),
.data_out(M_fifo_data_out)
);
wire [1-1:0] M_redser_iob_out;
reg [5-1:0] M_redser_data;
serdes_n_to_1 redser (
.ioclk(pclkx10),
.strobe(strobe),
.gclk(pclkx2),
.rst(rst),
.data(M_redser_data),
.iob_out(M_redser_iob_out)
);
wire [1-1:0] M_greenser_iob_out;
reg [5-1:0] M_greenser_data;
serdes_n_to_1 greenser (
.ioclk(pclkx10),
.strobe(strobe),
.gclk(pclkx2),
.rst(rst),
.data(M_greenser_data),
.iob_out(M_greenser_iob_out)
);
wire [1-1:0] M_blueser_iob_out;
reg [5-1:0] M_blueser_data;
serdes_n_to_1 blueser (
.ioclk(pclkx10),
.strobe(strobe),
.gclk(pclkx2),
.rst(rst),
.data(M_blueser_data),
.iob_out(M_blueser_iob_out)
);
wire [1-1:0] M_redbuf_O;
wire [1-1:0] M_redbuf_OB;
OBUFDS redbuf (
.I(M_redser_iob_out),
.O(M_redbuf_O),
.OB(M_redbuf_OB)
);
wire [1-1:0] M_greenbuf_O;
wire [1-1:0] M_greenbuf_OB;
OBUFDS greenbuf (
.I(M_greenser_iob_out),
.O(M_greenbuf_O),
.OB(M_greenbuf_OB)
);
wire [1-1:0] M_bluebuf_O;
wire [1-1:0] M_bluebuf_OB;
OBUFDS bluebuf (
.I(M_blueser_iob_out),
.O(M_bluebuf_O),
.OB(M_bluebuf_OB)
);
always @* begin
M_toggle_d = M_toggle_q;
M_toggle_d = ~M_toggle_q;
M_clkser_data = {3'h5{~M_toggle_q}};
tmds[3+0-:1] = M_clkbuf_O;
tmdsb[3+0-:1] = M_clkbuf_OB;
M_enc_red_data_in = red;
M_enc_green_data_in = green;
M_enc_blue_data_in = blue;
M_enc_red_c0 = hsync;
M_enc_red_c1 = vsync;
M_enc_red_de = de;
M_enc_green_c0 = hsync;
M_enc_green_c1 = vsync;
M_enc_green_de = de;
M_enc_blue_c0 = hsync;
M_enc_blue_c1 = vsync;
M_enc_blue_de = de;
M_fifo_data_in = {M_enc_red_data_out[5+4-:5], M_enc_green_data_out[5+4-:5], M_enc_blue_data_out[5+4-:5], M_enc_red_data_out[0+4-:5], M_enc_green_data_out[0+4-:5], M_enc_blue_data_out[0+4-:5]};
M_redser_data = M_fifo_data_out[10+4-:5];
M_greenser_data = M_fifo_data_out[5+4-:5];
M_blueser_data = M_fifo_data_out[0+4-:5];
tmds[0+0-:1] = M_bluebuf_O;
tmdsb[0+0-:1] = M_bluebuf_OB;
tmds[1+0-:1] = M_greenbuf_O;
tmdsb[1+0-:1] = M_greenbuf_OB;
tmds[2+0-:1] = M_redbuf_O;
tmdsb[2+0-:1] = M_redbuf_OB;
end
always @(posedge pclkx2) begin
if (rst == 1'b1) begin
M_toggle_q <= 1'h0;
end else begin
M_toggle_q <= M_toggle_d;
end
end
endmodule

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`timescale 1ns / 1ps
/*
This file was generated automatically by Alchitry Labs version 1.2.0.
Do not edit this file directly. Instead edit the original Lucid source.
This is a temporary file and any changes made to it will be destroyed.
*/
/*
Parameters:
DATA_IN_SIZE = 30
*/
module fifo_2x_reducer (
input rst,
input clk,
input clkx2,
input [29:0] data_in,
output reg [14:0] data_out
);
localparam DATA_IN_SIZE = 5'h1e;
wire [1-1:0] M_fifo_full;
wire [30-1:0] M_fifo_dout;
wire [1-1:0] M_fifo_empty;
reg [30-1:0] M_fifo_din;
reg [1-1:0] M_fifo_wput;
reg [1-1:0] M_fifo_rget;
async_fifo fifo (
.wclk(clk),
.rclk(clkx2),
.wrst(rst),
.rrst(rst),
.din(M_fifo_din),
.wput(M_fifo_wput),
.rget(M_fifo_rget),
.full(M_fifo_full),
.dout(M_fifo_dout),
.empty(M_fifo_empty)
);
reg M_flag_d, M_flag_q = 1'h0;
reg [29:0] M_word_d, M_word_q = 1'h0;
always @* begin
M_flag_d = M_flag_q;
M_word_d = M_word_q;
M_fifo_din = data_in;
M_fifo_wput = 1'h1;
M_fifo_rget = 1'h0;
if (!M_flag_q && !M_fifo_empty) begin
M_fifo_rget = 1'h1;
M_flag_d = 1'h1;
M_word_d = M_fifo_dout;
end
if (M_flag_q) begin
M_flag_d = 1'h0;
end
data_out = !M_flag_q ? M_word_q[15+14-:15] : M_word_q[0+14-:15];
end
always @(posedge clkx2) begin
M_flag_q <= M_flag_d;
M_word_q <= M_word_d;
end
endmodule

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`timescale 1ns / 1ps
/*
This file was generated automatically by Alchitry Labs version 1.2.0.
Do not edit this file directly. Instead edit the original Lucid source.
This is a temporary file and any changes made to it will be destroyed.
*/
/*
Parameters:
PCLK_DIV = 1
Y_RES = HEIGHT
X_RES = WIDTH
Y_FRAME = HEIGHT+30
X_FRAME = WIDTH+387
*/
module hdmi_encoder #(parameter Y_RES = 720, parameter X_RES = 1280, parameter Y_FRAME = Y_RES+30, parameter X_FRAME = X_RES+387) (
input clk,
input rst,
output reg pclk,
output reg [3:0] tmds,
output reg [3:0] tmdsb,
output reg active,
output reg [11:0] x,
output reg [10:0] y,
input [7:0] red,
input [7:0] green,
input [7:0] blue
);
localparam PCLK_DIV = 1'h1;
reg clkfbin;
wire [1-1:0] M_pll_oserdes_CLKOUT0;
wire [1-1:0] M_pll_oserdes_CLKOUT1;
wire [1-1:0] M_pll_oserdes_CLKOUT2;
wire [1-1:0] M_pll_oserdes_CLKOUT3;
wire [1-1:0] M_pll_oserdes_CLKOUT4;
wire [1-1:0] M_pll_oserdes_CLKOUT5;
wire [1-1:0] M_pll_oserdes_CLKFBOUT;
wire [1-1:0] M_pll_oserdes_LOCKED;
PLL_BASE #(.CLKIN_PERIOD(10), .CLKFBOUT_MULT(10), .CLKOUT0_DIVIDE(1), .CLKOUT1_DIVIDE(10), .CLKOUT2_DIVIDE(5), .COMPENSATION("SOURCE_SYNCHRONOUS")) pll_oserdes (
.CLKFBIN(clkfbin),
.CLKIN(clk),
.RST(1'h0),
.CLKOUT0(M_pll_oserdes_CLKOUT0),
.CLKOUT1(M_pll_oserdes_CLKOUT1),
.CLKOUT2(M_pll_oserdes_CLKOUT2),
.CLKOUT3(M_pll_oserdes_CLKOUT3),
.CLKOUT4(M_pll_oserdes_CLKOUT4),
.CLKOUT5(M_pll_oserdes_CLKOUT5),
.CLKFBOUT(M_pll_oserdes_CLKFBOUT),
.LOCKED(M_pll_oserdes_LOCKED)
);
wire [1-1:0] M_clkfb_buf_O;
BUFG clkfb_buf (
.I(M_pll_oserdes_CLKFBOUT),
.O(M_clkfb_buf_O)
);
always @* begin
clkfbin = M_clkfb_buf_O;
end
wire [1-1:0] M_pclkx2_buf_O;
BUFG pclkx2_buf (
.I(M_pll_oserdes_CLKOUT2),
.O(M_pclkx2_buf_O)
);
wire [1-1:0] M_pclk_buf_O;
BUFG pclk_buf (
.I(M_pll_oserdes_CLKOUT1),
.O(M_pclk_buf_O)
);
wire [1-1:0] M_ioclk_buf_IOCLK;
wire [1-1:0] M_ioclk_buf_SERDESSTROBE;
wire [1-1:0] M_ioclk_buf_LOCK;
BUFPLL #(.DIVIDE(5)) ioclk_buf (
.PLLIN(M_pll_oserdes_CLKOUT0),
.GCLK(M_pclkx2_buf_O),
.LOCKED(M_pll_oserdes_LOCKED),
.IOCLK(M_ioclk_buf_IOCLK),
.SERDESSTROBE(M_ioclk_buf_SERDESSTROBE),
.LOCK(M_ioclk_buf_LOCK)
);
reg [11:0] M_ctrX_d, M_ctrX_q = 1'h0;
reg [10:0] M_ctrY_d, M_ctrY_q = 1'h0;
reg hSync;
reg vSync;
reg drawArea;
wire [4-1:0] M_dvi_tmds;
wire [4-1:0] M_dvi_tmdsb;
dvi_encoder dvi (
.pclk(M_pclk_buf_O),
.pclkx2(M_pclkx2_buf_O),
.pclkx10(M_ioclk_buf_IOCLK),
.strobe(M_ioclk_buf_SERDESSTROBE),
.rst(~M_ioclk_buf_LOCK),
.blue(blue),
.green(green),
.red(red),
.hsync(hSync),
.vsync(vSync),
.de(drawArea),
.tmds(M_dvi_tmds),
.tmdsb(M_dvi_tmdsb)
);
always @* begin
M_ctrY_d = M_ctrY_q;
M_ctrX_d = M_ctrX_q;
M_ctrX_d = (M_ctrX_q == 13'h0682) ? 1'h0 : M_ctrX_q + 1'h1;
if (M_ctrX_q == 13'h0682) begin
M_ctrY_d = (M_ctrY_q == 12'h2ed) ? 1'h0 : M_ctrY_q + 1'h1;
end
pclk = M_pclk_buf_O;
hSync = (M_ctrX_q >= 12'h50a) && (M_ctrX_q < 12'h514);
vSync = (M_ctrY_q >= 11'h2da) && (M_ctrY_q < 11'h2dc);
drawArea = (M_ctrX_q < 11'h500) && (M_ctrY_q < 10'h2d0);
active = drawArea;
x = M_ctrX_q;
y = M_ctrY_q;
tmds = M_dvi_tmds;
tmdsb = M_dvi_tmdsb;
end
always @(posedge M_pclk_buf_O) begin
if (rst == 1'b1) begin
M_ctrX_q <= 1'h0;
M_ctrY_q <= 1'h0;
end else begin
M_ctrX_q <= M_ctrX_d;
M_ctrY_q <= M_ctrY_d;
end
end
endmodule

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`timescale 1ns / 1ps
/*
This file was generated automatically by Alchitry Labs version 1.2.0.
Do not edit this file directly. Instead edit the original Lucid source.
This is a temporary file and any changes made to it will be destroyed.
*/
/*
Parameters:
FACTOR = 5
*/
module serdes_n_to_1 (
input ioclk,
input strobe,
input rst,
input gclk,
input [4:0] data,
output reg iob_out
);
localparam FACTOR = 3'h5;
reg [7:0] padded_data;
integer i;
wire [1-1:0] M_mserdes_OQ;
wire [1-1:0] M_mserdes_TQ;
wire [1-1:0] M_mserdes_SHIFTOUT1;
wire [1-1:0] M_mserdes_SHIFTOUT2;
wire [1-1:0] M_mserdes_SHIFTOUT3;
wire [1-1:0] M_mserdes_SHIFTOUT4;
reg [1-1:0] M_mserdes_IOCE;
reg [1-1:0] M_mserdes_D1;
reg [1-1:0] M_mserdes_D2;
reg [1-1:0] M_mserdes_D3;
reg [1-1:0] M_mserdes_D4;
reg [1-1:0] M_mserdes_OCE;
reg [1-1:0] M_mserdes_T1;
reg [1-1:0] M_mserdes_T2;
reg [1-1:0] M_mserdes_T3;
reg [1-1:0] M_mserdes_T4;
reg [1-1:0] M_mserdes_TCE;
reg [1-1:0] M_mserdes_SHIFTIN1;
reg [1-1:0] M_mserdes_SHIFTIN2;
reg [1-1:0] M_mserdes_SHIFTIN3;
reg [1-1:0] M_mserdes_SHIFTIN4;
reg [1-1:0] M_mserdes_TRAIN;
OSERDES2 #(.DATA_WIDTH(5), .DATA_RATE_OQ("SDR"), .DATA_RATE_OT("SDR"), .SERDES_MODE("MASTER"), .OUTPUT_MODE("DIFFERENTIAL")) mserdes (
.CLK0(ioclk),
.CLK1(1'h0),
.RST(rst),
.CLKDIV(gclk),
.IOCE(M_mserdes_IOCE),
.D1(M_mserdes_D1),
.D2(M_mserdes_D2),
.D3(M_mserdes_D3),
.D4(M_mserdes_D4),
.OCE(M_mserdes_OCE),
.T1(M_mserdes_T1),
.T2(M_mserdes_T2),
.T3(M_mserdes_T3),
.T4(M_mserdes_T4),
.TCE(M_mserdes_TCE),
.SHIFTIN1(M_mserdes_SHIFTIN1),
.SHIFTIN2(M_mserdes_SHIFTIN2),
.SHIFTIN3(M_mserdes_SHIFTIN3),
.SHIFTIN4(M_mserdes_SHIFTIN4),
.TRAIN(M_mserdes_TRAIN),
.OQ(M_mserdes_OQ),
.TQ(M_mserdes_TQ),
.SHIFTOUT1(M_mserdes_SHIFTOUT1),
.SHIFTOUT2(M_mserdes_SHIFTOUT2),
.SHIFTOUT3(M_mserdes_SHIFTOUT3),
.SHIFTOUT4(M_mserdes_SHIFTOUT4)
);
wire [1-1:0] M_sserdes_OQ;
wire [1-1:0] M_sserdes_TQ;
wire [1-1:0] M_sserdes_SHIFTOUT1;
wire [1-1:0] M_sserdes_SHIFTOUT2;
wire [1-1:0] M_sserdes_SHIFTOUT3;
wire [1-1:0] M_sserdes_SHIFTOUT4;
reg [1-1:0] M_sserdes_IOCE;
reg [1-1:0] M_sserdes_D1;
reg [1-1:0] M_sserdes_D2;
reg [1-1:0] M_sserdes_D3;
reg [1-1:0] M_sserdes_D4;
reg [1-1:0] M_sserdes_OCE;
reg [1-1:0] M_sserdes_T1;
reg [1-1:0] M_sserdes_T2;
reg [1-1:0] M_sserdes_T3;
reg [1-1:0] M_sserdes_T4;
reg [1-1:0] M_sserdes_TCE;
reg [1-1:0] M_sserdes_SHIFTIN1;
reg [1-1:0] M_sserdes_SHIFTIN2;
reg [1-1:0] M_sserdes_SHIFTIN3;
reg [1-1:0] M_sserdes_SHIFTIN4;
reg [1-1:0] M_sserdes_TRAIN;
OSERDES2 #(.DATA_WIDTH(5), .DATA_RATE_OQ("SDR"), .DATA_RATE_OT("SDR"), .SERDES_MODE("SLAVE"), .OUTPUT_MODE("DIFFERENTIAL")) sserdes (
.CLK0(ioclk),
.CLK1(1'h0),
.RST(rst),
.CLKDIV(gclk),
.IOCE(M_sserdes_IOCE),
.D1(M_sserdes_D1),
.D2(M_sserdes_D2),
.D3(M_sserdes_D3),
.D4(M_sserdes_D4),
.OCE(M_sserdes_OCE),
.T1(M_sserdes_T1),
.T2(M_sserdes_T2),
.T3(M_sserdes_T3),
.T4(M_sserdes_T4),
.TCE(M_sserdes_TCE),
.SHIFTIN1(M_sserdes_SHIFTIN1),
.SHIFTIN2(M_sserdes_SHIFTIN2),
.SHIFTIN3(M_sserdes_SHIFTIN3),
.SHIFTIN4(M_sserdes_SHIFTIN4),
.TRAIN(M_sserdes_TRAIN),
.OQ(M_sserdes_OQ),
.TQ(M_sserdes_TQ),
.SHIFTOUT1(M_sserdes_SHIFTOUT1),
.SHIFTOUT2(M_sserdes_SHIFTOUT2),
.SHIFTOUT3(M_sserdes_SHIFTOUT3),
.SHIFTOUT4(M_sserdes_SHIFTOUT4)
);
always @* begin
padded_data = 8'h00;
for (i = 1'h0; i < 3'h5; i = i + 1) begin
padded_data[(i)*1+0-:1] = data[(i)*1+0-:1];
end
M_mserdes_OCE = 1'h1;
M_mserdes_IOCE = strobe;
M_mserdes_D4 = padded_data[7+0-:1];
M_mserdes_D3 = padded_data[6+0-:1];
M_mserdes_D2 = padded_data[5+0-:1];
M_mserdes_D1 = padded_data[4+0-:1];
M_mserdes_T1 = 1'h0;
M_mserdes_T2 = 1'h0;
M_mserdes_T3 = 1'h0;
M_mserdes_T4 = 1'h0;
M_mserdes_TRAIN = 1'h0;
M_mserdes_TCE = 1'h1;
M_mserdes_SHIFTIN1 = 1'h1;
M_mserdes_SHIFTIN2 = 1'h1;
M_mserdes_SHIFTIN3 = M_sserdes_SHIFTOUT3;
M_mserdes_SHIFTIN4 = M_sserdes_SHIFTOUT4;
M_sserdes_OCE = 1'h1;
M_sserdes_IOCE = strobe;
M_sserdes_D4 = padded_data[3+0-:1];
M_sserdes_D3 = padded_data[2+0-:1];
M_sserdes_D2 = padded_data[1+0-:1];
M_sserdes_D1 = padded_data[0+0-:1];
M_sserdes_T1 = 1'h0;
M_sserdes_T2 = 1'h0;
M_sserdes_T3 = 1'h0;
M_sserdes_T4 = 1'h0;
M_sserdes_TRAIN = 1'h0;
M_sserdes_TCE = 1'h1;
M_sserdes_SHIFTIN1 = M_mserdes_SHIFTOUT1;
M_sserdes_SHIFTIN2 = M_mserdes_SHIFTOUT2;
M_sserdes_SHIFTIN3 = 1'h1;
M_sserdes_SHIFTIN4 = 1'h1;
iob_out = M_mserdes_OQ;
end
endmodule

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`timescale 1ns / 1ps
/******************************************************************************
The MIT License (MIT)
Copyright (c) 2019 Alchitry
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*****************************************************************************
This module is a simple dual port RAM. This RAM is implemented in such a
way that Xilinx's tools will recognize it as a RAM and implement large
instances in block RAM instead of flip-flops.
The parameter SIZE is used to specify the word size. That is the size of
each entry in the RAM.
The parameter DEPTH is used to specify how many entries are in the RAM.
read_data outputs the value of the entry pointed to by raddr in the previous
clock cycle. That means to read address 10, you would set address to be 10
and wait one cycle for its value to show up. The RAM is always reading whatever
address is. If you don't need to read, just ignore this value.
To write, set write_en to 1, write_data to the value to write, and waddr to
the address you want to write.
You should avoid reading and writing to the same address simultaneously. The
value read in this case is undefined.
*/
module simple_dual_ram #(
parameter SIZE = 8, // size of each entry
parameter DEPTH = 8 // number of entries
)(
// write interface
input wclk, // write clock
input [$clog2(DEPTH)-1:0] waddr, // write address
input [SIZE-1:0] write_data, // write data
input write_en, // write enable (1 = write)
// read interface
input rclk, // read clock
input [$clog2(DEPTH)-1:0] raddr, // read address
output reg [SIZE-1:0] read_data // read data
);
reg [SIZE-1:0] mem [DEPTH-1:0]; // memory array
// write clock domain
always @(posedge wclk) begin
if (write_en) // if write enable
mem[waddr] <= write_data; // write memory
end
// read clock domain
always @(posedge rclk) begin
read_data <= mem[raddr]; // read memory
end
endmodule

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src/tmds_encoder.v Normal file
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`timescale 1ns / 1ps
/*
This file was generated automatically by Alchitry Labs version 1.2.0.
Do not edit this file directly. Instead edit the original Lucid source.
This is a temporary file and any changes made to it will be destroyed.
*/
module tmds_encoder (
input clk,
input rst,
input [7:0] data_in,
input c0,
input c1,
input de,
output reg [9:0] data_out
);
reg [9:0] M_dout_d, M_dout_q = 1'h0;
reg [4:0] M_count_d, M_count_q = 1'h0;
reg [3:0] M_num_ones_d, M_num_ones_q = 1'h0;
reg [7:0] M_din_d, M_din_q = 1'h0;
reg [3:0] M_num_ones9_d, M_num_ones9_q = 1'h0;
reg [1:0] M_c0_pipe_d, M_c0_pipe_q = 1'h0;
reg [1:0] M_c1_pipe_d, M_c1_pipe_q = 1'h0;
reg [1:0] M_de_pipe_d, M_de_pipe_q = 1'h0;
reg [8:0] M_data9_pipe_d, M_data9_pipe_q = 1'h0;
reg xor_flag;
reg [8:0] data9;
integer i;
reg cond_flip;
reg flip;
always @* begin
M_c0_pipe_d = M_c0_pipe_q;
M_dout_d = M_dout_q;
M_num_ones9_d = M_num_ones9_q;
M_din_d = M_din_q;
M_data9_pipe_d = M_data9_pipe_q;
M_count_d = M_count_q;
M_c1_pipe_d = M_c1_pipe_q;
M_de_pipe_d = M_de_pipe_q;
M_num_ones_d = M_num_ones_q;
data_out = M_dout_q;
M_c0_pipe_d = {M_c0_pipe_q[0+0-:1], c0};
M_c1_pipe_d = {M_c1_pipe_q[0+0-:1], c1};
M_de_pipe_d = {M_de_pipe_q[0+0-:1], de};
M_num_ones_d = data_in[0+0-:1] + data_in[1+0-:1] + data_in[2+0-:1] + data_in[3+0-:1] + data_in[4+0-:1] + data_in[5+0-:1] + data_in[6+0-:1] + data_in[7+0-:1];
M_din_d = data_in;
xor_flag = (M_num_ones_q > 3'h4) || (M_num_ones_q == 3'h4 && M_din_q[0+0-:1] == 1'h0);
data9[0+0-:1] = M_din_q[0+0-:1];
for (i = 1'h1; i < 4'h8; i = i + 1) begin
data9[(i)*1+0-:1] = xor_flag ? data9[(i - 1'h1)*1+0-:1] ~^ M_din_q[(i)*1+0-:1] : data9[(i - 1'h1)*1+0-:1] ^ M_din_q[(i)*1+0-:1];
end
data9[8+0-:1] = ~xor_flag;
M_num_ones9_d = data9[0+0-:1] + data9[1+0-:1] + data9[2+0-:1] + data9[3+0-:1] + data9[4+0-:1] + data9[5+0-:1] + data9[6+0-:1] + data9[7+0-:1];
M_data9_pipe_d = data9;
cond_flip = M_count_q == 1'h0 || M_num_ones9_q == 3'h4;
flip = ((~M_count_q[4+0-:1]) && (M_num_ones9_q > 3'h4)) || (M_count_q[4+0-:1] && (3'h4 > M_num_ones9_q));
if (M_de_pipe_q[1+0-:1]) begin
if (cond_flip) begin
M_dout_d[9+0-:1] = ~M_data9_pipe_q[8+0-:1];
M_dout_d[8+0-:1] = M_data9_pipe_q[8+0-:1];
M_dout_d[0+7-:8] = M_data9_pipe_q[8+0-:1] ? M_data9_pipe_q[0+7-:8] : ~M_data9_pipe_q[0+7-:8];
M_count_d = (~M_data9_pipe_q[8+0-:1]) ? (M_count_q + (4'h8 - M_num_ones9_q) - M_num_ones9_q) : (M_count_q + M_num_ones9_q - (4'h8 - M_num_ones9_q));
end else begin
if (flip) begin
M_dout_d[9+0-:1] = 1'h1;
M_dout_d[8+0-:1] = M_data9_pipe_q[8+0-:1];
M_dout_d[0+7-:8] = ~M_data9_pipe_q[0+7-:8];
M_count_d = M_count_q + {M_data9_pipe_q[8+0-:1], 1'h0} + (4'h8 - M_num_ones9_q) - M_num_ones9_q;
end else begin
M_dout_d[9+0-:1] = 1'h0;
M_dout_d[0+8-:9] = M_data9_pipe_q[0+8-:9];
M_count_d = M_count_q - {~M_data9_pipe_q[8+0-:1], 1'h0} + M_num_ones9_q - (4'h8 - M_num_ones9_q);
end
end
end else begin
case ({M_c1_pipe_q[1+0-:1], M_c0_pipe_q[1+0-:1]})
2'h0: begin
M_dout_d = 10'h354;
end
2'h1: begin
M_dout_d = 10'h0ab;
end
2'h2: begin
M_dout_d = 10'h154;
end
default: begin
M_dout_d = 10'h2ab;
end
endcase
M_count_d = 1'h0;
end
end
always @(posedge clk) begin
M_num_ones_q <= M_num_ones_d;
M_din_q <= M_din_d;
M_num_ones9_q <= M_num_ones9_d;
M_c0_pipe_q <= M_c0_pipe_d;
M_c1_pipe_q <= M_c1_pipe_d;
M_de_pipe_q <= M_de_pipe_d;
M_data9_pipe_q <= M_data9_pipe_d;
if (rst == 1'b1) begin
M_dout_q <= 1'h0;
M_count_q <= 1'h0;
end else begin
M_dout_q <= M_dout_d;
M_count_q <= M_count_d;
end
end
endmodule