z80/hdmi.old
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Fixed build issues and added upload to vimlocal

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This commit is contained in:
Dreaded_X
2020-09-21 20:52:58 +02:00
parent 637dfa2c07
commit 2c32ab39e7
123 changed files with 14049 additions and 34 deletions
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37
ipcore_dir/gen_hdmi_clk.tcl Normal file
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@@ -0,0 +1,37 @@
##
## Core Generator Run Script, generator for Project Navigator regen command
##
proc findRtfPath { relativePath } {
set xilenv ""
if { [info exists ::env(XILINX) ] } {
if { [info exists ::env(MYXILINX)] } {
set xilenv [join [list $::env(MYXILINX) $::env(XILINX)] $::xilinx::path_sep ]
} else {
set xilenv $::env(XILINX)
}
}
foreach path [ split $xilenv $::xilinx::path_sep ] {
set fullPath [ file join $path $relativePath ]
if { [ file exists $fullPath ] } {
return $fullPath
}
}
return ""
}
source [ findRtfPath "data/projnav/scripts/dpm_cgUtils.tcl" ]
set result [ run_cg_regen "hdmi_clk" xc6slx9-2tqg144 Verilog CURRENT ]
if { $result == 0 } {
puts "Core Generator regen command completed successfully."
} elseif { $result == 1 } {
puts "Core Generator regen command failed."
} elseif { $result == 3 || $result == 4 } {
# convert 'version check' result to real return range, bypassing any messages.
set result [ expr $result - 3 ]
} else {
puts "Core Generator regen cancelled."
}
exit $result

37
ipcore_dir/gen_microblaze_mcs.tcl Normal file
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@@ -0,0 +1,37 @@
##
## Core Generator Run Script, generator for Project Navigator regen command
##
proc findRtfPath { relativePath } {
set xilenv ""
if { [info exists ::env(XILINX) ] } {
if { [info exists ::env(MYXILINX)] } {
set xilenv [join [list $::env(MYXILINX) $::env(XILINX)] $::xilinx::path_sep ]
} else {
set xilenv $::env(XILINX)
}
}
foreach path [ split $xilenv $::xilinx::path_sep ] {
set fullPath [ file join $path $relativePath ]
if { [ file exists $fullPath ] } {
return $fullPath
}
}
return ""
}
source [ findRtfPath "data/projnav/scripts/dpm_cgUtils.tcl" ]
set result [ run_cg_regen "microblaze_mcs" xc6slx9-2tqg144 Verilog CURRENT ]
if { $result == 0 } {
puts "Core Generator regen command completed successfully."
} elseif { $result == 1 } {
puts "Core Generator regen command failed."
} elseif { $result == 3 || $result == 4 } {
# convert 'version check' result to real return range, bypassing any messages.
set result [ expr $result - 3 ]
} else {
puts "Core Generator regen cancelled."
}
exit $result

2
ipcore_dir/hdmi_clk.sym
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@@ -1,7 +1,7 @@
<?xml version="1.0" encoding="UTF-8"?>
<symbol version="7" name="hdmi_clk">
<symboltype>BLOCK</symboltype>
<timestamp>2020-9-17T15:18:55</timestamp>
<timestamp>2020-9-21T18:2:44</timestamp>
<pin polarity="Input" x="0" y="80" name="clk_in1" />
<pin polarity="Output" x="608" y="80" name="clk_out1" />
<pin polarity="Output" x="608" y="176" name="clk_out2" />

2
ipcore_dir/hdmi_clk.xco
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@@ -1,7 +1,7 @@
##############################################################
#
# Xilinx Core Generator version 14.7
# Date: Thu Sep 17 15:18:44 2020
# Date: Mon Sep 21 18:02:33 2020
#
##############################################################
#

4
ipcore_dir/hdmi_clk.xise
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@@ -50,8 +50,8 @@
<!-- -->
<property xil_pn:name="PROP_DesignName" xil_pn:value="hdmi_clk" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2020-09-17T17:18:57" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="9C4B53858E4C5064C7E51761156BB29A" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2020-09-21T20:02:45" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="3F469F5C71C64704824888D979DF0B8F" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties>

2
ipcore_dir/microblaze_mcs.sym
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@@ -1,7 +1,7 @@
<?xml version="1.0" encoding="UTF-8"?>
<symbol version="7" name="microblaze_mcs">
<symboltype>BLOCK</symboltype>
<timestamp>2020-9-20T19:27:36</timestamp>
<timestamp>2020-9-21T18:2:10</timestamp>
<pin polarity="Input" x="0" y="80" name="clk" />
<pin polarity="Input" x="0" y="112" name="reset" />
<pin polarity="Output" x="768" y="656" name="gpi2_interrupt" />

2
ipcore_dir/microblaze_mcs.v
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@@ -7,7 +7,7 @@
// \ \ \/ Version: P.20131013
// \ \ Application: netgen
// / / Filename: microblaze_mcs.v
// /___/ /\ Timestamp: Sun Sep 20 21:27:36 2020
// /___/ /\ Timestamp: Mon Sep 21 20:02:10 2020
// \ \ / \
// \___\/\___\
//

2
ipcore_dir/microblaze_mcs.xco
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@@ -1,7 +1,7 @@
##############################################################
#
# Xilinx Core Generator version 14.7
# Date: Sun Sep 20 19:25:41 2020
# Date: Mon Sep 21 18:00:15 2020
#
##############################################################
#

4
ipcore_dir/microblaze_mcs.xise
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@@ -66,8 +66,8 @@
<!-- -->
<property xil_pn:name="PROP_DesignName" xil_pn:value="microblaze_mcs" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2020-09-20T21:27:37" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="044D6B7A37DFFF9EFD796E528492BD84" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2020-09-21T20:02:11" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="534E782F69499841CE64BF2098D784B5" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties>

16
ipcore_dir/microblaze_mcs_bd.bmm
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@@ -20,14 +20,14 @@ ADDRESS_MAP microblaze_mcs MICROBLAZE-LE 100
ADDRESS_SPACE lmb_bram RAMB16 [0x00000000:0x00003FFF]
BUS_BLOCK
mcs_0/U0/lmb_bram_I/RAM_Inst/Using_B16_S4.The_BRAMs[0].RAMB16_S4_1 RAMB16 [31:28] [0:4095] INPUT = microblaze_mcs.lmb_bram_0.mem PLACED = X1Y18;
mcs_0/U0/lmb_bram_I/RAM_Inst/Using_B16_S4.The_BRAMs[1].RAMB16_S4_1 RAMB16 [27:24] [0:4095] INPUT = microblaze_mcs.lmb_bram_1.mem PLACED = X1Y24;
mcs_0/U0/lmb_bram_I/RAM_Inst/Using_B16_S4.The_BRAMs[2].RAMB16_S4_1 RAMB16 [23:20] [0:4095] INPUT = microblaze_mcs.lmb_bram_2.mem PLACED = X1Y8;
mcs_0/U0/lmb_bram_I/RAM_Inst/Using_B16_S4.The_BRAMs[3].RAMB16_S4_1 RAMB16 [19:16] [0:4095] INPUT = microblaze_mcs.lmb_bram_3.mem PLACED = X1Y28;
mcs_0/U0/lmb_bram_I/RAM_Inst/Using_B16_S4.The_BRAMs[4].RAMB16_S4_1 RAMB16 [15:12] [0:4095] INPUT = microblaze_mcs.lmb_bram_4.mem PLACED = X1Y20;
mcs_0/U0/lmb_bram_I/RAM_Inst/Using_B16_S4.The_BRAMs[5].RAMB16_S4_1 RAMB16 [11:8] [0:4095] INPUT = microblaze_mcs.lmb_bram_5.mem PLACED = X1Y26;
mcs_0/U0/lmb_bram_I/RAM_Inst/Using_B16_S4.The_BRAMs[6].RAMB16_S4_1 RAMB16 [7:4] [0:4095] INPUT = microblaze_mcs.lmb_bram_6.mem PLACED = X1Y16;
mcs_0/U0/lmb_bram_I/RAM_Inst/Using_B16_S4.The_BRAMs[7].RAMB16_S4_1 RAMB16 [3:0] [0:4095] INPUT = microblaze_mcs.lmb_bram_7.mem PLACED = X1Y22;
mcs_0/U0/lmb_bram_I/RAM_Inst/Using_B16_S4.The_BRAMs[0].RAMB16_S4_1 RAMB16 [31:28] [0:4095] INPUT = microblaze_mcs.lmb_bram_0.mem PLACED = X0Y26;
mcs_0/U0/lmb_bram_I/RAM_Inst/Using_B16_S4.The_BRAMs[1].RAMB16_S4_1 RAMB16 [27:24] [0:4095] INPUT = microblaze_mcs.lmb_bram_1.mem PLACED = X0Y20;
mcs_0/U0/lmb_bram_I/RAM_Inst/Using_B16_S4.The_BRAMs[2].RAMB16_S4_1 RAMB16 [23:20] [0:4095] INPUT = microblaze_mcs.lmb_bram_2.mem PLACED = X0Y24;
mcs_0/U0/lmb_bram_I/RAM_Inst/Using_B16_S4.The_BRAMs[3].RAMB16_S4_1 RAMB16 [19:16] [0:4095] INPUT = microblaze_mcs.lmb_bram_3.mem PLACED = X0Y18;
mcs_0/U0/lmb_bram_I/RAM_Inst/Using_B16_S4.The_BRAMs[4].RAMB16_S4_1 RAMB16 [15:12] [0:4095] INPUT = microblaze_mcs.lmb_bram_4.mem PLACED = X0Y30;
mcs_0/U0/lmb_bram_I/RAM_Inst/Using_B16_S4.The_BRAMs[5].RAMB16_S4_1 RAMB16 [11:8] [0:4095] INPUT = microblaze_mcs.lmb_bram_5.mem PLACED = X0Y22;
mcs_0/U0/lmb_bram_I/RAM_Inst/Using_B16_S4.The_BRAMs[6].RAMB16_S4_1 RAMB16 [7:4] [0:4095] INPUT = microblaze_mcs.lmb_bram_6.mem PLACED = X0Y28;
mcs_0/U0/lmb_bram_I/RAM_Inst/Using_B16_S4.The_BRAMs[7].RAMB16_S4_1 RAMB16 [3:0] [0:4095] INPUT = microblaze_mcs.lmb_bram_7.mem PLACED = X0Y16;
END_BUS_BLOCK;
END_ADDRESS_SPACE;

2
ipcore_dir/microblaze_mcs_sdk.xml
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@@ -1,6 +1,6 @@
<EDKSYSTEM EDKVERSION="14.5" EDWVERSION="1.2" TIMESTAMP="Sun Sep 20 21:27:35 2020">
<EDKSYSTEM EDKVERSION="14.5" EDWVERSION="1.2" TIMESTAMP="Mon Sep 21 20:02:09 2020">
<SYSTEMINFO ARCH="spartan6" DEVICE="xc6slx9" PACKAGE="tqg144" PART="xc6slx9tqg144-2" SOURCE="" SPEEDGRADE="-2"/>

505
ipcore_dir/tmp/customization_gui.0.405988320432.out Normal file
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@@ -0,0 +1,505 @@
SET_FLAG DEBUG FALSE
SET_FLAG MODE BATCH
SET_FLAG STANDALONE_MODE FALSE
SET_PREFERENCE devicefamily spartan6
SET_PREFERENCE device xc6slx9
SET_PREFERENCE speedgrade -2
SET_PREFERENCE package tqg144
SET_PREFERENCE verilogsim true
SET_PREFERENCE vhdlsim false
SET_PREFERENCE simulationfiles Behavioral
SET_PREFERENCE busformat BusFormatAngleBracketNotRipped
SET_PREFERENCE outputdirectory /home/tim/Projects/z80/hdmi/ipcore_dir/
SET_PREFERENCE workingdirectory /home/tim/Projects/z80/hdmi/ipcore_dir/tmp/
SET_PREFERENCE subworkingdirectory /home/tim/Projects/z80/hdmi/ipcore_dir/tmp/_cg/
SET_PREFERENCE transientdirectory /home/tim/Projects/z80/hdmi/ipcore_dir/tmp/_cg/_dbg/
SET_PREFERENCE designentry Verilog
SET_PREFERENCE flowvendor Other
SET_PREFERENCE addpads false
SET_PREFERENCE projectname coregen
SET_PREFERENCE formalverification false
SET_PREFERENCE asysymbol false
SET_PREFERENCE implementationfiletype Ngc
SET_PREFERENCE foundationsym false
SET_PREFERENCE createndf false
SET_PREFERENCE removerpms false
SET_PARAMETER Component_Name hdmi_clk
SET_PARAMETER Use_Freq_Synth true
SET_PARAMETER Use_Phase_Alignment false
SET_PARAMETER Use_Min_Power false
SET_PARAMETER Use_Dyn_Phase_Shift false
SET_PARAMETER Use_Dyn_Reconfig false
SET_PARAMETER Jitter_Sel No_Jitter
SET_PARAMETER Use_Spread_Spectrum false
SET_PARAMETER Use_Spread_Spectrum_1 false
SET_PARAMETER Prim_In_Freq 50
SET_PARAMETER In_Freq_Units Units_MHz
SET_PARAMETER In_Jitter_Units Units_UI
SET_PARAMETER Relative_Inclk REL_PRIMARY
SET_PARAMETER Secondary_In_Freq 100.000
SET_PARAMETER Jitter_Options UI
SET_PARAMETER Clkin1_UI_Jitter 0.010
SET_PARAMETER Clkin2_UI_Jitter 0.010
SET_PARAMETER Prim_In_Jitter 0.010
SET_PARAMETER Secondary_In_Jitter 0.010
SET_PARAMETER Clkin1_Jitter_Ps 200.0
SET_PARAMETER Clkin2_Jitter_Ps 100.0
SET_PARAMETER Clkout2_Used true
SET_PARAMETER Clkout3_Used false
SET_PARAMETER Clkout4_Used false
SET_PARAMETER Clkout5_Used false
SET_PARAMETER Clkout6_Used false
SET_PARAMETER Clkout7_Used false
SET_PARAMETER Num_Out_Clks 2
SET_PARAMETER Clk_Out1_Use_Fine_Ps_GUI false
SET_PARAMETER Clk_Out2_Use_Fine_Ps_GUI false
SET_PARAMETER Clk_Out3_Use_Fine_Ps_GUI false
SET_PARAMETER Clk_Out4_Use_Fine_Ps_GUI false
SET_PARAMETER Clk_Out5_Use_Fine_Ps_GUI false
SET_PARAMETER Clk_Out6_Use_Fine_Ps_GUI false
SET_PARAMETER Clk_Out7_Use_Fine_Ps_GUI false
SET_PARAMETER primary_port CLK_IN1
SET_PARAMETER CLK_OUT1_port CLK_OUT1
SET_PARAMETER CLK_OUT2_port CLK_OUT2
SET_PARAMETER CLK_OUT3_port CLK_OUT3
SET_PARAMETER CLK_OUT4_port CLK_OUT4
SET_PARAMETER CLK_OUT5_port CLK_OUT5
SET_PARAMETER CLK_OUT6_port CLK_OUT6
SET_PARAMETER CLK_OUT7_port CLK_OUT7
SET_PARAMETER DADDR_port DADDR
SET_PARAMETER DCLK_port DCLK
SET_PARAMETER DRDY_port DRDY
SET_PARAMETER DWE_port DWE
SET_PARAMETER DIN_port DIN
SET_PARAMETER DOUT_port DOUT
SET_PARAMETER DEN_port DEN
SET_PARAMETER PSCLK_port PSCLK
SET_PARAMETER PSEN_port PSEN
SET_PARAMETER PSINCDEC_port PSINCDEC
SET_PARAMETER PSDONE_port PSDONE
SET_PARAMETER Clkout1_Requested_Out_Freq 75
SET_PARAMETER Clkout1_Requested_Phase 0.000
SET_PARAMETER Clkout1_Requested_Duty_Cycle 50.000
SET_PARAMETER Clkout2_Requested_Out_Freq 150
SET_PARAMETER Clkout2_Requested_Phase 0.000
SET_PARAMETER Clkout2_Requested_Duty_Cycle 50.000
SET_PARAMETER Clkout3_Requested_Out_Freq 100.000
SET_PARAMETER Clkout3_Requested_Phase 0.000
SET_PARAMETER Clkout3_Requested_Duty_Cycle 50.000
SET_PARAMETER Clkout4_Requested_Out_Freq 100.000
SET_PARAMETER Clkout4_Requested_Phase 0.000
SET_PARAMETER Clkout4_Requested_Duty_Cycle 50.000
SET_PARAMETER Clkout5_Requested_Out_Freq 100.000
SET_PARAMETER Clkout5_Requested_Phase 0.000
SET_PARAMETER Clkout5_Requested_Duty_Cycle 50.000
SET_PARAMETER Clkout6_Requested_Out_Freq 100.000
SET_PARAMETER Clkout6_Requested_Phase 0.000
SET_PARAMETER Clkout6_Requested_Duty_Cycle 50.000
SET_PARAMETER Clkout7_Requested_Out_Freq 100.000
SET_PARAMETER Clkout7_Requested_Phase 0.000
SET_PARAMETER Clkout7_Requested_Duty_Cycle 50.000
SET_PARAMETER Use_Max_I_Jitter false
SET_PARAMETER Use_Min_O_Jitter false
SET_PARAMETER Prim_Source Single_ended_clock_capable_pin
SET_PARAMETER Use_Inclk_Switchover false
SET_PARAMETER secondary_port CLK_IN2
SET_PARAMETER Secondary_Source Single_ended_clock_capable_pin
SET_PARAMETER Clkout1_Drives BUFG
SET_PARAMETER Clkout2_Drives BUFG
SET_PARAMETER Clkout3_Drives BUFG
SET_PARAMETER Clkout4_Drives BUFG
SET_PARAMETER Clkout5_Drives BUFG
SET_PARAMETER Clkout6_Drives BUFG
SET_PARAMETER Clkout7_Drives BUFG
SET_PARAMETER Feedback_Source FDBK_AUTO
SET_PARAMETER Clkfb_In_Signaling SINGLE
SET_PARAMETER CLKFB_IN_port CLKFB_IN
SET_PARAMETER CLKFB_IN_P_port CLKFB_IN_P
SET_PARAMETER CLKFB_IN_N_port CLKFB_IN_N
SET_PARAMETER CLKFB_OUT_port CLKFB_OUT
SET_PARAMETER CLKFB_OUT_P_port CLKFB_OUT_P
SET_PARAMETER CLKFB_OUT_N_port CLKFB_OUT_N
SET_PARAMETER Platform lin64
SET_PARAMETER Summary_Strings empty
SET_PARAMETER Use_Locked false
SET_PARAMETER calc_done DONE
SET_PARAMETER Use_Reset false
SET_PARAMETER Use_Power_Down false
SET_PARAMETER Use_Status false
SET_PARAMETER Use_Freeze false
SET_PARAMETER Use_Clk_Valid false
SET_PARAMETER Use_Inclk_Stopped false
SET_PARAMETER Use_Clkfb_Stopped false
SET_PARAMETER RESET_port RESET
SET_PARAMETER LOCKED_port LOCKED
SET_PARAMETER Power_Down_port POWER_DOWN
SET_PARAMETER CLK_VALID_port CLK_VALID
SET_PARAMETER STATUS_port STATUS
SET_PARAMETER CLK_IN_SEL_port CLK_IN_SEL
SET_PARAMETER INPUT_CLK_STOPPED_port INPUT_CLK_STOPPED
SET_PARAMETER CLKFB_STOPPED_port CLKFB_STOPPED
SET_PARAMETER Override_Mmcm false
SET_PARAMETER Mmcm_Notes None
SET_PARAMETER Mmcm_Divclk_Divide 1
SET_PARAMETER Mmcm_Bandwidth OPTIMIZED
SET_PARAMETER Mmcm_Clkfbout_Mult_F 4.000
SET_PARAMETER Mmcm_Clkfbout_Phase 0.000
SET_PARAMETER Mmcm_Clkfbout_Use_Fine_Ps false
SET_PARAMETER Mmcm_Clkin1_Period 10.000
SET_PARAMETER Mmcm_Clkin2_Period 10.000
SET_PARAMETER Mmcm_Clkout4_Cascade false
SET_PARAMETER Mmcm_Clock_Hold false
SET_PARAMETER Mmcm_Compensation ZHOLD
SET_PARAMETER Mmcm_Ref_Jitter1 0.010
SET_PARAMETER Mmcm_Ref_Jitter2 0.010
SET_PARAMETER Mmcm_Startup_Wait false
SET_PARAMETER Mmcm_Clkout0_Divide_F 4.000
SET_PARAMETER Mmcm_Clkout0_Duty_Cycle 0.500
SET_PARAMETER Mmcm_Clkout0_Phase 0.000
SET_PARAMETER Mmcm_Clkout0_Use_Fine_Ps false
SET_PARAMETER Mmcm_Clkout1_Divide 1
SET_PARAMETER Mmcm_Clkout1_Duty_Cycle 0.500
SET_PARAMETER Mmcm_Clkout1_Phase 0.000
SET_PARAMETER Mmcm_Clkout1_Use_Fine_Ps false
SET_PARAMETER Mmcm_Clkout2_Divide 1
SET_PARAMETER Mmcm_Clkout2_Duty_Cycle 0.500
SET_PARAMETER Mmcm_Clkout2_Phase 0.000
SET_PARAMETER Mmcm_Clkout2_Use_Fine_Ps false
SET_PARAMETER Mmcm_Clkout3_Divide 1
SET_PARAMETER Mmcm_Clkout3_Duty_Cycle 0.500
SET_PARAMETER Mmcm_Clkout3_Phase 0.000
SET_PARAMETER Mmcm_Clkout3_Use_Fine_Ps false
SET_PARAMETER Mmcm_Clkout4_Divide 1
SET_PARAMETER Mmcm_Clkout4_Duty_Cycle 0.500
SET_PARAMETER Mmcm_Clkout4_Phase 0.000
SET_PARAMETER Mmcm_Clkout4_Use_Fine_Ps false
SET_PARAMETER Mmcm_Clkout5_Divide 1
SET_PARAMETER Mmcm_Clkout5_Duty_Cycle 0.500
SET_PARAMETER Mmcm_Clkout5_Phase 0.000
SET_PARAMETER Mmcm_Clkout5_Use_Fine_Ps false
SET_PARAMETER Mmcm_Clkout6_Divide 1
SET_PARAMETER Mmcm_Clkout6_Duty_Cycle 0.500
SET_PARAMETER Mmcm_Clkout6_Phase 0.000
SET_PARAMETER Mmcm_Clkout6_Use_Fine_Ps false
SET_PARAMETER Override_Dcm false
SET_PARAMETER Dcm_Notes None
SET_PARAMETER Dcm_Clkdv_Divide 2.0
SET_PARAMETER Dcm_Clkfx_Divide 2
SET_PARAMETER Dcm_Clkfx_Multiply 3
SET_PARAMETER Dcm_Clkin_Divide_By_2 false
SET_PARAMETER Dcm_Clkin_Period 20.000
SET_PARAMETER Dcm_Clkout_Phase_Shift NONE
SET_PARAMETER Dcm_Deskew_Adjust SYSTEM_SYNCHRONOUS
SET_PARAMETER Dcm_Phase_Shift 0
SET_PARAMETER Dcm_Clk_Feedback NONE
SET_PARAMETER Dcm_Startup_Wait false
SET_PARAMETER Dcm_Clk_Out1_Port CLKFX
SET_PARAMETER Dcm_Clk_Out2_Port CLK0
SET_PARAMETER Dcm_Clk_Out3_Port CLK0
SET_PARAMETER Dcm_Clk_Out4_Port CLK0
SET_PARAMETER Dcm_Clk_Out5_Port CLK0
SET_PARAMETER Dcm_Clk_Out6_Port CLK0
SET_PARAMETER Override_Dcm_Clkgen false
SET_PARAMETER Dcm_Clkgen_Notes None
SET_PARAMETER Dcm_Clkgen_Clkfx_Divide 1
SET_PARAMETER Dcm_Clkgen_Clkfx_Multiply 4
SET_PARAMETER Dcm_Clkgen_Clkfxdv_Divide 2
SET_PARAMETER Dcm_Clkgen_Clkfx_Md_Max 0.000
SET_PARAMETER Dcm_Clkgen_Startup_Wait false
SET_PARAMETER Dcm_Clkgen_Clkin_Period 10.000
SET_PARAMETER Dcm_Clkgen_Spread_Spectrum NONE
SET_PARAMETER Dcm_Clkgen_Clk_Out1_Port CLKFX
SET_PARAMETER Dcm_Clkgen_Clk_Out2_Port CLKFX
SET_PARAMETER Dcm_Clkgen_Clk_Out3_Port CLKFX
SET_PARAMETER Override_Pll false
SET_PARAMETER Pll_Notes None
SET_PARAMETER Pll_Bandwidth OPTIMIZED
SET_PARAMETER Pll_Clkfbout_Mult 9
SET_PARAMETER Pll_Clkfbout_Phase 0.000
SET_PARAMETER Pll_Clk_Feedback CLKFBOUT
SET_PARAMETER Pll_Divclk_Divide 1
SET_PARAMETER Pll_Clkin_Period 20.000
SET_PARAMETER Pll_Compensation INTERNAL
SET_PARAMETER Pll_Ref_Jitter 0.010
SET_PARAMETER Pll_Clkout0_Divide 6
SET_PARAMETER Pll_Clkout0_Duty_Cycle 0.500
SET_PARAMETER Pll_Clkout0_Phase 0.000
SET_PARAMETER Pll_Clkout1_Divide 3
SET_PARAMETER Pll_Clkout1_Duty_Cycle 0.500
SET_PARAMETER Pll_Clkout1_Phase 0.000
SET_PARAMETER Pll_Clkout2_Divide 1
SET_PARAMETER Pll_Clkout2_Duty_Cycle 0.500
SET_PARAMETER Pll_Clkout2_Phase 0.000
SET_PARAMETER Pll_Clkout3_Divide 1
SET_PARAMETER Pll_Clkout3_Duty_Cycle 0.500
SET_PARAMETER Pll_Clkout3_Phase 0.000
SET_PARAMETER Pll_Clkout4_Divide 1
SET_PARAMETER Pll_Clkout4_Duty_Cycle 0.500
SET_PARAMETER Pll_Clkout4_Phase 0.000
SET_PARAMETER Pll_Clkout5_Divide 1
SET_PARAMETER Pll_Clkout5_Duty_Cycle 0.500
SET_PARAMETER Pll_Clkout5_Phase 0.000
SET_PARAMETER dcm_pll_cascade NONE
SET_PARAMETER clock_mgr_type AUTO
SET_PARAMETER primtype_sel PLL_BASE
SET_PARAMETER primitive MMCM
SET_PARAMETER SS_Mode CENTER_HIGH
SET_PARAMETER SS_Mod_Freq 250
SET_SIM_PARAMETER c_clkout2_used 1
SET_SIM_PARAMETER c_clkout3_used 0
SET_SIM_PARAMETER c_clkout4_used 0
SET_SIM_PARAMETER c_clkout5_used 0
SET_SIM_PARAMETER c_clkout6_used 0
SET_SIM_PARAMETER c_clkout7_used 0
SET_SIM_PARAMETER c_use_clkout1_bar 0
SET_SIM_PARAMETER c_use_clkout2_bar 0
SET_SIM_PARAMETER c_use_clkout3_bar 0
SET_SIM_PARAMETER c_use_clkout4_bar 0
SET_SIM_PARAMETER c_component_name hdmi_clk
SET_SIM_PARAMETER c_platform lin64
SET_SIM_PARAMETER c_use_freq_synth 1
SET_SIM_PARAMETER c_use_phase_alignment 0
SET_SIM_PARAMETER c_prim_in_jitter 0.010
SET_SIM_PARAMETER c_secondary_in_jitter 0.010
SET_SIM_PARAMETER c_jitter_sel No_Jitter
SET_SIM_PARAMETER c_use_min_power 0
SET_SIM_PARAMETER c_use_min_o_jitter 0
SET_SIM_PARAMETER c_use_max_i_jitter 0
SET_SIM_PARAMETER c_use_dyn_phase_shift 0
SET_SIM_PARAMETER c_use_inclk_switchover 0
SET_SIM_PARAMETER c_use_dyn_reconfig 0
SET_SIM_PARAMETER c_use_spread_spectrum 0
SET_SIM_PARAMETER c_use_spread_spectrum_1 0
SET_SIM_PARAMETER c_primtype_sel PLL_BASE
SET_SIM_PARAMETER c_use_clk_valid 0
SET_SIM_PARAMETER c_prim_in_freq 50
SET_SIM_PARAMETER c_in_freq_units Units_MHz
SET_SIM_PARAMETER c_secondary_in_freq 100.000
SET_SIM_PARAMETER c_feedback_source FDBK_AUTO
SET_SIM_PARAMETER c_prim_source Single_ended_clock_capable_pin
SET_SIM_PARAMETER c_secondary_source Single_ended_clock_capable_pin
SET_SIM_PARAMETER c_clkfb_in_signaling SINGLE
SET_SIM_PARAMETER c_use_reset 0
SET_SIM_PARAMETER c_use_locked 0
SET_SIM_PARAMETER c_use_inclk_stopped 0
SET_SIM_PARAMETER c_use_clkfb_stopped 0
SET_SIM_PARAMETER c_use_power_down 0
SET_SIM_PARAMETER c_use_status 0
SET_SIM_PARAMETER c_use_freeze 0
SET_SIM_PARAMETER c_num_out_clks 2
SET_SIM_PARAMETER c_clkout1_drives BUFG
SET_SIM_PARAMETER c_clkout2_drives BUFG
SET_SIM_PARAMETER c_clkout3_drives BUFG
SET_SIM_PARAMETER c_clkout4_drives BUFG
SET_SIM_PARAMETER c_clkout5_drives BUFG
SET_SIM_PARAMETER c_clkout6_drives BUFG
SET_SIM_PARAMETER c_clkout7_drives BUFG
SET_SIM_PARAMETER c_inclk_sum_row0 "Input Clock Freq (MHz) Input Jitter (UI)"
SET_SIM_PARAMETER c_inclk_sum_row1 __primary______________50____________0.010
SET_SIM_PARAMETER c_inclk_sum_row2 no_secondary_input_clock
SET_SIM_PARAMETER c_outclk_sum_row0a "Output Output Phase Duty Pk-to-Pk Phase"
SET_SIM_PARAMETER c_outclk_sum_row0b "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
SET_SIM_PARAMETER c_outclk_sum_row1 CLK_OUT1____75.000______0.000______50.0______248.869____240.171
SET_SIM_PARAMETER c_outclk_sum_row2 CLK_OUT2___150.000______0.000______50.0______216.897____240.171
SET_SIM_PARAMETER c_outclk_sum_row3 no_CLK_OUT3_output
SET_SIM_PARAMETER c_outclk_sum_row4 no_CLK_OUT4_output
SET_SIM_PARAMETER c_outclk_sum_row5 no_CLK_OUT5_output
SET_SIM_PARAMETER c_outclk_sum_row6 no_CLK_OUT6_output
SET_SIM_PARAMETER c_outclk_sum_row7 no_CLK_OUT7_output
SET_SIM_PARAMETER c_clkout1_requested_out_freq 75
SET_SIM_PARAMETER c_clkout2_requested_out_freq 150
SET_SIM_PARAMETER c_clkout3_requested_out_freq 100.000
SET_SIM_PARAMETER c_clkout4_requested_out_freq 100.000
SET_SIM_PARAMETER c_clkout5_requested_out_freq 100.000
SET_SIM_PARAMETER c_clkout6_requested_out_freq 100.000
SET_SIM_PARAMETER c_clkout7_requested_out_freq 100.000
SET_SIM_PARAMETER c_clkout1_requested_phase 0.000
SET_SIM_PARAMETER c_clkout2_requested_phase 0.000
SET_SIM_PARAMETER c_clkout3_requested_phase 0.000
SET_SIM_PARAMETER c_clkout4_requested_phase 0.000
SET_SIM_PARAMETER c_clkout5_requested_phase 0.000
SET_SIM_PARAMETER c_clkout6_requested_phase 0.000
SET_SIM_PARAMETER c_clkout7_requested_phase 0.000
SET_SIM_PARAMETER c_clkout1_requested_duty_cycle 50.000
SET_SIM_PARAMETER c_clkout2_requested_duty_cycle 50.000
SET_SIM_PARAMETER c_clkout3_requested_duty_cycle 50.000
SET_SIM_PARAMETER c_clkout4_requested_duty_cycle 50.000
SET_SIM_PARAMETER c_clkout5_requested_duty_cycle 50.000
SET_SIM_PARAMETER c_clkout6_requested_duty_cycle 50.000
SET_SIM_PARAMETER c_clkout7_requested_duty_cycle 50.000
SET_SIM_PARAMETER c_clkout1_out_freq 75.000
SET_SIM_PARAMETER c_clkout2_out_freq 150.000
SET_SIM_PARAMETER c_clkout3_out_freq N/A
SET_SIM_PARAMETER c_clkout4_out_freq N/A
SET_SIM_PARAMETER c_clkout5_out_freq N/A
SET_SIM_PARAMETER c_clkout6_out_freq N/A
SET_SIM_PARAMETER c_clkout7_out_freq N/A
SET_SIM_PARAMETER c_clkout1_phase 0.000
SET_SIM_PARAMETER c_clkout2_phase 0.000
SET_SIM_PARAMETER c_clkout3_phase N/A
SET_SIM_PARAMETER c_clkout4_phase N/A
SET_SIM_PARAMETER c_clkout5_phase N/A
SET_SIM_PARAMETER c_clkout6_phase N/A
SET_SIM_PARAMETER c_clkout7_phase N/A
SET_SIM_PARAMETER c_clkout1_duty_cycle 50.0
SET_SIM_PARAMETER c_clkout2_duty_cycle 50.0
SET_SIM_PARAMETER c_clkout3_duty_cycle N/A
SET_SIM_PARAMETER c_clkout4_duty_cycle N/A
SET_SIM_PARAMETER c_clkout5_duty_cycle N/A
SET_SIM_PARAMETER c_clkout6_duty_cycle N/A
SET_SIM_PARAMETER c_clkout7_duty_cycle N/A
SET_SIM_PARAMETER c_mmcm_notes None
SET_SIM_PARAMETER c_mmcm_bandwidth OPTIMIZED
SET_SIM_PARAMETER c_mmcm_clkfbout_mult_f 4.000
SET_SIM_PARAMETER c_mmcm_clkin1_period 10.000
SET_SIM_PARAMETER c_mmcm_clkin2_period 10.000
SET_SIM_PARAMETER c_mmcm_clkout4_cascade FALSE
SET_SIM_PARAMETER c_mmcm_clock_hold FALSE
SET_SIM_PARAMETER c_mmcm_compensation ZHOLD
SET_SIM_PARAMETER c_mmcm_divclk_divide 1
SET_SIM_PARAMETER c_mmcm_ref_jitter1 0.010
SET_SIM_PARAMETER c_mmcm_ref_jitter2 0.010
SET_SIM_PARAMETER c_mmcm_startup_wait FALSE
SET_SIM_PARAMETER c_mmcm_clkout0_divide_f 4.000
SET_SIM_PARAMETER c_mmcm_clkout1_divide 1
SET_SIM_PARAMETER c_mmcm_clkout2_divide 1
SET_SIM_PARAMETER c_mmcm_clkout3_divide 1
SET_SIM_PARAMETER c_mmcm_clkout4_divide 1
SET_SIM_PARAMETER c_mmcm_clkout5_divide 1
SET_SIM_PARAMETER c_mmcm_clkout6_divide 1
SET_SIM_PARAMETER c_mmcm_clkout0_duty_cycle 0.500
SET_SIM_PARAMETER c_mmcm_clkout1_duty_cycle 0.500
SET_SIM_PARAMETER c_mmcm_clkout2_duty_cycle 0.500
SET_SIM_PARAMETER c_mmcm_clkout3_duty_cycle 0.500
SET_SIM_PARAMETER c_mmcm_clkout4_duty_cycle 0.500
SET_SIM_PARAMETER c_mmcm_clkout5_duty_cycle 0.500
SET_SIM_PARAMETER c_mmcm_clkout6_duty_cycle 0.500
SET_SIM_PARAMETER c_mmcm_clkfbout_phase 0.000
SET_SIM_PARAMETER c_mmcm_clkout0_phase 0.000
SET_SIM_PARAMETER c_mmcm_clkout1_phase 0.000
SET_SIM_PARAMETER c_mmcm_clkout2_phase 0.000
SET_SIM_PARAMETER c_mmcm_clkout3_phase 0.000
SET_SIM_PARAMETER c_mmcm_clkout4_phase 0.000
SET_SIM_PARAMETER c_mmcm_clkout5_phase 0.000
SET_SIM_PARAMETER c_mmcm_clkout6_phase 0.000
SET_SIM_PARAMETER c_mmcm_clkfbout_use_fine_ps FALSE
SET_SIM_PARAMETER c_mmcm_clkout0_use_fine_ps FALSE
SET_SIM_PARAMETER c_mmcm_clkout1_use_fine_ps FALSE
SET_SIM_PARAMETER c_mmcm_clkout2_use_fine_ps FALSE
SET_SIM_PARAMETER c_mmcm_clkout3_use_fine_ps FALSE
SET_SIM_PARAMETER c_mmcm_clkout4_use_fine_ps FALSE
SET_SIM_PARAMETER c_mmcm_clkout5_use_fine_ps FALSE
SET_SIM_PARAMETER c_mmcm_clkout6_use_fine_ps FALSE
SET_SIM_PARAMETER c_pll_notes None
SET_SIM_PARAMETER c_pll_bandwidth OPTIMIZED
SET_SIM_PARAMETER c_pll_clk_feedback CLKFBOUT
SET_SIM_PARAMETER c_pll_clkfbout_mult 9
SET_SIM_PARAMETER c_pll_clkin_period 20.000
SET_SIM_PARAMETER c_pll_compensation INTERNAL
SET_SIM_PARAMETER c_pll_divclk_divide 1
SET_SIM_PARAMETER c_pll_ref_jitter 0.010
SET_SIM_PARAMETER c_pll_clkout0_divide 6
SET_SIM_PARAMETER c_pll_clkout1_divide 3
SET_SIM_PARAMETER c_pll_clkout2_divide 1
SET_SIM_PARAMETER c_pll_clkout3_divide 1
SET_SIM_PARAMETER c_pll_clkout4_divide 1
SET_SIM_PARAMETER c_pll_clkout5_divide 1
SET_SIM_PARAMETER c_pll_clkout0_duty_cycle 0.500
SET_SIM_PARAMETER c_pll_clkout1_duty_cycle 0.500
SET_SIM_PARAMETER c_pll_clkout2_duty_cycle 0.500
SET_SIM_PARAMETER c_pll_clkout3_duty_cycle 0.500
SET_SIM_PARAMETER c_pll_clkout4_duty_cycle 0.500
SET_SIM_PARAMETER c_pll_clkout5_duty_cycle 0.500
SET_SIM_PARAMETER c_pll_clkfbout_phase 0.000
SET_SIM_PARAMETER c_pll_clkout0_phase 0.000
SET_SIM_PARAMETER c_pll_clkout1_phase 0.000
SET_SIM_PARAMETER c_pll_clkout2_phase 0.000
SET_SIM_PARAMETER c_pll_clkout3_phase 0.000
SET_SIM_PARAMETER c_pll_clkout4_phase 0.000
SET_SIM_PARAMETER c_pll_clkout5_phase 0.000
SET_SIM_PARAMETER c_dcm_notes None
SET_SIM_PARAMETER c_dcm_clkdv_divide 2.000
SET_SIM_PARAMETER c_dcm_clkfx_divide 2
SET_SIM_PARAMETER c_dcm_clkfx_multiply 3
SET_SIM_PARAMETER c_dcm_clkin_divide_by_2 FALSE
SET_SIM_PARAMETER c_dcm_clkin_period 20.0
SET_SIM_PARAMETER c_dcm_clkout_phase_shift NONE
SET_SIM_PARAMETER c_dcm_clk_feedback NONE
SET_SIM_PARAMETER c_dcm_clk_feedback_port NONE
SET_SIM_PARAMETER c_dcm_deskew_adjust SYSTEM_SYNCHRONOUS
SET_SIM_PARAMETER c_dcm_phase_shift 0
SET_SIM_PARAMETER c_dcm_startup_wait FALSE
SET_SIM_PARAMETER c_dcm_clk_out1_port CLKFX
SET_SIM_PARAMETER c_dcm_clk_out2_port CLK0
SET_SIM_PARAMETER c_dcm_clk_out3_port NONE
SET_SIM_PARAMETER c_dcm_clk_out4_port NONE
SET_SIM_PARAMETER c_dcm_clk_out5_port NONE
SET_SIM_PARAMETER c_dcm_clk_out6_port NONE
SET_SIM_PARAMETER c_dcm_clkgen_notes None
SET_SIM_PARAMETER c_dcm_clkgen_clkfxdv_divide 2
SET_SIM_PARAMETER c_dcm_clkgen_clkfx_divide 1
SET_SIM_PARAMETER c_dcm_clkgen_clkfx_multiply 4
SET_SIM_PARAMETER c_dcm_clkgen_dfs_bandwidth OPTIMIZED
SET_SIM_PARAMETER c_dcm_clkgen_prog_md_bandwidth OPTIMIZED
SET_SIM_PARAMETER c_dcm_clkgen_clkin_period 20.0
SET_SIM_PARAMETER c_dcm_clkgen_clkfx_md_max 0.000
SET_SIM_PARAMETER c_dcm_clkgen_spread_spectrum NONE
SET_SIM_PARAMETER c_dcm_clkgen_startup_wait FALSE
SET_SIM_PARAMETER c_dcm_clkgen_clk_out1_port CLKFX
SET_SIM_PARAMETER c_dcm_clkgen_clk_out2_port CLKFX
SET_SIM_PARAMETER c_dcm_clkgen_clk_out3_port NONE
SET_SIM_PARAMETER c_clock_mgr_type AUTO
SET_SIM_PARAMETER c_override_mmcm 0
SET_SIM_PARAMETER c_override_pll 0
SET_SIM_PARAMETER c_override_dcm 0
SET_SIM_PARAMETER c_override_dcm_clkgen 0
SET_SIM_PARAMETER c_dcm_pll_cascade NONE
SET_SIM_PARAMETER c_primary_port CLK_IN1
SET_SIM_PARAMETER c_secondary_port CLK_IN2
SET_SIM_PARAMETER c_clk_out1_port CLK_OUT1
SET_SIM_PARAMETER c_clk_out2_port CLK_OUT2
SET_SIM_PARAMETER c_clk_out3_port CLK_OUT3
SET_SIM_PARAMETER c_clk_out4_port CLK_OUT4
SET_SIM_PARAMETER c_clk_out5_port CLK_OUT5
SET_SIM_PARAMETER c_clk_out6_port CLK_OUT6
SET_SIM_PARAMETER c_clk_out7_port CLK_OUT7
SET_SIM_PARAMETER c_reset_port RESET
SET_SIM_PARAMETER c_locked_port LOCKED
SET_SIM_PARAMETER c_clkfb_in_port CLKFB_IN
SET_SIM_PARAMETER c_clkfb_in_p_port CLKFB_IN_P
SET_SIM_PARAMETER c_clkfb_in_n_port CLKFB_IN_N
SET_SIM_PARAMETER c_clkfb_out_port CLKFB_OUT
SET_SIM_PARAMETER c_clkfb_out_p_port CLKFB_OUT_P
SET_SIM_PARAMETER c_clkfb_out_n_port CLKFB_OUT_N
SET_SIM_PARAMETER c_power_down_port POWER_DOWN
SET_SIM_PARAMETER c_daddr_port DADDR
SET_SIM_PARAMETER c_dclk_port DCLK
SET_SIM_PARAMETER c_drdy_port DRDY
SET_SIM_PARAMETER c_dwe_port DWE
SET_SIM_PARAMETER c_din_port DIN
SET_SIM_PARAMETER c_dout_port DOUT
SET_SIM_PARAMETER c_den_port DEN
SET_SIM_PARAMETER c_psclk_port PSCLK
SET_SIM_PARAMETER c_psen_port PSEN
SET_SIM_PARAMETER c_psincdec_port PSINCDEC
SET_SIM_PARAMETER c_psdone_port PSDONE
SET_SIM_PARAMETER c_clk_valid_port CLK_VALID
SET_SIM_PARAMETER c_status_port STATUS
SET_SIM_PARAMETER c_clk_in_sel_port CLK_IN_SEL
SET_SIM_PARAMETER c_input_clk_stopped_port INPUT_CLK_STOPPED
SET_SIM_PARAMETER c_clkfb_stopped_port CLKFB_STOPPED
SET_SIM_PARAMETER c_clkin1_jitter_ps 200.0
SET_SIM_PARAMETER c_clkin2_jitter_ps 100.0
SET_SIM_PARAMETER c_primitive MMCM
SET_SIM_PARAMETER c_ss_mode CENTER_HIGH
SET_SIM_PARAMETER c_ss_mod_period 4000
SET_CORE_NAME Clocking Wizard
SET_CORE_VERSION 3.6
SET_CORE_VLNV xilinx.com:ip:clk_wiz:3.6
SET_CORE_CLASS com.xilinx.ip.clk_wiz_v3_6.clk_wiz_v3_6
SET_CORE_PATH /opt/Xilinx/14.7/ISE_DS/ISE/coregen/ip/xilinx/primary/com/xilinx/ip/clk_wiz_v3_6
SET_CORE_GUIPATH /opt/Xilinx/14.7/ISE_DS/ISE/coregen/ip/xilinx/primary/com/xilinx/ip/clk_wiz_v3_6/gui/clk_wiz_v3_6.tcl
SET_CORE_DATASHEET /opt/Xilinx/14.7/ISE_DS/ISE/coregen/ip/xilinx/primary/com/xilinx/ip/clk_wiz_v3_6/doc/pg065_clk_wiz.pdf
ADD_CORE_DOCUMENT </opt/Xilinx/14.7/ISE_DS/ISE/coregen/ip/xilinx/primary/com/xilinx/ip/clk_wiz_v3_6/doc/pg065_clk_wiz.pdf><pg065_clk_wiz.pdf>
ADD_CORE_DOCUMENT </opt/Xilinx/14.7/ISE_DS/ISE/coregen/ip/xilinx/primary/com/xilinx/ip/clk_wiz_v3_6/doc/clk_wiz_v3_6_readme.txt><clk_wiz_v3_6_readme.txt>
ADD_CORE_DOCUMENT </opt/Xilinx/14.7/ISE_DS/ISE/coregen/ip/xilinx/primary/com/xilinx/ip/clk_wiz_v3_6/doc/clk_wiz_v3_6_vinfo.html><clk_wiz_v3_6_vinfo.html>

505
ipcore_dir/tmp/customization_gui.0.901080844412.out Normal file
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SET_FLAG DEBUG FALSE
SET_FLAG MODE BATCH
SET_FLAG STANDALONE_MODE FALSE
SET_PREFERENCE devicefamily spartan6
SET_PREFERENCE device xc6slx9
SET_PREFERENCE speedgrade -2
SET_PREFERENCE package tqg144
SET_PREFERENCE verilogsim true
SET_PREFERENCE vhdlsim false
SET_PREFERENCE simulationfiles Behavioral
SET_PREFERENCE busformat BusFormatAngleBracketNotRipped
SET_PREFERENCE outputdirectory /home/tim/Projects/z80/hdmi/ipcore_dir/
SET_PREFERENCE workingdirectory /home/tim/Projects/z80/hdmi/ipcore_dir/tmp/
SET_PREFERENCE subworkingdirectory /home/tim/Projects/z80/hdmi/ipcore_dir/tmp/_cg/
SET_PREFERENCE transientdirectory /home/tim/Projects/z80/hdmi/ipcore_dir/tmp/_cg/_dbg/
SET_PREFERENCE designentry Verilog
SET_PREFERENCE flowvendor Other
SET_PREFERENCE addpads false
SET_PREFERENCE projectname coregen
SET_PREFERENCE formalverification false
SET_PREFERENCE asysymbol false
SET_PREFERENCE implementationfiletype Ngc
SET_PREFERENCE foundationsym false
SET_PREFERENCE createndf false
SET_PREFERENCE removerpms false
SET_PARAMETER Component_Name hdmi_clk
SET_PARAMETER Use_Freq_Synth true
SET_PARAMETER Use_Phase_Alignment false
SET_PARAMETER Use_Min_Power false
SET_PARAMETER Use_Dyn_Phase_Shift false
SET_PARAMETER Use_Dyn_Reconfig false
SET_PARAMETER Jitter_Sel No_Jitter
SET_PARAMETER Use_Spread_Spectrum false
SET_PARAMETER Use_Spread_Spectrum_1 false
SET_PARAMETER Prim_In_Freq 50
SET_PARAMETER In_Freq_Units Units_MHz
SET_PARAMETER In_Jitter_Units Units_UI
SET_PARAMETER Relative_Inclk REL_PRIMARY
SET_PARAMETER Secondary_In_Freq 100.000
SET_PARAMETER Jitter_Options UI
SET_PARAMETER Clkin1_UI_Jitter 0.010
SET_PARAMETER Clkin2_UI_Jitter 0.010
SET_PARAMETER Prim_In_Jitter 0.010
SET_PARAMETER Secondary_In_Jitter 0.010
SET_PARAMETER Clkin1_Jitter_Ps 200.0
SET_PARAMETER Clkin2_Jitter_Ps 100.0
SET_PARAMETER Clkout2_Used true
SET_PARAMETER Clkout3_Used false
SET_PARAMETER Clkout4_Used false
SET_PARAMETER Clkout5_Used false
SET_PARAMETER Clkout6_Used false
SET_PARAMETER Clkout7_Used false
SET_PARAMETER Num_Out_Clks 2
SET_PARAMETER Clk_Out1_Use_Fine_Ps_GUI false
SET_PARAMETER Clk_Out2_Use_Fine_Ps_GUI false
SET_PARAMETER Clk_Out3_Use_Fine_Ps_GUI false
SET_PARAMETER Clk_Out4_Use_Fine_Ps_GUI false
SET_PARAMETER Clk_Out5_Use_Fine_Ps_GUI false
SET_PARAMETER Clk_Out6_Use_Fine_Ps_GUI false
SET_PARAMETER Clk_Out7_Use_Fine_Ps_GUI false
SET_PARAMETER primary_port CLK_IN1
SET_PARAMETER CLK_OUT1_port CLK_OUT1
SET_PARAMETER CLK_OUT2_port CLK_OUT2
SET_PARAMETER CLK_OUT3_port CLK_OUT3
SET_PARAMETER CLK_OUT4_port CLK_OUT4
SET_PARAMETER CLK_OUT5_port CLK_OUT5
SET_PARAMETER CLK_OUT6_port CLK_OUT6
SET_PARAMETER CLK_OUT7_port CLK_OUT7
SET_PARAMETER DADDR_port DADDR
SET_PARAMETER DCLK_port DCLK
SET_PARAMETER DRDY_port DRDY
SET_PARAMETER DWE_port DWE
SET_PARAMETER DIN_port DIN
SET_PARAMETER DOUT_port DOUT
SET_PARAMETER DEN_port DEN
SET_PARAMETER PSCLK_port PSCLK
SET_PARAMETER PSEN_port PSEN
SET_PARAMETER PSINCDEC_port PSINCDEC
SET_PARAMETER PSDONE_port PSDONE
SET_PARAMETER Clkout1_Requested_Out_Freq 75
SET_PARAMETER Clkout1_Requested_Phase 0.000
SET_PARAMETER Clkout1_Requested_Duty_Cycle 50.000
SET_PARAMETER Clkout2_Requested_Out_Freq 150
SET_PARAMETER Clkout2_Requested_Phase 0.000
SET_PARAMETER Clkout2_Requested_Duty_Cycle 50.000
SET_PARAMETER Clkout3_Requested_Out_Freq 100.000
SET_PARAMETER Clkout3_Requested_Phase 0.000
SET_PARAMETER Clkout3_Requested_Duty_Cycle 50.000
SET_PARAMETER Clkout4_Requested_Out_Freq 100.000
SET_PARAMETER Clkout4_Requested_Phase 0.000
SET_PARAMETER Clkout4_Requested_Duty_Cycle 50.000
SET_PARAMETER Clkout5_Requested_Out_Freq 100.000
SET_PARAMETER Clkout5_Requested_Phase 0.000
SET_PARAMETER Clkout5_Requested_Duty_Cycle 50.000
SET_PARAMETER Clkout6_Requested_Out_Freq 100.000
SET_PARAMETER Clkout6_Requested_Phase 0.000
SET_PARAMETER Clkout6_Requested_Duty_Cycle 50.000
SET_PARAMETER Clkout7_Requested_Out_Freq 100.000
SET_PARAMETER Clkout7_Requested_Phase 0.000
SET_PARAMETER Clkout7_Requested_Duty_Cycle 50.000
SET_PARAMETER Use_Max_I_Jitter false
SET_PARAMETER Use_Min_O_Jitter false
SET_PARAMETER Prim_Source Single_ended_clock_capable_pin
SET_PARAMETER Use_Inclk_Switchover false
SET_PARAMETER secondary_port CLK_IN2
SET_PARAMETER Secondary_Source Single_ended_clock_capable_pin
SET_PARAMETER Clkout1_Drives BUFG
SET_PARAMETER Clkout2_Drives BUFG
SET_PARAMETER Clkout3_Drives BUFG
SET_PARAMETER Clkout4_Drives BUFG
SET_PARAMETER Clkout5_Drives BUFG
SET_PARAMETER Clkout6_Drives BUFG
SET_PARAMETER Clkout7_Drives BUFG
SET_PARAMETER Feedback_Source FDBK_AUTO
SET_PARAMETER Clkfb_In_Signaling SINGLE
SET_PARAMETER CLKFB_IN_port CLKFB_IN
SET_PARAMETER CLKFB_IN_P_port CLKFB_IN_P
SET_PARAMETER CLKFB_IN_N_port CLKFB_IN_N
SET_PARAMETER CLKFB_OUT_port CLKFB_OUT
SET_PARAMETER CLKFB_OUT_P_port CLKFB_OUT_P
SET_PARAMETER CLKFB_OUT_N_port CLKFB_OUT_N
SET_PARAMETER Platform lin64
SET_PARAMETER Summary_Strings empty
SET_PARAMETER Use_Locked false
SET_PARAMETER calc_done DONE
SET_PARAMETER Use_Reset false
SET_PARAMETER Use_Power_Down false
SET_PARAMETER Use_Status false
SET_PARAMETER Use_Freeze false
SET_PARAMETER Use_Clk_Valid false
SET_PARAMETER Use_Inclk_Stopped false
SET_PARAMETER Use_Clkfb_Stopped false
SET_PARAMETER RESET_port RESET
SET_PARAMETER LOCKED_port LOCKED
SET_PARAMETER Power_Down_port POWER_DOWN
SET_PARAMETER CLK_VALID_port CLK_VALID
SET_PARAMETER STATUS_port STATUS
SET_PARAMETER CLK_IN_SEL_port CLK_IN_SEL
SET_PARAMETER INPUT_CLK_STOPPED_port INPUT_CLK_STOPPED
SET_PARAMETER CLKFB_STOPPED_port CLKFB_STOPPED
SET_PARAMETER Override_Mmcm false
SET_PARAMETER Mmcm_Notes None
SET_PARAMETER Mmcm_Divclk_Divide 1
SET_PARAMETER Mmcm_Bandwidth OPTIMIZED
SET_PARAMETER Mmcm_Clkfbout_Mult_F 4.000
SET_PARAMETER Mmcm_Clkfbout_Phase 0.000
SET_PARAMETER Mmcm_Clkfbout_Use_Fine_Ps false
SET_PARAMETER Mmcm_Clkin1_Period 10.000
SET_PARAMETER Mmcm_Clkin2_Period 10.000
SET_PARAMETER Mmcm_Clkout4_Cascade false
SET_PARAMETER Mmcm_Clock_Hold false
SET_PARAMETER Mmcm_Compensation ZHOLD
SET_PARAMETER Mmcm_Ref_Jitter1 0.010
SET_PARAMETER Mmcm_Ref_Jitter2 0.010
SET_PARAMETER Mmcm_Startup_Wait false
SET_PARAMETER Mmcm_Clkout0_Divide_F 4.000
SET_PARAMETER Mmcm_Clkout0_Duty_Cycle 0.500
SET_PARAMETER Mmcm_Clkout0_Phase 0.000
SET_PARAMETER Mmcm_Clkout0_Use_Fine_Ps false
SET_PARAMETER Mmcm_Clkout1_Divide 1
SET_PARAMETER Mmcm_Clkout1_Duty_Cycle 0.500
SET_PARAMETER Mmcm_Clkout1_Phase 0.000
SET_PARAMETER Mmcm_Clkout1_Use_Fine_Ps false
SET_PARAMETER Mmcm_Clkout2_Divide 1
SET_PARAMETER Mmcm_Clkout2_Duty_Cycle 0.500
SET_PARAMETER Mmcm_Clkout2_Phase 0.000
SET_PARAMETER Mmcm_Clkout2_Use_Fine_Ps false
SET_PARAMETER Mmcm_Clkout3_Divide 1
SET_PARAMETER Mmcm_Clkout3_Duty_Cycle 0.500
SET_PARAMETER Mmcm_Clkout3_Phase 0.000
SET_PARAMETER Mmcm_Clkout3_Use_Fine_Ps false
SET_PARAMETER Mmcm_Clkout4_Divide 1
SET_PARAMETER Mmcm_Clkout4_Duty_Cycle 0.500
SET_PARAMETER Mmcm_Clkout4_Phase 0.000
SET_PARAMETER Mmcm_Clkout4_Use_Fine_Ps false
SET_PARAMETER Mmcm_Clkout5_Divide 1
SET_PARAMETER Mmcm_Clkout5_Duty_Cycle 0.500
SET_PARAMETER Mmcm_Clkout5_Phase 0.000
SET_PARAMETER Mmcm_Clkout5_Use_Fine_Ps false
SET_PARAMETER Mmcm_Clkout6_Divide 1
SET_PARAMETER Mmcm_Clkout6_Duty_Cycle 0.500
SET_PARAMETER Mmcm_Clkout6_Phase 0.000
SET_PARAMETER Mmcm_Clkout6_Use_Fine_Ps false
SET_PARAMETER Override_Dcm false
SET_PARAMETER Dcm_Notes None
SET_PARAMETER Dcm_Clkdv_Divide 2.0
SET_PARAMETER Dcm_Clkfx_Divide 2
SET_PARAMETER Dcm_Clkfx_Multiply 3
SET_PARAMETER Dcm_Clkin_Divide_By_2 false
SET_PARAMETER Dcm_Clkin_Period 20.000
SET_PARAMETER Dcm_Clkout_Phase_Shift NONE
SET_PARAMETER Dcm_Deskew_Adjust SYSTEM_SYNCHRONOUS
SET_PARAMETER Dcm_Phase_Shift 0
SET_PARAMETER Dcm_Clk_Feedback NONE
SET_PARAMETER Dcm_Startup_Wait false
SET_PARAMETER Dcm_Clk_Out1_Port CLKFX
SET_PARAMETER Dcm_Clk_Out2_Port CLK0
SET_PARAMETER Dcm_Clk_Out3_Port CLK0
SET_PARAMETER Dcm_Clk_Out4_Port CLK0
SET_PARAMETER Dcm_Clk_Out5_Port CLK0
SET_PARAMETER Dcm_Clk_Out6_Port CLK0
SET_PARAMETER Override_Dcm_Clkgen false
SET_PARAMETER Dcm_Clkgen_Notes None
SET_PARAMETER Dcm_Clkgen_Clkfx_Divide 1
SET_PARAMETER Dcm_Clkgen_Clkfx_Multiply 4
SET_PARAMETER Dcm_Clkgen_Clkfxdv_Divide 2
SET_PARAMETER Dcm_Clkgen_Clkfx_Md_Max 0.000
SET_PARAMETER Dcm_Clkgen_Startup_Wait false
SET_PARAMETER Dcm_Clkgen_Clkin_Period 10.000
SET_PARAMETER Dcm_Clkgen_Spread_Spectrum NONE
SET_PARAMETER Dcm_Clkgen_Clk_Out1_Port CLKFX
SET_PARAMETER Dcm_Clkgen_Clk_Out2_Port CLKFX
SET_PARAMETER Dcm_Clkgen_Clk_Out3_Port CLKFX
SET_PARAMETER Override_Pll false
SET_PARAMETER Pll_Notes None
SET_PARAMETER Pll_Bandwidth OPTIMIZED
SET_PARAMETER Pll_Clkfbout_Mult 9
SET_PARAMETER Pll_Clkfbout_Phase 0.000
SET_PARAMETER Pll_Clk_Feedback CLKFBOUT
SET_PARAMETER Pll_Divclk_Divide 1
SET_PARAMETER Pll_Clkin_Period 20.000
SET_PARAMETER Pll_Compensation INTERNAL
SET_PARAMETER Pll_Ref_Jitter 0.010
SET_PARAMETER Pll_Clkout0_Divide 6
SET_PARAMETER Pll_Clkout0_Duty_Cycle 0.500
SET_PARAMETER Pll_Clkout0_Phase 0.000
SET_PARAMETER Pll_Clkout1_Divide 3
SET_PARAMETER Pll_Clkout1_Duty_Cycle 0.500
SET_PARAMETER Pll_Clkout1_Phase 0.000
SET_PARAMETER Pll_Clkout2_Divide 1
SET_PARAMETER Pll_Clkout2_Duty_Cycle 0.500
SET_PARAMETER Pll_Clkout2_Phase 0.000
SET_PARAMETER Pll_Clkout3_Divide 1
SET_PARAMETER Pll_Clkout3_Duty_Cycle 0.500
SET_PARAMETER Pll_Clkout3_Phase 0.000
SET_PARAMETER Pll_Clkout4_Divide 1
SET_PARAMETER Pll_Clkout4_Duty_Cycle 0.500
SET_PARAMETER Pll_Clkout4_Phase 0.000
SET_PARAMETER Pll_Clkout5_Divide 1
SET_PARAMETER Pll_Clkout5_Duty_Cycle 0.500
SET_PARAMETER Pll_Clkout5_Phase 0.000
SET_PARAMETER dcm_pll_cascade NONE
SET_PARAMETER clock_mgr_type AUTO
SET_PARAMETER primtype_sel PLL_BASE
SET_PARAMETER primitive MMCM
SET_PARAMETER SS_Mode CENTER_HIGH
SET_PARAMETER SS_Mod_Freq 250
SET_SIM_PARAMETER c_clkout2_used 1
SET_SIM_PARAMETER c_clkout3_used 0
SET_SIM_PARAMETER c_clkout4_used 0
SET_SIM_PARAMETER c_clkout5_used 0
SET_SIM_PARAMETER c_clkout6_used 0
SET_SIM_PARAMETER c_clkout7_used 0
SET_SIM_PARAMETER c_use_clkout1_bar 0
SET_SIM_PARAMETER c_use_clkout2_bar 0
SET_SIM_PARAMETER c_use_clkout3_bar 0
SET_SIM_PARAMETER c_use_clkout4_bar 0
SET_SIM_PARAMETER c_component_name hdmi_clk
SET_SIM_PARAMETER c_platform lin64
SET_SIM_PARAMETER c_use_freq_synth 1
SET_SIM_PARAMETER c_use_phase_alignment 0
SET_SIM_PARAMETER c_prim_in_jitter 0.010
SET_SIM_PARAMETER c_secondary_in_jitter 0.010
SET_SIM_PARAMETER c_jitter_sel No_Jitter
SET_SIM_PARAMETER c_use_min_power 0
SET_SIM_PARAMETER c_use_min_o_jitter 0
SET_SIM_PARAMETER c_use_max_i_jitter 0
SET_SIM_PARAMETER c_use_dyn_phase_shift 0
SET_SIM_PARAMETER c_use_inclk_switchover 0
SET_SIM_PARAMETER c_use_dyn_reconfig 0
SET_SIM_PARAMETER c_use_spread_spectrum 0
SET_SIM_PARAMETER c_use_spread_spectrum_1 0
SET_SIM_PARAMETER c_primtype_sel PLL_BASE
SET_SIM_PARAMETER c_use_clk_valid 0
SET_SIM_PARAMETER c_prim_in_freq 50
SET_SIM_PARAMETER c_in_freq_units Units_MHz
SET_SIM_PARAMETER c_secondary_in_freq 100.000
SET_SIM_PARAMETER c_feedback_source FDBK_AUTO
SET_SIM_PARAMETER c_prim_source Single_ended_clock_capable_pin
SET_SIM_PARAMETER c_secondary_source Single_ended_clock_capable_pin
SET_SIM_PARAMETER c_clkfb_in_signaling SINGLE
SET_SIM_PARAMETER c_use_reset 0
SET_SIM_PARAMETER c_use_locked 0
SET_SIM_PARAMETER c_use_inclk_stopped 0
SET_SIM_PARAMETER c_use_clkfb_stopped 0
SET_SIM_PARAMETER c_use_power_down 0
SET_SIM_PARAMETER c_use_status 0
SET_SIM_PARAMETER c_use_freeze 0
SET_SIM_PARAMETER c_num_out_clks 2
SET_SIM_PARAMETER c_clkout1_drives BUFG
SET_SIM_PARAMETER c_clkout2_drives BUFG
SET_SIM_PARAMETER c_clkout3_drives BUFG
SET_SIM_PARAMETER c_clkout4_drives BUFG
SET_SIM_PARAMETER c_clkout5_drives BUFG
SET_SIM_PARAMETER c_clkout6_drives BUFG
SET_SIM_PARAMETER c_clkout7_drives BUFG
SET_SIM_PARAMETER c_inclk_sum_row0 "Input Clock Freq (MHz) Input Jitter (UI)"
SET_SIM_PARAMETER c_inclk_sum_row1 __primary______________50____________0.010
SET_SIM_PARAMETER c_inclk_sum_row2 no_secondary_input_clock
SET_SIM_PARAMETER c_outclk_sum_row0a "Output Output Phase Duty Pk-to-Pk Phase"
SET_SIM_PARAMETER c_outclk_sum_row0b "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
SET_SIM_PARAMETER c_outclk_sum_row1 CLK_OUT1____75.000______0.000______50.0______248.869____240.171
SET_SIM_PARAMETER c_outclk_sum_row2 CLK_OUT2___150.000______0.000______50.0______216.897____240.171
SET_SIM_PARAMETER c_outclk_sum_row3 no_CLK_OUT3_output
SET_SIM_PARAMETER c_outclk_sum_row4 no_CLK_OUT4_output
SET_SIM_PARAMETER c_outclk_sum_row5 no_CLK_OUT5_output
SET_SIM_PARAMETER c_outclk_sum_row6 no_CLK_OUT6_output
SET_SIM_PARAMETER c_outclk_sum_row7 no_CLK_OUT7_output
SET_SIM_PARAMETER c_clkout1_requested_out_freq 75
SET_SIM_PARAMETER c_clkout2_requested_out_freq 150
SET_SIM_PARAMETER c_clkout3_requested_out_freq 100.000
SET_SIM_PARAMETER c_clkout4_requested_out_freq 100.000
SET_SIM_PARAMETER c_clkout5_requested_out_freq 100.000
SET_SIM_PARAMETER c_clkout6_requested_out_freq 100.000
SET_SIM_PARAMETER c_clkout7_requested_out_freq 100.000
SET_SIM_PARAMETER c_clkout1_requested_phase 0.000
SET_SIM_PARAMETER c_clkout2_requested_phase 0.000
SET_SIM_PARAMETER c_clkout3_requested_phase 0.000
SET_SIM_PARAMETER c_clkout4_requested_phase 0.000
SET_SIM_PARAMETER c_clkout5_requested_phase 0.000
SET_SIM_PARAMETER c_clkout6_requested_phase 0.000
SET_SIM_PARAMETER c_clkout7_requested_phase 0.000
SET_SIM_PARAMETER c_clkout1_requested_duty_cycle 50.000
SET_SIM_PARAMETER c_clkout2_requested_duty_cycle 50.000
SET_SIM_PARAMETER c_clkout3_requested_duty_cycle 50.000
SET_SIM_PARAMETER c_clkout4_requested_duty_cycle 50.000
SET_SIM_PARAMETER c_clkout5_requested_duty_cycle 50.000
SET_SIM_PARAMETER c_clkout6_requested_duty_cycle 50.000
SET_SIM_PARAMETER c_clkout7_requested_duty_cycle 50.000
SET_SIM_PARAMETER c_clkout1_out_freq 75.000
SET_SIM_PARAMETER c_clkout2_out_freq 150.000
SET_SIM_PARAMETER c_clkout3_out_freq N/A
SET_SIM_PARAMETER c_clkout4_out_freq N/A
SET_SIM_PARAMETER c_clkout5_out_freq N/A
SET_SIM_PARAMETER c_clkout6_out_freq N/A
SET_SIM_PARAMETER c_clkout7_out_freq N/A
SET_SIM_PARAMETER c_clkout1_phase 0.000
SET_SIM_PARAMETER c_clkout2_phase 0.000
SET_SIM_PARAMETER c_clkout3_phase N/A
SET_SIM_PARAMETER c_clkout4_phase N/A
SET_SIM_PARAMETER c_clkout5_phase N/A
SET_SIM_PARAMETER c_clkout6_phase N/A
SET_SIM_PARAMETER c_clkout7_phase N/A
SET_SIM_PARAMETER c_clkout1_duty_cycle 50.0
SET_SIM_PARAMETER c_clkout2_duty_cycle 50.0
SET_SIM_PARAMETER c_clkout3_duty_cycle N/A
SET_SIM_PARAMETER c_clkout4_duty_cycle N/A
SET_SIM_PARAMETER c_clkout5_duty_cycle N/A
SET_SIM_PARAMETER c_clkout6_duty_cycle N/A
SET_SIM_PARAMETER c_clkout7_duty_cycle N/A
SET_SIM_PARAMETER c_mmcm_notes None
SET_SIM_PARAMETER c_mmcm_bandwidth OPTIMIZED
SET_SIM_PARAMETER c_mmcm_clkfbout_mult_f 4.000
SET_SIM_PARAMETER c_mmcm_clkin1_period 10.000
SET_SIM_PARAMETER c_mmcm_clkin2_period 10.000
SET_SIM_PARAMETER c_mmcm_clkout4_cascade FALSE
SET_SIM_PARAMETER c_mmcm_clock_hold FALSE
SET_SIM_PARAMETER c_mmcm_compensation ZHOLD
SET_SIM_PARAMETER c_mmcm_divclk_divide 1
SET_SIM_PARAMETER c_mmcm_ref_jitter1 0.010
SET_SIM_PARAMETER c_mmcm_ref_jitter2 0.010
SET_SIM_PARAMETER c_mmcm_startup_wait FALSE
SET_SIM_PARAMETER c_mmcm_clkout0_divide_f 4.000
SET_SIM_PARAMETER c_mmcm_clkout1_divide 1
SET_SIM_PARAMETER c_mmcm_clkout2_divide 1
SET_SIM_PARAMETER c_mmcm_clkout3_divide 1
SET_SIM_PARAMETER c_mmcm_clkout4_divide 1
SET_SIM_PARAMETER c_mmcm_clkout5_divide 1
SET_SIM_PARAMETER c_mmcm_clkout6_divide 1
SET_SIM_PARAMETER c_mmcm_clkout0_duty_cycle 0.500
SET_SIM_PARAMETER c_mmcm_clkout1_duty_cycle 0.500
SET_SIM_PARAMETER c_mmcm_clkout2_duty_cycle 0.500
SET_SIM_PARAMETER c_mmcm_clkout3_duty_cycle 0.500
SET_SIM_PARAMETER c_mmcm_clkout4_duty_cycle 0.500
SET_SIM_PARAMETER c_mmcm_clkout5_duty_cycle 0.500
SET_SIM_PARAMETER c_mmcm_clkout6_duty_cycle 0.500
SET_SIM_PARAMETER c_mmcm_clkfbout_phase 0.000
SET_SIM_PARAMETER c_mmcm_clkout0_phase 0.000
SET_SIM_PARAMETER c_mmcm_clkout1_phase 0.000
SET_SIM_PARAMETER c_mmcm_clkout2_phase 0.000
SET_SIM_PARAMETER c_mmcm_clkout3_phase 0.000
SET_SIM_PARAMETER c_mmcm_clkout4_phase 0.000
SET_SIM_PARAMETER c_mmcm_clkout5_phase 0.000
SET_SIM_PARAMETER c_mmcm_clkout6_phase 0.000
SET_SIM_PARAMETER c_mmcm_clkfbout_use_fine_ps FALSE
SET_SIM_PARAMETER c_mmcm_clkout0_use_fine_ps FALSE
SET_SIM_PARAMETER c_mmcm_clkout1_use_fine_ps FALSE
SET_SIM_PARAMETER c_mmcm_clkout2_use_fine_ps FALSE
SET_SIM_PARAMETER c_mmcm_clkout3_use_fine_ps FALSE
SET_SIM_PARAMETER c_mmcm_clkout4_use_fine_ps FALSE
SET_SIM_PARAMETER c_mmcm_clkout5_use_fine_ps FALSE
SET_SIM_PARAMETER c_mmcm_clkout6_use_fine_ps FALSE
SET_SIM_PARAMETER c_pll_notes None
SET_SIM_PARAMETER c_pll_bandwidth OPTIMIZED
SET_SIM_PARAMETER c_pll_clk_feedback CLKFBOUT
SET_SIM_PARAMETER c_pll_clkfbout_mult 9
SET_SIM_PARAMETER c_pll_clkin_period 20.000
SET_SIM_PARAMETER c_pll_compensation INTERNAL
SET_SIM_PARAMETER c_pll_divclk_divide 1
SET_SIM_PARAMETER c_pll_ref_jitter 0.010
SET_SIM_PARAMETER c_pll_clkout0_divide 6
SET_SIM_PARAMETER c_pll_clkout1_divide 3
SET_SIM_PARAMETER c_pll_clkout2_divide 1
SET_SIM_PARAMETER c_pll_clkout3_divide 1
SET_SIM_PARAMETER c_pll_clkout4_divide 1
SET_SIM_PARAMETER c_pll_clkout5_divide 1
SET_SIM_PARAMETER c_pll_clkout0_duty_cycle 0.500
SET_SIM_PARAMETER c_pll_clkout1_duty_cycle 0.500
SET_SIM_PARAMETER c_pll_clkout2_duty_cycle 0.500
SET_SIM_PARAMETER c_pll_clkout3_duty_cycle 0.500
SET_SIM_PARAMETER c_pll_clkout4_duty_cycle 0.500
SET_SIM_PARAMETER c_pll_clkout5_duty_cycle 0.500
SET_SIM_PARAMETER c_pll_clkfbout_phase 0.000
SET_SIM_PARAMETER c_pll_clkout0_phase 0.000
SET_SIM_PARAMETER c_pll_clkout1_phase 0.000
SET_SIM_PARAMETER c_pll_clkout2_phase 0.000
SET_SIM_PARAMETER c_pll_clkout3_phase 0.000
SET_SIM_PARAMETER c_pll_clkout4_phase 0.000
SET_SIM_PARAMETER c_pll_clkout5_phase 0.000
SET_SIM_PARAMETER c_dcm_notes None
SET_SIM_PARAMETER c_dcm_clkdv_divide 2.000
SET_SIM_PARAMETER c_dcm_clkfx_divide 2
SET_SIM_PARAMETER c_dcm_clkfx_multiply 3
SET_SIM_PARAMETER c_dcm_clkin_divide_by_2 FALSE
SET_SIM_PARAMETER c_dcm_clkin_period 20.0
SET_SIM_PARAMETER c_dcm_clkout_phase_shift NONE
SET_SIM_PARAMETER c_dcm_clk_feedback NONE
SET_SIM_PARAMETER c_dcm_clk_feedback_port NONE
SET_SIM_PARAMETER c_dcm_deskew_adjust SYSTEM_SYNCHRONOUS
SET_SIM_PARAMETER c_dcm_phase_shift 0
SET_SIM_PARAMETER c_dcm_startup_wait FALSE
SET_SIM_PARAMETER c_dcm_clk_out1_port CLKFX
SET_SIM_PARAMETER c_dcm_clk_out2_port CLK0
SET_SIM_PARAMETER c_dcm_clk_out3_port NONE
SET_SIM_PARAMETER c_dcm_clk_out4_port NONE
SET_SIM_PARAMETER c_dcm_clk_out5_port NONE
SET_SIM_PARAMETER c_dcm_clk_out6_port NONE
SET_SIM_PARAMETER c_dcm_clkgen_notes None
SET_SIM_PARAMETER c_dcm_clkgen_clkfxdv_divide 2
SET_SIM_PARAMETER c_dcm_clkgen_clkfx_divide 1
SET_SIM_PARAMETER c_dcm_clkgen_clkfx_multiply 4
SET_SIM_PARAMETER c_dcm_clkgen_dfs_bandwidth OPTIMIZED
SET_SIM_PARAMETER c_dcm_clkgen_prog_md_bandwidth OPTIMIZED
SET_SIM_PARAMETER c_dcm_clkgen_clkin_period 20.0
SET_SIM_PARAMETER c_dcm_clkgen_clkfx_md_max 0.000
SET_SIM_PARAMETER c_dcm_clkgen_spread_spectrum NONE
SET_SIM_PARAMETER c_dcm_clkgen_startup_wait FALSE
SET_SIM_PARAMETER c_dcm_clkgen_clk_out1_port CLKFX
SET_SIM_PARAMETER c_dcm_clkgen_clk_out2_port CLKFX
SET_SIM_PARAMETER c_dcm_clkgen_clk_out3_port NONE
SET_SIM_PARAMETER c_clock_mgr_type AUTO
SET_SIM_PARAMETER c_override_mmcm 0
SET_SIM_PARAMETER c_override_pll 0
SET_SIM_PARAMETER c_override_dcm 0
SET_SIM_PARAMETER c_override_dcm_clkgen 0
SET_SIM_PARAMETER c_dcm_pll_cascade NONE
SET_SIM_PARAMETER c_primary_port CLK_IN1
SET_SIM_PARAMETER c_secondary_port CLK_IN2
SET_SIM_PARAMETER c_clk_out1_port CLK_OUT1
SET_SIM_PARAMETER c_clk_out2_port CLK_OUT2
SET_SIM_PARAMETER c_clk_out3_port CLK_OUT3
SET_SIM_PARAMETER c_clk_out4_port CLK_OUT4
SET_SIM_PARAMETER c_clk_out5_port CLK_OUT5
SET_SIM_PARAMETER c_clk_out6_port CLK_OUT6
SET_SIM_PARAMETER c_clk_out7_port CLK_OUT7
SET_SIM_PARAMETER c_reset_port RESET
SET_SIM_PARAMETER c_locked_port LOCKED
SET_SIM_PARAMETER c_clkfb_in_port CLKFB_IN
SET_SIM_PARAMETER c_clkfb_in_p_port CLKFB_IN_P
SET_SIM_PARAMETER c_clkfb_in_n_port CLKFB_IN_N
SET_SIM_PARAMETER c_clkfb_out_port CLKFB_OUT
SET_SIM_PARAMETER c_clkfb_out_p_port CLKFB_OUT_P
SET_SIM_PARAMETER c_clkfb_out_n_port CLKFB_OUT_N
SET_SIM_PARAMETER c_power_down_port POWER_DOWN
SET_SIM_PARAMETER c_daddr_port DADDR
SET_SIM_PARAMETER c_dclk_port DCLK
SET_SIM_PARAMETER c_drdy_port DRDY
SET_SIM_PARAMETER c_dwe_port DWE
SET_SIM_PARAMETER c_din_port DIN
SET_SIM_PARAMETER c_dout_port DOUT
SET_SIM_PARAMETER c_den_port DEN
SET_SIM_PARAMETER c_psclk_port PSCLK
SET_SIM_PARAMETER c_psen_port PSEN
SET_SIM_PARAMETER c_psincdec_port PSINCDEC
SET_SIM_PARAMETER c_psdone_port PSDONE
SET_SIM_PARAMETER c_clk_valid_port CLK_VALID
SET_SIM_PARAMETER c_status_port STATUS
SET_SIM_PARAMETER c_clk_in_sel_port CLK_IN_SEL
SET_SIM_PARAMETER c_input_clk_stopped_port INPUT_CLK_STOPPED
SET_SIM_PARAMETER c_clkfb_stopped_port CLKFB_STOPPED
SET_SIM_PARAMETER c_clkin1_jitter_ps 200.0
SET_SIM_PARAMETER c_clkin2_jitter_ps 100.0
SET_SIM_PARAMETER c_primitive MMCM
SET_SIM_PARAMETER c_ss_mode CENTER_HIGH
SET_SIM_PARAMETER c_ss_mod_period 4000
SET_CORE_NAME Clocking Wizard
SET_CORE_VERSION 3.6
SET_CORE_VLNV xilinx.com:ip:clk_wiz:3.6
SET_CORE_CLASS com.xilinx.ip.clk_wiz_v3_6.clk_wiz_v3_6
SET_CORE_PATH /opt/Xilinx/14.7/ISE_DS/ISE/coregen/ip/xilinx/primary/com/xilinx/ip/clk_wiz_v3_6
SET_CORE_GUIPATH /opt/Xilinx/14.7/ISE_DS/ISE/coregen/ip/xilinx/primary/com/xilinx/ip/clk_wiz_v3_6/gui/clk_wiz_v3_6.tcl
SET_CORE_DATASHEET /opt/Xilinx/14.7/ISE_DS/ISE/coregen/ip/xilinx/primary/com/xilinx/ip/clk_wiz_v3_6/doc/pg065_clk_wiz.pdf
ADD_CORE_DOCUMENT </opt/Xilinx/14.7/ISE_DS/ISE/coregen/ip/xilinx/primary/com/xilinx/ip/clk_wiz_v3_6/doc/pg065_clk_wiz.pdf><pg065_clk_wiz.pdf>
ADD_CORE_DOCUMENT </opt/Xilinx/14.7/ISE_DS/ISE/coregen/ip/xilinx/primary/com/xilinx/ip/clk_wiz_v3_6/doc/clk_wiz_v3_6_readme.txt><clk_wiz_v3_6_readme.txt>
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