From 5d5fef95dffeb38a13a4c345676dcc50dd3dc1e6 Mon Sep 17 00:00:00 2001 From: Dreaded_X Date: Tue, 3 Mar 2020 00:08:05 +0100 Subject: [PATCH] Initial commit --- .gitignore | 1 + HDMI.alp | 25 + cores/clk_wiz_v3_6.asy | 13 + cores/clk_wiz_v3_6.gise | 31 + cores/clk_wiz_v3_6.ucf | 58 + cores/clk_wiz_v3_6.v | 145 ++ cores/clk_wiz_v3_6.veo | 75 + cores/clk_wiz_v3_6.xco | 269 ++++ cores/clk_wiz_v3_6.xdc | 66 + cores/clk_wiz_v3_6.xise | 403 +++++ cores/clk_wiz_v3_6/clk_wiz_v3_6_readme.txt | 184 +++ .../clk_wiz_v3_6/doc/clk_wiz_v3_6_readme.txt | 184 +++ .../clk_wiz_v3_6/doc/clk_wiz_v3_6_vinfo.html | 195 +++ cores/clk_wiz_v3_6/doc/pg065_clk_wiz.pdf | Bin 0 -> 42657 bytes .../example_design/clk_wiz_v3_6_exdes.ucf | 59 + .../example_design/clk_wiz_v3_6_exdes.v | 150 ++ .../example_design/clk_wiz_v3_6_exdes.xdc | 68 + cores/clk_wiz_v3_6/implement/implement.bat | 90 ++ cores/clk_wiz_v3_6/implement/implement.sh | 91 ++ .../clk_wiz_v3_6/implement/planAhead_ise.bat | 58 + cores/clk_wiz_v3_6/implement/planAhead_ise.sh | 59 + .../clk_wiz_v3_6/implement/planAhead_ise.tcl | 78 + .../clk_wiz_v3_6/implement/planAhead_rdn.bat | 58 + cores/clk_wiz_v3_6/implement/planAhead_rdn.sh | 57 + .../clk_wiz_v3_6/implement/planAhead_rdn.tcl | 69 + cores/clk_wiz_v3_6/implement/xst.prj | 2 + cores/clk_wiz_v3_6/implement/xst.scr | 9 + .../clk_wiz_v3_6/simulation/clk_wiz_v3_6_tb.v | 133 ++ .../simulation/functional/simcmds.tcl | 8 + .../simulation/functional/simulate_isim.bat | 59 + .../simulation/functional/simulate_isim.sh | 61 + .../simulation/functional/simulate_mti.bat | 61 + .../simulation/functional/simulate_mti.do | 65 + .../simulation/functional/simulate_mti.sh | 61 + .../simulation/functional/simulate_ncsim.sh | 62 + .../simulation/functional/simulate_vcs.sh | 72 + .../simulation/functional/ucli_commands.key | 5 + .../simulation/functional/vcs_session.tcl | 15 + .../simulation/functional/wave.do | 57 + .../simulation/functional/wave.sv | 111 ++ .../simulation/timing/clk_wiz_v3_6_tb.v | 136 ++ .../simulation/timing/sdf_cmd_file | 2 + .../simulation/timing/simcmds.tcl | 9 + .../simulation/timing/simulate_isim.sh | 62 + .../simulation/timing/simulate_mti.bat | 59 + .../simulation/timing/simulate_mti.do | 65 + .../simulation/timing/simulate_mti.sh | 61 + .../simulation/timing/simulate_ncsim.sh | 64 + .../simulation/timing/simulate_vcs.sh | 72 + .../simulation/timing/ucli_commands.key | 5 + .../simulation/timing/vcs_session.tcl | 1 + cores/clk_wiz_v3_6/simulation/timing/wave.do | 70 + cores/clk_wiz_v3_6_flist.txt | 53 + cores/clk_wiz_v3_6_xmdf.tcl | 140 ++ cores/coregen.cgc | 1339 +++++++++++++++++ cores/coregen.cgp | 22 + source/mojo_top.v | 256 ++++ source/mojo_top.v.bak | 178 +++ source/sram.v | 22 + 59 files changed, 5883 insertions(+) create mode 100644 .gitignore create mode 100644 HDMI.alp create mode 100644 cores/clk_wiz_v3_6.asy create mode 100644 cores/clk_wiz_v3_6.gise create mode 100644 cores/clk_wiz_v3_6.ucf create mode 100644 cores/clk_wiz_v3_6.v create mode 100644 cores/clk_wiz_v3_6.veo create mode 100644 cores/clk_wiz_v3_6.xco create mode 100644 cores/clk_wiz_v3_6.xdc create mode 100644 cores/clk_wiz_v3_6.xise create mode 100644 cores/clk_wiz_v3_6/clk_wiz_v3_6_readme.txt create mode 100644 cores/clk_wiz_v3_6/doc/clk_wiz_v3_6_readme.txt create mode 100644 cores/clk_wiz_v3_6/doc/clk_wiz_v3_6_vinfo.html create mode 100644 cores/clk_wiz_v3_6/doc/pg065_clk_wiz.pdf create mode 100644 cores/clk_wiz_v3_6/example_design/clk_wiz_v3_6_exdes.ucf create mode 100644 cores/clk_wiz_v3_6/example_design/clk_wiz_v3_6_exdes.v create mode 100644 cores/clk_wiz_v3_6/example_design/clk_wiz_v3_6_exdes.xdc create mode 100644 cores/clk_wiz_v3_6/implement/implement.bat create mode 100644 cores/clk_wiz_v3_6/implement/implement.sh create mode 100644 cores/clk_wiz_v3_6/implement/planAhead_ise.bat create mode 100644 cores/clk_wiz_v3_6/implement/planAhead_ise.sh create mode 100644 cores/clk_wiz_v3_6/implement/planAhead_ise.tcl create mode 100644 cores/clk_wiz_v3_6/implement/planAhead_rdn.bat create mode 100644 cores/clk_wiz_v3_6/implement/planAhead_rdn.sh create mode 100644 cores/clk_wiz_v3_6/implement/planAhead_rdn.tcl create mode 100644 cores/clk_wiz_v3_6/implement/xst.prj create mode 100644 cores/clk_wiz_v3_6/implement/xst.scr create mode 100644 cores/clk_wiz_v3_6/simulation/clk_wiz_v3_6_tb.v create mode 100644 cores/clk_wiz_v3_6/simulation/functional/simcmds.tcl create mode 100644 cores/clk_wiz_v3_6/simulation/functional/simulate_isim.bat create mode 100644 cores/clk_wiz_v3_6/simulation/functional/simulate_isim.sh create mode 100644 cores/clk_wiz_v3_6/simulation/functional/simulate_mti.bat create mode 100644 cores/clk_wiz_v3_6/simulation/functional/simulate_mti.do create mode 100644 cores/clk_wiz_v3_6/simulation/functional/simulate_mti.sh create mode 100644 cores/clk_wiz_v3_6/simulation/functional/simulate_ncsim.sh create mode 100644 cores/clk_wiz_v3_6/simulation/functional/simulate_vcs.sh create mode 100644 cores/clk_wiz_v3_6/simulation/functional/ucli_commands.key create mode 100644 cores/clk_wiz_v3_6/simulation/functional/vcs_session.tcl create mode 100644 cores/clk_wiz_v3_6/simulation/functional/wave.do create mode 100644 cores/clk_wiz_v3_6/simulation/functional/wave.sv create mode 100644 cores/clk_wiz_v3_6/simulation/timing/clk_wiz_v3_6_tb.v create mode 100644 cores/clk_wiz_v3_6/simulation/timing/sdf_cmd_file create mode 100644 cores/clk_wiz_v3_6/simulation/timing/simcmds.tcl create mode 100644 cores/clk_wiz_v3_6/simulation/timing/simulate_isim.sh create mode 100644 cores/clk_wiz_v3_6/simulation/timing/simulate_mti.bat create mode 100644 cores/clk_wiz_v3_6/simulation/timing/simulate_mti.do create mode 100644 cores/clk_wiz_v3_6/simulation/timing/simulate_mti.sh create mode 100644 cores/clk_wiz_v3_6/simulation/timing/simulate_ncsim.sh create mode 100644 cores/clk_wiz_v3_6/simulation/timing/simulate_vcs.sh create mode 100644 cores/clk_wiz_v3_6/simulation/timing/ucli_commands.key create mode 100644 cores/clk_wiz_v3_6/simulation/timing/vcs_session.tcl create mode 100644 cores/clk_wiz_v3_6/simulation/timing/wave.do create mode 100644 cores/clk_wiz_v3_6_flist.txt create mode 100644 cores/clk_wiz_v3_6_xmdf.tcl create mode 100644 cores/coregen.cgc create mode 100644 cores/coregen.cgp create mode 100644 source/mojo_top.v create mode 100644 source/mojo_top.v.bak create mode 100644 source/sram.v diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..9d931c4 --- /dev/null +++ b/.gitignore @@ -0,0 +1 @@ +work/ diff --git a/HDMI.alp b/HDMI.alp new file mode 100644 index 0000000..7a7e8f2 --- /dev/null +++ b/HDMI.alp @@ -0,0 +1,25 @@ + + + + cclk_detector.luc + simple_dual_ram.v + async_fifo.luc + uart_rx.luc + fifo_2x_reducer.luc + tmds_encoder.luc + spi_slave.luc + mojo_top.v + serdes_n_to_1.luc + uart_tx.luc + dvi_encoder.luc + hdmi_encoder.luc + sram.v + dvi_globals.luc + avr_interface.luc + hdmi.ucf + mojo.ucf + + ..\clk_wiz_v3_6.v + + + diff --git a/cores/clk_wiz_v3_6.asy b/cores/clk_wiz_v3_6.asy new file mode 100644 index 0000000..ab166bb --- /dev/null +++ b/cores/clk_wiz_v3_6.asy @@ -0,0 +1,13 @@ +Version 4 +SymbolType BLOCK +TEXT 32 32 LEFT 4 clk_wiz_v3_6 +RECTANGLE Normal 32 32 576 1088 +LINE Normal 0 80 32 80 +PIN 0 80 LEFT 36 +PINATTR PinName clk_in1 +PINATTR Polarity IN +LINE Normal 608 80 576 80 +PIN 608 80 RIGHT 36 +PINATTR PinName clk_out1 +PINATTR Polarity OUT + diff --git a/cores/clk_wiz_v3_6.gise b/cores/clk_wiz_v3_6.gise new file mode 100644 index 0000000..ecbfc28 --- /dev/null +++ b/cores/clk_wiz_v3_6.gise @@ -0,0 +1,31 @@ + + + + + + + + + + + + + + + + + + + + 11.1 + + + + + + + + + + + diff --git a/cores/clk_wiz_v3_6.ucf b/cores/clk_wiz_v3_6.ucf new file mode 100644 index 0000000..6b85232 --- /dev/null +++ b/cores/clk_wiz_v3_6.ucf @@ -0,0 +1,58 @@ +# file: clk_wiz_v3_6.ucf +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +# Input clock periods. These duplicate the values entered for the +# input clocks. You can use these to time your system +#---------------------------------------------------------------- +NET "CLK_IN1" TNM_NET = "CLK_IN1"; +TIMESPEC "TS_CLK_IN1" = PERIOD "CLK_IN1" 20.0 ns HIGH 50% INPUT_JITTER 200.0ps; + + +# FALSE PATH constraints + diff --git a/cores/clk_wiz_v3_6.v b/cores/clk_wiz_v3_6.v new file mode 100644 index 0000000..9f98085 --- /dev/null +++ b/cores/clk_wiz_v3_6.v @@ -0,0 +1,145 @@ +// file: clk_wiz_v3_6.v +// +// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//---------------------------------------------------------------------------- +// User entered comments +//---------------------------------------------------------------------------- +// None +// +//---------------------------------------------------------------------------- +// "Output Output Phase Duty Pk-to-Pk Phase" +// "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)" +//---------------------------------------------------------------------------- +// CLK_OUT1____75.000______0.000______50.0______466.667____150.000 +// +//---------------------------------------------------------------------------- +// "Input Clock Freq (MHz) Input Jitter (UI)" +//---------------------------------------------------------------------------- +// __primary__________50.000____________0.010 + +`timescale 1ps/1ps + +(* CORE_GENERATION_INFO = "clk_wiz_v3_6,clk_wiz_v3_6,{component_name=clk_wiz_v3_6,use_phase_alignment=false,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=1,clkin1_period=20.0,clkin2_period=20.0,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}" *) +module clk_wiz_v3_6 + (// Clock in ports + input CLK_IN1, + // Clock out ports + output CLK_OUT1 + ); + + // Input buffering + //------------------------------------ + IBUFG clkin1_buf + (.O (clkin1), + .I (CLK_IN1)); + + + // Clocking primitive + //------------------------------------ + + // Instantiation of the DCM primitive + // * Unused inputs are tied off + // * Unused outputs are labeled unused + wire psdone_unused; + wire locked_int; + wire [7:0] status_int; + wire clkfb; + wire clk0; + wire clkfx; + + DCM_SP + #(.CLKDV_DIVIDE (2.000), + .CLKFX_DIVIDE (2), + .CLKFX_MULTIPLY (3), + .CLKIN_DIVIDE_BY_2 ("FALSE"), + .CLKIN_PERIOD (20.0), + .CLKOUT_PHASE_SHIFT ("NONE"), + .CLK_FEEDBACK ("NONE"), + .DESKEW_ADJUST ("SYSTEM_SYNCHRONOUS"), + .PHASE_SHIFT (0), + .STARTUP_WAIT ("FALSE")) + dcm_sp_inst + // Input clock + (.CLKIN (clkin1), + .CLKFB (clkfb), + // Output clocks + .CLK0 (clk0), + .CLK90 (), + .CLK180 (), + .CLK270 (), + .CLK2X (), + .CLK2X180 (), + .CLKFX (clkfx), + .CLKFX180 (), + .CLKDV (), + // Ports for dynamic phase shift + .PSCLK (1'b0), + .PSEN (1'b0), + .PSINCDEC (1'b0), + .PSDONE (), + // Other control and status signals + .LOCKED (locked_int), + .STATUS (status_int), + .RST (1'b0), + // Unused pin- tie low + .DSSEN (1'b0)); + + + // Output buffering + //----------------------------------- + // no phase alignment active, connect to ground + assign clkfb = 1'b0; + + BUFG clkout1_buf + (.O (CLK_OUT1), + .I (clkfx)); + + + + +endmodule diff --git a/cores/clk_wiz_v3_6.veo b/cores/clk_wiz_v3_6.veo new file mode 100644 index 0000000..f219243 --- /dev/null +++ b/cores/clk_wiz_v3_6.veo @@ -0,0 +1,75 @@ +// +// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//---------------------------------------------------------------------------- +// User entered comments +//---------------------------------------------------------------------------- +// None +// +//---------------------------------------------------------------------------- +// "Output Output Phase Duty Pk-to-Pk Phase" +// "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)" +//---------------------------------------------------------------------------- +// CLK_OUT1____75.000______0.000______50.0______466.667____150.000 +// +//---------------------------------------------------------------------------- +// "Input Clock Freq (MHz) Input Jitter (UI)" +//---------------------------------------------------------------------------- +// __primary__________50.000____________0.010 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG + + clk_wiz_v3_6 instance_name + (// Clock in ports + .CLK_IN1(CLK_IN1), // IN + // Clock out ports + .CLK_OUT1(CLK_OUT1)); // OUT +// INST_TAG_END ------ End INSTANTIATION Template --------- diff --git a/cores/clk_wiz_v3_6.xco b/cores/clk_wiz_v3_6.xco new file mode 100644 index 0000000..de4f4ea --- /dev/null +++ b/cores/clk_wiz_v3_6.xco @@ -0,0 +1,269 @@ +############################################################## +# +# Xilinx Core Generator version 14.7 +# Date: Fri Feb 28 22:02:23 2020 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# Generated from component: xilinx.com:ip:clk_wiz:3.6 +# +############################################################## +# +# BEGIN Project Options +SET addpads = false +SET asysymbol = true +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = false +SET designentry = Verilog +SET device = xc6slx9 +SET devicefamily = spartan6 +SET flowvendor = Other +SET formalverification = false +SET foundationsym = false +SET implementationfiletype = Ngc +SET package = tqg144 +SET removerpms = false +SET simulationfiles = Behavioral +SET speedgrade = -2 +SET verilogsim = true +SET vhdlsim = false +# END Project Options +# BEGIN Select +SELECT Clocking_Wizard xilinx.com:ip:clk_wiz:3.6 +# END Select +# BEGIN Parameters +CSET calc_done=DONE +CSET clk_in_sel_port=CLK_IN_SEL +CSET clk_out1_port=CLK_OUT1 +CSET clk_out1_use_fine_ps_gui=false +CSET clk_out2_port=CLK_OUT2 +CSET clk_out2_use_fine_ps_gui=false +CSET clk_out3_port=CLK_OUT3 +CSET clk_out3_use_fine_ps_gui=false +CSET clk_out4_port=CLK_OUT4 +CSET clk_out4_use_fine_ps_gui=false +CSET clk_out5_port=CLK_OUT5 +CSET clk_out5_use_fine_ps_gui=false +CSET clk_out6_port=CLK_OUT6 +CSET clk_out6_use_fine_ps_gui=false +CSET clk_out7_port=CLK_OUT7 +CSET clk_out7_use_fine_ps_gui=false +CSET clk_valid_port=CLK_VALID +CSET clkfb_in_n_port=CLKFB_IN_N +CSET clkfb_in_p_port=CLKFB_IN_P +CSET clkfb_in_port=CLKFB_IN +CSET clkfb_in_signaling=SINGLE +CSET clkfb_out_n_port=CLKFB_OUT_N +CSET clkfb_out_p_port=CLKFB_OUT_P +CSET clkfb_out_port=CLKFB_OUT +CSET clkfb_stopped_port=CLKFB_STOPPED +CSET clkin1_jitter_ps=200.0 +CSET clkin1_ui_jitter=0.010 +CSET clkin2_jitter_ps=100.0 +CSET clkin2_ui_jitter=0.010 +CSET clkout1_drives=BUFG +CSET clkout1_requested_duty_cycle=50.000 +CSET clkout1_requested_out_freq=75.000 +CSET clkout1_requested_phase=0.000 +CSET clkout2_drives=BUFG +CSET clkout2_requested_duty_cycle=50.000 +CSET clkout2_requested_out_freq=100.000 +CSET clkout2_requested_phase=0.000 +CSET clkout2_used=false +CSET clkout3_drives=BUFG +CSET clkout3_requested_duty_cycle=50.000 +CSET clkout3_requested_out_freq=100.000 +CSET clkout3_requested_phase=0.000 +CSET clkout3_used=false +CSET clkout4_drives=BUFG +CSET clkout4_requested_duty_cycle=50.000 +CSET clkout4_requested_out_freq=100.000 +CSET clkout4_requested_phase=0.000 +CSET clkout4_used=false +CSET clkout5_drives=BUFG +CSET clkout5_requested_duty_cycle=50.000 +CSET clkout5_requested_out_freq=100.000 +CSET clkout5_requested_phase=0.000 +CSET clkout5_used=false +CSET clkout6_drives=BUFG +CSET clkout6_requested_duty_cycle=50.000 +CSET clkout6_requested_out_freq=100.000 +CSET clkout6_requested_phase=0.000 +CSET clkout6_used=false +CSET clkout7_drives=BUFG +CSET clkout7_requested_duty_cycle=50.000 +CSET clkout7_requested_out_freq=100.000 +CSET clkout7_requested_phase=0.000 +CSET clkout7_used=false +CSET clock_mgr_type=AUTO +CSET component_name=clk_wiz_v3_6 +CSET daddr_port=DADDR +CSET dclk_port=DCLK +CSET dcm_clk_feedback=NONE +CSET dcm_clk_out1_port=CLKFX +CSET dcm_clk_out2_port=CLK0 +CSET dcm_clk_out3_port=CLK0 +CSET dcm_clk_out4_port=CLK0 +CSET dcm_clk_out5_port=CLK0 +CSET dcm_clk_out6_port=CLK0 +CSET dcm_clkdv_divide=2.0 +CSET dcm_clkfx_divide=2 +CSET dcm_clkfx_multiply=3 +CSET dcm_clkgen_clk_out1_port=CLKFX +CSET dcm_clkgen_clk_out2_port=CLKFX +CSET dcm_clkgen_clk_out3_port=CLKFX +CSET dcm_clkgen_clkfx_divide=1 +CSET dcm_clkgen_clkfx_md_max=0.000 +CSET dcm_clkgen_clkfx_multiply=4 +CSET dcm_clkgen_clkfxdv_divide=2 +CSET dcm_clkgen_clkin_period=10.000 +CSET dcm_clkgen_notes=None +CSET dcm_clkgen_spread_spectrum=NONE +CSET dcm_clkgen_startup_wait=false +CSET dcm_clkin_divide_by_2=false +CSET dcm_clkin_period=20.000 +CSET dcm_clkout_phase_shift=NONE +CSET dcm_deskew_adjust=SYSTEM_SYNCHRONOUS +CSET dcm_notes=None +CSET dcm_phase_shift=0 +CSET dcm_pll_cascade=NONE +CSET dcm_startup_wait=false +CSET den_port=DEN +CSET din_port=DIN +CSET dout_port=DOUT +CSET drdy_port=DRDY +CSET dwe_port=DWE +CSET feedback_source=FDBK_AUTO +CSET in_freq_units=Units_MHz +CSET in_jitter_units=Units_UI +CSET input_clk_stopped_port=INPUT_CLK_STOPPED +CSET jitter_options=UI +CSET jitter_sel=No_Jitter +CSET locked_port=LOCKED +CSET mmcm_bandwidth=OPTIMIZED +CSET mmcm_clkfbout_mult_f=4.000 +CSET mmcm_clkfbout_phase=0.000 +CSET mmcm_clkfbout_use_fine_ps=false +CSET mmcm_clkin1_period=10.000 +CSET mmcm_clkin2_period=10.000 +CSET mmcm_clkout0_divide_f=4.000 +CSET mmcm_clkout0_duty_cycle=0.500 +CSET mmcm_clkout0_phase=0.000 +CSET mmcm_clkout0_use_fine_ps=false +CSET mmcm_clkout1_divide=1 +CSET mmcm_clkout1_duty_cycle=0.500 +CSET mmcm_clkout1_phase=0.000 +CSET mmcm_clkout1_use_fine_ps=false +CSET mmcm_clkout2_divide=1 +CSET mmcm_clkout2_duty_cycle=0.500 +CSET mmcm_clkout2_phase=0.000 +CSET mmcm_clkout2_use_fine_ps=false +CSET mmcm_clkout3_divide=1 +CSET mmcm_clkout3_duty_cycle=0.500 +CSET mmcm_clkout3_phase=0.000 +CSET mmcm_clkout3_use_fine_ps=false +CSET mmcm_clkout4_cascade=false +CSET mmcm_clkout4_divide=1 +CSET mmcm_clkout4_duty_cycle=0.500 +CSET mmcm_clkout4_phase=0.000 +CSET mmcm_clkout4_use_fine_ps=false +CSET mmcm_clkout5_divide=1 +CSET mmcm_clkout5_duty_cycle=0.500 +CSET mmcm_clkout5_phase=0.000 +CSET mmcm_clkout5_use_fine_ps=false +CSET mmcm_clkout6_divide=1 +CSET mmcm_clkout6_duty_cycle=0.500 +CSET mmcm_clkout6_phase=0.000 +CSET mmcm_clkout6_use_fine_ps=false +CSET mmcm_clock_hold=false +CSET mmcm_compensation=ZHOLD +CSET mmcm_divclk_divide=1 +CSET mmcm_notes=None +CSET mmcm_ref_jitter1=0.010 +CSET mmcm_ref_jitter2=0.010 +CSET mmcm_startup_wait=false +CSET num_out_clks=1 +CSET override_dcm=false +CSET override_dcm_clkgen=false +CSET override_mmcm=false +CSET override_pll=false +CSET platform=nt +CSET pll_bandwidth=OPTIMIZED +CSET pll_clk_feedback=CLKFBOUT +CSET pll_clkfbout_mult=8 +CSET pll_clkfbout_phase=0.000 +CSET pll_clkin_period=20.0 +CSET pll_clkout0_divide=128 +CSET pll_clkout0_duty_cycle=0.500 +CSET pll_clkout0_phase=0.000 +CSET pll_clkout1_divide=1 +CSET pll_clkout1_duty_cycle=0.500 +CSET pll_clkout1_phase=0.000 +CSET pll_clkout2_divide=1 +CSET pll_clkout2_duty_cycle=0.500 +CSET pll_clkout2_phase=0.000 +CSET pll_clkout3_divide=1 +CSET pll_clkout3_duty_cycle=0.500 +CSET pll_clkout3_phase=0.000 +CSET pll_clkout4_divide=1 +CSET pll_clkout4_duty_cycle=0.500 +CSET pll_clkout4_phase=0.000 +CSET pll_clkout5_divide=1 +CSET pll_clkout5_duty_cycle=0.500 +CSET pll_clkout5_phase=0.000 +CSET pll_compensation=INTERNAL +CSET pll_divclk_divide=1 +CSET pll_notes=None +CSET pll_ref_jitter=0.010 +CSET power_down_port=POWER_DOWN +CSET prim_in_freq=50.000 +CSET prim_in_jitter=0.010 +CSET prim_source=Single_ended_clock_capable_pin +CSET primary_port=CLK_IN1 +CSET primitive=MMCM +CSET primtype_sel=PLL_BASE +CSET psclk_port=PSCLK +CSET psdone_port=PSDONE +CSET psen_port=PSEN +CSET psincdec_port=PSINCDEC +CSET relative_inclk=REL_PRIMARY +CSET reset_port=RESET +CSET secondary_in_freq=100.000 +CSET secondary_in_jitter=0.010 +CSET secondary_port=CLK_IN2 +CSET secondary_source=Single_ended_clock_capable_pin +CSET ss_mod_freq=250 +CSET ss_mode=CENTER_HIGH +CSET status_port=STATUS +CSET summary_strings=empty +CSET use_clk_valid=false +CSET use_clkfb_stopped=false +CSET use_dyn_phase_shift=false +CSET use_dyn_reconfig=false +CSET use_freeze=false +CSET use_freq_synth=true +CSET use_inclk_stopped=false +CSET use_inclk_switchover=false +CSET use_locked=false +CSET use_max_i_jitter=false +CSET use_min_o_jitter=false +CSET use_min_power=false +CSET use_phase_alignment=false +CSET use_power_down=false +CSET use_reset=false +CSET use_spread_spectrum=false +CSET use_spread_spectrum_1=false +CSET use_status=false +# END Parameters +# BEGIN Extra information +MISC pkg_timestamp=2012-05-10T12:44:55Z +# END Extra information +GENERATE +# CRC: 78c63287 diff --git a/cores/clk_wiz_v3_6.xdc b/cores/clk_wiz_v3_6.xdc new file mode 100644 index 0000000..edcee4f --- /dev/null +++ b/cores/clk_wiz_v3_6.xdc @@ -0,0 +1,66 @@ +# file: clk_wiz_v3_6.xdc +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +# Input clock periods. These duplicate the values entered for the +# input clocks. You can use these to time your system +#---------------------------------------------------------------- +create_clock -name CLK_IN1 -period 20.0 [get_ports CLK_IN1] +set_propagated_clock CLK_IN1 +set_input_jitter CLK_IN1 0.2 + + +# Derived clock periods. These are commented out because they are +# automatically propogated by the tools +# However, if you'd like to use them for module level testing, you +# can copy them into your module level timing checks +#----------------------------------------------------------------- + +#----------------------------------------------------------------- + +#----------------------------------------------------------------- diff --git a/cores/clk_wiz_v3_6.xise b/cores/clk_wiz_v3_6.xise new file mode 100644 index 0000000..1e12b69 --- /dev/null +++ b/cores/clk_wiz_v3_6.xise @@ -0,0 +1,403 @@ + + + +
+ + + + + + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/cores/clk_wiz_v3_6/clk_wiz_v3_6_readme.txt b/cores/clk_wiz_v3_6/clk_wiz_v3_6_readme.txt new file mode 100644 index 0000000..91dcdd0 --- /dev/null +++ b/cores/clk_wiz_v3_6/clk_wiz_v3_6_readme.txt @@ -0,0 +1,184 @@ +CHANGE LOG for LogiCORE Clocking Wizard V3.6 + + Release Date: June 19, 2013 +-------------------------------------------------------------------------------- + +Table of Contents + +1. INTRODUCTION +2. DEVICE SUPPORT +3. NEW FEATURE HISTORY +4. RESOLVED ISSUES +5. KNOWN ISSUES & LIMITATIONS +6. TECHNICAL SUPPORT & FEEDBACK +7. CORE RELEASE HISTORY +8. LEGAL DISCLAIMER + +-------------------------------------------------------------------------------- + + +1. INTRODUCTION + +For installation instructions for this release, please go to: + + http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm + +For system requirements: + + http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm + +This file contains release notes for the Xilinx LogiCORE IP Clocking Wizard v3.6 +solution. For the latest core updates, see the product page at: + + http://www.xilinx.com/products/design_resources/conn_central/solution_kits/wizards/ + +................................................................................ + +2. DEVICE SUPPORT + + + 2.1 ISE + + + The following device families are supported by the core for this release. + + All 7 Series devices + + + Zynq-7000 devices + Zynq-7000 + Defense Grade Zynq-7000Q (XQ) + + + All Virtex-6 devices + + + All Spartan-6 devices + + +................................................................................ + +3. NEW FEATURE HISTORY + + + 3.1 ISE + + - Spread Spectrum support for 7 series MMCME2 + + - ISE 14.2 software support + +................................................................................ + +4. RESOLVED ISSUES + + + 4.1 ISE + + Resolved issue with example design becoming core top in planAhead + + Resolved issue with Virtex6 MMCM instantiation for VHDL project + Please refer to AR 50719 - http://www.xilinx.com/support/answers/50719.htm + +................................................................................ + +5. KNOWN ISSUES & LIMITATIONS + + + 5.1 ISE + + + The most recent information, including known issues, workarounds, and + resolutions for this version is provided in the IP Release Notes Guide + located at + + www.xilinx.com/support/documentation/user_guides/xtp025.pdf + + +................................................................................ + +6. TECHNICAL SUPPORT & FEEDBACK + + +To obtain technical support, create a WebCase at www.xilinx.com/support. +Questions are routed to a team with expertise using this product. + +Xilinx provides technical support for use of this product when used +according to the guidelines described in the core documentation, and +cannot guarantee timing, functionality, or support of this product for +designs that do not follow specified guidelines. + + +................................................................................ + +7. CORE RELEASE HISTORY + + +Date By Version Description +================================================================================ +06/19/2013 Xilinx, Inc. 3.6(Rev3) ISE 14.6 support +10/16/2012 Xilinx, Inc. 3.6(Rev2) ISE 14.3 support +07/25/2012 Xilinx, Inc. 3.6 ISE 14.2 support +04/24/2012 Xilinx, Inc. 3.5 ISE 14.1 support +01/18/2012 Xilinx, Inc. 3.3 ISE 13.4 support +06/22/2011 Xilinx, Inc. 3.2 ISE 13.2 support +03/01/2011 Xilinx, Inc. 3.1 ISE 13.1 support +12/14/2010 Xilinx, Inc. 1.8 ISE 12.4 support +09/21/2010 Xilinx, Inc. 1.7 ISE 12.3 support +07/23/2010 Xilinx, Inc. 1.6 ISE 12.2 support +04/19/2010 Xilinx, Inc. 1.5 ISE 12.1 support +12/02/2009 Xilinx, Inc. 1.4 ISE 11.4 support +09/16/2009 Xilinx, Inc. 1.3 ISE 11.3 support +06/24/2009 Xilinx, Inc. 1.2 ISE 11.2 support +04/24/2009 Xilinx, Inc. 1.1 Initial release; 11.1 support +================================================================================ + +................................................................................ + +8. LEGAL DISCLAIMER + +(c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. + +This file contains confidential and proprietary information +of Xilinx, Inc. and is protected under U.S. and +international copyright and other intellectual property +laws. + +DISCLAIMER +This disclaimer is not a license and does not grant any +rights to the materials distributed herewith. Except as +otherwise provided in a valid license issued to you by +Xilinx, and to the maximum extent permitted by applicable +law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +(2) Xilinx shall not be liable (whether in contract or tort, +including negligence, or under any other theory of +liability) for any loss or damage of any kind or nature +related to, arising under or in connection with these +materials, including for any direct, or any indirect, +special, incidental, or consequential loss or damage +(including loss of data, profits, goodwill, or any type of +loss or damage suffered as a result of any action brought +by a third party) even if such damage or loss was +reasonably foreseeable or Xilinx had been advised of the +possibility of the same. + +CRITICAL APPLICATIONS +Xilinx products are not designed or intended to be fail- +safe, or for use in any application requiring fail-safe +performance, such as life-support or safety devices or +systems, Class III medical devices, nuclear facilities, +applications related to the deployment of airbags, or any +other applications that could lead to death, personal +injury, or severe property or environmental damage +(individually and collectively, "Critical +Applications"). Customer assumes the sole risk and +liability of any use of Xilinx products in Critical +Applications, subject only to applicable laws and +regulations governing limitations on product liability. + +THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +PART OF THIS FILE AT ALL TIMES. + diff --git a/cores/clk_wiz_v3_6/doc/clk_wiz_v3_6_readme.txt b/cores/clk_wiz_v3_6/doc/clk_wiz_v3_6_readme.txt new file mode 100644 index 0000000..91dcdd0 --- /dev/null +++ b/cores/clk_wiz_v3_6/doc/clk_wiz_v3_6_readme.txt @@ -0,0 +1,184 @@ +CHANGE LOG for LogiCORE Clocking Wizard V3.6 + + Release Date: June 19, 2013 +-------------------------------------------------------------------------------- + +Table of Contents + +1. INTRODUCTION +2. DEVICE SUPPORT +3. NEW FEATURE HISTORY +4. RESOLVED ISSUES +5. KNOWN ISSUES & LIMITATIONS +6. TECHNICAL SUPPORT & FEEDBACK +7. CORE RELEASE HISTORY +8. LEGAL DISCLAIMER + +-------------------------------------------------------------------------------- + + +1. INTRODUCTION + +For installation instructions for this release, please go to: + + http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm + +For system requirements: + + http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm + +This file contains release notes for the Xilinx LogiCORE IP Clocking Wizard v3.6 +solution. For the latest core updates, see the product page at: + + http://www.xilinx.com/products/design_resources/conn_central/solution_kits/wizards/ + +................................................................................ + +2. DEVICE SUPPORT + + + 2.1 ISE + + + The following device families are supported by the core for this release. + + All 7 Series devices + + + Zynq-7000 devices + Zynq-7000 + Defense Grade Zynq-7000Q (XQ) + + + All Virtex-6 devices + + + All Spartan-6 devices + + +................................................................................ + +3. NEW FEATURE HISTORY + + + 3.1 ISE + + - Spread Spectrum support for 7 series MMCME2 + + - ISE 14.2 software support + +................................................................................ + +4. RESOLVED ISSUES + + + 4.1 ISE + + Resolved issue with example design becoming core top in planAhead + + Resolved issue with Virtex6 MMCM instantiation for VHDL project + Please refer to AR 50719 - http://www.xilinx.com/support/answers/50719.htm + +................................................................................ + +5. KNOWN ISSUES & LIMITATIONS + + + 5.1 ISE + + + The most recent information, including known issues, workarounds, and + resolutions for this version is provided in the IP Release Notes Guide + located at + + www.xilinx.com/support/documentation/user_guides/xtp025.pdf + + +................................................................................ + +6. TECHNICAL SUPPORT & FEEDBACK + + +To obtain technical support, create a WebCase at www.xilinx.com/support. +Questions are routed to a team with expertise using this product. + +Xilinx provides technical support for use of this product when used +according to the guidelines described in the core documentation, and +cannot guarantee timing, functionality, or support of this product for +designs that do not follow specified guidelines. + + +................................................................................ + +7. CORE RELEASE HISTORY + + +Date By Version Description +================================================================================ +06/19/2013 Xilinx, Inc. 3.6(Rev3) ISE 14.6 support +10/16/2012 Xilinx, Inc. 3.6(Rev2) ISE 14.3 support +07/25/2012 Xilinx, Inc. 3.6 ISE 14.2 support +04/24/2012 Xilinx, Inc. 3.5 ISE 14.1 support +01/18/2012 Xilinx, Inc. 3.3 ISE 13.4 support +06/22/2011 Xilinx, Inc. 3.2 ISE 13.2 support +03/01/2011 Xilinx, Inc. 3.1 ISE 13.1 support +12/14/2010 Xilinx, Inc. 1.8 ISE 12.4 support +09/21/2010 Xilinx, Inc. 1.7 ISE 12.3 support +07/23/2010 Xilinx, Inc. 1.6 ISE 12.2 support +04/19/2010 Xilinx, Inc. 1.5 ISE 12.1 support +12/02/2009 Xilinx, Inc. 1.4 ISE 11.4 support +09/16/2009 Xilinx, Inc. 1.3 ISE 11.3 support +06/24/2009 Xilinx, Inc. 1.2 ISE 11.2 support +04/24/2009 Xilinx, Inc. 1.1 Initial release; 11.1 support +================================================================================ + +................................................................................ + +8. LEGAL DISCLAIMER + +(c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. + +This file contains confidential and proprietary information +of Xilinx, Inc. and is protected under U.S. and +international copyright and other intellectual property +laws. + +DISCLAIMER +This disclaimer is not a license and does not grant any +rights to the materials distributed herewith. Except as +otherwise provided in a valid license issued to you by +Xilinx, and to the maximum extent permitted by applicable +law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +(2) Xilinx shall not be liable (whether in contract or tort, +including negligence, or under any other theory of +liability) for any loss or damage of any kind or nature +related to, arising under or in connection with these +materials, including for any direct, or any indirect, +special, incidental, or consequential loss or damage +(including loss of data, profits, goodwill, or any type of +loss or damage suffered as a result of any action brought +by a third party) even if such damage or loss was +reasonably foreseeable or Xilinx had been advised of the +possibility of the same. + +CRITICAL APPLICATIONS +Xilinx products are not designed or intended to be fail- +safe, or for use in any application requiring fail-safe +performance, such as life-support or safety devices or +systems, Class III medical devices, nuclear facilities, +applications related to the deployment of airbags, or any +other applications that could lead to death, personal +injury, or severe property or environmental damage +(individually and collectively, "Critical +Applications"). Customer assumes the sole risk and +liability of any use of Xilinx products in Critical +Applications, subject only to applicable laws and +regulations governing limitations on product liability. + +THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +PART OF THIS FILE AT ALL TIMES. + diff --git a/cores/clk_wiz_v3_6/doc/clk_wiz_v3_6_vinfo.html b/cores/clk_wiz_v3_6/doc/clk_wiz_v3_6_vinfo.html new file mode 100644 index 0000000..d6deba0 --- /dev/null +++ b/cores/clk_wiz_v3_6/doc/clk_wiz_v3_6_vinfo.html @@ -0,0 +1,195 @@ + + +clk_wiz_v3_6_vinfo + + + +

+CHANGE LOG for LogiCORE Clocking Wizard V3.6 
+
+                    Release Date: June 19, 2013
+--------------------------------------------------------------------------------
+
+Table of Contents
+
+1. INTRODUCTION 
+2. DEVICE SUPPORT    
+3. NEW FEATURE HISTORY   
+4. RESOLVED ISSUES 
+5. KNOWN ISSUES & LIMITATIONS 
+6. TECHNICAL SUPPORT & FEEDBACK
+7. CORE RELEASE HISTORY 
+8. LEGAL DISCLAIMER 
+
+--------------------------------------------------------------------------------
+
+
+1. INTRODUCTION
+
+For installation instructions for this release, please go to:
+
+  www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm
+
+For system requirements:
+
+   www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm
+
+This file contains release notes for the Xilinx LogiCORE IP Clocking Wizard v3.6
+solution. For the latest core updates, see the product page at:
+
+   www.xilinx.com/products/design_resources/conn_central/solution_kits/wizards/
+
+................................................................................
+
+2. DEVICE SUPPORT
+
+
+  2.1 ISE 
+   
+  
+  The following device families are supported by the core for this release.
+  
+  All 7 Series devices
+
+
+  Zynq-7000 devices
+    Zynq-7000
+    Defense Grade Zynq-7000Q (XQ)
+
+
+  All Virtex-6 devices
+  
+  
+  All Spartan-6 devices
+  
+  
+................................................................................
+
+3. NEW FEATURE HISTORY 
+
+
+  3.1 ISE 
+  
+    - Spread Spectrum support for 7 series MMCME2
+
+    - ISE 14.2 software support
+
+................................................................................
+
+4. RESOLVED ISSUES
+
+
+  4.1 ISE 
+  
+      Resolved issue with example design becoming core top in planAhead
+
+      Resolved issue with Virtex6 MMCM instantiation for VHDL project
+      Please refer to AR 50719 - www.xilinx.com/support/answers/50719.htm
+
+................................................................................
+
+5. KNOWN ISSUES & LIMITATIONS
+
+
+  5.1 ISE 
+  
+  
+  The most recent information, including known issues, workarounds, and
+  resolutions for this version is provided in the IP Release Notes Guide
+  located at
+
+   www.xilinx.com/support/documentation/user_guides/xtp025.pdf
+  
+  
+................................................................................
+
+6. TECHNICAL SUPPORT & FEEDBACK
+
+
+To obtain technical support, create a WebCase at www.xilinx.com/support.
+Questions are routed to a team with expertise using this product.
+
+Xilinx provides technical support for use of this product when used
+according to the guidelines described in the core documentation, and
+cannot guarantee timing, functionality, or support of this product for
+designs that do not follow specified guidelines.
+
+
+................................................................................
+
+7. CORE RELEASE HISTORY
+
+
+Date        By            Version      Description
+================================================================================
+06/19/2013  Xilinx, Inc.  3.6(Rev3)    ISE 14.6 support
+10/16/2012  Xilinx, Inc.  3.6(Rev2)    ISE 14.3 support
+07/25/2012  Xilinx, Inc.  3.6          ISE 14.2 support
+04/24/2012  Xilinx, Inc.  3.5          ISE 14.1 support
+01/18/2012  Xilinx, Inc.  3.3          ISE 13.4 support
+06/22/2011  Xilinx, Inc.  3.2          ISE 13.2 support
+03/01/2011  Xilinx, Inc.  3.1          ISE 13.1 support
+12/14/2010  Xilinx, Inc.  1.8          ISE 12.4 support
+09/21/2010  Xilinx, Inc.  1.7          ISE 12.3 support
+07/23/2010  Xilinx, Inc.  1.6          ISE 12.2 support
+04/19/2010  Xilinx, Inc.  1.5          ISE 12.1 support
+12/02/2009  Xilinx, Inc.  1.4          ISE 11.4 support
+09/16/2009  Xilinx, Inc.  1.3          ISE 11.3 support
+06/24/2009  Xilinx, Inc.  1.2          ISE 11.2 support
+04/24/2009  Xilinx, Inc.  1.1          Initial release; 11.1 support
+================================================================================
+                          
+................................................................................
+
+8. LEGAL DISCLAIMER
+
+(c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
+
+This file contains confidential and proprietary information
+of Xilinx, Inc. and is protected under U.S. and
+international copyright and other intellectual property
+laws.
+
+DISCLAIMER
+This disclaimer is not a license and does not grant any
+rights to the materials distributed herewith. Except as
+otherwise provided in a valid license issued to you by
+Xilinx, and to the maximum extent permitted by applicable
+law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+(2) Xilinx shall not be liable (whether in contract or tort,
+including negligence, or under any other theory of
+liability) for any loss or damage of any kind or nature
+related to, arising under or in connection with these
+materials, including for any direct, or any indirect,
+special, incidental, or consequential loss or damage
+(including loss of data, profits, goodwill, or any type of
+loss or damage suffered as a result of any action brought
+by a third party) even if such damage or loss was
+reasonably foreseeable or Xilinx had been advised of the
+possibility of the same.
+
+CRITICAL APPLICATIONS
+Xilinx products are not designed or intended to be fail-
+safe, or for use in any application requiring fail-safe
+performance, such as life-support or safety devices or
+systems, Class III medical devices, nuclear facilities,
+applications related to the deployment of airbags, or any
+other applications that could lead to death, personal
+injury, or severe property or environmental damage
+(individually and collectively, "Critical
+Applications"). Customer assumes the sole risk and
+liability of any use of Xilinx products in Critical
+Applications, subject only to applicable laws and
+regulations governing limitations on product liability.
+
+THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+PART OF THIS FILE AT ALL TIMES.
+
+
+
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zF^O@R`_nyrmdPC9R=zA@G2P`>@=FZNh&IU%NM&Plul+=o7;K&$gK+O=iRt`j%f(Ua3W9&n1Mxe32G6mp(7v`87 zaOf5^6RnSD%xzB2kpo9&{GQ&}+1M!PVqjqOH-5`=dtv6uh7(S&IL{!Ez>sUo#*8K8 PkOtdKjEoH};KOYIFuVn2 literal 0 HcmV?d00001 diff --git a/cores/clk_wiz_v3_6/example_design/clk_wiz_v3_6_exdes.ucf b/cores/clk_wiz_v3_6/example_design/clk_wiz_v3_6_exdes.ucf new file mode 100644 index 0000000..2d58d30 --- /dev/null +++ b/cores/clk_wiz_v3_6/example_design/clk_wiz_v3_6_exdes.ucf @@ -0,0 +1,59 @@ +# file: clk_wiz_v3_6_exdes.ucf +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +# Input clock periods. These duplicate the values entered for the +# input clocks. You can use these to time your system +#---------------------------------------------------------------- +NET "CLK_IN1" TNM_NET = "CLK_IN1"; +TIMESPEC "TS_CLK_IN1" = PERIOD "CLK_IN1" 20.0 ns HIGH 50% INPUT_JITTER 200.0ps; + + +# FALSE PATH constraints +PIN "COUNTER_RESET" TIG; + diff --git a/cores/clk_wiz_v3_6/example_design/clk_wiz_v3_6_exdes.v b/cores/clk_wiz_v3_6/example_design/clk_wiz_v3_6_exdes.v new file mode 100644 index 0000000..8bb2356 --- /dev/null +++ b/cores/clk_wiz_v3_6/example_design/clk_wiz_v3_6_exdes.v @@ -0,0 +1,150 @@ +// file: clk_wiz_v3_6_exdes.v +// +// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// + +//---------------------------------------------------------------------------- +// Clocking wizard example design +//---------------------------------------------------------------------------- +// This example design instantiates the created clocking network, where each +// output clock drives a counter. The high bit of each counter is ported. +//---------------------------------------------------------------------------- + +`timescale 1ps/1ps + +module clk_wiz_v3_6_exdes + #( + parameter TCQ = 100 + ) + (// Clock in ports + input CLK_IN1, + // Reset that only drives logic in example design + input COUNTER_RESET, + output [1:1] CLK_OUT, + // High bits of counters driven by clocks + output COUNT + ); + + // Parameters for the counters + //------------------------------- + // Counter width + localparam C_W = 16; + // Create reset for the counters + wire reset_int = COUNTER_RESET; + + reg rst_sync; + reg rst_sync_int; + reg rst_sync_int1; + reg rst_sync_int2; + + + + // Declare the clocks and counter + wire clk_int; + wire clk_n; + wire clk; + reg [C_W-1:0] counter; + + // Instantiation of the clocking network + //-------------------------------------- + clk_wiz_v3_6 clknetwork + (// Clock in ports + .CLK_IN1 (CLK_IN1), + // Clock out ports + .CLK_OUT1 (clk_int)); + + assign clk_n = ~clk; + + ODDR2 clkout_oddr + (.Q (CLK_OUT[1]), + .C0 (clk), + .C1 (clk_n), + .CE (1'b1), + .D0 (1'b1), + .D1 (1'b0), + .R (1'b0), + .S (1'b0)); + + // Connect the output clocks to the design + //----------------------------------------- + assign clk = clk_int; + + + // Reset synchronizer + //----------------------------------- + always @(posedge reset_int or posedge clk) begin + if (reset_int) begin + rst_sync <= 1'b1; + rst_sync_int <= 1'b1; + rst_sync_int1 <= 1'b1; + rst_sync_int2 <= 1'b1; + end + else begin + rst_sync <= 1'b0; + rst_sync_int <= rst_sync; + rst_sync_int1 <= rst_sync_int; + rst_sync_int2 <= rst_sync_int1; + end + end + + + // Output clock sampling + //----------------------------------- + always @(posedge clk or posedge rst_sync_int2) begin + if (rst_sync_int2) begin + counter <= #TCQ { C_W { 1'b 0 } }; + end else begin + counter <= #TCQ counter + 1'b 1; + end + end + + // alias the high bit to the output + assign COUNT = counter[C_W-1]; + + + +endmodule diff --git a/cores/clk_wiz_v3_6/example_design/clk_wiz_v3_6_exdes.xdc b/cores/clk_wiz_v3_6/example_design/clk_wiz_v3_6_exdes.xdc new file mode 100644 index 0000000..51bdbe4 --- /dev/null +++ b/cores/clk_wiz_v3_6/example_design/clk_wiz_v3_6_exdes.xdc @@ -0,0 +1,68 @@ +# file: clk_wiz_v3_6_exdes.xdc +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +# Input clock periods. These duplicate the values entered for the +# input clocks. You can use these to time your system +#---------------------------------------------------------------- +create_clock -name CLK_IN1 -period 20.0 [get_ports CLK_IN1] +set_propagated_clock CLK_IN1 +set_input_jitter CLK_IN1 0.2 + +# FALSE PATH constraint added on COUNTER_RESET +set_false_path -from [get_ports "COUNTER_RESET"] + +# Derived clock periods. These are commented out because they are +# automatically propogated by the tools +# However, if you'd like to use them for module level testing, you +# can copy them into your module level timing checks +#----------------------------------------------------------------- + +#----------------------------------------------------------------- + +#----------------------------------------------------------------- diff --git a/cores/clk_wiz_v3_6/implement/implement.bat b/cores/clk_wiz_v3_6/implement/implement.bat new file mode 100644 index 0000000..6418c54 --- /dev/null +++ b/cores/clk_wiz_v3_6/implement/implement.bat @@ -0,0 +1,90 @@ +REM file: implement.bat +REM +REM (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +REM +REM This file contains confidential and proprietary information +REM of Xilinx, Inc. and is protected under U.S. and +REM international copyright and other intellectual property +REM laws. +REM +REM DISCLAIMER +REM This disclaimer is not a license and does not grant any +REM rights to the materials distributed herewith. Except as +REM otherwise provided in a valid license issued to you by +REM Xilinx, and to the maximum extent permitted by applicable +REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +REM (2) Xilinx shall not be liable (whether in contract or tort, +REM including negligence, or under any other theory of +REM liability) for any loss or damage of any kind or nature +REM related to, arising under or in connection with these +REM materials, including for any direct, or any indirect, +REM special, incidental, or consequential loss or damage +REM (including loss of data, profits, goodwill, or any type of +REM loss or damage suffered as a result of any action brought +REM by a third party) even if such damage or loss was +REM reasonably foreseeable or Xilinx had been advised of the +REM possibility of the same. +REM +REM CRITICAL APPLICATIONS +REM Xilinx products are not designed or intended to be fail- +REM safe, or for use in any application requiring fail-safe +REM performance, such as life-support or safety devices or +REM systems, Class III medical devices, nuclear facilities, +REM applications related to the deployment of airbags, or any +REM other applications that could lead to death, personal +REM injury, or severe property or environmental damage +REM (individually and collectively, "Critical +REM Applications"). Customer assumes the sole risk and +REM liability of any use of Xilinx products in Critical +REM Applications, subject only to applicable laws and +REM regulations governing limitations on product liability. +REM +REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +REM PART OF THIS FILE AT ALL TIMES. +REM + +REM ----------------------------------------------------------------------------- +REM Script to synthesize and implement the RTL provided for the clocking wizard +REM ----------------------------------------------------------------------------- + +REM Clean up the results directory +rmdir /S /Q results +mkdir results + +REM Copy unisim_comp.v file to results directory +copy %XILINX%\verilog\src\iSE\unisim_comp.v .\results\ + +REM Synthesize the Verilog Wrapper Files +echo 'Synthesizing Clocking Wizard design with XST' +xst -ifn xst.scr +move clk_wiz_v3_6_exdes.ngc results\ + +REM Copy the constraints files generated by Coregen +echo 'Copying files from constraints directory to results directory' +copy ..\example_design\clk_wiz_v3_6_exdes.ucf results\ + +cd results + +echo 'Running ngdbuild' +ngdbuild -uc clk_wiz_v3_6_exdes.ucf clk_wiz_v3_6_exdes + +echo 'Running map' +map -timing -pr b clk_wiz_v3_6_exdes -o mapped.ncd + +echo 'Running par' +par -w mapped.ncd routed mapped.pcf + +echo 'Running trce' +trce -e 10 routed -o routed mapped.pcf + +echo 'Running design through bitgen' +bitgen -w routed + +echo 'Running netgen to create gate level model for the clocking wizard example design' +netgen -ofmt verilog -sim -sdf_anno false -tm clk_wiz_v3_6_exdes -w routed.ncd routed.v +cd .. + diff --git a/cores/clk_wiz_v3_6/implement/implement.sh b/cores/clk_wiz_v3_6/implement/implement.sh new file mode 100644 index 0000000..3f9f3df --- /dev/null +++ b/cores/clk_wiz_v3_6/implement/implement.sh @@ -0,0 +1,91 @@ +#!/bin/sh +# file: implement.sh +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +#----------------------------------------------------------------------------- +# Script to synthesize and implement the RTL provided for the clocking wizard +#----------------------------------------------------------------------------- + +# Clean up the results directory +rm -rf results +mkdir results + +# Copy unisim_comp.v file to results directory +cp $XILINX/verilog/src/iSE/unisim_comp.v ./results/ + +# Synthesize the Verilog Wrapper Files +echo 'Synthesizing Clocking Wizard design with XST' +xst -ifn xst.scr +mv clk_wiz_v3_6_exdes.ngc results/ + +# Copy the constraints files generated by Coregen +echo 'Copying files from constraints directory to results directory' +cp ../example_design/clk_wiz_v3_6_exdes.ucf results/ + +cd results + +echo 'Running ngdbuild' +ngdbuild -uc clk_wiz_v3_6_exdes.ucf clk_wiz_v3_6_exdes + +echo 'Running map' +map -timing clk_wiz_v3_6_exdes -o mapped.ncd + +echo 'Running par' +par -w mapped.ncd routed mapped.pcf + +echo 'Running trce' +trce -e 10 routed -o routed mapped.pcf + +echo 'Running design through bitgen' +bitgen -w routed + +echo 'Running netgen to create gate level model for the clocking wizard example design' +netgen -ofmt verilog -sim -sdf_anno false -tm clk_wiz_v3_6_exdes -w routed.ncd routed.v + +cd .. diff --git a/cores/clk_wiz_v3_6/implement/planAhead_ise.bat b/cores/clk_wiz_v3_6/implement/planAhead_ise.bat new file mode 100644 index 0000000..8ac7718 --- /dev/null +++ b/cores/clk_wiz_v3_6/implement/planAhead_ise.bat @@ -0,0 +1,58 @@ +REM file: planAhead_ise.bat +REM +REM (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +REM +REM This file contains confidential and proprietary information +REM of Xilinx, Inc. and is protected under U.S. and +REM international copyright and other intellectual property +REM laws. +REM +REM DISCLAIMER +REM This disclaimer is not a license and does not grant any +REM rights to the materials distributed herewith. Except as +REM otherwise provided in a valid license issued to you by +REM Xilinx, and to the maximum extent permitted by applicable +REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +REM (2) Xilinx shall not be liable (whether in contract or tort, +REM including negligence, or under any other theory of +REM liability) for any loss or damage of any kind or nature +REM related to, arising under or in connection with these +REM materials, including for any direct, or any indirect, +REM special, incidental, or consequential loss or damage +REM (including loss of data, profits, goodwill, or any type of +REM loss or damage suffered as a result of any action brought +REM by a third party) even if such damage or loss was +REM reasonably foreseeable or Xilinx had been advised of the +REM possibility of the same. +REM +REM CRITICAL APPLICATIONS +REM Xilinx products are not designed or intended to be fail- +REM safe, or for use in any application requiring fail-safe +REM performance, such as life-support or safety devices or +REM systems, Class III medical devices, nuclear facilities, +REM applications related to the deployment of airbags, or any +REM other applications that could lead to death, personal +REM injury, or severe property or environmental damage +REM (individually and collectively, "Critical +REM Applications"). Customer assumes the sole risk and +REM liability of any use of Xilinx products in Critical +REM Applications, subject only to applicable laws and +REM regulations governing limitations on product liability. +REM +REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +REM PART OF THIS FILE AT ALL TIMES. +REM + +REM----------------------------------------------------------------------------- +REM Script to synthesize and implement the RTL provided for the clocking wizard +REM----------------------------------------------------------------------------- + +del \f results +mkdir results +cd results + +planAhead -mode batch -source ..\planAhead_ise.tcl diff --git a/cores/clk_wiz_v3_6/implement/planAhead_ise.sh b/cores/clk_wiz_v3_6/implement/planAhead_ise.sh new file mode 100644 index 0000000..6c8c837 --- /dev/null +++ b/cores/clk_wiz_v3_6/implement/planAhead_ise.sh @@ -0,0 +1,59 @@ +#!/bin/sh +# file: planAhead_ise.sh +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +#----------------------------------------------------------------------------- +# Script to synthesize and implement the RTL provided for the clocking wizard +#----------------------------------------------------------------------------- + +rm -rf results +mkdir results +cd results + +planAhead -mode batch -source ../planAhead_ise.tcl diff --git a/cores/clk_wiz_v3_6/implement/planAhead_ise.tcl b/cores/clk_wiz_v3_6/implement/planAhead_ise.tcl new file mode 100644 index 0000000..2d56798 --- /dev/null +++ b/cores/clk_wiz_v3_6/implement/planAhead_ise.tcl @@ -0,0 +1,78 @@ +# file: planAhead_ise.tcl +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +set projDir [file dirname [info script]] +set projName clk_wiz_v3_6 +set topName clk_wiz_v3_6_exdes +set device xc6slx9tqg144-2 + +create_project $projName $projDir/results/$projName -part $device + +set_property design_mode RTL [get_filesets sources_1] + +## Source files +#set verilogSources [glob $srcDir/*.v] +import_files -fileset [get_filesets sources_1] -force -norecurse ../../example_design/clk_wiz_v3_6_exdes.v +import_files -fileset [get_filesets sources_1] -force -norecurse ../../../clk_wiz_v3_6.v + + +#UCF file +import_files -fileset [get_filesets constrs_1] -force -norecurse ../../example_design/clk_wiz_v3_6_exdes.ucf + +set_property top $topName [get_property srcset [current_run]] + +launch_runs -runs synth_1 +wait_on_run synth_1 + +set_property add_step Bitgen [get_runs impl_1] +launch_runs -runs impl_1 +wait_on_run impl_1 + + + diff --git a/cores/clk_wiz_v3_6/implement/planAhead_rdn.bat b/cores/clk_wiz_v3_6/implement/planAhead_rdn.bat new file mode 100644 index 0000000..42273f5 --- /dev/null +++ b/cores/clk_wiz_v3_6/implement/planAhead_rdn.bat @@ -0,0 +1,58 @@ +REM file: planAhead_rdn.sh +REM +REM (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +REM +REM This file contains confidential and proprietary information +REM of Xilinx, Inc. and is protected under U.S. and +REM international copyright and other intellectual property +REM laws. +REM +REM DISCLAIMER +REM This disclaimer is not a license and does not grant any +REM rights to the materials distributed herewith. Except as +REM otherwise provided in a valid license issued to you by +REM Xilinx, and to the maximum extent permitted by applicable +REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +REM (2) Xilinx shall not be liable (whether in contract or tort, +REM including negligence, or under any other theory of +REM liability) for any loss or damage of any kind or nature +REM related to, arising under or in connection with these +REM materials, including for any direct, or any indirect, +REM special, incidental, or consequential loss or damage +REM (including loss of data, profits, goodwill, or any type of +REM loss or damage suffered as a result of any action brought +REM by a third party) even if such damage or loss was +REM reasonably foreseeable or Xilinx had been advised of the +REM possibility of the same. +REM +REM CRITICAL APPLICATIONS +REM Xilinx products are not designed or intended to be fail- +REM safe, or for use in any application requiring fail-safe +REM performance, such as life-support or safety devices or +REM systems, Class III medical devices, nuclear facilities, +REM applications related to the deployment of airbags, or any +REM other applications that could lead to death, personal +REM injury, or severe property or environmental damage +REM (individually and collectively, "Critical +REM Applications"). Customer assumes the sole risk and +REM liability of any use of Xilinx products in Critical +REM Applications, subject only to applicable laws and +REM regulations governing limitations on product liability. +REM +REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +REM PART OF THIS FILE AT ALL TIMES. +REM + +REM----------------------------------------------------------------------------- +REM Script to synthesize and implement the RTL provided for the XADC wizard +REM----------------------------------------------------------------------------- + +del \f results +mkdir results +cd results + +planAhead -mode batch -source ..\planAhead_rdn.tcl diff --git a/cores/clk_wiz_v3_6/implement/planAhead_rdn.sh b/cores/clk_wiz_v3_6/implement/planAhead_rdn.sh new file mode 100644 index 0000000..f4c1472 --- /dev/null +++ b/cores/clk_wiz_v3_6/implement/planAhead_rdn.sh @@ -0,0 +1,57 @@ +#!/bin/sh +# file: planAhead_rdn.sh +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +#----------------------------------------------------------------------------- +# Script to synthesize and implement the RTL provided for the XADC wizard +#----------------------------------------------------------------------------- +rm -rf results +mkdir results +cd results +planAhead -mode batch -source ../planAhead_rdn.tcl diff --git a/cores/clk_wiz_v3_6/implement/planAhead_rdn.tcl b/cores/clk_wiz_v3_6/implement/planAhead_rdn.tcl new file mode 100644 index 0000000..ffa98a3 --- /dev/null +++ b/cores/clk_wiz_v3_6/implement/planAhead_rdn.tcl @@ -0,0 +1,69 @@ +# file : planAhead_rdn.tcl +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +set device xc6slx9tqg144-2 +set projName clk_wiz_v3_6 +set design clk_wiz_v3_6 +set projDir [file dirname [info script]] +create_project $projName $projDir/results/$projName -part $device -force +set_property design_mode RTL [current_fileset -srcset] +set top_module clk_wiz_v3_6_exdes +set_property top clk_wiz_v3_6_exdes [get_property srcset [current_run]] +add_files -norecurse {../../../clk_wiz_v3_6.v} +add_files -norecurse {../../example_design/clk_wiz_v3_6_exdes.v} +import_files -fileset [get_filesets constrs_1 ] -force -norecurse {../../example_design/clk_wiz_v3_6_exdes.xdc} +synth_design +opt_design +place_design +route_design +write_sdf -rename_top_module clk_wiz_v3_6_exdes -file routed.sdf +write_verilog -nolib -mode timesim -sdf_anno false -rename_top_module clk_wiz_v3_6_exdes -file routed.v +report_timing -nworst 30 -path_type full -file routed.twr +report_drc -file report.drc +write_bitstream -bitgen_options {-g UnconstrainedPins:Allow} -file routed.bit diff --git a/cores/clk_wiz_v3_6/implement/xst.prj b/cores/clk_wiz_v3_6/implement/xst.prj new file mode 100644 index 0000000..8e858dd --- /dev/null +++ b/cores/clk_wiz_v3_6/implement/xst.prj @@ -0,0 +1,2 @@ +verilog work ../../clk_wiz_v3_6.v +verilog work ../example_design/clk_wiz_v3_6_exdes.v diff --git a/cores/clk_wiz_v3_6/implement/xst.scr b/cores/clk_wiz_v3_6/implement/xst.scr new file mode 100644 index 0000000..b0dc4df --- /dev/null +++ b/cores/clk_wiz_v3_6/implement/xst.scr @@ -0,0 +1,9 @@ +run +-ifmt MIXED +-top clk_wiz_v3_6_exdes +-p xc6slx9-tqg144-2 +-ifn xst.prj +-ofn clk_wiz_v3_6_exdes +-keep_hierarchy soft +-equivalent_register_removal no +-max_fanout 65535 diff --git a/cores/clk_wiz_v3_6/simulation/clk_wiz_v3_6_tb.v b/cores/clk_wiz_v3_6/simulation/clk_wiz_v3_6_tb.v new file mode 100644 index 0000000..0991d6a --- /dev/null +++ b/cores/clk_wiz_v3_6/simulation/clk_wiz_v3_6_tb.v @@ -0,0 +1,133 @@ +// file: clk_wiz_v3_6_tb.v +// +// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// + +//---------------------------------------------------------------------------- +// Clocking wizard demonstration testbench +//---------------------------------------------------------------------------- +// This demonstration testbench instantiates the example design for the +// clocking wizard. Input clocks are toggled, which cause the clocking +// network to lock and the counters to increment. +//---------------------------------------------------------------------------- + +`timescale 1ps/1ps + +`define wait_lock @(posedge dut.clknetwork.dcm_sp_inst.LOCKED) + +module clk_wiz_v3_6_tb (); + + // Clock to Q delay of 100ps + localparam TCQ = 100; + + + // timescale is 1ps/1ps + localparam ONE_NS = 1000; + localparam PHASE_ERR_MARGIN = 100; // 100ps + // how many cycles to run + localparam COUNT_PHASE = 1024; + // we'll be using the period in many locations + localparam time PER1 = 20.0*ONE_NS; + localparam time PER1_1 = PER1/2; + localparam time PER1_2 = PER1 - PER1/2; + + // Declare the input clock signals + reg CLK_IN1 = 1; + + // The high bit of the sampling counter + wire COUNT; + reg COUNTER_RESET = 0; +wire [1:1] CLK_OUT; +//Freq Check using the M & D values setting and actual Frequency generated + + + // Input clock generation + //------------------------------------ + always begin + CLK_IN1 = #PER1_1 ~CLK_IN1; + CLK_IN1 = #PER1_2 ~CLK_IN1; + end + + // Test sequence + reg [15*8-1:0] test_phase = ""; + initial begin + // Set up any display statements using time to be readable + $timeformat(-12, 2, "ps", 10); + COUNTER_RESET = 0; + test_phase = "wait lock"; + `wait_lock; + #(PER1*6); + COUNTER_RESET = 1; + #(PER1*20) + COUNTER_RESET = 0; + + test_phase = "counting"; + #(PER1*COUNT_PHASE); + + $display("SIMULATION PASSED"); + $display("SYSTEM_CLOCK_COUNTER : %0d\n",$time/PER1); + $finish; + end + + // Instantiation of the example design containing the clock + // network and sampling counters + //--------------------------------------------------------- + clk_wiz_v3_6_exdes + #( + .TCQ (TCQ) + ) dut + (// Clock in ports + .CLK_IN1 (CLK_IN1), + // Reset for logic in example design + .COUNTER_RESET (COUNTER_RESET), + .CLK_OUT (CLK_OUT), + // High bits of the counters + .COUNT (COUNT)); + +// Freq Check + +endmodule diff --git a/cores/clk_wiz_v3_6/simulation/functional/simcmds.tcl b/cores/clk_wiz_v3_6/simulation/functional/simcmds.tcl new file mode 100644 index 0000000..112310b --- /dev/null +++ b/cores/clk_wiz_v3_6/simulation/functional/simcmds.tcl @@ -0,0 +1,8 @@ +# file: simcmds.tcl + +# create the simulation script +vcd dumpfile isim.vcd +vcd dumpvars -m /clk_wiz_v3_6_tb -l 0 +wave add / +run 50000ns +quit diff --git a/cores/clk_wiz_v3_6/simulation/functional/simulate_isim.bat b/cores/clk_wiz_v3_6/simulation/functional/simulate_isim.bat new file mode 100644 index 0000000..72ea9a1 --- /dev/null +++ b/cores/clk_wiz_v3_6/simulation/functional/simulate_isim.bat @@ -0,0 +1,59 @@ +REM file: simulate_isim.bat +REM +REM (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +REM +REM This file contains confidential and proprietary information +REM of Xilinx, Inc. and is protected under U.S. and +REM international copyright and other intellectual property +REM laws. +REM +REM DISCLAIMER +REM This disclaimer is not a license and does not grant any +REM rights to the materials distributed herewith. Except as +REM otherwise provided in a valid license issued to you by +REM Xilinx, and to the maximum extent permitted by applicable +REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +REM (2) Xilinx shall not be liable (whether in contract or tort, +REM including negligence, or under any other theory of +REM liability) for any loss or damage of any kind or nature +REM related to, arising under or in connection with these +REM materials, including for any direct, or any indirect, +REM special, incidental, or consequential loss or damage +REM (including loss of data, profits, goodwill, or any type of +REM loss or damage suffered as a result of any action brought +REM by a third party) even if such damage or loss was +REM reasonably foreseeable or Xilinx had been advised of the +REM possibility of the same. +REM +REM CRITICAL APPLICATIONS +REM Xilinx products are not designed or intended to be fail- +REM safe, or for use in any application requiring fail-safe +REM performance, such as life-support or safety devices or +REM systems, Class III medical devices, nuclear facilities, +REM applications related to the deployment of airbags, or any +REM other applications that could lead to death, personal +REM injury, or severe property or environmental damage +REM (individually and collectively, "Critical +REM Applications"). Customer assumes the sole risk and +REM liability of any use of Xilinx products in Critical +REM Applications, subject only to applicable laws and +REM regulations governing limitations on product liability. +REM +REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +REM PART OF THIS FILE AT ALL TIMES. +REM + +vlogcomp -work work %XILINX%\verilog\src\glbl.v +vlogcomp -work work ..\..\..\clk_wiz_v3_6.v +vlogcomp -work work ..\..\example_design\clk_wiz_v3_6_exdes.v +vlogcomp -work work ..\clk_wiz_v3_6_tb.v + +REM compile the project +fuse work.clk_wiz_v3_6_tb work.glbl -L unisims_ver -o clk_wiz_v3_6_isim.exe + +REM run the simulation script +.\clk_wiz_v3_6_isim.exe -gui -tclbatch simcmds.tcl diff --git a/cores/clk_wiz_v3_6/simulation/functional/simulate_isim.sh b/cores/clk_wiz_v3_6/simulation/functional/simulate_isim.sh new file mode 100644 index 0000000..5c77458 --- /dev/null +++ b/cores/clk_wiz_v3_6/simulation/functional/simulate_isim.sh @@ -0,0 +1,61 @@ +# file: simulate_isim.sh +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +# nt +# create the project +vlogcomp -work work ${XILINX}/verilog/src/glbl.v +vlogcomp -work work ../../../clk_wiz_v3_6.v +vlogcomp -work work ../../example_design/clk_wiz_v3_6_exdes.v +vlogcomp -work work ../clk_wiz_v3_6_tb.v + +# compile the project +fuse work.clk_wiz_v3_6_tb work.glbl -L unisims_ver -o clk_wiz_v3_6_isim.exe + +# run the simulation script +./clk_wiz_v3_6_isim.exe -gui -tclbatch simcmds.tcl diff --git a/cores/clk_wiz_v3_6/simulation/functional/simulate_mti.bat b/cores/clk_wiz_v3_6/simulation/functional/simulate_mti.bat new file mode 100644 index 0000000..aced925 --- /dev/null +++ b/cores/clk_wiz_v3_6/simulation/functional/simulate_mti.bat @@ -0,0 +1,61 @@ +REM file: simulate_mti.bat +REM +REM (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +REM +REM This file contains confidential and proprietary information +REM of Xilinx, Inc. and is protected under U.S. and +REM international copyright and other intellectual property +REM laws. +REM +REM DISCLAIMER +REM This disclaimer is not a license and does not grant any +REM rights to the materials distributed herewith. Except as +REM otherwise provided in a valid license issued to you by +REM Xilinx, and to the maximum extent permitted by applicable +REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +REM (2) Xilinx shall not be liable (whether in contract or tort, +REM including negligence, or under any other theory of +REM liability) for any loss or damage of any kind or nature +REM related to, arising under or in connection with these +REM materials, including for any direct, or any indirect, +REM special, incidental, or consequential loss or damage +REM (including loss of data, profits, goodwill, or any type of +REM loss or damage suffered as a result of any action brought +REM by a third party) even if such damage or loss was +REM reasonably foreseeable or Xilinx had been advised of the +REM possibility of the same. +REM +REM CRITICAL APPLICATIONS +REM Xilinx products are not designed or intended to be fail- +REM safe, or for use in any application requiring fail-safe +REM performance, such as life-support or safety devices or +REM systems, Class III medical devices, nuclear facilities, +REM applications related to the deployment of airbags, or any +REM other applications that could lead to death, personal +REM injury, or severe property or environmental damage +REM (individually and collectively, "Critical +REM Applications"). Customer assumes the sole risk and +REM liability of any use of Xilinx products in Critical +REM Applications, subject only to applicable laws and +REM regulations governing limitations on product liability. +REM +REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +REM PART OF THIS FILE AT ALL TIMES. +REM + +REM set up the working directory +vlib work + +REM compile all of the files +vlog -work work %XILINX%\verilog\src\glbl.v +vlog -work work ..\..\..\clk_wiz_v3_6.v +vlog -work work ..\..\example_design\clk_wiz_v3_6_exdes.v +vlog -work work ..\clk_wiz_v3_6_tb.v + +REM run the simulation +vsim -c -t ps -voptargs="+acc" -L secureip -L unisims_ver work.clk_wiz_v3_6_tb work.glbl + diff --git a/cores/clk_wiz_v3_6/simulation/functional/simulate_mti.do b/cores/clk_wiz_v3_6/simulation/functional/simulate_mti.do new file mode 100644 index 0000000..6f409db --- /dev/null +++ b/cores/clk_wiz_v3_6/simulation/functional/simulate_mti.do @@ -0,0 +1,65 @@ +# file: simulate_mti.do +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +# set up the working directory +set work work +vlib work + +# compile all of the files +vlog -work work $env(XILINX)/verilog/src/glbl.v +vlog -work work ../../../clk_wiz_v3_6.v +vlog -work work ../../example_design/clk_wiz_v3_6_exdes.v +vlog -work work ../clk_wiz_v3_6_tb.v + +# run the simulation +vsim -t ps -voptargs="+acc" -L unisims_ver work.clk_wiz_v3_6_tb work.glbl +do wave.do +log clk_wiz_v3_6_tb/dut/counter +log -r /* +run 50000ns diff --git a/cores/clk_wiz_v3_6/simulation/functional/simulate_mti.sh b/cores/clk_wiz_v3_6/simulation/functional/simulate_mti.sh new file mode 100644 index 0000000..076df7b --- /dev/null +++ b/cores/clk_wiz_v3_6/simulation/functional/simulate_mti.sh @@ -0,0 +1,61 @@ +#/bin/sh +# file: simulate_mti.sh +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# +# set up the working directory +set work work +vlib work + +# compile all of the files +vlog -work work $XILINX/verilog/src/glbl.v +vlog -work work ../../../clk_wiz_v3_6.v +vlog -work work ../../example_design/clk_wiz_v3_6_exdes.v +vlog -work work ../clk_wiz_v3_6_tb.v + +# run the simulation +vsim -c -t ps -voptargs="+acc" -L secureip -L unisims_ver work.clk_wiz_v3_6_tb work.glbl diff --git a/cores/clk_wiz_v3_6/simulation/functional/simulate_ncsim.sh b/cores/clk_wiz_v3_6/simulation/functional/simulate_ncsim.sh new file mode 100644 index 0000000..7160e5a --- /dev/null +++ b/cores/clk_wiz_v3_6/simulation/functional/simulate_ncsim.sh @@ -0,0 +1,62 @@ +#/bin/sh +# file: simulate_ncsim.sh +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +# set up the working directory +mkdir work + +# compile all of the files +ncvlog -work work ${XILINX}/verilog/src/glbl.v +ncvlog -work work ../../../clk_wiz_v3_6.v +ncvlog -work work ../../example_design/clk_wiz_v3_6_exdes.v +ncvlog -work work ../clk_wiz_v3_6_tb.v + +# elaborate and run the simulation +ncelab -work work -access +wc work.clk_wiz_v3_6_tb work.glbl +ncsim -input "@database -open -shm nc; probe -create -database nc -all -depth all; probe dut.counter; run 50000ns; exit" work.clk_wiz_v3_6_tb diff --git a/cores/clk_wiz_v3_6/simulation/functional/simulate_vcs.sh b/cores/clk_wiz_v3_6/simulation/functional/simulate_vcs.sh new file mode 100644 index 0000000..703b296 --- /dev/null +++ b/cores/clk_wiz_v3_6/simulation/functional/simulate_vcs.sh @@ -0,0 +1,72 @@ +#!/bin/sh +# file: simulate_vcs.sh +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +# remove old files +rm -rf simv* csrc DVEfiles AN.DB + +# compile all of the files +# Note that -sverilog is not strictly required- You can +# remove the -sverilog if you change the type of the +# localparam for the periods in the testbench file to +# [63:0] from time +vlogan -sverilog \ + ${XILINX}/verilog/src/glbl.v \ + ../../../clk_wiz_v3_6.v \ + ../../example_design/clk_wiz_v3_6_exdes.v \ + ../clk_wiz_v3_6_tb.v + +# prepare the simulation +vcs +vcs+lic+wait -debug clk_wiz_v3_6_tb glbl + +# run the simulation +./simv -ucli -i ucli_commands.key + +# launch the viewer +dve -vpd vcdplus.vpd -session vcs_session.tcl diff --git a/cores/clk_wiz_v3_6/simulation/functional/ucli_commands.key b/cores/clk_wiz_v3_6/simulation/functional/ucli_commands.key new file mode 100644 index 0000000..0f99eaf --- /dev/null +++ b/cores/clk_wiz_v3_6/simulation/functional/ucli_commands.key @@ -0,0 +1,5 @@ +call {$vcdpluson} +call {$vcdplusmemon(clk_wiz_v3_6_tb.dut.counter)} +run +call {$vcdplusclose} +quit diff --git a/cores/clk_wiz_v3_6/simulation/functional/vcs_session.tcl b/cores/clk_wiz_v3_6/simulation/functional/vcs_session.tcl new file mode 100644 index 0000000..4075e64 --- /dev/null +++ b/cores/clk_wiz_v3_6/simulation/functional/vcs_session.tcl @@ -0,0 +1,15 @@ +gui_open_window Wave +gui_sg_create clk_wiz_v3_6_group +gui_list_add_group -id Wave.1 {clk_wiz_v3_6_group} +gui_sg_addsignal -group clk_wiz_v3_6_group {clk_wiz_v3_6_tb.test_phase} +gui_set_radix -radix {ascii} -signals {clk_wiz_v3_6_tb.test_phase} +gui_sg_addsignal -group clk_wiz_v3_6_group {{Input_clocks}} -divider +gui_sg_addsignal -group clk_wiz_v3_6_group {clk_wiz_v3_6_tb.CLK_IN1} +gui_sg_addsignal -group clk_wiz_v3_6_group {{Output_clocks}} -divider +gui_sg_addsignal -group clk_wiz_v3_6_group {clk_wiz_v3_6_tb.dut.clk} +gui_list_expand -id Wave.1 clk_wiz_v3_6_tb.dut.clk +gui_sg_addsignal -group clk_wiz_v3_6_group {{Counters}} -divider +gui_sg_addsignal -group clk_wiz_v3_6_group {clk_wiz_v3_6_tb.COUNT} +gui_sg_addsignal -group clk_wiz_v3_6_group {clk_wiz_v3_6_tb.dut.counter} +gui_list_expand -id Wave.1 clk_wiz_v3_6_tb.dut.counter +gui_zoom -window Wave.1 -full diff --git a/cores/clk_wiz_v3_6/simulation/functional/wave.do b/cores/clk_wiz_v3_6/simulation/functional/wave.do new file mode 100644 index 0000000..df78b23 --- /dev/null +++ b/cores/clk_wiz_v3_6/simulation/functional/wave.do @@ -0,0 +1,57 @@ +# file: wave.do +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +add wave -noupdate -format Literal -radix ascii /clk_wiz_v3_6_tb/test_phase +add wave -noupdate -divider {Input clocks} +add wave -noupdate -format Logic /clk_wiz_v3_6_tb/CLK_IN1 +add wave -noupdate -divider {Output clocks} +add wave -noupdate -format Logic /clk_wiz_v3_6_tb/dut/clk +add wave -noupdate -divider Counters +add wave -noupdate -format Literal -radix hexadecimal /clk_wiz_v3_6_tb/COUNT +add wave -noupdate -format Literal -radix hexadecimal /clk_wiz_v3_6_tb/dut/counter diff --git a/cores/clk_wiz_v3_6/simulation/functional/wave.sv b/cores/clk_wiz_v3_6/simulation/functional/wave.sv new file mode 100644 index 0000000..5569b3a --- /dev/null +++ b/cores/clk_wiz_v3_6/simulation/functional/wave.sv @@ -0,0 +1,111 @@ +# file: wave.sv +# +# (c) Copyright 2008 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# +# Get the windows set up +# +if {[catch {window new WatchList -name "Design Browser 1" -geometry 1054x819+536+322}] != ""} { + window geometry "Design Browser 1" 1054x819+536+322 +} +window target "Design Browser 1" on +browser using {Design Browser 1} +browser set \ + -scope nc::clk_wiz_v3_6_tb +browser yview see nc::clk_wiz_v3_6_tb +browser timecontrol set -lock 0 + +if {[catch {window new WaveWindow -name "Waveform 1" -geometry 1010x600+0+541}] != ""} { + window geometry "Waveform 1" 1010x600+0+541 +} +window target "Waveform 1" on +waveform using {Waveform 1} +waveform sidebar visibility partial +waveform set \ + -primarycursor TimeA \ + -signalnames name \ + -signalwidth 175 \ + -units ns \ + -valuewidth 75 +cursor set -using TimeA -time 0 +waveform baseline set -time 0 +waveform xview limits 0 20000n + +# +# Define signal groups +# +catch {group new -name {Output clocks} -overlay 0} +catch {group new -name {Status/control} -overlay 0} +catch {group new -name {Counters} -overlay 0} + +set id [waveform add -signals [list {nc::clk_wiz_v3_6_tb.CLK_IN1}]] + +group using {Output clocks} +group set -overlay 0 +group set -comment {} +group clear 0 end + +group insert \ + {clk_wiz_v3_6_tb.dut.clk} \ + +group using {Counters} +group set -overlay 0 +group set -comment {} +group clear 0 end + +group insert \ + {clk_wiz_v3_6_tb.dut.counter} \ + + +set id [waveform add -signals [list {nc::clk_wiz_v3_6_tb.COUNT} ]] + +set id [waveform add -signals [list {nc::clk_wiz_v3_6_tb.test_phase} ]] +waveform format $id -radix %a + +set groupId [waveform add -groups {{Input clocks}}] +set groupId [waveform add -groups {{Output clocks}}] +set groupId [waveform add -groups {{Status/control}}] +set groupId [waveform add -groups {{Counters}}] diff --git a/cores/clk_wiz_v3_6/simulation/timing/clk_wiz_v3_6_tb.v b/cores/clk_wiz_v3_6/simulation/timing/clk_wiz_v3_6_tb.v new file mode 100644 index 0000000..faa34e2 --- /dev/null +++ b/cores/clk_wiz_v3_6/simulation/timing/clk_wiz_v3_6_tb.v @@ -0,0 +1,136 @@ +// file: clk_wiz_v3_6_tb.v +// +// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// + +//---------------------------------------------------------------------------- +// Clocking wizard demonstration testbench +//---------------------------------------------------------------------------- +// This demonstration testbench instantiates the example design for the +// clocking wizard. Input clocks are toggled, which cause the clocking +// network to lock and the counters to increment. +//---------------------------------------------------------------------------- + +`timescale 1ps/1ps + + +module clk_wiz_v3_6_tb (); + + // Clock to Q delay of 100ps + localparam TCQ = 100; + + + // timescale is 1ps/1ps + localparam ONE_NS = 1000; + localparam PHASE_ERR_MARGIN = 100; // 100ps + // how many cycles to run + localparam COUNT_PHASE = 1024; + // we'll be using the period in many locations + localparam time PER1 = 20.0*ONE_NS; + localparam time PER1_1 = PER1/2; + localparam time PER1_2 = PER1 - PER1/2; + + // Declare the input clock signals + reg CLK_IN1 = 1; + + // The high bit of the sampling counter + wire COUNT; + reg COUNTER_RESET = 0; +wire [1:1] CLK_OUT; +//Freq Check using the M & D values setting and actual Frequency generated + + reg [13:0] timeout_counter = 14'b00000000000000; + + // Input clock generation + //------------------------------------ + always begin + CLK_IN1 = #PER1_1 ~CLK_IN1; + CLK_IN1 = #PER1_2 ~CLK_IN1; + end + + // Test sequence + reg [15*8-1:0] test_phase = ""; + initial begin + // Set up any display statements using time to be readable + $timeformat(-12, 2, "ps", 10); + $display ("Timing checks are not valid"); + COUNTER_RESET = 0; + test_phase = "wait lock"; + #(PER1*50); + #(PER1*6); + COUNTER_RESET = 1; + #(PER1*19.5) + COUNTER_RESET = 0; + #(PER1*1) + $display ("Timing checks are valid"); + test_phase = "counting"; + #(PER1*COUNT_PHASE); + + $display("SIMULATION PASSED"); + $display("SYSTEM_CLOCK_COUNTER : %0d\n",$time/PER1); + $finish; + end + + + + // Instantiation of the example design containing the clock + // network and sampling counters + //--------------------------------------------------------- + clk_wiz_v3_6_exdes + dut + (// Clock in ports + .CLK_IN1 (CLK_IN1), + // Reset for logic in example design + .COUNTER_RESET (COUNTER_RESET), + .CLK_OUT (CLK_OUT), + // High bits of the counters + .COUNT (COUNT)); + + +// Freq Check + +endmodule diff --git a/cores/clk_wiz_v3_6/simulation/timing/sdf_cmd_file b/cores/clk_wiz_v3_6/simulation/timing/sdf_cmd_file new file mode 100644 index 0000000..52c97ca --- /dev/null +++ b/cores/clk_wiz_v3_6/simulation/timing/sdf_cmd_file @@ -0,0 +1,2 @@ +COMPILED_SDF_FILE = "../../implement/results/routed.sdf.X", +SCOPE = clk_wiz_v3_6_tb.dut; diff --git a/cores/clk_wiz_v3_6/simulation/timing/simcmds.tcl b/cores/clk_wiz_v3_6/simulation/timing/simcmds.tcl new file mode 100644 index 0000000..c673da5 --- /dev/null +++ b/cores/clk_wiz_v3_6/simulation/timing/simcmds.tcl @@ -0,0 +1,9 @@ +# file: simcmds.tcl + +# create the simulation script +vcd dumpfile isim.vcd +vcd dumpvars -m /clk_wiz_v3_6_tb -l 0 +wave add / +run 50000ns +quit + diff --git a/cores/clk_wiz_v3_6/simulation/timing/simulate_isim.sh b/cores/clk_wiz_v3_6/simulation/timing/simulate_isim.sh new file mode 100644 index 0000000..14639f6 --- /dev/null +++ b/cores/clk_wiz_v3_6/simulation/timing/simulate_isim.sh @@ -0,0 +1,62 @@ +# file: simulate_isim.sh +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +# create the project +vlogcomp -work work ${XILINX}/verilog/src/glbl.v +vlogcomp -work work ../../implement/results/routed.v +vlogcomp -work work clk_wiz_v3_6_tb.v + +# compile the project +fuse work.clk_wiz_v3_6_tb work.glbl -L secureip -L simprims_ver -o clk_wiz_v3_6_isim.exe + +# run the simulation script +./clk_wiz_v3_6_isim.exe -tclbatch simcmds.tcl -sdfmax /clk_wiz_v3_6_tb/dut=../../implement/results/routed.sdf + +# run the simulation script +#./clk_wiz_v3_6_isim.exe -gui -tclbatch simcmds.tcl diff --git a/cores/clk_wiz_v3_6/simulation/timing/simulate_mti.bat b/cores/clk_wiz_v3_6/simulation/timing/simulate_mti.bat new file mode 100644 index 0000000..800b0bd --- /dev/null +++ b/cores/clk_wiz_v3_6/simulation/timing/simulate_mti.bat @@ -0,0 +1,59 @@ +REM file: simulate_mti.bat +REM +REM (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +REM +REM This file contains confidential and proprietary information +REM of Xilinx, Inc. and is protected under U.S. and +REM international copyright and other intellectual property +REM laws. +REM +REM DISCLAIMER +REM This disclaimer is not a license and does not grant any +REM rights to the materials distributed herewith. Except as +REM otherwise provided in a valid license issued to you by +REM Xilinx, and to the maximum extent permitted by applicable +REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +REM (2) Xilinx shall not be liable (whether in contract or tort, +REM including negligence, or under any other theory of +REM liability) for any loss or damage of any kind or nature +REM related to, arising under or in connection with these +REM materials, including for any direct, or any indirect, +REM special, incidental, or consequential loss or damage +REM (including loss of data, profits, goodwill, or any type of +REM loss or damage suffered as a result of any action brought +REM by a third party) even if such damage or loss was +REM reasonably foreseeable or Xilinx had been advised of the +REM possibility of the same. +REM +REM CRITICAL APPLICATIONS +REM Xilinx products are not designed or intended to be fail- +REM safe, or for use in any application requiring fail-safe +REM performance, such as life-support or safety devices or +REM systems, Class III medical devices, nuclear facilities, +REM applications related to the deployment of airbags, or any +REM other applications that could lead to death, personal +REM injury, or severe property or environmental damage +REM (individually and collectively, "Critical +REM Applications"). Customer assumes the sole risk and +REM liability of any use of Xilinx products in Critical +REM Applications, subject only to applicable laws and +REM regulations governing limitations on product liability. +REM +REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +REM PART OF THIS FILE AT ALL TIMES. +REM +# set up the working directory +set work work +vlib work + +REM compile all of the files +vlog -work work %XILINX%\verilog\src\glbl.v +vlog -work work ..\..\implement\results\routed.v +vlog -work work clk_wiz_v3_6_tb.v + +REM run the simulation +vsim -c -t ps +transport_int_delays -voptargs="+acc" -L secureip -L simprims_ver -sdfmax clk_wiz_v3_6_tb\dut=..\..\implement\results\routed.sdf +no_notifier work.clk_wiz_v3_6_tb work.glbl diff --git a/cores/clk_wiz_v3_6/simulation/timing/simulate_mti.do b/cores/clk_wiz_v3_6/simulation/timing/simulate_mti.do new file mode 100644 index 0000000..7246613 --- /dev/null +++ b/cores/clk_wiz_v3_6/simulation/timing/simulate_mti.do @@ -0,0 +1,65 @@ +# file: simulate_mti.do +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +# set up the working directory +set work work +vlib work + +# compile all of the files +vlog -work work $env(XILINX)/verilog/src/glbl.v +vlog -work work ../../implement/results/routed.v +vlog -work work clk_wiz_v3_6_tb.v + +# run the simulation +vsim -t ps +transport_int_delays -voptargs="+acc" -L secureip -L simprims_ver -sdfmax clk_wiz_v3_6_tb/dut=../../implement/results/routed.sdf +no_notifier work.clk_wiz_v3_6_tb work.glbl +#do wave.do +#log -r /* +run 50000ns + + diff --git a/cores/clk_wiz_v3_6/simulation/timing/simulate_mti.sh b/cores/clk_wiz_v3_6/simulation/timing/simulate_mti.sh new file mode 100644 index 0000000..86e7f0a --- /dev/null +++ b/cores/clk_wiz_v3_6/simulation/timing/simulate_mti.sh @@ -0,0 +1,61 @@ +#/bin/sh +# file: simulate_mti.sh +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +# set up the working directory +set work work +vlib work + +# compile all of the files +vlog -work work $XILINX/verilog/src/glbl.v +vlog -work work ../../implement/results/routed.v +vlog -work work clk_wiz_v3_6_tb.v + +# run the simulation +vsim -c -t ps +transport_int_delays -voptargs="+acc" -L secureip -L simprims_ver -sdfmax clk_wiz_v3_6_tb/dut=../../implement/results/routed.sdf +no_notifier work.clk_wiz_v3_6_tb work.glbl diff --git a/cores/clk_wiz_v3_6/simulation/timing/simulate_ncsim.sh b/cores/clk_wiz_v3_6/simulation/timing/simulate_ncsim.sh new file mode 100644 index 0000000..9756cd8 --- /dev/null +++ b/cores/clk_wiz_v3_6/simulation/timing/simulate_ncsim.sh @@ -0,0 +1,64 @@ +#!/bin/sh +# file: simulate_ncsim.sh +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +# set up the working directory +mkdir work + +# compile all of the files +ncvlog -work work ${XILINX}/verilog/src/glbl.v +ncvlog -work work ../../implement/results/routed.v +ncvlog -work work clk_wiz_v3_6_tb.v + +# elaborate and run the simulation +ncsdfc ../../implement/results/routed.sdf + +ncelab -work work -access +wc -pulse_r 10 -nonotifier work.clk_wiz_v3_6_tb work.glbl -sdf_cmd_file sdf_cmd_file +ncsim -input "@database -open -shm nc; probe -create -database nc -all -depth all; run 50000ns; exit" work.clk_wiz_v3_6_tb + diff --git a/cores/clk_wiz_v3_6/simulation/timing/simulate_vcs.sh b/cores/clk_wiz_v3_6/simulation/timing/simulate_vcs.sh new file mode 100644 index 0000000..c51b886 --- /dev/null +++ b/cores/clk_wiz_v3_6/simulation/timing/simulate_vcs.sh @@ -0,0 +1,72 @@ +#!/bin/sh +# file: simulate_vcs.sh +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +# remove old files +rm -rf simv* csrc DVEfiles AN.DB + +# compile all of the files +# Note that -sverilog is not strictly required- You can +# remove the -sverilog if you change the type of the +# localparam for the periods in the testbench file to +# [63:0] from time + vlogan -sverilog \ + clk_wiz_v3_6_tb.v \ + ../../implement/results/routed.v + + +# prepare the simulation +vcs -sdf max:clk_wiz_v3_6_exdes:../../implement/results/routed.sdf +v2k -y $XILINX/verilog/src/simprims \ + +libext+.v -debug clk_wiz_v3_6_tb.v ../../implement/results/routed.v + +# run the simulation +./simv -ucli -i ucli_commands.key + +# launch the viewer +#dve -vpd vcdplus.vpd -session vcs_session.tcl diff --git a/cores/clk_wiz_v3_6/simulation/timing/ucli_commands.key b/cores/clk_wiz_v3_6/simulation/timing/ucli_commands.key new file mode 100644 index 0000000..0548d17 --- /dev/null +++ b/cores/clk_wiz_v3_6/simulation/timing/ucli_commands.key @@ -0,0 +1,5 @@ + +call {$vcdpluson} +run 50000ns +call {$vcdplusclose} +quit diff --git a/cores/clk_wiz_v3_6/simulation/timing/vcs_session.tcl b/cores/clk_wiz_v3_6/simulation/timing/vcs_session.tcl new file mode 100644 index 0000000..1438f6b --- /dev/null +++ b/cores/clk_wiz_v3_6/simulation/timing/vcs_session.tcl @@ -0,0 +1 @@ +gui_open_window Wave diff --git a/cores/clk_wiz_v3_6/simulation/timing/wave.do b/cores/clk_wiz_v3_6/simulation/timing/wave.do new file mode 100644 index 0000000..67bd2b4 --- /dev/null +++ b/cores/clk_wiz_v3_6/simulation/timing/wave.do @@ -0,0 +1,70 @@ +# file: wave.do +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate /clk_wiz_v3_6_tb/CLK_IN1 +add wave -noupdate /clk_wiz_v3_6_tb/COUNT +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {3223025 ps} 0} +configure wave -namecolwidth 238 +configure wave -valuecolwidth 107 +configure wave -justifyvalue left +configure wave -signalnamewidth 0 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits ps +update +WaveRestoreZoom {0 ps} {74848022 ps} diff --git a/cores/clk_wiz_v3_6_flist.txt b/cores/clk_wiz_v3_6_flist.txt new file mode 100644 index 0000000..e9e36d3 --- /dev/null +++ b/cores/clk_wiz_v3_6_flist.txt @@ -0,0 +1,53 @@ +# Output products list for +clk_wiz_v3_6.asy +clk_wiz_v3_6.gise +clk_wiz_v3_6.ucf +clk_wiz_v3_6.v +clk_wiz_v3_6.veo +clk_wiz_v3_6.xco +clk_wiz_v3_6.xdc +clk_wiz_v3_6.xise +clk_wiz_v3_6\clk_wiz_v3_6_readme.txt +clk_wiz_v3_6\doc\clk_wiz_v3_6_readme.txt +clk_wiz_v3_6\doc\clk_wiz_v3_6_vinfo.html +clk_wiz_v3_6\doc\pg065_clk_wiz.pdf +clk_wiz_v3_6\example_design\clk_wiz_v3_6_exdes.ucf +clk_wiz_v3_6\example_design\clk_wiz_v3_6_exdes.v +clk_wiz_v3_6\example_design\clk_wiz_v3_6_exdes.xdc +clk_wiz_v3_6\implement\implement.bat +clk_wiz_v3_6\implement\implement.sh +clk_wiz_v3_6\implement\planAhead_ise.bat +clk_wiz_v3_6\implement\planAhead_ise.sh +clk_wiz_v3_6\implement\planAhead_ise.tcl +clk_wiz_v3_6\implement\planAhead_rdn.bat +clk_wiz_v3_6\implement\planAhead_rdn.sh +clk_wiz_v3_6\implement\planAhead_rdn.tcl +clk_wiz_v3_6\implement\xst.prj +clk_wiz_v3_6\implement\xst.scr +clk_wiz_v3_6\simulation\clk_wiz_v3_6_tb.v +clk_wiz_v3_6\simulation\functional\simcmds.tcl +clk_wiz_v3_6\simulation\functional\simulate_isim.bat +clk_wiz_v3_6\simulation\functional\simulate_isim.sh +clk_wiz_v3_6\simulation\functional\simulate_mti.bat +clk_wiz_v3_6\simulation\functional\simulate_mti.do +clk_wiz_v3_6\simulation\functional\simulate_mti.sh +clk_wiz_v3_6\simulation\functional\simulate_ncsim.sh +clk_wiz_v3_6\simulation\functional\simulate_vcs.sh +clk_wiz_v3_6\simulation\functional\ucli_commands.key +clk_wiz_v3_6\simulation\functional\vcs_session.tcl +clk_wiz_v3_6\simulation\functional\wave.do +clk_wiz_v3_6\simulation\functional\wave.sv +clk_wiz_v3_6\simulation\timing\clk_wiz_v3_6_tb.v +clk_wiz_v3_6\simulation\timing\sdf_cmd_file +clk_wiz_v3_6\simulation\timing\simcmds.tcl +clk_wiz_v3_6\simulation\timing\simulate_isim.sh +clk_wiz_v3_6\simulation\timing\simulate_mti.bat +clk_wiz_v3_6\simulation\timing\simulate_mti.do +clk_wiz_v3_6\simulation\timing\simulate_mti.sh +clk_wiz_v3_6\simulation\timing\simulate_ncsim.sh +clk_wiz_v3_6\simulation\timing\simulate_vcs.sh +clk_wiz_v3_6\simulation\timing\ucli_commands.key +clk_wiz_v3_6\simulation\timing\vcs_session.tcl +clk_wiz_v3_6\simulation\timing\wave.do +clk_wiz_v3_6_flist.txt +clk_wiz_v3_6_xmdf.tcl diff --git a/cores/clk_wiz_v3_6_xmdf.tcl b/cores/clk_wiz_v3_6_xmdf.tcl new file mode 100644 index 0000000..37773d8 --- /dev/null +++ b/cores/clk_wiz_v3_6_xmdf.tcl @@ -0,0 +1,140 @@ +# The package naming convention is _xmdf +package provide clk_wiz_v3_6_xmdf 1.0 + +# This includes some utilities that support common XMDF operations +package require utilities_xmdf + +# Define a namespace for this package. The name of the name space +# is _xmdf +namespace eval ::clk_wiz_v3_6_xmdf { +# Use this to define any statics +} + +# Function called by client to rebuild the params and port arrays +# Optional when the use context does not require the param or ports +# arrays to be available. +proc ::clk_wiz_v3_6_xmdf::xmdfInit { instance } { +# Variable containg name of library into which module is compiled +# Recommendation: +# Required +utilities_xmdf::xmdfSetData $instance Module Attributes Name clk_wiz_v3_6 +} +# ::clk_wiz_v3_6_xmdf::xmdfInit + +# Function called by client to fill in all the xmdf* data variables +# based on the current settings of the parameters +proc ::clk_wiz_v3_6_xmdf::xmdfApplyParams { instance } { + +set fcount 0 +# Array containing libraries that are assumed to exist +# Examples include unisim and xilinxcorelib +# Optional +# In this example, we assume that the unisim library will +# be magically +# available to the simulation and synthesis tool +utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library +utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clk_wiz_v3_6/clk_wiz_readme.txt +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clk_wiz_v3_6/doc/clk_wiz_ds709.pdf +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clk_wiz_v3_6/doc/clk_wiz_gsg521.pdf +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clk_wiz_v3_6/implement/implement.bat +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clk_wiz_v3_6/implement/implement.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clk_wiz_v3_6/implement/xst.prj +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clk_wiz_v3_6/implement/xst.scr +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clk_wiz_v3_6/simulation/clk_wiz_v3_6_tb.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clk_wiz_v3_6/simulation/functional/simcmds.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clk_wiz_v3_6/simulation/functional/simulate_isim.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clk_wiz_v3_6/simulation/functional/simulate_mti.do +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clk_wiz_v3_6/simulation/functional/simulate_ncsim.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clk_wiz_v3_6/simulation/functional/simulate_vcs.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clk_wiz_v3_6/simulation/functional/ucli_commands.key +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clk_wiz_v3_6/simulation/functional/vcs_session.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clk_wiz_v3_6/simulation/functional/wave.do +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clk_wiz_v3_6/simulation/functional/wave.sv +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clk_wiz_v3_6.asy +utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clk_wiz_v3_6.ejp +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clk_wiz_v3_6.ucf +utilities_xmdf::xmdfSetData $instance FileSet $fcount type ucf +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clk_wiz_v3_6.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clk_wiz_v3_6.veo +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clk_wiz_v3_6.xco +utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clk_wiz_v3_6_xmdf.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module clk_wiz_v3_6 +incr fcount + +} + +# ::gen_comp_name_xmdf::xmdfApplyParams diff --git a/cores/coregen.cgc b/cores/coregen.cgc new file mode 100644 index 0000000..affe0bf --- /dev/null +++ b/cores/coregen.cgc @@ -0,0 +1,1339 @@ + + + xilinx.com + CoreGen + coregen + 1.0 + + + clk_wiz_v3_6 + + + clk_wiz_v3_6 + true + false + false + false + false + No_Jitter + false + false + 50.000 + Units_MHz + Units_UI + REL_PRIMARY + 100.000 + UI + 0.010 + 0.010 + 0.010 + 0.010 + 200.0 + 100.0 + false + false + false + false + false + false + 1 + false + false + false + false + false + false + false + CLK_IN1 + CLK_OUT1 + CLK_OUT2 + CLK_OUT3 + CLK_OUT4 + CLK_OUT5 + CLK_OUT6 + CLK_OUT7 + DADDR + DCLK + DRDY + DWE + DIN + DOUT + DEN + PSCLK + PSEN + PSINCDEC + PSDONE + 75.000 + 0.000 + 50.000 + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 50.000 + false + false + Single_ended_clock_capable_pin + false + CLK_IN2 + Single_ended_clock_capable_pin + BUFG + BUFG + BUFG + BUFG + BUFG + BUFG + BUFG + FDBK_AUTO + SINGLE + CLKFB_IN + CLKFB_IN_P + CLKFB_IN_N + CLKFB_OUT + CLKFB_OUT_P + CLKFB_OUT_N + nt + empty + false + DONE + false + false + false + false + false + false + false + RESET + LOCKED + POWER_DOWN + CLK_VALID + STATUS + CLK_IN_SEL + INPUT_CLK_STOPPED + CLKFB_STOPPED + false + None + 1 + OPTIMIZED + 4.000 + 0.000 + false + 10.000 + 10.000 + false + false + ZHOLD + 0.010 + 0.010 + false + 4.000 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + false + None + 2.0 + 2 + 3 + false + 20.000 + NONE + SYSTEM_SYNCHRONOUS + 0 + NONE + false + CLKFX + CLK0 + CLK0 + CLK0 + CLK0 + CLK0 + false + None + 1 + 4 + 2 + 0.000 + false + 10.000 + NONE + CLKFX + CLKFX + CLKFX + false + None + OPTIMIZED + 8 + 0.000 + CLKFBOUT + 1 + 20.0 + INTERNAL + 0.010 + 128 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + NONE + AUTO + PLL_BASE + MMCM + CENTER_HIGH + 250 + 0 + 0 + 0 + 0 + 0 + 0 + clk_wiz_v3_6 + nt + 1 + 0 + 0.010 + 0.010 + No_Jitter + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + DCM_SP + 0 + 50.000 + Units_MHz + 100.000 + FDBK_AUTO + Single_ended_clock_capable_pin + Single_ended_clock_capable_pin + SINGLE + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + BUFG + BUFG + BUFG + BUFG + BUFG + BUFG + BUFG + __primary__________50.000____________0.010 + no_secondary_input_clock + CLK_OUT1____75.000______0.000______50.0______466.667____150.000 + no_CLK_OUT2_output + no_CLK_OUT3_output + no_CLK_OUT4_output + no_CLK_OUT5_output + no_CLK_OUT6_output + no_CLK_OUT7_output + 75.000 + 100.000 + 100.000 + 100.000 + 100.000 + 100.000 + 100.000 + 0.000 + 0.000 + 0.000 + 0.000 + 0.000 + 0.000 + 0.000 + 50.000 + 50.000 + 50.000 + 50.000 + 50.000 + 50.000 + 50.000 + 75.000 + N/A + N/A + N/A + N/A + N/A + N/A + 0.000 + N/A + N/A + N/A + N/A + N/A + N/A + 50.0 + N/A + N/A + N/A + N/A + N/A + N/A + None + OPTIMIZED + 4.000 + 10.000 + 10.000 + FALSE + FALSE + ZHOLD + 1 + 0.010 + 0.010 + FALSE + 4.000 + 1 + 1 + 1 + 1 + 1 + 1 + 0.500 + 0.500 + 0.500 + 0.500 + 0.500 + 0.500 + 0.500 + 0.000 + 0.000 + 0.000 + 0.000 + 0.000 + 0.000 + 0.000 + 0.000 + FALSE + FALSE + FALSE + FALSE + FALSE + FALSE + FALSE + FALSE + None + OPTIMIZED + CLKFBOUT + 8 + 20.0 + INTERNAL + 1 + 0.010 + 128 + 1 + 1 + 1 + 1 + 1 + 0.500 + 0.500 + 0.500 + 0.500 + 0.500 + 0.500 + 0.000 + 0.000 + 0.000 + 0.000 + 0.000 + 0.000 + 0.000 + None + 2.000 + 2 + 3 + FALSE + 20.0 + NONE + NONE + NONE + SYSTEM_SYNCHRONOUS + 0 + FALSE + CLKFX + NONE + NONE + NONE + NONE + NONE + None + 2 + 1 + 4 + 20.0 + 0.000 + NONE + FALSE + CLKFX + NONE + NONE + AUTO + 0 + 0 + 0 + 0 + NONE + CLK_IN1 + CLK_IN2 + CLK_OUT1 + CLK_OUT2 + CLK_OUT3 + CLK_OUT4 + CLK_OUT5 + CLK_OUT6 + CLK_OUT7 + RESET + LOCKED + CLKFB_IN + CLKFB_IN_P + CLKFB_IN_N + CLKFB_OUT + CLKFB_OUT_P + CLKFB_OUT_N + POWER_DOWN + DADDR + DCLK + DRDY + DWE + DIN + DOUT + DEN + PSCLK + PSEN + PSINCDEC + PSDONE + CLK_VALID + STATUS + CLK_IN_SEL + INPUT_CLK_STOPPED + CLKFB_STOPPED + 200.0 + 100.0 + MMCM + CENTER_HIGH + 4000 + + + + + coregen + ./ + C:/Program Files/Alchitry/Alchitry Labs/ + C:/Program Files/Alchitry/Alchitry Labs/_cg/ + + + xc6slx9 + spartan6 + tqg144 + -2 + + + BusFormatAngleBracketNotRipped + Verilog + true + Other + false + false + false + Ngc + false + + + Behavioral + Verilog + false + + + 2012-05-10+12:44 + + + + + apply_current_project_options_generator + + + customization_generator + + + model_parameter_resolution_generator + + + ip_xco_generator + + ./clk_wiz_v3_6.xco + xco + Fri Feb 28 22:02:23 GMT 2020 + 0x8939EF15 + generationID_1879581046 + + + + tcl_flow_generator + + ./clk_wiz_v3_6/example_design/clk_wiz_v3_6_exdes.ucf + ignore + ucf + Fri Feb 28 22:02:34 GMT 2020 + 0x19A045DD + generationID_1879581046 + + + ./clk_wiz_v3_6/example_design/clk_wiz_v3_6_exdes.v + ignore + verilog + Fri Feb 28 22:02:24 GMT 2020 + 0xAC64F57E + generationID_1879581046 + + + ./clk_wiz_v3_6/example_design/clk_wiz_v3_6_exdes.xdc + ignore + xdc + Fri Feb 28 22:02:34 GMT 2020 + 0x38870E64 + generationID_1879581046 + + + ./clk_wiz_v3_6/implement/implement.bat + ignore + unknown + Fri Feb 28 22:02:33 GMT 2020 + 0x4ED49AF9 + generationID_1879581046 + + + ./clk_wiz_v3_6/implement/implement.sh + ignore + unknown + Fri Feb 28 22:02:33 GMT 2020 + 0xEFECD5E5 + generationID_1879581046 + + + ./clk_wiz_v3_6/implement/planAhead_ise.bat + ignore + unknown + Fri Feb 28 22:02:31 GMT 2020 + 0x6966A508 + generationID_1879581046 + + + ./clk_wiz_v3_6/implement/planAhead_ise.sh + ignore + unknown + Fri Feb 28 22:02:32 GMT 2020 + 0x7F8B5943 + generationID_1879581046 + + + ./clk_wiz_v3_6/implement/planAhead_ise.tcl + ignore + tcl + Fri Feb 28 22:02:32 GMT 2020 + 0x0F692296 + generationID_1879581046 + + + ./clk_wiz_v3_6/implement/planAhead_rdn.bat + ignore + unknown + Fri Feb 28 22:02:32 GMT 2020 + 0xB9373CFA + generationID_1879581046 + + + ./clk_wiz_v3_6/implement/planAhead_rdn.sh + ignore + unknown + Fri Feb 28 22:02:32 GMT 2020 + 0xDCE9D96C + generationID_1879581046 + + + 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0xAC64F57E + generationID_1879581046 + + + ./clk_wiz_v3_6/example_design/clk_wiz_v3_6_exdes.xdc + ignore + xdc + Fri Feb 28 22:02:37 GMT 2020 + 0x38870E64 + generationID_1879581046 + + + ./clk_wiz_v3_6/implement/implement.bat + ignore + unknown + Fri Feb 28 22:02:37 GMT 2020 + 0x4ED49AF9 + generationID_1879581046 + + + ./clk_wiz_v3_6/implement/implement.sh + ignore + unknown + Fri Feb 28 22:02:37 GMT 2020 + 0xEFECD5E5 + generationID_1879581046 + + + ./clk_wiz_v3_6/implement/planAhead_ise.bat + ignore + unknown + Fri Feb 28 22:02:37 GMT 2020 + 0x6966A508 + generationID_1879581046 + + + ./clk_wiz_v3_6/implement/planAhead_ise.sh + ignore + unknown + Fri Feb 28 22:02:37 GMT 2020 + 0x7F8B5943 + generationID_1879581046 + + + ./clk_wiz_v3_6/implement/planAhead_ise.tcl + ignore + tcl + Fri Feb 28 22:02:37 GMT 2020 + 0x0F692296 + generationID_1879581046 + + + ./clk_wiz_v3_6/implement/planAhead_rdn.bat + ignore + unknown + Fri Feb 28 22:02:37 GMT 2020 + 0xB9373CFA + generationID_1879581046 + + + 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GMT 2020 + 0x28340249 + generationID_1879581046 + + + ./clk_wiz_v3_6/simulation/timing/wave.do + ignore + unknown + Fri Feb 28 22:02:37 GMT 2020 + 0xEDE0E39F + generationID_1879581046 + + + ./clk_wiz_v3_6.ucf + ucf + Fri Feb 28 22:02:37 GMT 2020 + 0x8BA05682 + generationID_1879581046 + + + ./clk_wiz_v3_6.v + verilog + Fri Feb 28 22:02:37 GMT 2020 + 0xF90EB239 + generationID_1879581046 + + + ./clk_wiz_v3_6.veo + veo + Fri Feb 28 22:02:37 GMT 2020 + 0x7B4DCC20 + generationID_1879581046 + + + ./clk_wiz_v3_6.xdc + ignore + xdc + Fri Feb 28 22:02:37 GMT 2020 + 0xDB639994 + generationID_1879581046 + + + ./clk_wiz_v3_6_xmdf.tcl + tcl + Fri Feb 28 22:02:37 GMT 2020 + 0xF1D6EDD0 + generationID_1879581046 + + + + all_documents_generator + + ./clk_wiz_v3_6/doc/clk_wiz_v3_6_readme.txt + ignore + txt + Fri Feb 28 22:02:42 GMT 2020 + 0x5B63DA78 + generationID_1879581046 + + + ./clk_wiz_v3_6/doc/clk_wiz_v3_6_vinfo.html + ignore + unknown + Fri Feb 28 22:02:42 GMT 2020 + 0xF2E77607 + generationID_1879581046 + + + ./clk_wiz_v3_6/doc/pg065_clk_wiz.pdf + ignore + pdf + Fri Feb 28 22:02:42 GMT 2020 + 0x2F883891 + generationID_1879581046 + + + + readme_documents_generator + + + asy_generator + + ./clk_wiz_v3_6.asy + asy + Fri Feb 28 22:02:49 GMT 2020 + 0xB3495C04 + generationID_1879581046 + + + + ise_generator + + ./clk_wiz_v3_6.gise + ignore + gise + Fri Feb 28 22:02:52 GMT 2020 + 0xDC71B9A6 + generationID_1879581046 + + + ./clk_wiz_v3_6.xise + ignore + xise + Fri Feb 28 22:02:52 GMT 2020 + 0x97B6FAE0 + generationID_1879581046 + + + + deliver_readme_generator + + + flist_generator + + ./clk_wiz_v3_6_flist.txt + ignore + txtFlist + txt + Fri Feb 28 22:02:52 GMT 2020 + 0x33F5EAC3 + generationID_1879581046 + + + + view_readme_generator + + + + + + + + + coregen + ./ + C:/Program Files/Alchitry/Alchitry Labs/ + C:/Program Files/Alchitry/Alchitry Labs/_cg/ + + + xc6slx9 + spartan6 + tqg144 + -2 + + + BusFormatAngleBracketNotRipped + Verilog + true + Other + false + false + false + Ngc + false + + + Behavioral + Verilog + false + + + + + diff --git a/cores/coregen.cgp b/cores/coregen.cgp new file mode 100644 index 0000000..eac9d0b --- /dev/null +++ b/cores/coregen.cgp @@ -0,0 +1,22 @@ +# Date: Fri Feb 28 22:01:30 2020 + +SET addpads = false +SET asysymbol = true +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = false +SET designentry = Verilog +SET device = xc6slx9 +SET devicefamily = spartan6 +SET flowvendor = Other +SET formalverification = false +SET foundationsym = false +SET implementationfiletype = Ngc +SET package = tqg144 +SET removerpms = false +SET simulationfiles = Behavioral +SET speedgrade = -2 +SET verilogsim = true +SET vhdlsim = false +SET workingdirectory = "C:\Program Files\Alchitry\Alchitry Labs\" + +# CRC: 38e944ea diff --git a/source/mojo_top.v b/source/mojo_top.v new file mode 100644 index 0000000..f8e4c1b --- /dev/null +++ b/source/mojo_top.v @@ -0,0 +1,256 @@ +module mojo_top( + // 50MHz clock input + input clk, + // Input from reset button (active low) + input rst_n, + // cclk input from AVR, high when AVR is ready + input cclk, + // Outputs to the 8 onboard LEDs + output[7:0]led, + // AVR SPI connections + output spi_miso, + input spi_ss, + input spi_mosi, + input spi_sck, + // AVR ADC channel select + output [3:0] spi_channel, + // Serial connections + input avr_tx, // AVR Tx => FPGA Rx + output avr_rx, // AVR Rx => FPGA Tx + input avr_rx_busy, // AVR Rx buffer full + output[3:0] hdmi1_tmds, + output[3:0] hdmi1_tmdsb + ); + + wire rst = ~rst_n; // make reset active high + + wire hdmi_clk; + + reg[7:0] hdmired, hdmigreen, hdmiblue; + wire[10:0] hdmix; + wire[9:0] hdmiy; + + reg[7:0] frame_q, frame_d; + + clk_wiz_v3_6 clk_wiz( + .CLK_IN1(clk), + .CLK_OUT1(hdmi_clk) + ); + + hdmi_encoder hdmi( + .clk(hdmi_clk), + .rst(rst), + .tmds(hdmi1_tmds), + .tmdsb(hdmi1_tmdsb), + .x(hdmix), + .y(hdmiy), + .red(hdmired), + .green(hdmigreen), + .blue(hdmiblue) + ); + + wire [29:0] char_data [94:0]; + + assign char_data[0] = 30'h00000000; // + assign char_data[1] = 30'h1CE7380E; // ! + assign char_data[2] = 30'h14A00000; // " + assign char_data[3] = 30'hAFABEA; // # + assign char_data[4] = 30'h8FA38BE; // $ + assign char_data[5] = 30'h19D1173; // % + assign char_data[6] = 30'h1905324D; // & + assign char_data[7] = 30'h8400000; // ' + assign char_data[8] = 30'hCC63186; // ( + assign char_data[9] = 30'h186318CC; // ) + assign char_data[10] = 30'h4ABAA4; // * + assign char_data[11] = 30'h427C84; // + + assign char_data[12] = 30'h0x8C; // , + assign char_data[13] = 30'h3800; // - + assign char_data[14] = 30'hC; // . + assign char_data[15] = 30'hC663318; // / + assign char_data[16] = 30'h3FBDEF7F; // 0 + assign char_data[17] = 30'h3C6318DF; // 1 + assign char_data[18] = 30'h3E3FE31F; // 2 + assign char_data[19] = 30'h3E378C7F; // 3 + assign char_data[20] = 30'h37BF8C63; // 4 + assign char_data[21] = 30'h3F8F8C7F; // 5 + assign char_data[22] = 30'h3F8FEF7F; // 6 + assign char_data[23] = 30'h3E33318C; // 7 + assign char_data[24] = 30'h3FBFEF7F; // 8 + assign char_data[25] = 30'h3FBF8C7F; // 9 + assign char_data[26] = 30'hC00180; // : + assign char_data[27] = 30'hC00198; // ; + assign char_data[28] = 30'h666186; // < + assign char_data[29] = 30'h701C0; // = + assign char_data[30] = 30'hC30CCC; // > + assign char_data[31] = 30'h3C31B80C; // ? + assign char_data[32] = 30'h1D1BDE0F; // @ + assign char_data[33] = 30'h1DBDFF7B; // A + assign char_data[34] = 30'h3DBF6F7E; // B + assign char_data[35] = 30'h1DBC636E; // C + assign char_data[36] = 30'h3DBDEF7E; // D + assign char_data[37] = 30'h1F8F630F; // E + assign char_data[38] = 30'h1F8F6318; // F + assign char_data[39] = 30'h1F8C6F6F; // G + assign char_data[40] = 30'h37BFEF7B; // H + assign char_data[41] = 30'h3CC6319E; // I + assign char_data[42] = 30'h3E6318DC; // J + assign char_data[43] = 30'h37BE6F7B; // K + assign char_data[44] = 30'h318C631F; // L + assign char_data[45] = 30'h37FFEF7B; // M + assign char_data[46] = 30'h3DBDEF7B; // N + assign char_data[47] = 30'h1DBDEF6E; // O + assign char_data[48] = 30'h3DBDFB18; // P + assign char_data[49] = 30'h1DBDEFCF; // Q + assign char_data[50] = 30'h3DBDF37B; // R + assign char_data[51] = 30'h1F870C7E; // S + assign char_data[52] = 30'h3EC6318C; // T + assign char_data[53] = 30'h37BDEF6E; // U + assign char_data[54] = 30'h37BDEDC4; // V + assign char_data[55] = 30'h37BDFFFB; // W + assign char_data[56] = 30'h37B26F7B; // X + assign char_data[57] = 30'h37BF8C7E; // Y + assign char_data[58] = 30'h3E33331F; // X + assign char_data[59] = 30'h1CC6318E; // [ + assign char_data[60] = 30'h18C31863; // \ + assign char_data[61] = 30'h1C6318CE; // ] + assign char_data[62] = 30'h8A00000; // ^ + assign char_data[63] = 30'h1F; // _ + assign char_data[64] = 30'h10400000; // ` + assign char_data[65] = 30'h7EF7D; // a + assign char_data[66] = 30'h318F6F7F; // b + assign char_data[67] = 30'h7E30F; // c + assign char_data[68] = 30'h637EF6F; // d + assign char_data[69] = 30'h76F8F; // e + assign char_data[70] = 30'hEC67D8C; // f + assign char_data[71] = 30'h1FBDBC7E; // g + assign char_data[72] = 30'h318F6F7B; // h + assign char_data[73] = 30'h18063186; // i + assign char_data[74] = 30'hC6318DC; // j + assign char_data[75] = 30'h31BD735B; // k + assign char_data[76] = 30'h18C63186; // l + assign char_data[77] = 30'h57F7B; // m + assign char_data[78] = 30'hF6F7B; // n + assign char_data[79] = 30'h7EF7E; // o + assign char_data[80] = 30'h3DBDFB18; // p + assign char_data[81] = 30'h1FBDBC63; // q + assign char_data[82] = 30'h76F18; // r + assign char_data[83] = 30'h7F0FE; // s + assign char_data[84] = 30'h18CF3186; // t + assign char_data[85] = 30'hDEF6F; // u + assign char_data[86] = 30'hDED44; // v + assign char_data[87] = 30'hDEFEA; // w + assign char_data[88] = 30'hDBB7B; // x + assign char_data[89] = 30'h37BDBC6E; // y + assign char_data[90] = 30'hF999F; // z + assign char_data[91] = 30'h623086; // { + assign char_data[92] = 30'h421084; // | + assign char_data[93] = 30'h610C46; // } + assign char_data[94] = 30'hAA0000; // ~ + + reg[11:0] char_index_q, char_index_d; + + reg[10:0] charx; + reg[9:0] chary; + + localparam SCALE = 2; + + reg[7:0] tx_data; + reg new_tx_data; + wire tx_busy; + wire[7:0] rx_data; + wire new_rx_data; + + assign led[7:0] = rx_data; + + avr_interface #(.CLK_FREQ(75000000)) vr_interface ( + .clk(hdmi_clk), + .rst(rst), + .cclk(cclk), + .spi_miso(spi_miso), + .spi_mosi(spi_mose), + .spi_sck(spi_sck), + .spi_ss(spi_ss), + .spi_channel(spi_channel), + .tx(avr_rx), + .rx(avr_tx), + .channel(4'd15), + .new_sample(), + .sample(), + .sample_channel(), + .tx_data(tx_data), + .new_tx_data(new_tx_data), + .tx_busy(tx_busy), + .tx_block(avr_rx_busy), + .rx_data(rx_data), + .new_rx_data(new_rx_data) + ); + + reg [11:0] addr_q, addr_d; + reg[7:0] write_data; + reg write_enable; + wire[7:0] sram_read_data; + sram #(.SIZE(8), .DEPTH(3600)) sram( + .clk(hdmi_clk), + .read_address(char_index_q), + .write_address(addr_q), + .read_data(sram_read_data), + .write_data(write_data), + .write_en(write_enable) + ); + + always @(*) begin + hdmired = 1'h28; + hdmigreen = 1'h28; + hdmiblue = 1'h28; + + charx = (hdmix >> (SCALE-1)) % 8; + chary = (hdmiy >> (SCALE-1)) % 8; + + if (char_index_q < 3600 && charx > 0 && charx < 6 && chary > 1 && char_data[sram_read_data][29 - (charx - 1) - 5*(chary - 2)] == 1) begin + hdmired = 8'hEB; + hdmigreen = 8'hDB; + hdmiblue = 8'hB2; + end + + frame_d = frame_q; + char_index_d = ((hdmix >> (SCALE+2)) + 80*(hdmiy >> (SCALE+2))); + + if (hdmix == 1279 && hdmiy == 719) begin + frame_d = frame_q + 1'b1; + end + + new_tx_data = 1'b0; + write_enable = 1'b0; + write_data = 1'b0; + addr_d = addr_q; + if (new_rx_data) begin + new_tx_data = 1'b1; + tx_data = rx_data; + + if (rx_data == "\r") begin + addr_d = addr_q - (addr_q % 80); + end else if (rx_data == "\n") begin + addr_d = addr_q + 80; + end else if (rx_data == 8) begin + addr_d = addr_q - 1'b1; + end else begin + write_enable = 1'b1; + write_data = rx_data - 32; + addr_d = addr_q + 1'b1; + end + end + end + + always @(posedge hdmi_clk) begin + if (rst) begin + frame_q <= 1'b0; + char_index_q <= 1'b0; + addr_q <= 1'b0; + end else begin + addr_q <= addr_d; + frame_q <= frame_d; + char_index_q <= char_index_d; + end + end + +endmodule diff --git a/source/mojo_top.v.bak b/source/mojo_top.v.bak new file mode 100644 index 0000000..e850855 --- /dev/null +++ b/source/mojo_top.v.bak @@ -0,0 +1,178 @@ +module mojo_top( + // 50MHz clock input + input clk, + // Input from reset button (active low) + input rst_n, + // cclk input from AVR, high when AVR is ready + input cclk, + // Outputs to the 8 onboard LEDs + output[7:0]led, + // AVR SPI connections + output spi_miso, + input spi_ss, + input spi_mosi, + input spi_sck, + // AVR ADC channel select + output [3:0] spi_channel, + // Serial connections + input avr_tx, // AVR Tx => FPGA Rx + output avr_rx, // AVR Rx => FPGA Tx + input avr_rx_busy, // AVR Rx buffer full + output[3:0] hdmi1_tmds, + output[3:0] hdmi1_tmdsb + ); + + wire rst = ~rst_n; // make reset active high + + wire hdmi_clk; + + reg[7:0] hdmired, hdmigreen, hdmiblue; + wire[10:0] hdmix; + wire[9:0] hdmiy; + + reg[7:0] frame_q, frame_d; + + clk_wiz_v3_6 clk_wiz( + .CLK_IN1(clk), + .CLK_OUT1(hdmi_clk) + ); + + hdmi_encoder hdmi( + .clk(hdmi_clk), + .rst(rst), + .tmds(hdmi1_tmds), + .tmdsb(hdmi1_tmdsb), + .x(hdmix), + .y(hdmiy), + .red(hdmired), + .green(hdmigreen), + .blue(hdmiblue) + ); + + // these signals should be high-z when not used + assign spi_miso = 1'bz; + assign avr_rx = 1'bz; + assign spi_channel = 4'bzzzz; + + assign led[6:0] = 7'b1000000; + assign led[7] = char_index_q; + + wire [7:0] char_data [7:0][7:0]; + + assign char_data[0][0] = 8'b00000000; + assign char_data[0][1] = 8'b00000000; + assign char_data[0][2] = 8'b00111000; + assign char_data[0][3] = 8'b01101100; + assign char_data[0][4] = 8'b01101100; + assign char_data[0][5] = 8'b01111100; + assign char_data[0][6] = 8'b01101100; + assign char_data[0][7] = 8'b01101100; + + assign char_data[1][0] = 8'b00000000; + assign char_data[1][1] = 8'b00000000; + assign char_data[1][2] = 8'b01111000; + assign char_data[1][3] = 8'b01101100; + assign char_data[1][4] = 8'b01111000; + assign char_data[1][5] = 8'b01101100; + assign char_data[1][6] = 8'b01101100; + assign char_data[1][7] = 8'b01111000; + + assign char_data[2][0] = 8'b00000000; + assign char_data[2][1] = 8'b00000000; + assign char_data[2][2] = 8'b00111000; + assign char_data[2][3] = 8'b01101100; + assign char_data[2][4] = 8'b01100000; + assign char_data[2][5] = 8'b01100000; + assign char_data[2][6] = 8'b01101100; + assign char_data[2][7] = 8'b00111000; + + assign char_data[3][0] = 8'b00000000; + assign char_data[3][1] = 8'b00000000; + assign char_data[3][2] = 8'b01111000; + assign char_data[3][3] = 8'b01101100; + assign char_data[3][4] = 8'b01101100; + assign char_data[3][5] = 8'b01101100; + assign char_data[3][6] = 8'b01101100; + assign char_data[3][7] = 8'b01111000; + + assign char_data[4][0] = 8'b00000000; + assign char_data[4][1] = 8'b00000000; + assign char_data[4][2] = 8'b00111100; + assign char_data[4][3] = 8'b01100000; + assign char_data[4][4] = 8'b01111000; + assign char_data[4][5] = 8'b01100000; + assign char_data[4][6] = 8'b01100000; + assign char_data[4][7] = 8'b00111100; + + assign char_data[5][0] = 8'b00000000; + assign char_data[5][1] = 8'b00000000; + assign char_data[5][2] = 8'b00111100; + assign char_data[5][3] = 8'b01100000; + assign char_data[5][4] = 8'b01111000; + assign char_data[5][5] = 8'b01100000; + assign char_data[5][6] = 8'b01100000; + assign char_data[5][7] = 8'b01100000; + + assign char_data[6][0] = 8'b00000000; + assign char_data[6][1] = 8'b00000000; + assign char_data[6][2] = 8'b00111100; + assign char_data[6][3] = 8'b01100000; + assign char_data[6][4] = 8'b01100000; + assign char_data[6][5] = 8'b01101100; + assign char_data[6][6] = 8'b01101100; + assign char_data[6][7] = 8'b00111100; + + assign char_data[7][0] = 8'b00000000; + assign char_data[7][1] = 8'b00000000; + assign char_data[7][2] = 8'b01101100; + assign char_data[7][3] = 8'b01101100; + assign char_data[7][4] = 8'b01111100; + assign char_data[7][5] = 8'b01101100; + assign char_data[7][6] = 8'b01101100; + assign char_data[7][7] = 8'b01101100; + + //assign char_data[2][0] = 8'b00000000; + //assign char_data[2][1] = 8'b00000000; + //assign char_data[2][2] = 8'b00000000; + //assign char_data[2][3] = 8'b00000000; + //assign char_data[2][4] = 8'b00000000; + //assign char_data[2][5] = 8'b00000000; + //assign char_data[2][6] = 8'b00000000; + //assign char_data[2][7] = 8'b00000000; + + reg[2:0] char_index_q, char_index_d; + + always @(*) begin + //hdmired = hdmix[7:0] + frame_q; + //hdmigreen = hdmiy[7:0] + frame_q; + //hdmiblue = hdmix[7:0] ^ hdmiy[7:0]; + + hdmired = 1'h28; + hdmigreen = 1'h28; + hdmiblue = 1'h28; + + if (char_data[char_index_q][(hdmiy >> 1) % 8][7 - ((hdmix >> 1) % 8)] == 1) begin + hdmired = 8'hEB; + hdmigreen = 8'hDB; + hdmiblue = 8'hB2; + end + + frame_d = frame_q; + char_index_d = (hdmix >> 4) % 8; + + if (hdmix == 1279 && hdmiy == 719) begin + frame_d = frame_q + 1'b1; + end + end + + always @(posedge hdmi_clk) begin + if (rst) begin + frame_q <= 1'b0; + char_index_q <= 1'b0; + end else begin + frame_q <= frame_d; + char_index_q <= char_index_d; + end + end + +endmodule \ No newline at end of file diff --git a/source/sram.v b/source/sram.v new file mode 100644 index 0000000..d84a9f9 --- /dev/null +++ b/source/sram.v @@ -0,0 +1,22 @@ +module sram #( + parameter SIZE = 1, + parameter DEPTH = 1 + )( + input clk, + input [$clog2(DEPTH)-1:0] read_address, + input [$clog2(DEPTH)-1:0] write_address, + output reg [SIZE-1:0] read_data, + input [SIZE-1:0] write_data, + input write_en + ); + + reg [SIZE-1:0] ram [DEPTH-1:0]; + + always @(posedge clk) begin + read_data <= ram[read_address]; + + if (write_en) + ram[write_address] <= write_data; + end + +endmodule