Created Makefile to build entire project and moved microblaze code back into the repo

This commit is contained in:
2020-09-21 02:55:13 +02:00
parent afd4ba4fe4
commit 637dfa2c07
30 changed files with 7105 additions and 6 deletions

4
syn/.gitignore vendored
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# Ignore everything in this directory
*
# Except this file
!.gitignore

12
syn/main.prj Normal file
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verilog work "../ipcore_dir/microblaze_mcs.v"
verilog work "../ipcore_dir/hdmi_clk.v"
verilog work "../src/simple_dual_ram.v"
verilog work "../src/async_fifo.v"
verilog work "../src/tmds_encoder.v"
verilog work "../src/serdes_n_to_1.v"
verilog work "../src/fifo_2x_reducer.v"
verilog work "../src/dvi_encoder.v"
verilog work "../src/hdmi_encoder.v"
verilog work "../src/color_map.v"
verilog work "../src/char_map.v"
verilog work "../src/main.v"

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syn/main.ut Normal file
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-bd "/home/tim/Projects/z80/hdmi-mb/Graphics/Release/Graphics.elf" tag microblaze_mcs
-w
-g Binary:yes
-g Compress
-g CRC:Enable
-g Reset_on_err:No
-g ConfigRate:2
-g ProgPin:PullUp
-g TckPin:PullUp
-g TdiPin:PullUp
-g TdoPin:PullUp
-g TmsPin:PullUp
-g UnusedPin:PullDown
-g UserID:0xFFFFFFFF
-g ExtMasterCclk_en:No
-g SPI_buswidth:1
-g TIMER_CFG:0xFFFF
-g multipin_wakeup:No
-g StartUpClk:CClk
-g DONE_cycle:4
-g GTS_cycle:5
-g GWE_cycle:6
-g LCK_cycle:NoWait
-g Security:None
-g DonePipe:Yes
-g DriveDone:No
-g en_sw_gsr:No
-g drive_awake:No
-g sw_clk:Startupclk
-g sw_gwe_cycle:5
-g sw_gts_cycle:4

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syn/main.xst Normal file
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set -tmpdir "xst/projnav.tmp"
set -xsthdpdir "xst"
run
-ifn main.prj
-ofn main
-ofmt NGC
-p xc6slx9-2-tqg144
-top main
-opt_mode Speed
-opt_level 1
-power NO
-iuc NO
-keep_hierarchy No
-netlist_hierarchy As_Optimized
-rtlview Yes
-glob_opt AllClockNets
-read_cores YES
-sd {"../ipcore_dir" }
-write_timing_constraints NO
-cross_clock_analysis NO
-hierarchy_separator /
-bus_delimiter <>
-case Maintain
-slice_utilization_ratio 100
-bram_utilization_ratio 100
-dsp_utilization_ratio 100
-lc Auto
-reduce_control_sets Auto
-fsm_extract YES -fsm_encoding Auto
-safe_implementation No
-fsm_style LUT
-ram_extract Yes
-ram_style Auto
-rom_extract Yes
-shreg_extract YES
-rom_style Auto
-auto_bram_packing NO
-resource_sharing YES
-async_to_sync NO
-shreg_min_size 2
-use_dsp48 Auto
-iobuf YES
-max_fanout 100000
-bufg 16
-register_duplication YES
-register_balancing No
-optimize_primitives NO
-use_clock_enable Auto
-use_sync_set Auto
-use_sync_reset Auto
-iob Auto
-equivalent_register_removal YES
-slice_utilization_ratio_maxmargin 5