clk_wiz_v3_6

commit 90e280af07496f74eddcdd04e8c05018c3618b75 Author: Dreaded_X Date: Sat Sep 19 23:42:44 2020 +0200 First commit diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..3e2244c --- /dev/null +++ b/.gitignore @@ -0,0 +1,2 @@ +*.log +syn diff --git a/.project b/.project new file mode 100644 index 0000000..cc05a57 --- /dev/null +++ b/.project @@ -0,0 +1,45 @@ + + + Mojo-Demo + + + + + + net.sourceforge.veditor.simulateBuilder + + + net.sourceforge.veditor.simulateBuilder.00000000Default.CleanCommand + echo 'Clean' + + + net.sourceforge.veditor.simulateBuilder.00000000Default.buildOrder + 0 + + + net.sourceforge.veditor.simulateBuilder.00000000Default.command + echo 'No Build Configuration Specified' + + + net.sourceforge.veditor.simulateBuilder.00000000Default.enable + false + + + net.sourceforge.veditor.simulateBuilder.00000000Default.name + Default + + + net.sourceforge.veditor.simulateBuilder.00000000Default.parser + + + + net.sourceforge.veditor.simulateBuilder.00000000Default.workFolder + + + + + + + net.sourceforge.veditor.HdlNature + + diff --git a/LICENSE.txt b/LICENSE.txt new file mode 100644 index 0000000..680bd9f --- /dev/null +++ b/LICENSE.txt @@ -0,0 +1,21 @@ +The MIT License (MIT) + +Copyright (c) 2015 Embedded Micro + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. diff --git a/Mojo-Base.xise b/Mojo-Base.xise new file mode 100644 index 0000000..3ea6ee6 --- /dev/null +++ b/Mojo-Base.xise @@ -0,0 +1,551 @@ + + + +

+ + + + + + + + +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/async_fifo.v b/async_fifo.v new file mode 100644 index 0000000..0ae038a --- /dev/null +++ b/async_fifo.v @@ -0,0 +1,117 @@ +`timescale 1ns / 1ps +/* + This file was generated automatically by Alchitry Labs version 1.2.0. + Do not edit this file directly. Instead edit the original Lucid source. + This is a temporary file and any changes made to it will be destroyed. +*/ + +/* + Parameters: + SIZE = DATA_IN_SIZE + DEPTH = 16 +*/ +module async_fifo ( + input wclk, + input wrst, + input [29:0] din, + input wput, + output reg full, + input rclk, + input rrst, + output reg [29:0] dout, + input rget, + output reg empty + ); + + localparam SIZE = 5'h1e; + localparam DEPTH = 5'h10; + + + localparam ADDR_SIZE = 3'h4; + + reg [3:0] M_waddr_d, M_waddr_q = 1'h0; + reg [7:0] M_wsync_d, M_wsync_q = 1'h0; + + reg [3:0] M_raddr_d, M_raddr_q = 1'h0; + reg [7:0] M_rsync_d, M_rsync_q = 1'h0; + + wire [30-1:0] M_ram_read_data; + reg [1-1:0] M_ram_wclk; + reg [4-1:0] M_ram_waddr; + reg [30-1:0] M_ram_write_data; + reg [1-1:0] M_ram_write_en; + reg [1-1:0] M_ram_rclk; + reg [4-1:0] M_ram_raddr; + simple_dual_ram #(.SIZE(5'h1e), .DEPTH(5'h10)) ram ( + .wclk(M_ram_wclk), + .waddr(M_ram_waddr), + .write_data(M_ram_write_data), + .write_en(M_ram_write_en), + .rclk(M_ram_rclk), + .raddr(M_ram_raddr), + .read_data(M_ram_read_data) + ); + + reg [3:0] waddr_gray; + + reg [3:0] wnext_gray; + + reg [3:0] raddr_gray; + + reg wrdy; + reg rrdy; + + always @* begin + M_rsync_d = M_rsync_q; + M_wsync_d = M_wsync_q; + M_waddr_d = M_waddr_q; + M_raddr_d = M_raddr_q; + + M_ram_wclk = wclk; + M_ram_rclk = rclk; + M_ram_write_en = 1'h0; + waddr_gray = (M_waddr_q >> 1'h1) ^ M_waddr_q; + wnext_gray = ((M_waddr_q + 1'h1) >> 1'h1) ^ (M_waddr_q + 1'h1); + raddr_gray = (M_raddr_q >> 1'h1) ^ M_raddr_q; + M_rsync_d = {M_rsync_q[0+3-:4], waddr_gray}; + M_wsync_d = {M_wsync_q[0+3-:4], raddr_gray}; + wrdy = wnext_gray != M_wsync_q[4+3-:4]; + rrdy = raddr_gray != M_rsync_q[4+3-:4]; + full = !wrdy; + empty = !rrdy; + M_ram_waddr = M_waddr_q; + M_ram_raddr = M_raddr_q; + M_ram_write_data = din; + if (wput && wrdy) begin + M_waddr_d = M_waddr_q + 1'h1; + M_ram_write_en = 1'h1; + end + if (rget && rrdy) begin + M_raddr_d = M_raddr_q + 1'h1; + M_ram_raddr = M_raddr_q + 1'h1; + end + dout = M_ram_read_data; + end + + always @(posedge rclk) begin + if (rrst == 1'b1) begin + M_raddr_q <= 1'h0; + M_rsync_q <= 1'h0; + end else begin + M_raddr_q <= M_raddr_d; + M_rsync_q <= M_rsync_d; + end + end + + + always @(posedge wclk) begin + if (wrst == 1'b1) begin + M_waddr_q <= 1'h0; + M_wsync_q <= 1'h0; + end else begin + M_waddr_q <= M_waddr_d; + M_wsync_q <= M_wsync_d; + end + end + +endmodule \ No newline at end of file diff --git a/char_map.v b/char_map.v new file mode 100644 index 0000000..04ecf1e --- /dev/null +++ b/char_map.v @@ -0,0 +1,226 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 20:18:41 09/13/2020 +// Design Name: +// Module Name: char_map +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module char_map( + input clk, + input [7:0] index, + output reg [255:0] char +); + +wire [255:0] char_data [94:0]; + +always @(posedge clk) begin + char <= char_data[index]; +end + +assign char_data[ 0] = 256'h0000000000000000000000000000000000000000000000000000000000000000; // +assign char_data[ 1] = 256'h0000000007000f800f800f800f800f8007000700000000000700070007000000; // ! +assign char_data[ 2] = 256'h00000e380e380e380e3806300000000000000000000000000000000000000000; // " +assign char_data[ 3] = 256'h00000c300c300c307ffe7ffe0c300c300c300c307ffe7ffe0c300c300c300000; // # +assign char_data[ 4] = 256'h0000024002400ff81ff81a401a401ff00ff8025802581ff81ff0024002400000; // $ +assign char_data[ 5] = 256'h0000000000000e100e300e7000e001c0038007000e700c700870000000000000; // % +assign char_data[ 6] = 256'h000000000f001980198019800f000f080f9819f818f018e019f00f9800000000; // & +assign char_data[ 7] = 256'h000000000700070007000e000000000000000000000000000000000000000000; // ' +assign char_data[ 8] = 256'h0000000000f001c0038007000e000e000e000e000700038001c000f000000000; // ( +assign char_data[ 9] = 256'h000000000f00038001c000e0007000700070007000e001c003800f0000000000; // ) +assign char_data[10] = 256'h0000000001801188099007e007e03ffc3ffc07e007e009901188018000000000; // * +assign char_data[11] = 256'h00000000000001800180018001801ff81ff80180018001800180000000000000; // + +assign char_data[12] = 256'h000000000000000000000000000000000000000000000700070007000e000000; // , +assign char_data[13] = 256'h00000000000000000000000000001ff81ff80000000000000000000000000000; // - +assign char_data[14] = 256'h0000000000000000000000000000000000000000000007000700070000000000; // . +assign char_data[15] = 256'h0000000000020006000e001c0038007000e001c0038007000e001c0000000000; // / +assign char_data[16] = 256'h000000000ff01c381c781cf81cf81db81db81f381f381e381c380ff000000000; // 0 +assign char_data[17] = 256'h000000000180018003801f801f800380038003800380038003801ff000000000; // 1 +assign char_data[18] = 256'h000000000fe01c701c380038007000e001c0038007000e381c381ff800000000; // 2 +assign char_data[19] = 256'h000000000fe01c701c380038007003e003e0007000381c381c700fe000000000; // 3 +assign char_data[20] = 256'h0000000000e001e003e006e00ce018e01ff81ff800e000e000e003f800000000; // 4 +assign char_data[21] = 256'h000000001ff81c001c001c001c001fe01ff0007800381c381c700fe000000000; // 5 +assign char_data[22] = 256'h0000000003e007000e001c001c001ff01ff81c381c381c381c380ff000000000; // 6 +assign char_data[23] = 256'h000000001ffc1c1c1c1c1c1c001c0038007000e001c003800380038000000000; // 7 +assign char_data[24] = 256'h000000000ff01c381c381c381f3807e007e01cf81c381c381c380ff000000000; // 8 +assign char_data[25] = 256'h000000000ff01c381c381c381c381ff80ff800380038007000e007c000000000; // 9 +assign char_data[26] = 256'h0000000000000000038003800380000000000380038003800000000000000000; // : +assign char_data[27] = 256'h0000000000000000070007000700000000000700070007000e00000000000000; // ; +assign char_data[28] = 256'h0000007000e001c0038007000e001c001c000e000700038001c000e000700000; // < +assign char_data[29] = 256'h000000000000000000003ffc3ffc000000003ffc3ffc00000000000000000000; // = +assign char_data[30] = 256'h00001c000e000700038001c000e00070007000e001c0038007000e001c000000; // > +assign char_data[31] = 256'h000003c00ff01e7818380038007000e001c001c00000000001c001c001c00000; // ? +assign char_data[32] = 256'h000007f81c1c1c1c1c1c1c1c1cfc1cfc1cfc1cfc1c001c001c001c0007f80000; // @ +assign char_data[33] = 256'h0000000003c007e00e701c381c381c381c381ff81c381c381c381c3800000000; // A +assign char_data[34] = 256'h000000001ff00e380e380e380e380ff00ff00e380e380e380e381ff000000000; // B +assign char_data[35] = 256'h0000000007f00e381c381c001c001c001c001c001c001c380e3807f000000000; // C +assign char_data[36] = 256'h000000001fe00e700e380e380e380e380e380e380e380e380e701fe000000000; // D +assign char_data[37] = 256'h000000001ff80e180e080e000e300ff00ff00e300e000e080e181ff800000000; // E +assign char_data[38] = 256'h000000001ff80e180e080e000e300ff00ff00e300e000e000e001f0000000000; // F +assign char_data[39] = 256'h0000000007f00e381c381c381c001c001c001cf81c381c380e3807f800000000; // G +assign char_data[40] = 256'h000000001c701c701c701c701c701ff01ff01c701c701c701c701c7000000000; // H +assign char_data[41] = 256'h000000001fc007000700070007000700070007000700070007001fc000000000; // I +assign char_data[42] = 256'h0000000001fc0070007000700070007000701c701c701c701c700fe000000000; // J +assign char_data[43] = 256'h000000001e380e380e700ee00fc00f800f800fc00ee00e700e381e3800000000; // K +assign char_data[44] = 256'h000000001f000e000e000e000e000e000e000e000e080e180e381ff800000000; // L +assign char_data[45] = 256'h000000001c1c1e3c1f7c1ffc1ffc1ddc1c9c1c1c1c1c1c1c1c1c1c1c00000000; // M +assign char_data[46] = 256'h000000001c1c1c1c1e1c1f1c1f9c1ddc1cfc1c7c1c3c1c1c1c1c1c1c00000000; // N +assign char_data[47] = 256'h0000000003e007700e381c1c1c1c1c1c1c1c1c1c1c1c0e38077003e000000000; // O +assign char_data[48] = 256'h000000001ff00e380e380e380e380ff00ff00e000e000e000e001f0000000000; // P +assign char_data[49] = 256'h0000000003e00f780e381c1c1c1c1c1c1c1c1c7c1cfc0ff80ff8003800fc0000; // Q +assign char_data[50] = 256'h000000001ff00e380e380e380e380ff00ff00e700e380e380e381e3800000000; // R +assign char_data[51] = 256'h000000000ff01c381c381c381c000fe007f000381c381c381c380ff000000000; // S +assign char_data[52] = 256'h000000001ffc19cc11c401c001c001c001c001c001c001c001c007f000000000; // T +assign char_data[53] = 256'h000000001c701c701c701c701c701c701c701c701c701c701c700fe000000000; // U +assign char_data[54] = 256'h000000001c701c701c701c701c701c701c701c701c700ee007c0038000000000; // V +assign char_data[55] = 256'h000000001c1c1c1c1c1c1c1c1c1c1c9c1c9c1c9c0ff80f780770077000000000; // W +assign char_data[56] = 256'h000000001c701c701c700ee007c00380038007c00ee01c701c701c7000000000; // X +assign char_data[57] = 256'h000000001c701c701c701c701c700ee007c003800380038003800fe000000000; // Y +assign char_data[58] = 256'h000000001ff81c381838107000e001c0038007000e081c181c381ff800000000; // Z +assign char_data[59] = 256'h0000000007f0070007000700070007000700070007000700070007f000000000; // [ +assign char_data[60] = 256'h00000000100018001c000e000700038001c000e000700038001c000e00000000; // \ +assign char_data[61] = 256'h0000000007f0007000700070007000700070007000700070007007f000000000; // ] +assign char_data[62] = 256'h0000018003c007e00e701c380000000000000000000000000000000000000000; // ^ +assign char_data[63] = 256'h00000000000000000000000000000000000000000000000000000000ffffffff; // _ +assign char_data[64] = 256'h000000001c001c00070007000000000000000000000000000000000000000000; // ` +assign char_data[65] = 256'h0000000000000000000000000fe0007000700ff01c701c701c700f9800000000; // a +assign char_data[66] = 256'h000000001e000e000e000e000ff00e380e380e380e380e380e3819f000000000; // b +assign char_data[67] = 256'h0000000000000000000000000fe01c701c701c001c001c701c700fe000000000; // c +assign char_data[68] = 256'h0000000000f80070007000700ff01c701c701c701c701c701c700f9800000000; // d +assign char_data[69] = 256'h0000000000000000000000000fe01c701c701ff01c001c701c700fe000000000; // e +assign char_data[70] = 256'h0000000003e007700770070007001fe01fe007000700070007001fc000000000; // f +assign char_data[71] = 256'h0000000000000000000000000f981c701c701c701c700ff007f000701c700fe0; // g +assign char_data[72] = 256'h000000001e000e000e000e000ef00f380f380e380e380e380e381e3800000000; // h +assign char_data[73] = 256'h0000000001c001c001c000000fc001c001c001c001c001c001c00ff800000000; // i +assign char_data[74] = 256'h00000000007000700070000003f00070007000700070007000701c701c7007e0; // j +assign char_data[75] = 256'h000000001e000e000e000e000e380e700ee00fc00ee00e700e381e3800000000; // k +assign char_data[76] = 256'h000000000fc001c001c001c001c001c001c001c001c001c001c00ff800000000; // l +assign char_data[77] = 256'h0000000000000000000000001ff81c9c1c9c1c9c1c9c1c9c1c9c1c1c00000000; // m +assign char_data[78] = 256'h0000000000000000000000001fe01c701c701c701c701c701c701c7000000000; // n +assign char_data[79] = 256'h0000000000000000000000000fe01c701c701c701c701c701c700fe000000000; // o +assign char_data[80] = 256'h00000000000000000000000019f00e380e380e380e380e380ff00e000e001f00; // p +assign char_data[81] = 256'h0000000000000000000000001f3038e038e038e038e038e01fe000e000e001f0; // q +assign char_data[82] = 256'h0000000000000000000000001e700ff80f380e000e000e000e001f0000000000; // r +assign char_data[83] = 256'h0000000000000000000000000fe01c301c300f8003e0187018700fe000000000; // s +assign char_data[84] = 256'h0000000000000100030007001ff007000700070007000770077003e000000000; // t +assign char_data[85] = 256'h0000000000000000000000001c701c701c701c701c701c701c700f9800000000; // u +assign char_data[86] = 256'h0000000000000000000000001c701c701c701c701c700ee007c0038000000000; // v +assign char_data[87] = 256'h0000000000000000000000001c1c1c1c1c1c1c9c1c9c0f780770077000000000; // w +assign char_data[88] = 256'h0000000000000000000000001ce01ce00fc0078007800fc01ce01ce000000000; // x +assign char_data[89] = 256'h0000000000000000000000000e380e380e380e380e3807f003e000e001c01f80; // y +assign char_data[90] = 256'h0000000000000000000000001fe018e011c0038007000e201c601fe000000000; // z +assign char_data[91] = 256'h0000000001f803800380038007001c001c00070003800380038001f800000000; // { +assign char_data[92] = 256'h0000000003c003c003c003c003c00000000003c003c003c003c003c000000000; // | +assign char_data[93] = 256'h000000001f8001c001c001c000e00038003800e001c001c001c01f8000000000; // } +assign char_data[94] = 256'h000000001f1c3b9c39dc38f80000000000000000000000000000000000000000; // ~ + +//assign char_data[0] = 30'h00000000; // +//assign char_data[1] = 30'h1CE7380E; // ! +//assign char_data[2] = 30'h14A00000; // " +//assign char_data[3] = 30'hAFABEA; // # +//assign char_data[4] = 30'h8FA38BE; // $ +//assign char_data[5] = 30'h19D1173; // % +//assign char_data[6] = 30'h1905324D; // & +//assign char_data[7] = 30'h8400000; // ' +//assign char_data[8] = 30'hCC63186; // ( +//assign char_data[9] = 30'h186318CC; // ) +//assign char_data[10] = 30'h4ABAA4; // * +//assign char_data[11] = 30'h427C84; // + +//assign char_data[12] = 30'h0x8C; // , +//assign char_data[13] = 30'h3800; // - +//assign char_data[14] = 30'hC; // . +//assign char_data[15] = 30'hC663318; // / +//assign char_data[16] = 30'h3FBDEF7F; // 0 +//assign char_data[17] = 30'h3C6318DF; // 1 +//assign char_data[18] = 30'h3E3FE31F; // 2 +//assign char_data[19] = 30'h3E378C7F; // 3 +//assign char_data[20] = 30'h37BF8C63; // 4 +//assign char_data[21] = 30'h3F8F8C7F; // 5 +//assign char_data[22] = 30'h3F8FEF7F; // 6 +//assign char_data[23] = 30'h3E33318C; // 7 +//assign char_data[24] = 30'h3FBFEF7F; // 8 +//assign char_data[25] = 30'h3FBF8C7F; // 9 +//assign char_data[26] = 30'hC00180; // : +//assign char_data[27] = 30'hC00198; // ; +//assign char_data[28] = 30'h666186; // < +//assign char_data[29] = 30'h701C0; // = +//assign char_data[30] = 30'hC30CCC; // > +//assign char_data[31] = 30'h3C31B80C; // ? +//assign char_data[32] = 30'h1D1BDE0F; // @ +//assign char_data[33] = 30'h1DBDFF7B; // A +//assign char_data[34] = 30'h3DBF6F7E; // B +//assign char_data[35] = 30'h1DBC636E; // C +//assign char_data[36] = 30'h3DBDEF7E; // D +//assign char_data[37] = 30'h1F8F630F; // E +//assign char_data[38] = 30'h1F8F6318; // F +//assign char_data[39] = 30'h1F8C6F6F; // G +//assign char_data[40] = 30'h37BFEF7B; // H +//assign char_data[41] = 30'h3CC6319E; // I +//assign char_data[42] = 30'h3E6318DC; // J +//assign char_data[43] = 30'h37BE6F7B; // K +//assign char_data[44] = 30'h318C631F; // L +//assign char_data[45] = 30'h37FFEF7B; // M +//assign char_data[46] = 30'h3DBDEF7B; // N +//assign char_data[47] = 30'h1DBDEF6E; // O +//assign char_data[48] = 30'h3DBDFB18; // P +//assign char_data[49] = 30'h1DBDEFCF; // Q +//assign char_data[50] = 30'h3DBDF37B; // R +//assign char_data[51] = 30'h1F870C7E; // S +//assign char_data[52] = 30'h3EC6318C; // T +//assign char_data[53] = 30'h37BDEF6E; // U +//assign char_data[54] = 30'h37BDEDC4; // V +//assign char_data[55] = 30'h37BDFFFB; // W +//assign char_data[56] = 30'h37B26F7B; // X +//assign char_data[57] = 30'h37BF8C7E; // Y +//assign char_data[58] = 30'h3E33331F; // Z +//assign char_data[59] = 30'h1CC6318E; // [ +//assign char_data[60] = 30'h18C31863; // \ +//assign char_data[61] = 30'h1C6318CE; // ] +//assign char_data[62] = 30'h8A00000; // ^ +//assign char_data[63] = 30'h1F; // _ +//assign char_data[64] = 30'h10400000; // ` +//assign char_data[65] = 30'h7EF7D; // a +//assign char_data[66] = 30'h318F6F7F; // b +//assign char_data[67] = 30'h7E30F; // c +//assign char_data[68] = 30'h637EF6F; // d +//assign char_data[69] = 30'h76F8F; // e +//assign char_data[70] = 30'hEC67D8C; // f +//assign char_data[71] = 30'h1FBDBC7E; // g +//assign char_data[72] = 30'h318F6F7B; // h +//assign char_data[73] = 30'h18063186; // i +//assign char_data[74] = 30'hC6318DC; // j +//assign char_data[75] = 30'h31BD735B; // k +//assign char_data[76] = 30'h18C63186; // l +//assign char_data[77] = 30'h57F7B; // m +//assign char_data[78] = 30'hF6F7B; // n +//assign char_data[79] = 30'h7EF7E; // o +//assign char_data[80] = 30'h3DBDFB18; // p +//assign char_data[81] = 30'h1FBDBC63; // q +//assign char_data[82] = 30'h76F18; // r +//assign char_data[83] = 30'h7F0FE; // s +//assign char_data[84] = 30'h18CF3186; // t +//assign char_data[85] = 30'hDEF6F; // u +//assign char_data[86] = 30'hDED44; // v +//assign char_data[87] = 30'hDEFEA; // w +//assign char_data[88] = 30'hDBB7B; // x +//assign char_data[89] = 30'h37BDBC6E; // y +//assign char_data[90] = 30'hF999F; // z +//assign char_data[91] = 30'h623086; // { +//assign char_data[92] = 30'h421084; // | +//assign char_data[93] = 30'h610C46; // } +//assign char_data[94] = 30'hAA0000; // ~ + + +endmodule diff --git a/color_map.v b/color_map.v new file mode 100644 index 0000000..302dc6e --- /dev/null +++ b/color_map.v @@ -0,0 +1,55 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 22:16:37 09/18/2020 +// Design Name: +// Module Name: color_map +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module color_map( + input clk, + input[3:0] colorcode, + output reg[23:0] color +); + +wire [23:0] colors [15:0]; + +always @(posedge clk) begin + color <= colors[colorcode]; +end + +// VGA Colors +// Normal colors +assign colors[0] = 24'h000000; +assign colors[1] = 24'hAA0000; +assign colors[2] = 24'h00AA00; +assign colors[3] = 24'hAA5500; +assign colors[4] = 24'h0000AA; +assign colors[5] = 24'hAA00AA; +assign colors[6] = 24'h00AAAA; +assign colors[7] = 24'hAAAAAA; + +// Bright colors +assign colors[8] = 24'h555555; +assign colors[9] = 24'hFF5555; +assign colors[10] = 24'h55FF55; +assign colors[11] = 24'hFFFF55; +assign colors[12] = 24'h5555FF; +assign colors[13] = 24'hFF55FF; +assign colors[14] = 24'h55FFFF; +assign colors[15] = 24'hFFFFFF; + + +endmodule diff --git a/dvi_encoder.v b/dvi_encoder.v new file mode 100644 index 0000000..4ad5479 --- /dev/null +++ b/dvi_encoder.v @@ -0,0 +1,198 @@ +`timescale 1ns / 1ps +/* + This file was generated automatically by Alchitry Labs version 1.2.0. + Do not edit this file directly. Instead edit the original Lucid source. + This is a temporary file and any changes made to it will be destroyed. +*/ + +module dvi_encoder ( + input pclk, + input pclkx2, + input pclkx10, + input strobe, + input rst, + input [7:0] red, + input [7:0] green, + input [7:0] blue, + input hsync, + input vsync, + input de, + output reg [3:0] tmds, + output reg [3:0] tmdsb + ); + + + + reg M_toggle_d, M_toggle_q = 1'h0; + + wire [1-1:0] M_clkser_iob_out; + reg [5-1:0] M_clkser_data; + serdes_n_to_1 clkser ( + .ioclk(pclkx10), + .strobe(strobe), + .gclk(pclkx2), + .rst(rst), + .data(M_clkser_data), + .iob_out(M_clkser_iob_out) + ); + + wire [1-1:0] M_clkbuf_O; + wire [1-1:0] M_clkbuf_OB; + OBUFDS clkbuf ( + .I(M_clkser_iob_out), + .O(M_clkbuf_O), + .OB(M_clkbuf_OB) + ); + + wire [10-1:0] M_enc_blue_data_out; + reg [8-1:0] M_enc_blue_data_in; + reg [1-1:0] M_enc_blue_c0; + reg [1-1:0] M_enc_blue_c1; + reg [1-1:0] M_enc_blue_de; + tmds_encoder enc_blue ( + .clk(pclk), + .rst(rst), + .data_in(M_enc_blue_data_in), + .c0(M_enc_blue_c0), + .c1(M_enc_blue_c1), + .de(M_enc_blue_de), + .data_out(M_enc_blue_data_out) + ); + + wire [10-1:0] M_enc_green_data_out; + reg [8-1:0] M_enc_green_data_in; + reg [1-1:0] M_enc_green_c0; + reg [1-1:0] M_enc_green_c1; + reg [1-1:0] M_enc_green_de; + tmds_encoder enc_green ( + .clk(pclk), + .rst(rst), + .data_in(M_enc_green_data_in), + .c0(M_enc_green_c0), + .c1(M_enc_green_c1), + .de(M_enc_green_de), + .data_out(M_enc_green_data_out) + ); + + wire [10-1:0] M_enc_red_data_out; + reg [8-1:0] M_enc_red_data_in; + reg [1-1:0] M_enc_red_c0; + reg [1-1:0] M_enc_red_c1; + reg [1-1:0] M_enc_red_de; + tmds_encoder enc_red ( + .clk(pclk), + .rst(rst), + .data_in(M_enc_red_data_in), + .c0(M_enc_red_c0), + .c1(M_enc_red_c1), + .de(M_enc_red_de), + .data_out(M_enc_red_data_out) + ); + + wire [15-1:0] M_fifo_data_out; + reg [30-1:0] M_fifo_data_in; + fifo_2x_reducer fifo ( + .rst(rst), + .clk(pclk), + .clkx2(pclkx2), + .data_in(M_fifo_data_in), + .data_out(M_fifo_data_out) + ); + + wire [1-1:0] M_redser_iob_out; + reg [5-1:0] M_redser_data; + serdes_n_to_1 redser ( + .ioclk(pclkx10), + .strobe(strobe), + .gclk(pclkx2), + .rst(rst), + .data(M_redser_data), + .iob_out(M_redser_iob_out) + ); + + wire [1-1:0] M_greenser_iob_out; + reg [5-1:0] M_greenser_data; + serdes_n_to_1 greenser ( + .ioclk(pclkx10), + .strobe(strobe), + .gclk(pclkx2), + .rst(rst), + .data(M_greenser_data), + .iob_out(M_greenser_iob_out) + ); + + wire [1-1:0] M_blueser_iob_out; + reg [5-1:0] M_blueser_data; + serdes_n_to_1 blueser ( + .ioclk(pclkx10), + .strobe(strobe), + .gclk(pclkx2), + .rst(rst), + .data(M_blueser_data), + .iob_out(M_blueser_iob_out) + ); + + wire [1-1:0] M_redbuf_O; + wire [1-1:0] M_redbuf_OB; + OBUFDS redbuf ( + .I(M_redser_iob_out), + .O(M_redbuf_O), + .OB(M_redbuf_OB) + ); + + wire [1-1:0] M_greenbuf_O; + wire [1-1:0] M_greenbuf_OB; + OBUFDS greenbuf ( + .I(M_greenser_iob_out), + .O(M_greenbuf_O), + .OB(M_greenbuf_OB) + ); + + wire [1-1:0] M_bluebuf_O; + wire [1-1:0] M_bluebuf_OB; + OBUFDS bluebuf ( + .I(M_blueser_iob_out), + .O(M_bluebuf_O), + .OB(M_bluebuf_OB) + ); + + always @* begin + M_toggle_d = M_toggle_q; + + M_toggle_d = ~M_toggle_q; + M_clkser_data = {3'h5{~M_toggle_q}}; + tmds[3+0-:1] = M_clkbuf_O; + tmdsb[3+0-:1] = M_clkbuf_OB; + M_enc_red_data_in = red; + M_enc_green_data_in = green; + M_enc_blue_data_in = blue; + M_enc_red_c0 = hsync; + M_enc_red_c1 = vsync; + M_enc_red_de = de; + M_enc_green_c0 = hsync; + M_enc_green_c1 = vsync; + M_enc_green_de = de; + M_enc_blue_c0 = hsync; + M_enc_blue_c1 = vsync; + M_enc_blue_de = de; + M_fifo_data_in = {M_enc_red_data_out[5+4-:5], M_enc_green_data_out[5+4-:5], M_enc_blue_data_out[5+4-:5], M_enc_red_data_out[0+4-:5], M_enc_green_data_out[0+4-:5], M_enc_blue_data_out[0+4-:5]}; + M_redser_data = M_fifo_data_out[10+4-:5]; + M_greenser_data = M_fifo_data_out[5+4-:5]; + M_blueser_data = M_fifo_data_out[0+4-:5]; + tmds[0+0-:1] = M_bluebuf_O; + tmdsb[0+0-:1] = M_bluebuf_OB; + tmds[1+0-:1] = M_greenbuf_O; + tmdsb[1+0-:1] = M_greenbuf_OB; + tmds[2+0-:1] = M_redbuf_O; + tmdsb[2+0-:1] = M_redbuf_OB; + end + + always @(posedge pclkx2) begin + if (rst == 1'b1) begin + M_toggle_q <= 1'h0; + end else begin + M_toggle_q <= M_toggle_d; + end + end + +endmodule \ No newline at end of file diff --git a/fifo_2x_reducer.v b/fifo_2x_reducer.v new file mode 100644 index 0000000..928911c --- /dev/null +++ b/fifo_2x_reducer.v @@ -0,0 +1,68 @@ +`timescale 1ns / 1ps +/* + This file was generated automatically by Alchitry Labs version 1.2.0. + Do not edit this file directly. Instead edit the original Lucid source. + This is a temporary file and any changes made to it will be destroyed. +*/ + +/* + Parameters: + DATA_IN_SIZE = 30 +*/ +module fifo_2x_reducer ( + input rst, + input clk, + input clkx2, + input [29:0] data_in, + output reg [14:0] data_out + ); + + localparam DATA_IN_SIZE = 5'h1e; + + + wire [1-1:0] M_fifo_full; + wire [30-1:0] M_fifo_dout; + wire [1-1:0] M_fifo_empty; + reg [30-1:0] M_fifo_din; + reg [1-1:0] M_fifo_wput; + reg [1-1:0] M_fifo_rget; + async_fifo fifo ( + .wclk(clk), + .rclk(clkx2), + .wrst(rst), + .rrst(rst), + .din(M_fifo_din), + .wput(M_fifo_wput), + .rget(M_fifo_rget), + .full(M_fifo_full), + .dout(M_fifo_dout), + .empty(M_fifo_empty) + ); + + reg M_flag_d, M_flag_q = 1'h0; + reg [29:0] M_word_d, M_word_q = 1'h0; + + always @* begin + M_flag_d = M_flag_q; + M_word_d = M_word_q; + + M_fifo_din = data_in; + M_fifo_wput = 1'h1; + M_fifo_rget = 1'h0; + if (!M_flag_q && !M_fifo_empty) begin + M_fifo_rget = 1'h1; + M_flag_d = 1'h1; + M_word_d = M_fifo_dout; + end + if (M_flag_q) begin + M_flag_d = 1'h0; + end + data_out = !M_flag_q ? M_word_q[15+14-:15] : M_word_q[0+14-:15]; + end + + always @(posedge clkx2) begin + M_flag_q <= M_flag_d; + M_word_q <= M_word_d; + end + +endmodule \ No newline at end of file diff --git a/hdmi_encoder.v b/hdmi_encoder.v new file mode 100644 index 0000000..b4e9362 --- /dev/null +++ b/hdmi_encoder.v @@ -0,0 +1,146 @@ +`timescale 1ns / 1ps +/* + This file was generated automatically by Alchitry Labs version 1.2.0. + Do not edit this file directly. Instead edit the original Lucid source. + This is a temporary file and any changes made to it will be destroyed. +*/ + +/* + Parameters: + PCLK_DIV = 1 + Y_RES = HEIGHT + X_RES = WIDTH + Y_FRAME = HEIGHT+30 + X_FRAME = WIDTH+387 +*/ + +module hdmi_encoder #(parameter Y_RES = 720, parameter X_RES = 1280, parameter Y_FRAME = Y_RES+30, parameter X_FRAME = X_RES+387) ( + input clk, + input rst, + output reg pclk, + output reg [3:0] tmds, + output reg [3:0] tmdsb, + output reg active, + output reg [11:0] x, + output reg [10:0] y, + input [7:0] red, + input [7:0] green, + input [7:0] blue + ); + + localparam PCLK_DIV = 1'h1; + + + reg clkfbin; + + wire [1-1:0] M_pll_oserdes_CLKOUT0; + wire [1-1:0] M_pll_oserdes_CLKOUT1; + wire [1-1:0] M_pll_oserdes_CLKOUT2; + wire [1-1:0] M_pll_oserdes_CLKOUT3; + wire [1-1:0] M_pll_oserdes_CLKOUT4; + wire [1-1:0] M_pll_oserdes_CLKOUT5; + wire [1-1:0] M_pll_oserdes_CLKFBOUT; + wire [1-1:0] M_pll_oserdes_LOCKED; + PLL_BASE #(.CLKIN_PERIOD(10), .CLKFBOUT_MULT(10), .CLKOUT0_DIVIDE(1), .CLKOUT1_DIVIDE(10), .CLKOUT2_DIVIDE(5), .COMPENSATION("SOURCE_SYNCHRONOUS")) pll_oserdes ( + .CLKFBIN(clkfbin), + .CLKIN(clk), + .RST(1'h0), + .CLKOUT0(M_pll_oserdes_CLKOUT0), + .CLKOUT1(M_pll_oserdes_CLKOUT1), + .CLKOUT2(M_pll_oserdes_CLKOUT2), + .CLKOUT3(M_pll_oserdes_CLKOUT3), + .CLKOUT4(M_pll_oserdes_CLKOUT4), + .CLKOUT5(M_pll_oserdes_CLKOUT5), + .CLKFBOUT(M_pll_oserdes_CLKFBOUT), + .LOCKED(M_pll_oserdes_LOCKED) + ); + + wire [1-1:0] M_clkfb_buf_O; + BUFG clkfb_buf ( + .I(M_pll_oserdes_CLKFBOUT), + .O(M_clkfb_buf_O) + ); + + always @* begin + clkfbin = M_clkfb_buf_O; + end + + wire [1-1:0] M_pclkx2_buf_O; + BUFG pclkx2_buf ( + .I(M_pll_oserdes_CLKOUT2), + .O(M_pclkx2_buf_O) + ); + + wire [1-1:0] M_pclk_buf_O; + BUFG pclk_buf ( + .I(M_pll_oserdes_CLKOUT1), + .O(M_pclk_buf_O) + ); + + wire [1-1:0] M_ioclk_buf_IOCLK; + wire [1-1:0] M_ioclk_buf_SERDESSTROBE; + wire [1-1:0] M_ioclk_buf_LOCK; + BUFPLL #(.DIVIDE(5)) ioclk_buf ( + .PLLIN(M_pll_oserdes_CLKOUT0), + .GCLK(M_pclkx2_buf_O), + .LOCKED(M_pll_oserdes_LOCKED), + .IOCLK(M_ioclk_buf_IOCLK), + .SERDESSTROBE(M_ioclk_buf_SERDESSTROBE), + .LOCK(M_ioclk_buf_LOCK) + ); + + reg [11:0] M_ctrX_d, M_ctrX_q = 1'h0; + reg [10:0] M_ctrY_d, M_ctrY_q = 1'h0; + + reg hSync; + reg vSync; + reg drawArea; + + wire [4-1:0] M_dvi_tmds; + wire [4-1:0] M_dvi_tmdsb; + dvi_encoder dvi ( + .pclk(M_pclk_buf_O), + .pclkx2(M_pclkx2_buf_O), + .pclkx10(M_ioclk_buf_IOCLK), + .strobe(M_ioclk_buf_SERDESSTROBE), + .rst(~M_ioclk_buf_LOCK), + .blue(blue), + .green(green), + .red(red), + .hsync(hSync), + .vsync(vSync), + .de(drawArea), + .tmds(M_dvi_tmds), + .tmdsb(M_dvi_tmdsb) + ); + + always @* begin + M_ctrY_d = M_ctrY_q; + M_ctrX_d = M_ctrX_q; + + M_ctrX_d = (M_ctrX_q == 13'h0682) ? 1'h0 : M_ctrX_q + 1'h1; + if (M_ctrX_q == 13'h0682) begin + M_ctrY_d = (M_ctrY_q == 12'h2ed) ? 1'h0 : M_ctrY_q + 1'h1; + end + pclk = M_pclk_buf_O; + hSync = (M_ctrX_q >= 12'h50a) && (M_ctrX_q < 12'h514); + vSync = (M_ctrY_q >= 11'h2da) && (M_ctrY_q < 11'h2dc); + drawArea = (M_ctrX_q < 11'h500) && (M_ctrY_q < 10'h2d0); + active = drawArea; + x = M_ctrX_q; + y = M_ctrY_q; + tmds = M_dvi_tmds; + tmdsb = M_dvi_tmdsb; + end + + always @(posedge M_pclk_buf_O) begin + if (rst == 1'b1) begin + M_ctrX_q <= 1'h0; + M_ctrY_q <= 1'h0; + end else begin + M_ctrX_q <= M_ctrX_d; + M_ctrY_q <= M_ctrY_d; + end + end + +endmodule \ No newline at end of file diff --git a/ipcore_dir/.gitignore b/ipcore_dir/.gitignore new file mode 100644 index 0000000..e69de29 diff --git a/ipcore_dir/_xmsgs/cg.xmsgs b/ipcore_dir/_xmsgs/cg.xmsgs new file mode 100644 index 0000000..099f344 --- /dev/null +++ b/ipcore_dir/_xmsgs/cg.xmsgs @@ -0,0 +1,78 @@ + + + +Generating IP... + + +Verilog simulation file type 'Behavioral' is not valid for this core. Overriding with simulation file type 'Structural'. + + +A core named 'microblaze_mcs' already exists in the project. Output products for this core may be overwritten. + + +Verilog simulation file type 'Behavioral' is not valid for this core. Overriding with simulation file type 'Structural'. + + +A core named 'microblaze_mcs' already exists in the project. Output products for this core may be overwritten. + + +Pre-processing HDL files for 'microblaze_mcs'... + + +Running microblaze_mcs_gen_script.tcl + + +Please source the "microblaze_mcs_setup.tcl" script in the Tcl Console to complete MicroBlaze MCS core generation + + +Verilog simulation file type 'Behavioral' is not valid for this core. Overriding with simulation file type 'Structural'. + + +Verilog simulation file type 'Behavioral' is not valid for this core. Overriding with simulation file type 'Structural'. + + +Running microblaze_mcs_sim_script.tcl + + +C_MICROBLAZE_INSTANCE = microblaze_mcs + + +Netlist filename = ./_cg/microblaze_mcs.v + + +Setting INIT_FILE = "microblaze_mcs.lmb_bram_7.mem" for BRAM 7 + + +Setting INIT_FILE = "microblaze_mcs.lmb_bram_6.mem" for BRAM 6 + + +Setting INIT_FILE = "microblaze_mcs.lmb_bram_5.mem" for BRAM 5 + + +Setting INIT_FILE = "microblaze_mcs.lmb_bram_4.mem" for BRAM 4 + + +Setting INIT_FILE = "microblaze_mcs.lmb_bram_3.mem" for BRAM 3 + + +Setting INIT_FILE = "microblaze_mcs.lmb_bram_2.mem" for BRAM 2 + + +Setting INIT_FILE = "microblaze_mcs.lmb_bram_1.mem" for BRAM 1 + + +Setting INIT_FILE = "microblaze_mcs.lmb_bram_0.mem" for BRAM 0 + + +Finished generation of ASY schematic symbol. + + +Finished FLIST file generation. + + + + diff --git a/ipcore_dir/_xmsgs/pn_parser.xmsgs b/ipcore_dir/_xmsgs/pn_parser.xmsgs new file mode 100644 index 0000000..8d59638 --- /dev/null +++ b/ipcore_dir/_xmsgs/pn_parser.xmsgs @@ -0,0 +1,15 @@ + + + + + + + + + + +Analyzing Verilog file "/home/tim/Projects/z80/hdmi/ipcore_dir/hdmi_clk.v" into library work + + + + diff --git a/ipcore_dir/coregen.cgc b/ipcore_dir/coregen.cgc new file mode 100644 index 0000000..b0f9ef0 --- /dev/null +++ b/ipcore_dir/coregen.cgc @@ -0,0 +1,426 @@ + + + xilinx.com + project + coregen + 1.0 + + + hdmi_clk + + + hdmi_clk + true + false + false + false + false + No_Jitter + false + false + 50 + Units_MHz + Units_UI + REL_PRIMARY + 100.000 + UI + 0.010 + 0.010 + 0.010 + 0.010 + 200.0 + 100.0 + true + false + false + false + false + false + 2 + false + false + false + false + false + false + false + CLK_IN1 + CLK_OUT1 + CLK_OUT2 + CLK_OUT3 + CLK_OUT4 + CLK_OUT5 + CLK_OUT6 + CLK_OUT7 + DADDR + DCLK + DRDY + DWE + DIN + DOUT + DEN + PSCLK + PSEN + PSINCDEC + PSDONE + 75 + 0.000 + 50.000 + 150 + 0.000 + 50.000 + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 50.000 + false + false + Single_ended_clock_capable_pin + false + CLK_IN2 + Single_ended_clock_capable_pin + BUFG + BUFG + BUFG + BUFG + BUFG + BUFG + BUFG + FDBK_AUTO + SINGLE + CLKFB_IN + CLKFB_IN_P + CLKFB_IN_N + CLKFB_OUT + CLKFB_OUT_P + CLKFB_OUT_N + lin64 + empty + false + DONE + false + false + false + false + false + false + false + RESET + LOCKED + POWER_DOWN + CLK_VALID + STATUS + CLK_IN_SEL + INPUT_CLK_STOPPED + CLKFB_STOPPED + false + None + 1 + OPTIMIZED + 4.000 + 0.000 + false + 10.000 + 10.000 + false + false + ZHOLD + 0.010 + 0.010 + false + 4.000 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + false + None + 2.0 + 2 + 3 + false + 20.000 + NONE + SYSTEM_SYNCHRONOUS + 0 + NONE + false + CLKFX + CLK0 + CLK0 + CLK0 + CLK0 + CLK0 + false + None + 1 + 4 + 2 + 0.000 + false + 10.000 + NONE + CLKFX + CLKFX + CLKFX + false + None + OPTIMIZED + 9 + 0.000 + CLKFBOUT + 1 + 20.000 + INTERNAL + 0.010 + 6 + 0.500 + 0.000 + 3 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + NONE + AUTO + PLL_BASE + MMCM + CENTER_HIGH + 250 + hdmi_clk + + + + + coregen + ./ + ./tmp/ + ./tmp/_cg/ + + + xc6slx9 + spartan6 + tqg144 + -2 + + + BusFormatAngleBracketNotRipped + Verilog + true + Other + false + false + false + Ngc + false + + + Behavioral + Verilog + false + + + 2012-05-10+12:44 + + + + + + microblaze_mcs + + + USER2 + microblaze_mcs_v1_4 + mcs_0 + 150 + false + false + 16KB + false + false + false + 9600 + false + 8 + false + Even + false + false + false + false + 6216 + false + false + 6216 + false + false + 6216 + false + false + 6216 + false + false + 32 + true + None + false + false + 32 + true + None + false + false + 32 + true + None + false + false + 32 + true + None + false + true + 8 + 0x00000000 + true + 16 + 0x00000000 + true + 2 + 0x00000000 + true + 6 + 0x00000000 + true + 8 + None + true + 1 + Falling_Edge + true + 2 + None + false + 32 + None + false + 1 + 0x0000 + 0xFFFF + microblaze_mcs + + + + + coregen + ./ + ./tmp/ + ./tmp/_cg/ + + + xc6slx9 + spartan6 + tqg144 + -2 + + + BusFormatAngleBracketNotRipped + Verilog + true + Other + false + false + false + Ngc + false + + + Behavioral + Verilog + false + + + 2012-11-21+08:11 + + + + + + + + + coregen + ./ + ./tmp/ + ./tmp/_cg/ + + + xc6slx9 + spartan6 + tqg144 + -2 + + + BusFormatAngleBracketNotRipped + Verilog + true + Other + false + false + false + Ngc + false + + + Behavioral + Verilog + false + + + + + diff --git a/ipcore_dir/coregen.cgp b/ipcore_dir/coregen.cgp new file mode 100644 index 0000000..d58f8d7 --- /dev/null +++ b/ipcore_dir/coregen.cgp @@ -0,0 +1,9 @@ +SET busformat = BusFormatAngleBracketNotRipped +SET designentry = Verilog +SET device = xc6slx9 +SET devicefamily = spartan6 +SET flowvendor = Other +SET package = tqg144 +SET speedgrade = -2 +SET verilogsim = true +SET vhdlsim = false diff --git a/ipcore_dir/create_clk_wiz.tcl b/ipcore_dir/create_clk_wiz.tcl new file mode 100644 index 0000000..43ce562 --- /dev/null +++ b/ipcore_dir/create_clk_wiz.tcl @@ -0,0 +1,37 @@ +## +## Core Generator Run Script, generator for Project Navigator create command +## + +proc findRtfPath { relativePath } { + set xilenv "" + if { [info exists ::env(XILINX) ] } { + if { [info exists ::env(MYXILINX)] } { + set xilenv [join [list $::env(MYXILINX) $::env(XILINX)] $::xilinx::path_sep ] + } else { + set xilenv $::env(XILINX) + } + } + foreach path [ split $xilenv $::xilinx::path_sep ] { + set fullPath [ file join $path $relativePath ] + if { [ file exists $fullPath ] } { + return $fullPath + } + } + return "" +} + +source [ findRtfPath "data/projnav/scripts/dpm_cgUtils.tcl" ] + +set result [ run_cg_create "xilinx.com:ip:clk_wiz:3.6" "clk_wiz" "Clocking Wizard" "Clocking Wizard (xilinx.com:ip:clk_wiz:3.6) generated by Project Navigator" xc6slx9-2tqg144 Verilog ] + +if { $result == 0 } { + puts "Core Generator create command completed successfully." +} elseif { $result == 1 } { + puts "Core Generator create command failed." +} elseif { $result == 3 || $result == 4 } { + # convert 'version check' result to real return range, bypassing any messages. + set result [ expr $result - 3 ] +} else { + puts "Core Generator create cancelled." +} +exit $result diff --git a/ipcore_dir/create_hdmi_clk.tcl b/ipcore_dir/create_hdmi_clk.tcl new file mode 100644 index 0000000..c49d9f9 --- /dev/null +++ b/ipcore_dir/create_hdmi_clk.tcl @@ -0,0 +1,37 @@ +## +## Core Generator Run Script, generator for Project Navigator create command +## + +proc findRtfPath { relativePath } { + set xilenv "" + if { [info exists ::env(XILINX) ] } { + if { [info exists ::env(MYXILINX)] } { + set xilenv [join [list $::env(MYXILINX) $::env(XILINX)] $::xilinx::path_sep ] + } else { + set xilenv $::env(XILINX) + } + } + foreach path [ split $xilenv $::xilinx::path_sep ] { + set fullPath [ file join $path $relativePath ] + if { [ file exists $fullPath ] } { + return $fullPath + } + } + return "" +} + +source [ findRtfPath "data/projnav/scripts/dpm_cgUtils.tcl" ] + +set result [ run_cg_create "xilinx.com:ip:clk_wiz:3.6" "hdmi_clk" "Clocking Wizard" "Clocking Wizard (xilinx.com:ip:clk_wiz:3.6) generated by Project Navigator" xc6slx9-2tqg144 Verilog ] + +if { $result == 0 } { + puts "Core Generator create command completed successfully." +} elseif { $result == 1 } { + puts "Core Generator create command failed." +} elseif { $result == 3 || $result == 4 } { + # convert 'version check' result to real return range, bypassing any messages. + set result [ expr $result - 3 ] +} else { + puts "Core Generator create cancelled." +} +exit $result diff --git a/ipcore_dir/create_microblaze_mcs.tcl b/ipcore_dir/create_microblaze_mcs.tcl new file mode 100644 index 0000000..05e4463 --- /dev/null +++ b/ipcore_dir/create_microblaze_mcs.tcl @@ -0,0 +1,37 @@ +## +## Core Generator Run Script, generator for Project Navigator create command +## + +proc findRtfPath { relativePath } { + set xilenv "" + if { [info exists ::env(XILINX) ] } { + if { [info exists ::env(MYXILINX)] } { + set xilenv [join [list $::env(MYXILINX) $::env(XILINX)] $::xilinx::path_sep ] + } else { + set xilenv $::env(XILINX) + } + } + foreach path [ split $xilenv $::xilinx::path_sep ] { + set fullPath [ file join $path $relativePath ] + if { [ file exists $fullPath ] } { + return $fullPath + } + } + return "" +} + +source [ findRtfPath "data/projnav/scripts/dpm_cgUtils.tcl" ] + +set result [ run_cg_create "xilinx.com:ip:microblaze_mcs:1.4" "microblaze_mcs" "MicroBlaze MCS" "MicroBlaze MCS (xilinx.com:ip:microblaze_mcs:1.4) generated by Project Navigator" xc6slx9-2tqg144 Verilog ] + +if { $result == 0 } { + puts "Core Generator create command completed successfully." +} elseif { $result == 1 } { + puts "Core Generator create command failed." +} elseif { $result == 3 || $result == 4 } { + # convert 'version check' result to real return range, bypassing any messages. + set result [ expr $result - 3 ] +} else { + puts "Core Generator create cancelled." +} +exit $result diff --git a/ipcore_dir/edit_hdmi_clk.tcl b/ipcore_dir/edit_hdmi_clk.tcl new file mode 100644 index 0000000..1063920 --- /dev/null +++ b/ipcore_dir/edit_hdmi_clk.tcl @@ -0,0 +1,37 @@ +## +## Core Generator Run Script, generator for Project Navigator edit command +## + +proc findRtfPath { relativePath } { + set xilenv "" + if { [info exists ::env(XILINX) ] } { + if { [info exists ::env(MYXILINX)] } { + set xilenv [join [list $::env(MYXILINX) $::env(XILINX)] $::xilinx::path_sep ] + } else { + set xilenv $::env(XILINX) + } + } + foreach path [ split $xilenv $::xilinx::path_sep ] { + set fullPath [ file join $path $relativePath ] + if { [ file exists $fullPath ] } { + return $fullPath + } + } + return "" +} + +source [ findRtfPath "data/projnav/scripts/dpm_cgUtils.tcl" ] + +set result [ run_cg_edit "hdmi_clk" xc6slx9-2tqg144 Verilog ] + +if { $result == 0 } { + puts "Core Generator edit command completed successfully." +} elseif { $result == 1 } { + puts "Core Generator edit command failed." +} elseif { $result == 3 || $result == 4 } { + # convert 'version check' result to real return range, bypassing any messages. + set result [ expr $result - 3 ] +} else { + puts "Core Generator edit cancelled." +} +exit $result diff --git a/ipcore_dir/edit_microblaze_mcs.tcl b/ipcore_dir/edit_microblaze_mcs.tcl new file mode 100644 index 0000000..9a441b7 --- /dev/null +++ b/ipcore_dir/edit_microblaze_mcs.tcl @@ -0,0 +1,37 @@ +## +## Core Generator Run Script, generator for Project Navigator edit command +## + +proc findRtfPath { relativePath } { + set xilenv "" + if { [info exists ::env(XILINX) ] } { + if { [info exists ::env(MYXILINX)] } { + set xilenv [join [list $::env(MYXILINX) $::env(XILINX)] $::xilinx::path_sep ] + } else { + set xilenv $::env(XILINX) + } + } + foreach path [ split $xilenv $::xilinx::path_sep ] { + set fullPath [ file join $path $relativePath ] + if { [ file exists $fullPath ] } { + return $fullPath + } + } + return "" +} + +source [ findRtfPath "data/projnav/scripts/dpm_cgUtils.tcl" ] + +set result [ run_cg_edit "microblaze_mcs" xc6slx9-2tqg144 Verilog ] + +if { $result == 0 } { + puts "Core Generator edit command completed successfully." +} elseif { $result == 1 } { + puts "Core Generator edit command failed." +} elseif { $result == 3 || $result == 4 } { + # convert 'version check' result to real return range, bypassing any messages. + set result [ expr $result - 3 ] +} else { + puts "Core Generator edit cancelled." +} +exit $result diff --git a/ipcore_dir/hdmi_clk.asy b/ipcore_dir/hdmi_clk.asy new file mode 100644 index 0000000..62ce00e --- /dev/null +++ b/ipcore_dir/hdmi_clk.asy @@ -0,0 +1,17 @@ +Version 4 +SymbolType BLOCK +TEXT 32 32 LEFT 4 hdmi_clk +RECTANGLE Normal 32 32 576 1088 +LINE Normal 0 80 32 80 +PIN 0 80 LEFT 36 +PINATTR PinName clk_in1 +PINATTR Polarity IN +LINE Normal 608 80 576 80 +PIN 608 80 RIGHT 36 +PINATTR PinName clk_out1 +PINATTR Polarity OUT +LINE Normal 608 176 576 176 +PIN 608 176 RIGHT 36 +PINATTR PinName clk_out2 +PINATTR Polarity OUT + diff --git a/ipcore_dir/hdmi_clk.gise b/ipcore_dir/hdmi_clk.gise new file mode 100644 index 0000000..b5fff2c --- /dev/null +++ b/ipcore_dir/hdmi_clk.gise @@ -0,0 +1,52 @@ + + + + + + + + + + + + + + + + + + + + 11.1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ipcore_dir/hdmi_clk.ncf b/ipcore_dir/hdmi_clk.ncf new file mode 100644 index 0000000..d7c4fad --- /dev/null +++ b/ipcore_dir/hdmi_clk.ncf @@ -0,0 +1,59 @@ +# file: hdmi_clk.ucf +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +# Input clock periods. These duplicate the values entered for the +# input clocks. You can use these to time your system +#---------------------------------------------------------------- +NET "CLK_IN1" TNM_NET = "CLK_IN1"; +TIMESPEC "TS_CLK_IN1" = PERIOD "CLK_IN1" 20.000 ns HIGH 50% INPUT_JITTER 200.0ps; + + +# FALSE PATH constraints + + diff --git a/ipcore_dir/hdmi_clk.sym b/ipcore_dir/hdmi_clk.sym new file mode 100644 index 0000000..5ea4f73 --- /dev/null +++ b/ipcore_dir/hdmi_clk.sym @@ -0,0 +1,18 @@ + + + BLOCK + 2020-9-17T15:18:55 + + + + + hdmi_clk + + + + + + + + + diff --git a/ipcore_dir/hdmi_clk.ucf b/ipcore_dir/hdmi_clk.ucf new file mode 100755 index 0000000..8e2a3a8 --- /dev/null +++ b/ipcore_dir/hdmi_clk.ucf @@ -0,0 +1,58 @@ +# file: hdmi_clk.ucf +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +# Input clock periods. These duplicate the values entered for the +# input clocks. You can use these to time your system +#---------------------------------------------------------------- +NET "CLK_IN1" TNM_NET = "CLK_IN1"; +TIMESPEC "TS_CLK_IN1" = PERIOD "CLK_IN1" 20.000 ns HIGH 50% INPUT_JITTER 200.0ps; + + +# FALSE PATH constraints + diff --git a/ipcore_dir/hdmi_clk.v b/ipcore_dir/hdmi_clk.v new file mode 100755 index 0000000..bfcc7fc --- /dev/null +++ b/ipcore_dir/hdmi_clk.v @@ -0,0 +1,143 @@ +// file: hdmi_clk.v +// +// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//---------------------------------------------------------------------------- +// User entered comments +//---------------------------------------------------------------------------- +// None +// +//---------------------------------------------------------------------------- +// "Output Output Phase Duty Pk-to-Pk Phase" +// "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)" +//---------------------------------------------------------------------------- +// CLK_OUT1____75.000______0.000______50.0______248.869____240.171 +// CLK_OUT2___150.000______0.000______50.0______216.897____240.171 +// +//---------------------------------------------------------------------------- +// "Input Clock Freq (MHz) Input Jitter (UI)" +//---------------------------------------------------------------------------- +// __primary______________50____________0.010 + +`timescale 1ps/1ps + +(* CORE_GENERATION_INFO = "hdmi_clk,clk_wiz_v3_6,{component_name=hdmi_clk,use_phase_alignment=false,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=PLL_BASE,num_out_clk=2,clkin1_period=20.000,clkin2_period=20.000,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}" *) +module hdmi_clk + (// Clock in ports + input CLK_IN1, + // Clock out ports + output CLK_OUT1, + output CLK_OUT2 + ); + + // Input buffering + //------------------------------------ + IBUFG clkin1_buf + (.O (clkin1), + .I (CLK_IN1)); + + + // Clocking primitive + //------------------------------------ + // Instantiation of the PLL primitive + // * Unused inputs are tied off + // * Unused outputs are labeled unused + wire [15:0] do_unused; + wire drdy_unused; + wire locked_unused; + wire clkfbout; + wire clkout2_unused; + wire clkout3_unused; + wire clkout4_unused; + wire clkout5_unused; + + PLL_BASE + #(.BANDWIDTH ("OPTIMIZED"), + .CLK_FEEDBACK ("CLKFBOUT"), + .COMPENSATION ("INTERNAL"), + .DIVCLK_DIVIDE (1), + .CLKFBOUT_MULT (9), + .CLKFBOUT_PHASE (0.000), + .CLKOUT0_DIVIDE (6), + .CLKOUT0_PHASE (0.000), + .CLKOUT0_DUTY_CYCLE (0.500), + .CLKOUT1_DIVIDE (3), + .CLKOUT1_PHASE (0.000), + .CLKOUT1_DUTY_CYCLE (0.500), + .CLKIN_PERIOD (20.000), + .REF_JITTER (0.010)) + pll_base_inst + // Output clocks + (.CLKFBOUT (clkfbout), + .CLKOUT0 (clkout0), + .CLKOUT1 (clkout1), + .CLKOUT2 (clkout2_unused), + .CLKOUT3 (clkout3_unused), + .CLKOUT4 (clkout4_unused), + .CLKOUT5 (clkout5_unused), + .LOCKED (locked_unused), + .RST (1'b0), + // Input clock control + .CLKFBIN (clkfbout), + .CLKIN (clkin1)); + + + // Output buffering + //----------------------------------- + + BUFG clkout1_buf + (.O (CLK_OUT1), + .I (clkout0)); + + + BUFG clkout2_buf + (.O (CLK_OUT2), + .I (clkout1)); + + + +endmodule diff --git a/ipcore_dir/hdmi_clk.veo b/ipcore_dir/hdmi_clk.veo new file mode 100755 index 0000000..b33065b --- /dev/null +++ b/ipcore_dir/hdmi_clk.veo @@ -0,0 +1,77 @@ +// +// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//---------------------------------------------------------------------------- +// User entered comments +//---------------------------------------------------------------------------- +// None +// +//---------------------------------------------------------------------------- +// "Output Output Phase Duty Pk-to-Pk Phase" +// "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)" +//---------------------------------------------------------------------------- +// CLK_OUT1____75.000______0.000______50.0______248.869____240.171 +// CLK_OUT2___150.000______0.000______50.0______216.897____240.171 +// +//---------------------------------------------------------------------------- +// "Input Clock Freq (MHz) Input Jitter (UI)" +//---------------------------------------------------------------------------- +// __primary______________50____________0.010 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG + + hdmi_clk instance_name + (// Clock in ports + .CLK_IN1(CLK_IN1), // IN + // Clock out ports + .CLK_OUT1(CLK_OUT1), // OUT + .CLK_OUT2(CLK_OUT2)); // OUT +// INST_TAG_END ------ End INSTANTIATION Template --------- diff --git a/ipcore_dir/hdmi_clk.xco b/ipcore_dir/hdmi_clk.xco new file mode 100644 index 0000000..b3e4514 --- /dev/null +++ b/ipcore_dir/hdmi_clk.xco @@ -0,0 +1,269 @@ +############################################################## +# +# Xilinx Core Generator version 14.7 +# Date: Thu Sep 17 15:18:44 2020 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# Generated from component: xilinx.com:ip:clk_wiz:3.6 +# +############################################################## +# +# BEGIN Project Options +SET addpads = false +SET asysymbol = true +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = false +SET designentry = Verilog +SET device = xc6slx9 +SET devicefamily = spartan6 +SET flowvendor = Other +SET formalverification = false +SET foundationsym = false +SET implementationfiletype = Ngc +SET package = tqg144 +SET removerpms = false +SET simulationfiles = Behavioral +SET speedgrade = -2 +SET verilogsim = true +SET vhdlsim = false +# END Project Options +# BEGIN Select +SELECT Clocking_Wizard xilinx.com:ip:clk_wiz:3.6 +# END Select +# BEGIN Parameters +CSET calc_done=DONE +CSET clk_in_sel_port=CLK_IN_SEL +CSET clk_out1_port=CLK_OUT1 +CSET clk_out1_use_fine_ps_gui=false +CSET clk_out2_port=CLK_OUT2 +CSET clk_out2_use_fine_ps_gui=false +CSET clk_out3_port=CLK_OUT3 +CSET clk_out3_use_fine_ps_gui=false +CSET clk_out4_port=CLK_OUT4 +CSET clk_out4_use_fine_ps_gui=false +CSET clk_out5_port=CLK_OUT5 +CSET clk_out5_use_fine_ps_gui=false +CSET clk_out6_port=CLK_OUT6 +CSET clk_out6_use_fine_ps_gui=false +CSET clk_out7_port=CLK_OUT7 +CSET clk_out7_use_fine_ps_gui=false +CSET clk_valid_port=CLK_VALID +CSET clkfb_in_n_port=CLKFB_IN_N +CSET clkfb_in_p_port=CLKFB_IN_P +CSET clkfb_in_port=CLKFB_IN +CSET clkfb_in_signaling=SINGLE +CSET clkfb_out_n_port=CLKFB_OUT_N +CSET clkfb_out_p_port=CLKFB_OUT_P +CSET clkfb_out_port=CLKFB_OUT +CSET clkfb_stopped_port=CLKFB_STOPPED +CSET clkin1_jitter_ps=200.0 +CSET clkin1_ui_jitter=0.010 +CSET clkin2_jitter_ps=100.0 +CSET clkin2_ui_jitter=0.010 +CSET clkout1_drives=BUFG +CSET clkout1_requested_duty_cycle=50.000 +CSET clkout1_requested_out_freq=75 +CSET clkout1_requested_phase=0.000 +CSET clkout2_drives=BUFG +CSET clkout2_requested_duty_cycle=50.000 +CSET clkout2_requested_out_freq=150 +CSET clkout2_requested_phase=0.000 +CSET clkout2_used=true +CSET clkout3_drives=BUFG +CSET clkout3_requested_duty_cycle=50.000 +CSET clkout3_requested_out_freq=100.000 +CSET clkout3_requested_phase=0.000 +CSET clkout3_used=false +CSET clkout4_drives=BUFG +CSET clkout4_requested_duty_cycle=50.000 +CSET clkout4_requested_out_freq=100.000 +CSET clkout4_requested_phase=0.000 +CSET clkout4_used=false +CSET clkout5_drives=BUFG +CSET clkout5_requested_duty_cycle=50.000 +CSET clkout5_requested_out_freq=100.000 +CSET clkout5_requested_phase=0.000 +CSET clkout5_used=false +CSET clkout6_drives=BUFG +CSET clkout6_requested_duty_cycle=50.000 +CSET clkout6_requested_out_freq=100.000 +CSET clkout6_requested_phase=0.000 +CSET clkout6_used=false +CSET clkout7_drives=BUFG +CSET clkout7_requested_duty_cycle=50.000 +CSET clkout7_requested_out_freq=100.000 +CSET clkout7_requested_phase=0.000 +CSET clkout7_used=false +CSET clock_mgr_type=AUTO +CSET component_name=hdmi_clk +CSET daddr_port=DADDR +CSET dclk_port=DCLK +CSET dcm_clk_feedback=NONE +CSET dcm_clk_out1_port=CLKFX +CSET dcm_clk_out2_port=CLK0 +CSET dcm_clk_out3_port=CLK0 +CSET dcm_clk_out4_port=CLK0 +CSET dcm_clk_out5_port=CLK0 +CSET dcm_clk_out6_port=CLK0 +CSET dcm_clkdv_divide=2.0 +CSET dcm_clkfx_divide=2 +CSET dcm_clkfx_multiply=3 +CSET dcm_clkgen_clk_out1_port=CLKFX +CSET dcm_clkgen_clk_out2_port=CLKFX +CSET dcm_clkgen_clk_out3_port=CLKFX +CSET dcm_clkgen_clkfx_divide=1 +CSET dcm_clkgen_clkfx_md_max=0.000 +CSET dcm_clkgen_clkfx_multiply=4 +CSET dcm_clkgen_clkfxdv_divide=2 +CSET dcm_clkgen_clkin_period=10.000 +CSET dcm_clkgen_notes=None +CSET dcm_clkgen_spread_spectrum=NONE +CSET dcm_clkgen_startup_wait=false +CSET dcm_clkin_divide_by_2=false +CSET dcm_clkin_period=20.000 +CSET dcm_clkout_phase_shift=NONE +CSET dcm_deskew_adjust=SYSTEM_SYNCHRONOUS +CSET dcm_notes=None +CSET dcm_phase_shift=0 +CSET dcm_pll_cascade=NONE +CSET dcm_startup_wait=false +CSET den_port=DEN +CSET din_port=DIN +CSET dout_port=DOUT +CSET drdy_port=DRDY +CSET dwe_port=DWE +CSET feedback_source=FDBK_AUTO +CSET in_freq_units=Units_MHz +CSET in_jitter_units=Units_UI +CSET input_clk_stopped_port=INPUT_CLK_STOPPED +CSET jitter_options=UI +CSET jitter_sel=No_Jitter +CSET locked_port=LOCKED +CSET mmcm_bandwidth=OPTIMIZED +CSET mmcm_clkfbout_mult_f=4.000 +CSET mmcm_clkfbout_phase=0.000 +CSET mmcm_clkfbout_use_fine_ps=false +CSET mmcm_clkin1_period=10.000 +CSET mmcm_clkin2_period=10.000 +CSET mmcm_clkout0_divide_f=4.000 +CSET mmcm_clkout0_duty_cycle=0.500 +CSET mmcm_clkout0_phase=0.000 +CSET mmcm_clkout0_use_fine_ps=false +CSET mmcm_clkout1_divide=1 +CSET mmcm_clkout1_duty_cycle=0.500 +CSET mmcm_clkout1_phase=0.000 +CSET mmcm_clkout1_use_fine_ps=false +CSET mmcm_clkout2_divide=1 +CSET mmcm_clkout2_duty_cycle=0.500 +CSET mmcm_clkout2_phase=0.000 +CSET mmcm_clkout2_use_fine_ps=false +CSET mmcm_clkout3_divide=1 +CSET mmcm_clkout3_duty_cycle=0.500 +CSET mmcm_clkout3_phase=0.000 +CSET mmcm_clkout3_use_fine_ps=false +CSET mmcm_clkout4_cascade=false +CSET mmcm_clkout4_divide=1 +CSET mmcm_clkout4_duty_cycle=0.500 +CSET mmcm_clkout4_phase=0.000 +CSET mmcm_clkout4_use_fine_ps=false +CSET mmcm_clkout5_divide=1 +CSET mmcm_clkout5_duty_cycle=0.500 +CSET mmcm_clkout5_phase=0.000 +CSET mmcm_clkout5_use_fine_ps=false +CSET mmcm_clkout6_divide=1 +CSET mmcm_clkout6_duty_cycle=0.500 +CSET mmcm_clkout6_phase=0.000 +CSET mmcm_clkout6_use_fine_ps=false +CSET mmcm_clock_hold=false +CSET mmcm_compensation=ZHOLD +CSET mmcm_divclk_divide=1 +CSET mmcm_notes=None +CSET mmcm_ref_jitter1=0.010 +CSET mmcm_ref_jitter2=0.010 +CSET mmcm_startup_wait=false +CSET num_out_clks=2 +CSET override_dcm=false +CSET override_dcm_clkgen=false +CSET override_mmcm=false +CSET override_pll=false +CSET platform=lin64 +CSET pll_bandwidth=OPTIMIZED +CSET pll_clk_feedback=CLKFBOUT +CSET pll_clkfbout_mult=9 +CSET pll_clkfbout_phase=0.000 +CSET pll_clkin_period=20.000 +CSET pll_clkout0_divide=6 +CSET pll_clkout0_duty_cycle=0.500 +CSET pll_clkout0_phase=0.000 +CSET pll_clkout1_divide=3 +CSET pll_clkout1_duty_cycle=0.500 +CSET pll_clkout1_phase=0.000 +CSET pll_clkout2_divide=1 +CSET pll_clkout2_duty_cycle=0.500 +CSET pll_clkout2_phase=0.000 +CSET pll_clkout3_divide=1 +CSET pll_clkout3_duty_cycle=0.500 +CSET pll_clkout3_phase=0.000 +CSET pll_clkout4_divide=1 +CSET pll_clkout4_duty_cycle=0.500 +CSET pll_clkout4_phase=0.000 +CSET pll_clkout5_divide=1 +CSET pll_clkout5_duty_cycle=0.500 +CSET pll_clkout5_phase=0.000 +CSET pll_compensation=INTERNAL +CSET pll_divclk_divide=1 +CSET pll_notes=None +CSET pll_ref_jitter=0.010 +CSET power_down_port=POWER_DOWN +CSET prim_in_freq=50 +CSET prim_in_jitter=0.010 +CSET prim_source=Single_ended_clock_capable_pin +CSET primary_port=CLK_IN1 +CSET primitive=MMCM +CSET primtype_sel=PLL_BASE +CSET psclk_port=PSCLK +CSET psdone_port=PSDONE +CSET psen_port=PSEN +CSET psincdec_port=PSINCDEC +CSET relative_inclk=REL_PRIMARY +CSET reset_port=RESET +CSET secondary_in_freq=100.000 +CSET secondary_in_jitter=0.010 +CSET secondary_port=CLK_IN2 +CSET secondary_source=Single_ended_clock_capable_pin +CSET ss_mod_freq=250 +CSET ss_mode=CENTER_HIGH +CSET status_port=STATUS +CSET summary_strings=empty +CSET use_clk_valid=false +CSET use_clkfb_stopped=false +CSET use_dyn_phase_shift=false +CSET use_dyn_reconfig=false +CSET use_freeze=false +CSET use_freq_synth=true +CSET use_inclk_stopped=false +CSET use_inclk_switchover=false +CSET use_locked=false +CSET use_max_i_jitter=false +CSET use_min_o_jitter=false +CSET use_min_power=false +CSET use_phase_alignment=false +CSET use_power_down=false +CSET use_reset=false +CSET use_spread_spectrum=false +CSET use_spread_spectrum_1=false +CSET use_status=false +# END Parameters +# BEGIN Extra information +MISC pkg_timestamp=2012-05-10T12:44:55Z +# END Extra information +GENERATE +# CRC: 9368653d diff --git a/ipcore_dir/hdmi_clk.xdc b/ipcore_dir/hdmi_clk.xdc new file mode 100755 index 0000000..a686655 --- /dev/null +++ b/ipcore_dir/hdmi_clk.xdc @@ -0,0 +1,66 @@ +# file: hdmi_clk.xdc +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +# Input clock periods. These duplicate the values entered for the +# input clocks. You can use these to time your system +#---------------------------------------------------------------- +create_clock -name CLK_IN1 -period 20.000 [get_ports CLK_IN1] +set_propagated_clock CLK_IN1 +set_input_jitter CLK_IN1 0.2 + + +# Derived clock periods. These are commented out because they are +# automatically propogated by the tools +# However, if you'd like to use them for module level testing, you +# can copy them into your module level timing checks +#----------------------------------------------------------------- + +#----------------------------------------------------------------- + +#----------------------------------------------------------------- diff --git a/ipcore_dir/hdmi_clk.xise b/ipcore_dir/hdmi_clk.xise new file mode 100644 index 0000000..df07c32 --- /dev/null +++ b/ipcore_dir/hdmi_clk.xise @@ -0,0 +1,74 @@ + + + +

+ + + + + + + + +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ipcore_dir/hdmi_clk/clk_wiz_v3_6_readme.txt b/ipcore_dir/hdmi_clk/clk_wiz_v3_6_readme.txt new file mode 100644 index 0000000..91dcdd0 --- /dev/null +++ b/ipcore_dir/hdmi_clk/clk_wiz_v3_6_readme.txt @@ -0,0 +1,184 @@ +CHANGE LOG for LogiCORE Clocking Wizard V3.6 + + Release Date: June 19, 2013 +-------------------------------------------------------------------------------- + +Table of Contents + +1. INTRODUCTION +2. DEVICE SUPPORT +3. NEW FEATURE HISTORY +4. RESOLVED ISSUES +5. KNOWN ISSUES & LIMITATIONS +6. TECHNICAL SUPPORT & FEEDBACK +7. CORE RELEASE HISTORY +8. LEGAL DISCLAIMER + +-------------------------------------------------------------------------------- + + +1. INTRODUCTION + +For installation instructions for this release, please go to: + + http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm + +For system requirements: + + http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm + +This file contains release notes for the Xilinx LogiCORE IP Clocking Wizard v3.6 +solution. For the latest core updates, see the product page at: + + http://www.xilinx.com/products/design_resources/conn_central/solution_kits/wizards/ + +................................................................................ + +2. DEVICE SUPPORT + + + 2.1 ISE + + + The following device families are supported by the core for this release. + + All 7 Series devices + + + Zynq-7000 devices + Zynq-7000 + Defense Grade Zynq-7000Q (XQ) + + + All Virtex-6 devices + + + All Spartan-6 devices + + +................................................................................ + +3. NEW FEATURE HISTORY + + + 3.1 ISE + + - Spread Spectrum support for 7 series MMCME2 + + - ISE 14.2 software support + +................................................................................ + +4. RESOLVED ISSUES + + + 4.1 ISE + + Resolved issue with example design becoming core top in planAhead + + Resolved issue with Virtex6 MMCM instantiation for VHDL project + Please refer to AR 50719 - http://www.xilinx.com/support/answers/50719.htm + +................................................................................ + +5. KNOWN ISSUES & LIMITATIONS + + + 5.1 ISE + + + The most recent information, including known issues, workarounds, and + resolutions for this version is provided in the IP Release Notes Guide + located at + + www.xilinx.com/support/documentation/user_guides/xtp025.pdf + + +................................................................................ + +6. TECHNICAL SUPPORT & FEEDBACK + + +To obtain technical support, create a WebCase at www.xilinx.com/support. +Questions are routed to a team with expertise using this product. + +Xilinx provides technical support for use of this product when used +according to the guidelines described in the core documentation, and +cannot guarantee timing, functionality, or support of this product for +designs that do not follow specified guidelines. + + +................................................................................ + +7. CORE RELEASE HISTORY + + +Date By Version Description +================================================================================ +06/19/2013 Xilinx, Inc. 3.6(Rev3) ISE 14.6 support +10/16/2012 Xilinx, Inc. 3.6(Rev2) ISE 14.3 support +07/25/2012 Xilinx, Inc. 3.6 ISE 14.2 support +04/24/2012 Xilinx, Inc. 3.5 ISE 14.1 support +01/18/2012 Xilinx, Inc. 3.3 ISE 13.4 support +06/22/2011 Xilinx, Inc. 3.2 ISE 13.2 support +03/01/2011 Xilinx, Inc. 3.1 ISE 13.1 support +12/14/2010 Xilinx, Inc. 1.8 ISE 12.4 support +09/21/2010 Xilinx, Inc. 1.7 ISE 12.3 support +07/23/2010 Xilinx, Inc. 1.6 ISE 12.2 support +04/19/2010 Xilinx, Inc. 1.5 ISE 12.1 support +12/02/2009 Xilinx, Inc. 1.4 ISE 11.4 support +09/16/2009 Xilinx, Inc. 1.3 ISE 11.3 support +06/24/2009 Xilinx, Inc. 1.2 ISE 11.2 support +04/24/2009 Xilinx, Inc. 1.1 Initial release; 11.1 support +================================================================================ + +................................................................................ + +8. LEGAL DISCLAIMER + +(c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. + +This file contains confidential and proprietary information +of Xilinx, Inc. and is protected under U.S. and +international copyright and other intellectual property +laws. + +DISCLAIMER +This disclaimer is not a license and does not grant any +rights to the materials distributed herewith. Except as +otherwise provided in a valid license issued to you by +Xilinx, and to the maximum extent permitted by applicable +law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +(2) Xilinx shall not be liable (whether in contract or tort, +including negligence, or under any other theory of +liability) for any loss or damage of any kind or nature +related to, arising under or in connection with these +materials, including for any direct, or any indirect, +special, incidental, or consequential loss or damage +(including loss of data, profits, goodwill, or any type of +loss or damage suffered as a result of any action brought +by a third party) even if such damage or loss was +reasonably foreseeable or Xilinx had been advised of the +possibility of the same. + +CRITICAL APPLICATIONS +Xilinx products are not designed or intended to be fail- +safe, or for use in any application requiring fail-safe +performance, such as life-support or safety devices or +systems, Class III medical devices, nuclear facilities, +applications related to the deployment of airbags, or any +other applications that could lead to death, personal +injury, or severe property or environmental damage +(individually and collectively, "Critical +Applications"). Customer assumes the sole risk and +liability of any use of Xilinx products in Critical +Applications, subject only to applicable laws and +regulations governing limitations on product liability. + +THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +PART OF THIS FILE AT ALL TIMES. + diff --git a/ipcore_dir/hdmi_clk/doc/clk_wiz_v3_6_readme.txt b/ipcore_dir/hdmi_clk/doc/clk_wiz_v3_6_readme.txt new file mode 100644 index 0000000..91dcdd0 --- /dev/null +++ b/ipcore_dir/hdmi_clk/doc/clk_wiz_v3_6_readme.txt @@ -0,0 +1,184 @@ +CHANGE LOG for LogiCORE Clocking Wizard V3.6 + + Release Date: June 19, 2013 +-------------------------------------------------------------------------------- + +Table of Contents + +1. INTRODUCTION +2. DEVICE SUPPORT +3. NEW FEATURE HISTORY +4. RESOLVED ISSUES +5. KNOWN ISSUES & LIMITATIONS +6. TECHNICAL SUPPORT & FEEDBACK +7. CORE RELEASE HISTORY +8. LEGAL DISCLAIMER + +-------------------------------------------------------------------------------- + + +1. INTRODUCTION + +For installation instructions for this release, please go to: + + http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm + +For system requirements: + + http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm + +This file contains release notes for the Xilinx LogiCORE IP Clocking Wizard v3.6 +solution. For the latest core updates, see the product page at: + + http://www.xilinx.com/products/design_resources/conn_central/solution_kits/wizards/ + +................................................................................ + +2. DEVICE SUPPORT + + + 2.1 ISE + + + The following device families are supported by the core for this release. + + All 7 Series devices + + + Zynq-7000 devices + Zynq-7000 + Defense Grade Zynq-7000Q (XQ) + + + All Virtex-6 devices + + + All Spartan-6 devices + + +................................................................................ + +3. NEW FEATURE HISTORY + + + 3.1 ISE + + - Spread Spectrum support for 7 series MMCME2 + + - ISE 14.2 software support + +................................................................................ + +4. RESOLVED ISSUES + + + 4.1 ISE + + Resolved issue with example design becoming core top in planAhead + + Resolved issue with Virtex6 MMCM instantiation for VHDL project + Please refer to AR 50719 - http://www.xilinx.com/support/answers/50719.htm + +................................................................................ + +5. KNOWN ISSUES & LIMITATIONS + + + 5.1 ISE + + + The most recent information, including known issues, workarounds, and + resolutions for this version is provided in the IP Release Notes Guide + located at + + www.xilinx.com/support/documentation/user_guides/xtp025.pdf + + +................................................................................ + +6. TECHNICAL SUPPORT & FEEDBACK + + +To obtain technical support, create a WebCase at www.xilinx.com/support. +Questions are routed to a team with expertise using this product. + +Xilinx provides technical support for use of this product when used +according to the guidelines described in the core documentation, and +cannot guarantee timing, functionality, or support of this product for +designs that do not follow specified guidelines. + + +................................................................................ + +7. CORE RELEASE HISTORY + + +Date By Version Description +================================================================================ +06/19/2013 Xilinx, Inc. 3.6(Rev3) ISE 14.6 support +10/16/2012 Xilinx, Inc. 3.6(Rev2) ISE 14.3 support +07/25/2012 Xilinx, Inc. 3.6 ISE 14.2 support +04/24/2012 Xilinx, Inc. 3.5 ISE 14.1 support +01/18/2012 Xilinx, Inc. 3.3 ISE 13.4 support +06/22/2011 Xilinx, Inc. 3.2 ISE 13.2 support +03/01/2011 Xilinx, Inc. 3.1 ISE 13.1 support +12/14/2010 Xilinx, Inc. 1.8 ISE 12.4 support +09/21/2010 Xilinx, Inc. 1.7 ISE 12.3 support +07/23/2010 Xilinx, Inc. 1.6 ISE 12.2 support +04/19/2010 Xilinx, Inc. 1.5 ISE 12.1 support +12/02/2009 Xilinx, Inc. 1.4 ISE 11.4 support +09/16/2009 Xilinx, Inc. 1.3 ISE 11.3 support +06/24/2009 Xilinx, Inc. 1.2 ISE 11.2 support +04/24/2009 Xilinx, Inc. 1.1 Initial release; 11.1 support +================================================================================ + +................................................................................ + +8. LEGAL DISCLAIMER + +(c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. + +This file contains confidential and proprietary information +of Xilinx, Inc. and is protected under U.S. and +international copyright and other intellectual property +laws. + +DISCLAIMER +This disclaimer is not a license and does not grant any +rights to the materials distributed herewith. Except as +otherwise provided in a valid license issued to you by +Xilinx, and to the maximum extent permitted by applicable +law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +(2) Xilinx shall not be liable (whether in contract or tort, +including negligence, or under any other theory of +liability) for any loss or damage of any kind or nature +related to, arising under or in connection with these +materials, including for any direct, or any indirect, +special, incidental, or consequential loss or damage +(including loss of data, profits, goodwill, or any type of +loss or damage suffered as a result of any action brought +by a third party) even if such damage or loss was +reasonably foreseeable or Xilinx had been advised of the +possibility of the same. + +CRITICAL APPLICATIONS +Xilinx products are not designed or intended to be fail- +safe, or for use in any application requiring fail-safe +performance, such as life-support or safety devices or +systems, Class III medical devices, nuclear facilities, +applications related to the deployment of airbags, or any +other applications that could lead to death, personal +injury, or severe property or environmental damage +(individually and collectively, "Critical +Applications"). Customer assumes the sole risk and +liability of any use of Xilinx products in Critical +Applications, subject only to applicable laws and +regulations governing limitations on product liability. + +THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +PART OF THIS FILE AT ALL TIMES. + diff --git a/ipcore_dir/hdmi_clk/doc/clk_wiz_v3_6_vinfo.html b/ipcore_dir/hdmi_clk/doc/clk_wiz_v3_6_vinfo.html new file mode 100644 index 0000000..d6deba0 --- /dev/null +++ b/ipcore_dir/hdmi_clk/doc/clk_wiz_v3_6_vinfo.html @@ -0,0 +1,195 @@ + + +clk_wiz_v3_6_vinfo + + + +


+CHANGE LOG for LogiCORE Clocking Wizard V3.6 
+
+                    Release Date: June 19, 2013
+--------------------------------------------------------------------------------
+
+Table of Contents
+
+1. INTRODUCTION 
+2. DEVICE SUPPORT    
+3. NEW FEATURE HISTORY   
+4. RESOLVED ISSUES 
+5. KNOWN ISSUES & LIMITATIONS 
+6. TECHNICAL SUPPORT & FEEDBACK
+7. CORE RELEASE HISTORY 
+8. LEGAL DISCLAIMER 
+
+--------------------------------------------------------------------------------
+
+
+1. INTRODUCTION
+
+For installation instructions for this release, please go to:
+
+  www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm
+
+For system requirements:
+
+   www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm
+
+This file contains release notes for the Xilinx LogiCORE IP Clocking Wizard v3.6
+solution. For the latest core updates, see the product page at:
+
+   www.xilinx.com/products/design_resources/conn_central/solution_kits/wizards/
+
+................................................................................
+
+2. DEVICE SUPPORT
+
+
+  2.1 ISE 
+   
+  
+  The following device families are supported by the core for this release.
+  
+  All 7 Series devices
+
+
+  Zynq-7000 devices
+    Zynq-7000
+    Defense Grade Zynq-7000Q (XQ)
+
+
+  All Virtex-6 devices
+  
+  
+  All Spartan-6 devices
+  
+  
+................................................................................
+
+3. NEW FEATURE HISTORY 
+
+
+  3.1 ISE 
+  
+    - Spread Spectrum support for 7 series MMCME2
+
+    - ISE 14.2 software support
+
+................................................................................
+
+4. RESOLVED ISSUES
+
+
+  4.1 ISE 
+  
+      Resolved issue with example design becoming core top in planAhead
+
+      Resolved issue with Virtex6 MMCM instantiation for VHDL project
+      Please refer to AR 50719 - www.xilinx.com/support/answers/50719.htm
+
+................................................................................
+
+5. KNOWN ISSUES & LIMITATIONS
+
+
+  5.1 ISE 
+  
+  
+  The most recent information, including known issues, workarounds, and
+  resolutions for this version is provided in the IP Release Notes Guide
+  located at
+
+   www.xilinx.com/support/documentation/user_guides/xtp025.pdf
+  
+  
+................................................................................
+
+6. TECHNICAL SUPPORT & FEEDBACK
+
+
+To obtain technical support, create a WebCase at www.xilinx.com/support.
+Questions are routed to a team with expertise using this product.
+
+Xilinx provides technical support for use of this product when used
+according to the guidelines described in the core documentation, and
+cannot guarantee timing, functionality, or support of this product for
+designs that do not follow specified guidelines.
+
+
+................................................................................
+
+7. CORE RELEASE HISTORY
+
+
+Date        By            Version      Description
+================================================================================
+06/19/2013  Xilinx, Inc.  3.6(Rev3)    ISE 14.6 support
+10/16/2012  Xilinx, Inc.  3.6(Rev2)    ISE 14.3 support
+07/25/2012  Xilinx, Inc.  3.6          ISE 14.2 support
+04/24/2012  Xilinx, Inc.  3.5          ISE 14.1 support
+01/18/2012  Xilinx, Inc.  3.3          ISE 13.4 support
+06/22/2011  Xilinx, Inc.  3.2          ISE 13.2 support
+03/01/2011  Xilinx, Inc.  3.1          ISE 13.1 support
+12/14/2010  Xilinx, Inc.  1.8          ISE 12.4 support
+09/21/2010  Xilinx, Inc.  1.7          ISE 12.3 support
+07/23/2010  Xilinx, Inc.  1.6          ISE 12.2 support
+04/19/2010  Xilinx, Inc.  1.5          ISE 12.1 support
+12/02/2009  Xilinx, Inc.  1.4          ISE 11.4 support
+09/16/2009  Xilinx, Inc.  1.3          ISE 11.3 support
+06/24/2009  Xilinx, Inc.  1.2          ISE 11.2 support
+04/24/2009  Xilinx, Inc.  1.1          Initial release; 11.1 support
+================================================================================
+                          
+................................................................................
+
+8. LEGAL DISCLAIMER
+
+(c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
+
+This file contains confidential and proprietary information
+of Xilinx, Inc. and is protected under U.S. and
+international copyright and other intellectual property
+laws.
+
+DISCLAIMER
+This disclaimer is not a license and does not grant any
+rights to the materials distributed herewith. Except as
+otherwise provided in a valid license issued to you by
+Xilinx, and to the maximum extent permitted by applicable
+law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+(2) Xilinx shall not be liable (whether in contract or tort,
+including negligence, or under any other theory of
+liability) for any loss or damage of any kind or nature
+related to, arising under or in connection with these
+materials, including for any direct, or any indirect,
+special, incidental, or consequential loss or damage
+(including loss of data, profits, goodwill, or any type of
+loss or damage suffered as a result of any action brought
+by a third party) even if such damage or loss was
+reasonably foreseeable or Xilinx had been advised of the
+possibility of the same.
+
+CRITICAL APPLICATIONS
+Xilinx products are not designed or intended to be fail-
+safe, or for use in any application requiring fail-safe
+performance, such as life-support or safety devices or
+systems, Class III medical devices, nuclear facilities,
+applications related to the deployment of airbags, or any
+other applications that could lead to death, personal
+injury, or severe property or environmental damage
+(individually and collectively, "Critical
+Applications"). Customer assumes the sole risk and
+liability of any use of Xilinx products in Critical
+Applications, subject only to applicable laws and
+regulations governing limitations on product liability.
+
+THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+PART OF THIS FILE AT ALL TIMES.
+
+
+

+ + diff --git a/ipcore_dir/hdmi_clk/doc/pg065_clk_wiz.pdf b/ipcore_dir/hdmi_clk/doc/pg065_clk_wiz.pdf new file mode 100644 index 0000000..a7daa60 Binary files /dev/null and b/ipcore_dir/hdmi_clk/doc/pg065_clk_wiz.pdf differ diff --git a/ipcore_dir/hdmi_clk/example_design/hdmi_clk_exdes.ucf b/ipcore_dir/hdmi_clk/example_design/hdmi_clk_exdes.ucf new file mode 100755 index 0000000..d67e2c5 --- /dev/null +++ b/ipcore_dir/hdmi_clk/example_design/hdmi_clk_exdes.ucf @@ -0,0 +1,59 @@ +# file: hdmi_clk_exdes.ucf +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +# Input clock periods. These duplicate the values entered for the +# input clocks. You can use these to time your system +#---------------------------------------------------------------- +NET "CLK_IN1" TNM_NET = "CLK_IN1"; +TIMESPEC "TS_CLK_IN1" = PERIOD "CLK_IN1" 20.000 ns HIGH 50% INPUT_JITTER 200.0ps; + + +# FALSE PATH constraints +PIN "COUNTER_RESET" TIG; + diff --git a/ipcore_dir/hdmi_clk/example_design/hdmi_clk_exdes.v b/ipcore_dir/hdmi_clk/example_design/hdmi_clk_exdes.v new file mode 100755 index 0000000..3a5e32b --- /dev/null +++ b/ipcore_dir/hdmi_clk/example_design/hdmi_clk_exdes.v @@ -0,0 +1,169 @@ +// file: hdmi_clk_exdes.v +// +// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// + +//---------------------------------------------------------------------------- +// Clocking wizard example design +//---------------------------------------------------------------------------- +// This example design instantiates the created clocking network, where each +// output clock drives a counter. The high bit of each counter is ported. +//---------------------------------------------------------------------------- + +`timescale 1ps/1ps + +module hdmi_clk_exdes + #( + parameter TCQ = 100 + ) + (// Clock in ports + input CLK_IN1, + // Reset that only drives logic in example design + input COUNTER_RESET, + output [2:1] CLK_OUT, + // High bits of counters driven by clocks + output [2:1] COUNT + ); + + // Parameters for the counters + //------------------------------- + // Counter width + localparam C_W = 16; + localparam NUM_C = 2; + genvar count_gen; + // Create reset for the counters + wire reset_int = COUNTER_RESET; + + reg [NUM_C:1] rst_sync; + reg [NUM_C:1] rst_sync_int; + reg [NUM_C:1] rst_sync_int1; + reg [NUM_C:1] rst_sync_int2; + + + // Declare the clocks and counters + wire [NUM_C:1] clk_int; + wire [NUM_C:1] clk_n; + wire [NUM_C:1] clk; + reg [C_W-1:0] counter [NUM_C:1]; + + // Instantiation of the clocking network + //-------------------------------------- + hdmi_clk clknetwork + (// Clock in ports + .CLK_IN1 (CLK_IN1), + // Clock out ports + .CLK_OUT1 (clk_int[1]), + .CLK_OUT2 (clk_int[2])); + +genvar clk_out_pins; + +generate + for (clk_out_pins = 1; clk_out_pins <= NUM_C; clk_out_pins = clk_out_pins + 1) + begin: gen_outclk_oddr + assign clk_n[clk_out_pins] = ~clk[clk_out_pins]; + + ODDR2 clkout_oddr + (.Q (CLK_OUT[clk_out_pins]), + .C0 (clk[clk_out_pins]), + .C1 (clk_n[clk_out_pins]), + .CE (1'b1), + .D0 (1'b1), + .D1 (1'b0), + .R (1'b0), + .S (1'b0)); + end +endgenerate + + // Connect the output clocks to the design + //----------------------------------------- + assign clk[1] = clk_int[1]; + assign clk[2] = clk_int[2]; + + + // Reset synchronizer + //----------------------------------- + generate for (count_gen = 1; count_gen <= NUM_C; count_gen = count_gen + 1) begin: counters_1 + always @(posedge reset_int or posedge clk[count_gen]) begin + if (reset_int) begin + rst_sync[count_gen] <= 1'b1; + rst_sync_int[count_gen]<= 1'b1; + rst_sync_int1[count_gen]<= 1'b1; + rst_sync_int2[count_gen]<= 1'b1; + end + else begin + rst_sync[count_gen] <= 1'b0; + rst_sync_int[count_gen] <= rst_sync[count_gen]; + rst_sync_int1[count_gen] <= rst_sync_int[count_gen]; + rst_sync_int2[count_gen] <= rst_sync_int1[count_gen]; + end + end + end + endgenerate + + + // Output clock sampling + //----------------------------------- + generate for (count_gen = 1; count_gen <= NUM_C; count_gen = count_gen + 1) begin: counters + + always @(posedge clk[count_gen] or posedge rst_sync_int2[count_gen]) begin + if (rst_sync_int2[count_gen]) begin + counter[count_gen] <= #TCQ { C_W { 1'b 0 } }; + end else begin + counter[count_gen] <= #TCQ counter[count_gen] + 1'b 1; + end + end + // alias the high bit of each counter to the corresponding + // bit in the output bus + assign COUNT[count_gen] = counter[count_gen][C_W-1]; + end + endgenerate + + + + + +endmodule diff --git a/ipcore_dir/hdmi_clk/example_design/hdmi_clk_exdes.xdc b/ipcore_dir/hdmi_clk/example_design/hdmi_clk_exdes.xdc new file mode 100755 index 0000000..a363ab5 --- /dev/null +++ b/ipcore_dir/hdmi_clk/example_design/hdmi_clk_exdes.xdc @@ -0,0 +1,68 @@ +# file: hdmi_clk_exdes.xdc +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +# Input clock periods. These duplicate the values entered for the +# input clocks. You can use these to time your system +#---------------------------------------------------------------- +create_clock -name CLK_IN1 -period 20.000 [get_ports CLK_IN1] +set_propagated_clock CLK_IN1 +set_input_jitter CLK_IN1 0.2 + +# FALSE PATH constraint added on COUNTER_RESET +set_false_path -from [get_ports "COUNTER_RESET"] + +# Derived clock periods. These are commented out because they are +# automatically propogated by the tools +# However, if you'd like to use them for module level testing, you +# can copy them into your module level timing checks +#----------------------------------------------------------------- + +#----------------------------------------------------------------- + +#----------------------------------------------------------------- diff --git a/ipcore_dir/hdmi_clk/implement/implement.bat b/ipcore_dir/hdmi_clk/implement/implement.bat new file mode 100755 index 0000000..b20b724 --- /dev/null +++ b/ipcore_dir/hdmi_clk/implement/implement.bat @@ -0,0 +1,90 @@ +REM file: implement.bat +REM +REM (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +REM +REM This file contains confidential and proprietary information +REM of Xilinx, Inc. and is protected under U.S. and +REM international copyright and other intellectual property +REM laws. +REM +REM DISCLAIMER +REM This disclaimer is not a license and does not grant any +REM rights to the materials distributed herewith. Except as +REM otherwise provided in a valid license issued to you by +REM Xilinx, and to the maximum extent permitted by applicable +REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +REM (2) Xilinx shall not be liable (whether in contract or tort, +REM including negligence, or under any other theory of +REM liability) for any loss or damage of any kind or nature +REM related to, arising under or in connection with these +REM materials, including for any direct, or any indirect, +REM special, incidental, or consequential loss or damage +REM (including loss of data, profits, goodwill, or any type of +REM loss or damage suffered as a result of any action brought +REM by a third party) even if such damage or loss was +REM reasonably foreseeable or Xilinx had been advised of the +REM possibility of the same. +REM +REM CRITICAL APPLICATIONS +REM Xilinx products are not designed or intended to be fail- +REM safe, or for use in any application requiring fail-safe +REM performance, such as life-support or safety devices or +REM systems, Class III medical devices, nuclear facilities, +REM applications related to the deployment of airbags, or any +REM other applications that could lead to death, personal +REM injury, or severe property or environmental damage +REM (individually and collectively, "Critical +REM Applications"). Customer assumes the sole risk and +REM liability of any use of Xilinx products in Critical +REM Applications, subject only to applicable laws and +REM regulations governing limitations on product liability. +REM +REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +REM PART OF THIS FILE AT ALL TIMES. +REM + +REM ----------------------------------------------------------------------------- +REM Script to synthesize and implement the RTL provided for the clocking wizard +REM ----------------------------------------------------------------------------- + +REM Clean up the results directory +rmdir /S /Q results +mkdir results + +REM Copy unisim_comp.v file to results directory +copy %XILINX%\verilog\src\iSE\unisim_comp.v .\results\ + +REM Synthesize the Verilog Wrapper Files +echo 'Synthesizing Clocking Wizard design with XST' +xst -ifn xst.scr +move hdmi_clk_exdes.ngc results\ + +REM Copy the constraints files generated by Coregen +echo 'Copying files from constraints directory to results directory' +copy ..\example_design\hdmi_clk_exdes.ucf results\ + +cd results + +echo 'Running ngdbuild' +ngdbuild -uc hdmi_clk_exdes.ucf hdmi_clk_exdes + +echo 'Running map' +map -timing -pr b hdmi_clk_exdes -o mapped.ncd + +echo 'Running par' +par -w mapped.ncd routed mapped.pcf + +echo 'Running trce' +trce -e 10 routed -o routed mapped.pcf + +echo 'Running design through bitgen' +bitgen -w routed + +echo 'Running netgen to create gate level model for the clocking wizard example design' +netgen -ofmt verilog -sim -sdf_anno false -tm hdmi_clk_exdes -w routed.ncd routed.v +cd .. + diff --git a/ipcore_dir/hdmi_clk/implement/implement.sh b/ipcore_dir/hdmi_clk/implement/implement.sh new file mode 100755 index 0000000..64dca60 --- /dev/null +++ b/ipcore_dir/hdmi_clk/implement/implement.sh @@ -0,0 +1,91 @@ +#!/bin/sh +# file: implement.sh +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +#----------------------------------------------------------------------------- +# Script to synthesize and implement the RTL provided for the clocking wizard +#----------------------------------------------------------------------------- + +# Clean up the results directory +rm -rf results +mkdir results + +# Copy unisim_comp.v file to results directory +cp $XILINX/verilog/src/iSE/unisim_comp.v ./results/ + +# Synthesize the Verilog Wrapper Files +echo 'Synthesizing Clocking Wizard design with XST' +xst -ifn xst.scr +mv hdmi_clk_exdes.ngc results/ + +# Copy the constraints files generated by Coregen +echo 'Copying files from constraints directory to results directory' +cp ../example_design/hdmi_clk_exdes.ucf results/ + +cd results + +echo 'Running ngdbuild' +ngdbuild -uc hdmi_clk_exdes.ucf hdmi_clk_exdes + +echo 'Running map' +map -timing hdmi_clk_exdes -o mapped.ncd + +echo 'Running par' +par -w mapped.ncd routed mapped.pcf + +echo 'Running trce' +trce -e 10 routed -o routed mapped.pcf + +echo 'Running design through bitgen' +bitgen -w routed + +echo 'Running netgen to create gate level model for the clocking wizard example design' +netgen -ofmt verilog -sim -sdf_anno false -tm hdmi_clk_exdes -w routed.ncd routed.v + +cd .. diff --git a/ipcore_dir/hdmi_clk/implement/planAhead_ise.bat b/ipcore_dir/hdmi_clk/implement/planAhead_ise.bat new file mode 100755 index 0000000..8ac7718 --- /dev/null +++ b/ipcore_dir/hdmi_clk/implement/planAhead_ise.bat @@ -0,0 +1,58 @@ +REM file: planAhead_ise.bat +REM +REM (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +REM +REM This file contains confidential and proprietary information +REM of Xilinx, Inc. and is protected under U.S. and +REM international copyright and other intellectual property +REM laws. +REM +REM DISCLAIMER +REM This disclaimer is not a license and does not grant any +REM rights to the materials distributed herewith. Except as +REM otherwise provided in a valid license issued to you by +REM Xilinx, and to the maximum extent permitted by applicable +REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +REM (2) Xilinx shall not be liable (whether in contract or tort, +REM including negligence, or under any other theory of +REM liability) for any loss or damage of any kind or nature +REM related to, arising under or in connection with these +REM materials, including for any direct, or any indirect, +REM special, incidental, or consequential loss or damage +REM (including loss of data, profits, goodwill, or any type of +REM loss or damage suffered as a result of any action brought +REM by a third party) even if such damage or loss was +REM reasonably foreseeable or Xilinx had been advised of the +REM possibility of the same. +REM +REM CRITICAL APPLICATIONS +REM Xilinx products are not designed or intended to be fail- +REM safe, or for use in any application requiring fail-safe +REM performance, such as life-support or safety devices or +REM systems, Class III medical devices, nuclear facilities, +REM applications related to the deployment of airbags, or any +REM other applications that could lead to death, personal +REM injury, or severe property or environmental damage +REM (individually and collectively, "Critical +REM Applications"). Customer assumes the sole risk and +REM liability of any use of Xilinx products in Critical +REM Applications, subject only to applicable laws and +REM regulations governing limitations on product liability. +REM +REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +REM PART OF THIS FILE AT ALL TIMES. +REM + +REM----------------------------------------------------------------------------- +REM Script to synthesize and implement the RTL provided for the clocking wizard +REM----------------------------------------------------------------------------- + +del \f results +mkdir results +cd results + +planAhead -mode batch -source ..\planAhead_ise.tcl diff --git a/ipcore_dir/hdmi_clk/implement/planAhead_ise.sh b/ipcore_dir/hdmi_clk/implement/planAhead_ise.sh new file mode 100755 index 0000000..6c8c837 --- /dev/null +++ b/ipcore_dir/hdmi_clk/implement/planAhead_ise.sh @@ -0,0 +1,59 @@ +#!/bin/sh +# file: planAhead_ise.sh +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +#----------------------------------------------------------------------------- +# Script to synthesize and implement the RTL provided for the clocking wizard +#----------------------------------------------------------------------------- + +rm -rf results +mkdir results +cd results + +planAhead -mode batch -source ../planAhead_ise.tcl diff --git a/ipcore_dir/hdmi_clk/implement/planAhead_ise.tcl b/ipcore_dir/hdmi_clk/implement/planAhead_ise.tcl new file mode 100755 index 0000000..a9334d8 --- /dev/null +++ b/ipcore_dir/hdmi_clk/implement/planAhead_ise.tcl @@ -0,0 +1,78 @@ +# file: planAhead_ise.tcl +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +set projDir [file dirname [info script]] +set projName hdmi_clk +set topName hdmi_clk_exdes +set device xc6slx9tqg144-2 + +create_project $projName $projDir/results/$projName -part $device + +set_property design_mode RTL [get_filesets sources_1] + +## Source files +#set verilogSources [glob $srcDir/*.v] +import_files -fileset [get_filesets sources_1] -force -norecurse ../../example_design/hdmi_clk_exdes.v +import_files -fileset [get_filesets sources_1] -force -norecurse ../../../hdmi_clk.v + + +#UCF file +import_files -fileset [get_filesets constrs_1] -force -norecurse ../../example_design/hdmi_clk_exdes.ucf + +set_property top $topName [get_property srcset [current_run]] + +launch_runs -runs synth_1 +wait_on_run synth_1 + +set_property add_step Bitgen [get_runs impl_1] +launch_runs -runs impl_1 +wait_on_run impl_1 + + + diff --git a/ipcore_dir/hdmi_clk/implement/planAhead_rdn.bat b/ipcore_dir/hdmi_clk/implement/planAhead_rdn.bat new file mode 100755 index 0000000..42273f5 --- /dev/null +++ b/ipcore_dir/hdmi_clk/implement/planAhead_rdn.bat @@ -0,0 +1,58 @@ +REM file: planAhead_rdn.sh +REM +REM (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +REM +REM This file contains confidential and proprietary information +REM of Xilinx, Inc. and is protected under U.S. and +REM international copyright and other intellectual property +REM laws. +REM +REM DISCLAIMER +REM This disclaimer is not a license and does not grant any +REM rights to the materials distributed herewith. Except as +REM otherwise provided in a valid license issued to you by +REM Xilinx, and to the maximum extent permitted by applicable +REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +REM (2) Xilinx shall not be liable (whether in contract or tort, +REM including negligence, or under any other theory of +REM liability) for any loss or damage of any kind or nature +REM related to, arising under or in connection with these +REM materials, including for any direct, or any indirect, +REM special, incidental, or consequential loss or damage +REM (including loss of data, profits, goodwill, or any type of +REM loss or damage suffered as a result of any action brought +REM by a third party) even if such damage or loss was +REM reasonably foreseeable or Xilinx had been advised of the +REM possibility of the same. +REM +REM CRITICAL APPLICATIONS +REM Xilinx products are not designed or intended to be fail- +REM safe, or for use in any application requiring fail-safe +REM performance, such as life-support or safety devices or +REM systems, Class III medical devices, nuclear facilities, +REM applications related to the deployment of airbags, or any +REM other applications that could lead to death, personal +REM injury, or severe property or environmental damage +REM (individually and collectively, "Critical +REM Applications"). Customer assumes the sole risk and +REM liability of any use of Xilinx products in Critical +REM Applications, subject only to applicable laws and +REM regulations governing limitations on product liability. +REM +REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +REM PART OF THIS FILE AT ALL TIMES. +REM + +REM----------------------------------------------------------------------------- +REM Script to synthesize and implement the RTL provided for the XADC wizard +REM----------------------------------------------------------------------------- + +del \f results +mkdir results +cd results + +planAhead -mode batch -source ..\planAhead_rdn.tcl diff --git a/ipcore_dir/hdmi_clk/implement/planAhead_rdn.sh b/ipcore_dir/hdmi_clk/implement/planAhead_rdn.sh new file mode 100755 index 0000000..f4c1472 --- /dev/null +++ b/ipcore_dir/hdmi_clk/implement/planAhead_rdn.sh @@ -0,0 +1,57 @@ +#!/bin/sh +# file: planAhead_rdn.sh +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +#----------------------------------------------------------------------------- +# Script to synthesize and implement the RTL provided for the XADC wizard +#----------------------------------------------------------------------------- +rm -rf results +mkdir results +cd results +planAhead -mode batch -source ../planAhead_rdn.tcl diff --git a/ipcore_dir/hdmi_clk/implement/planAhead_rdn.tcl b/ipcore_dir/hdmi_clk/implement/planAhead_rdn.tcl new file mode 100755 index 0000000..38d8bd2 --- /dev/null +++ b/ipcore_dir/hdmi_clk/implement/planAhead_rdn.tcl @@ -0,0 +1,69 @@ +# file : planAhead_rdn.tcl +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +set device xc6slx9tqg144-2 +set projName hdmi_clk +set design hdmi_clk +set projDir [file dirname [info script]] +create_project $projName $projDir/results/$projName -part $device -force +set_property design_mode RTL [current_fileset -srcset] +set top_module hdmi_clk_exdes +set_property top hdmi_clk_exdes [get_property srcset [current_run]] +add_files -norecurse {../../../hdmi_clk.v} +add_files -norecurse {../../example_design/hdmi_clk_exdes.v} +import_files -fileset [get_filesets constrs_1 ] -force -norecurse {../../example_design/hdmi_clk_exdes.xdc} +synth_design +opt_design +place_design +route_design +write_sdf -rename_top_module hdmi_clk_exdes -file routed.sdf +write_verilog -nolib -mode timesim -sdf_anno false -rename_top_module hdmi_clk_exdes -file routed.v +report_timing -nworst 30 -path_type full -file routed.twr +report_drc -file report.drc +write_bitstream -bitgen_options {-g UnconstrainedPins:Allow} -file routed.bit diff --git a/ipcore_dir/hdmi_clk/implement/xst.prj b/ipcore_dir/hdmi_clk/implement/xst.prj new file mode 100755 index 0000000..d66fff4 --- /dev/null +++ b/ipcore_dir/hdmi_clk/implement/xst.prj @@ -0,0 +1,2 @@ +verilog work ../../hdmi_clk.v +verilog work ../example_design/hdmi_clk_exdes.v diff --git a/ipcore_dir/hdmi_clk/implement/xst.scr b/ipcore_dir/hdmi_clk/implement/xst.scr new file mode 100755 index 0000000..fc25306 --- /dev/null +++ b/ipcore_dir/hdmi_clk/implement/xst.scr @@ -0,0 +1,9 @@ +run +-ifmt MIXED +-top hdmi_clk_exdes +-p xc6slx9-tqg144-2 +-ifn xst.prj +-ofn hdmi_clk_exdes +-keep_hierarchy soft +-equivalent_register_removal no +-max_fanout 65535 diff --git a/ipcore_dir/hdmi_clk/simulation/functional/simcmds.tcl b/ipcore_dir/hdmi_clk/simulation/functional/simcmds.tcl new file mode 100755 index 0000000..45884f6 --- /dev/null +++ b/ipcore_dir/hdmi_clk/simulation/functional/simcmds.tcl @@ -0,0 +1,8 @@ +# file: simcmds.tcl + +# create the simulation script +vcd dumpfile isim.vcd +vcd dumpvars -m /hdmi_clk_tb -l 0 +wave add / +run 50000ns +quit diff --git a/ipcore_dir/hdmi_clk/simulation/functional/simulate_isim.bat b/ipcore_dir/hdmi_clk/simulation/functional/simulate_isim.bat new file mode 100755 index 0000000..d42dcbe --- /dev/null +++ b/ipcore_dir/hdmi_clk/simulation/functional/simulate_isim.bat @@ -0,0 +1,59 @@ +REM file: simulate_isim.bat +REM +REM (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +REM +REM This file contains confidential and proprietary information +REM of Xilinx, Inc. and is protected under U.S. and +REM international copyright and other intellectual property +REM laws. +REM +REM DISCLAIMER +REM This disclaimer is not a license and does not grant any +REM rights to the materials distributed herewith. Except as +REM otherwise provided in a valid license issued to you by +REM Xilinx, and to the maximum extent permitted by applicable +REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +REM (2) Xilinx shall not be liable (whether in contract or tort, +REM including negligence, or under any other theory of +REM liability) for any loss or damage of any kind or nature +REM related to, arising under or in connection with these +REM materials, including for any direct, or any indirect, +REM special, incidental, or consequential loss or damage +REM (including loss of data, profits, goodwill, or any type of +REM loss or damage suffered as a result of any action brought +REM by a third party) even if such damage or loss was +REM reasonably foreseeable or Xilinx had been advised of the +REM possibility of the same. +REM +REM CRITICAL APPLICATIONS +REM Xilinx products are not designed or intended to be fail- +REM safe, or for use in any application requiring fail-safe +REM performance, such as life-support or safety devices or +REM systems, Class III medical devices, nuclear facilities, +REM applications related to the deployment of airbags, or any +REM other applications that could lead to death, personal +REM injury, or severe property or environmental damage +REM (individually and collectively, "Critical +REM Applications"). Customer assumes the sole risk and +REM liability of any use of Xilinx products in Critical +REM Applications, subject only to applicable laws and +REM regulations governing limitations on product liability. +REM +REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +REM PART OF THIS FILE AT ALL TIMES. +REM + +vlogcomp -work work %XILINX%\verilog\src\glbl.v +vlogcomp -work work ..\..\..\hdmi_clk.v +vlogcomp -work work ..\..\example_design\hdmi_clk_exdes.v +vlogcomp -work work ..\hdmi_clk_tb.v + +REM compile the project +fuse work.hdmi_clk_tb work.glbl -L unisims_ver -o hdmi_clk_isim.exe + +REM run the simulation script +.\hdmi_clk_isim.exe -gui -tclbatch simcmds.tcl diff --git a/ipcore_dir/hdmi_clk/simulation/functional/simulate_isim.sh b/ipcore_dir/hdmi_clk/simulation/functional/simulate_isim.sh new file mode 100755 index 0000000..771e369 --- /dev/null +++ b/ipcore_dir/hdmi_clk/simulation/functional/simulate_isim.sh @@ -0,0 +1,61 @@ +# file: simulate_isim.sh +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +# lin64 +# create the project +vlogcomp -work work ${XILINX}/verilog/src/glbl.v +vlogcomp -work work ../../../hdmi_clk.v +vlogcomp -work work ../../example_design/hdmi_clk_exdes.v +vlogcomp -work work ../hdmi_clk_tb.v + +# compile the project +fuse work.hdmi_clk_tb work.glbl -L unisims_ver -o hdmi_clk_isim.exe + +# run the simulation script +./hdmi_clk_isim.exe -gui -tclbatch simcmds.tcl diff --git a/ipcore_dir/hdmi_clk/simulation/functional/simulate_mti.bat b/ipcore_dir/hdmi_clk/simulation/functional/simulate_mti.bat new file mode 100755 index 0000000..7248eab --- /dev/null +++ b/ipcore_dir/hdmi_clk/simulation/functional/simulate_mti.bat @@ -0,0 +1,61 @@ +REM file: simulate_mti.bat +REM +REM (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +REM +REM This file contains confidential and proprietary information +REM of Xilinx, Inc. and is protected under U.S. and +REM international copyright and other intellectual property +REM laws. +REM +REM DISCLAIMER +REM This disclaimer is not a license and does not grant any +REM rights to the materials distributed herewith. Except as +REM otherwise provided in a valid license issued to you by +REM Xilinx, and to the maximum extent permitted by applicable +REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +REM (2) Xilinx shall not be liable (whether in contract or tort, +REM including negligence, or under any other theory of +REM liability) for any loss or damage of any kind or nature +REM related to, arising under or in connection with these +REM materials, including for any direct, or any indirect, +REM special, incidental, or consequential loss or damage +REM (including loss of data, profits, goodwill, or any type of +REM loss or damage suffered as a result of any action brought +REM by a third party) even if such damage or loss was +REM reasonably foreseeable or Xilinx had been advised of the +REM possibility of the same. +REM +REM CRITICAL APPLICATIONS +REM Xilinx products are not designed or intended to be fail- +REM safe, or for use in any application requiring fail-safe +REM performance, such as life-support or safety devices or +REM systems, Class III medical devices, nuclear facilities, +REM applications related to the deployment of airbags, or any +REM other applications that could lead to death, personal +REM injury, or severe property or environmental damage +REM (individually and collectively, "Critical +REM Applications"). Customer assumes the sole risk and +REM liability of any use of Xilinx products in Critical +REM Applications, subject only to applicable laws and +REM regulations governing limitations on product liability. +REM +REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +REM PART OF THIS FILE AT ALL TIMES. +REM + +REM set up the working directory +vlib work + +REM compile all of the files +vlog -work work %XILINX%\verilog\src\glbl.v +vlog -work work ..\..\..\hdmi_clk.v +vlog -work work ..\..\example_design\hdmi_clk_exdes.v +vlog -work work ..\hdmi_clk_tb.v + +REM run the simulation +vsim -c -t ps -voptargs="+acc" -L secureip -L unisims_ver work.hdmi_clk_tb work.glbl + diff --git a/ipcore_dir/hdmi_clk/simulation/functional/simulate_mti.do b/ipcore_dir/hdmi_clk/simulation/functional/simulate_mti.do new file mode 100755 index 0000000..82293a7 --- /dev/null +++ b/ipcore_dir/hdmi_clk/simulation/functional/simulate_mti.do @@ -0,0 +1,65 @@ +# file: simulate_mti.do +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +# set up the working directory +set work work +vlib work + +# compile all of the files +vlog -work work $env(XILINX)/verilog/src/glbl.v +vlog -work work ../../../hdmi_clk.v +vlog -work work ../../example_design/hdmi_clk_exdes.v +vlog -work work ../hdmi_clk_tb.v + +# run the simulation +vsim -t ps -voptargs="+acc" -L unisims_ver work.hdmi_clk_tb work.glbl +do wave.do +log hdmi_clk_tb/dut/counter +log -r /* +run 50000ns diff --git a/ipcore_dir/hdmi_clk/simulation/functional/simulate_mti.sh b/ipcore_dir/hdmi_clk/simulation/functional/simulate_mti.sh new file mode 100755 index 0000000..b1adf8e --- /dev/null +++ b/ipcore_dir/hdmi_clk/simulation/functional/simulate_mti.sh @@ -0,0 +1,61 @@ +#/bin/sh +# file: simulate_mti.sh +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# +# set up the working directory +set work work +vlib work + +# compile all of the files +vlog -work work $XILINX/verilog/src/glbl.v +vlog -work work ../../../hdmi_clk.v +vlog -work work ../../example_design/hdmi_clk_exdes.v +vlog -work work ../hdmi_clk_tb.v + +# run the simulation +vsim -c -t ps -voptargs="+acc" -L secureip -L unisims_ver work.hdmi_clk_tb work.glbl diff --git a/ipcore_dir/hdmi_clk/simulation/functional/simulate_ncsim.sh b/ipcore_dir/hdmi_clk/simulation/functional/simulate_ncsim.sh new file mode 100755 index 0000000..b38567f --- /dev/null +++ b/ipcore_dir/hdmi_clk/simulation/functional/simulate_ncsim.sh @@ -0,0 +1,62 @@ +#/bin/sh +# file: simulate_ncsim.sh +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +# set up the working directory +mkdir work + +# compile all of the files +ncvlog -work work ${XILINX}/verilog/src/glbl.v +ncvlog -work work ../../../hdmi_clk.v +ncvlog -work work ../../example_design/hdmi_clk_exdes.v +ncvlog -work work ../hdmi_clk_tb.v + +# elaborate and run the simulation +ncelab -work work -access +wc work.hdmi_clk_tb work.glbl +ncsim -input "@database -open -shm nc; probe -create -database nc -all -depth all; probe dut.counter; run 50000ns; exit" work.hdmi_clk_tb diff --git a/ipcore_dir/hdmi_clk/simulation/functional/simulate_vcs.sh b/ipcore_dir/hdmi_clk/simulation/functional/simulate_vcs.sh new file mode 100755 index 0000000..f8434f6 --- /dev/null +++ b/ipcore_dir/hdmi_clk/simulation/functional/simulate_vcs.sh @@ -0,0 +1,72 @@ +#!/bin/sh +# file: simulate_vcs.sh +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +# remove old files +rm -rf simv* csrc DVEfiles AN.DB + +# compile all of the files +# Note that -sverilog is not strictly required- You can +# remove the -sverilog if you change the type of the +# localparam for the periods in the testbench file to +# [63:0] from time +vlogan -sverilog \ + ${XILINX}/verilog/src/glbl.v \ + ../../../hdmi_clk.v \ + ../../example_design/hdmi_clk_exdes.v \ + ../hdmi_clk_tb.v + +# prepare the simulation +vcs +vcs+lic+wait -debug hdmi_clk_tb glbl + +# run the simulation +./simv -ucli -i ucli_commands.key + +# launch the viewer +dve -vpd vcdplus.vpd -session vcs_session.tcl diff --git a/ipcore_dir/hdmi_clk/simulation/functional/ucli_commands.key b/ipcore_dir/hdmi_clk/simulation/functional/ucli_commands.key new file mode 100755 index 0000000..bde2894 --- /dev/null +++ b/ipcore_dir/hdmi_clk/simulation/functional/ucli_commands.key @@ -0,0 +1,5 @@ +call {$vcdpluson} +call {$vcdplusmemon(hdmi_clk_tb.dut.counter)} +run +call {$vcdplusclose} +quit diff --git a/ipcore_dir/hdmi_clk/simulation/functional/vcs_session.tcl b/ipcore_dir/hdmi_clk/simulation/functional/vcs_session.tcl new file mode 100755 index 0000000..013047a --- /dev/null +++ b/ipcore_dir/hdmi_clk/simulation/functional/vcs_session.tcl @@ -0,0 +1,15 @@ +gui_open_window Wave +gui_sg_create hdmi_clk_group +gui_list_add_group -id Wave.1 {hdmi_clk_group} +gui_sg_addsignal -group hdmi_clk_group {hdmi_clk_tb.test_phase} +gui_set_radix -radix {ascii} -signals {hdmi_clk_tb.test_phase} +gui_sg_addsignal -group hdmi_clk_group {{Input_clocks}} -divider +gui_sg_addsignal -group hdmi_clk_group {hdmi_clk_tb.CLK_IN1} +gui_sg_addsignal -group hdmi_clk_group {{Output_clocks}} -divider +gui_sg_addsignal -group hdmi_clk_group {hdmi_clk_tb.dut.clk} +gui_list_expand -id Wave.1 hdmi_clk_tb.dut.clk +gui_sg_addsignal -group hdmi_clk_group {{Counters}} -divider +gui_sg_addsignal -group hdmi_clk_group {hdmi_clk_tb.COUNT} +gui_sg_addsignal -group hdmi_clk_group {hdmi_clk_tb.dut.counter} +gui_list_expand -id Wave.1 hdmi_clk_tb.dut.counter +gui_zoom -window Wave.1 -full diff --git a/ipcore_dir/hdmi_clk/simulation/functional/wave.do b/ipcore_dir/hdmi_clk/simulation/functional/wave.do new file mode 100755 index 0000000..ee7fd93 --- /dev/null +++ b/ipcore_dir/hdmi_clk/simulation/functional/wave.do @@ -0,0 +1,57 @@ +# file: wave.do +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +add wave -noupdate -format Literal -radix ascii /hdmi_clk_tb/test_phase +add wave -noupdate -divider {Input clocks} +add wave -noupdate -format Logic /hdmi_clk_tb/CLK_IN1 +add wave -noupdate -divider {Output clocks} +add wave -noupdate -format Literal -expand /hdmi_clk_tb/dut/clk +add wave -noupdate -divider Counters +add wave -noupdate -format Literal -radix hexadecimal /hdmi_clk_tb/COUNT +add wave -noupdate -format Literal -radix hexadecimal -expand /hdmi_clk_tb/dut/counter diff --git a/ipcore_dir/hdmi_clk/simulation/functional/wave.sv b/ipcore_dir/hdmi_clk/simulation/functional/wave.sv new file mode 100755 index 0000000..6b6cc52 --- /dev/null +++ b/ipcore_dir/hdmi_clk/simulation/functional/wave.sv @@ -0,0 +1,111 @@ +# file: wave.sv +# +# (c) Copyright 2008 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# +# Get the windows set up +# +if {[catch {window new WatchList -name "Design Browser 1" -geometry 1054x819+536+322}] != ""} { + window geometry "Design Browser 1" 1054x819+536+322 +} +window target "Design Browser 1" on +browser using {Design Browser 1} +browser set \ + -scope nc::hdmi_clk_tb +browser yview see nc::hdmi_clk_tb +browser timecontrol set -lock 0 + +if {[catch {window new WaveWindow -name "Waveform 1" -geometry 1010x600+0+541}] != ""} { + window geometry "Waveform 1" 1010x600+0+541 +} +window target "Waveform 1" on +waveform using {Waveform 1} +waveform sidebar visibility partial +waveform set \ + -primarycursor TimeA \ + -signalnames name \ + -signalwidth 175 \ + -units ns \ + -valuewidth 75 +cursor set -using TimeA -time 0 +waveform baseline set -time 0 +waveform xview limits 0 20000n + +# +# Define signal groups +# +catch {group new -name {Output clocks} -overlay 0} +catch {group new -name {Status/control} -overlay 0} +catch {group new -name {Counters} -overlay 0} + +set id [waveform add -signals [list {nc::hdmi_clk_tb.CLK_IN1}]] + +group using {Output clocks} +group set -overlay 0 +group set -comment {} +group clear 0 end + +group insert \ + {hdmi_clk_tb.dut.clk[1]} \ + {hdmi_clk_tb.dut.clk[2]} +group using {Counters} +group set -overlay 0 +group set -comment {} +group clear 0 end + +group insert \ + {hdmi_clk_tb.dut.counter[1]} \ + {hdmi_clk_tb.dut.counter[2]} + +set id [waveform add -signals [list {nc::hdmi_clk_tb.COUNT} ]] + +set id [waveform add -signals [list {nc::hdmi_clk_tb.test_phase} ]] +waveform format $id -radix %a + +set groupId [waveform add -groups {{Input clocks}}] +set groupId [waveform add -groups {{Output clocks}}] +set groupId [waveform add -groups {{Status/control}}] +set groupId [waveform add -groups {{Counters}}] diff --git a/ipcore_dir/hdmi_clk/simulation/hdmi_clk_tb.v b/ipcore_dir/hdmi_clk/simulation/hdmi_clk_tb.v new file mode 100755 index 0000000..d50264e --- /dev/null +++ b/ipcore_dir/hdmi_clk/simulation/hdmi_clk_tb.v @@ -0,0 +1,133 @@ +// file: hdmi_clk_tb.v +// +// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// + +//---------------------------------------------------------------------------- +// Clocking wizard demonstration testbench +//---------------------------------------------------------------------------- +// This demonstration testbench instantiates the example design for the +// clocking wizard. Input clocks are toggled, which cause the clocking +// network to lock and the counters to increment. +//---------------------------------------------------------------------------- + +`timescale 1ps/1ps + +`define wait_lock @(posedge dut.clknetwork.pll_base_inst.LOCKED) + +module hdmi_clk_tb (); + + // Clock to Q delay of 100ps + localparam TCQ = 100; + + + // timescale is 1ps/1ps + localparam ONE_NS = 1000; + localparam PHASE_ERR_MARGIN = 100; // 100ps + // how many cycles to run + localparam COUNT_PHASE = 1024; + // we'll be using the period in many locations + localparam time PER1 = 20.000*ONE_NS; + localparam time PER1_1 = PER1/2; + localparam time PER1_2 = PER1 - PER1/2; + + // Declare the input clock signals + reg CLK_IN1 = 1; + + // The high bits of the sampling counters + wire [2:1] COUNT; + reg COUNTER_RESET = 0; +wire [2:1] CLK_OUT; +//Freq Check using the M & D values setting and actual Frequency generated + + + // Input clock generation + //------------------------------------ + always begin + CLK_IN1 = #PER1_1 ~CLK_IN1; + CLK_IN1 = #PER1_2 ~CLK_IN1; + end + + // Test sequence + reg [15*8-1:0] test_phase = ""; + initial begin + // Set up any display statements using time to be readable + $timeformat(-12, 2, "ps", 10); + COUNTER_RESET = 0; + test_phase = "wait lock"; + `wait_lock; + #(PER1*6); + COUNTER_RESET = 1; + #(PER1*20) + COUNTER_RESET = 0; + + test_phase = "counting"; + #(PER1*COUNT_PHASE); + + $display("SIMULATION PASSED"); + $display("SYSTEM_CLOCK_COUNTER : %0d\n",$time/PER1); + $finish; + end + + // Instantiation of the example design containing the clock + // network and sampling counters + //--------------------------------------------------------- + hdmi_clk_exdes + #( + .TCQ (TCQ) + ) dut + (// Clock in ports + .CLK_IN1 (CLK_IN1), + // Reset for logic in example design + .COUNTER_RESET (COUNTER_RESET), + .CLK_OUT (CLK_OUT), + // High bits of the counters + .COUNT (COUNT)); + +// Freq Check + +endmodule diff --git a/ipcore_dir/hdmi_clk/simulation/timing/hdmi_clk_tb.v b/ipcore_dir/hdmi_clk/simulation/timing/hdmi_clk_tb.v new file mode 100755 index 0000000..956623a --- /dev/null +++ b/ipcore_dir/hdmi_clk/simulation/timing/hdmi_clk_tb.v @@ -0,0 +1,136 @@ +// file: hdmi_clk_tb.v +// +// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// + +//---------------------------------------------------------------------------- +// Clocking wizard demonstration testbench +//---------------------------------------------------------------------------- +// This demonstration testbench instantiates the example design for the +// clocking wizard. Input clocks are toggled, which cause the clocking +// network to lock and the counters to increment. +//---------------------------------------------------------------------------- + +`timescale 1ps/1ps + + +module hdmi_clk_tb (); + + // Clock to Q delay of 100ps + localparam TCQ = 100; + + + // timescale is 1ps/1ps + localparam ONE_NS = 1000; + localparam PHASE_ERR_MARGIN = 100; // 100ps + // how many cycles to run + localparam COUNT_PHASE = 1024; + // we'll be using the period in many locations + localparam time PER1 = 20.000*ONE_NS; + localparam time PER1_1 = PER1/2; + localparam time PER1_2 = PER1 - PER1/2; + + // Declare the input clock signals + reg CLK_IN1 = 1; + + // The high bits of the sampling counters + wire [2:1] COUNT; + reg COUNTER_RESET = 0; +wire [2:1] CLK_OUT; +//Freq Check using the M & D values setting and actual Frequency generated + + reg [13:0] timeout_counter = 14'b00000000000000; + + // Input clock generation + //------------------------------------ + always begin + CLK_IN1 = #PER1_1 ~CLK_IN1; + CLK_IN1 = #PER1_2 ~CLK_IN1; + end + + // Test sequence + reg [15*8-1:0] test_phase = ""; + initial begin + // Set up any display statements using time to be readable + $timeformat(-12, 2, "ps", 10); + $display ("Timing checks are not valid"); + COUNTER_RESET = 0; + test_phase = "wait lock"; + #(PER1*50); + #(PER1*6); + COUNTER_RESET = 1; + #(PER1*19.5) + COUNTER_RESET = 0; + #(PER1*1) + $display ("Timing checks are valid"); + test_phase = "counting"; + #(PER1*COUNT_PHASE); + + $display("SIMULATION PASSED"); + $display("SYSTEM_CLOCK_COUNTER : %0d\n",$time/PER1); + $finish; + end + + + + // Instantiation of the example design containing the clock + // network and sampling counters + //--------------------------------------------------------- + hdmi_clk_exdes + dut + (// Clock in ports + .CLK_IN1 (CLK_IN1), + // Reset for logic in example design + .COUNTER_RESET (COUNTER_RESET), + .CLK_OUT (CLK_OUT), + // High bits of the counters + .COUNT (COUNT)); + + +// Freq Check + +endmodule diff --git a/ipcore_dir/hdmi_clk/simulation/timing/sdf_cmd_file b/ipcore_dir/hdmi_clk/simulation/timing/sdf_cmd_file new file mode 100755 index 0000000..013059f --- /dev/null +++ b/ipcore_dir/hdmi_clk/simulation/timing/sdf_cmd_file @@ -0,0 +1,2 @@ +COMPILED_SDF_FILE = "../../implement/results/routed.sdf.X", +SCOPE = hdmi_clk_tb.dut; diff --git a/ipcore_dir/hdmi_clk/simulation/timing/simcmds.tcl b/ipcore_dir/hdmi_clk/simulation/timing/simcmds.tcl new file mode 100755 index 0000000..759c927 --- /dev/null +++ b/ipcore_dir/hdmi_clk/simulation/timing/simcmds.tcl @@ -0,0 +1,9 @@ +# file: simcmds.tcl + +# create the simulation script +vcd dumpfile isim.vcd +vcd dumpvars -m /hdmi_clk_tb -l 0 +wave add / +run 50000ns +quit + diff --git a/ipcore_dir/hdmi_clk/simulation/timing/simulate_isim.sh b/ipcore_dir/hdmi_clk/simulation/timing/simulate_isim.sh new file mode 100755 index 0000000..4d0e5df --- /dev/null +++ b/ipcore_dir/hdmi_clk/simulation/timing/simulate_isim.sh @@ -0,0 +1,62 @@ +# file: simulate_isim.sh +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +# create the project +vlogcomp -work work ${XILINX}/verilog/src/glbl.v +vlogcomp -work work ../../implement/results/routed.v +vlogcomp -work work hdmi_clk_tb.v + +# compile the project +fuse work.hdmi_clk_tb work.glbl -L secureip -L simprims_ver -o hdmi_clk_isim.exe + +# run the simulation script +./hdmi_clk_isim.exe -tclbatch simcmds.tcl -sdfmax /hdmi_clk_tb/dut=../../implement/results/routed.sdf + +# run the simulation script +#./hdmi_clk_isim.exe -gui -tclbatch simcmds.tcl diff --git a/ipcore_dir/hdmi_clk/simulation/timing/simulate_mti.bat b/ipcore_dir/hdmi_clk/simulation/timing/simulate_mti.bat new file mode 100755 index 0000000..67a386c --- /dev/null +++ b/ipcore_dir/hdmi_clk/simulation/timing/simulate_mti.bat @@ -0,0 +1,59 @@ +REM file: simulate_mti.bat +REM +REM (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +REM +REM This file contains confidential and proprietary information +REM of Xilinx, Inc. and is protected under U.S. and +REM international copyright and other intellectual property +REM laws. +REM +REM DISCLAIMER +REM This disclaimer is not a license and does not grant any +REM rights to the materials distributed herewith. Except as +REM otherwise provided in a valid license issued to you by +REM Xilinx, and to the maximum extent permitted by applicable +REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +REM (2) Xilinx shall not be liable (whether in contract or tort, +REM including negligence, or under any other theory of +REM liability) for any loss or damage of any kind or nature +REM related to, arising under or in connection with these +REM materials, including for any direct, or any indirect, +REM special, incidental, or consequential loss or damage +REM (including loss of data, profits, goodwill, or any type of +REM loss or damage suffered as a result of any action brought +REM by a third party) even if such damage or loss was +REM reasonably foreseeable or Xilinx had been advised of the +REM possibility of the same. +REM +REM CRITICAL APPLICATIONS +REM Xilinx products are not designed or intended to be fail- +REM safe, or for use in any application requiring fail-safe +REM performance, such as life-support or safety devices or +REM systems, Class III medical devices, nuclear facilities, +REM applications related to the deployment of airbags, or any +REM other applications that could lead to death, personal +REM injury, or severe property or environmental damage +REM (individually and collectively, "Critical +REM Applications"). Customer assumes the sole risk and +REM liability of any use of Xilinx products in Critical +REM Applications, subject only to applicable laws and +REM regulations governing limitations on product liability. +REM +REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +REM PART OF THIS FILE AT ALL TIMES. +REM +# set up the working directory +set work work +vlib work + +REM compile all of the files +vlog -work work %XILINX%\verilog\src\glbl.v +vlog -work work ..\..\implement\results\routed.v +vlog -work work hdmi_clk_tb.v + +REM run the simulation +vsim -c -t ps +transport_int_delays -voptargs="+acc" -L secureip -L simprims_ver -sdfmax hdmi_clk_tb\dut=..\..\implement\results\routed.sdf +no_notifier work.hdmi_clk_tb work.glbl diff --git a/ipcore_dir/hdmi_clk/simulation/timing/simulate_mti.do b/ipcore_dir/hdmi_clk/simulation/timing/simulate_mti.do new file mode 100755 index 0000000..a4d2946 --- /dev/null +++ b/ipcore_dir/hdmi_clk/simulation/timing/simulate_mti.do @@ -0,0 +1,65 @@ +# file: simulate_mti.do +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +# set up the working directory +set work work +vlib work + +# compile all of the files +vlog -work work $env(XILINX)/verilog/src/glbl.v +vlog -work work ../../implement/results/routed.v +vlog -work work hdmi_clk_tb.v + +# run the simulation +vsim -t ps +transport_int_delays -voptargs="+acc" -L secureip -L simprims_ver -sdfmax hdmi_clk_tb/dut=../../implement/results/routed.sdf +no_notifier work.hdmi_clk_tb work.glbl +#do wave.do +#log -r /* +run 50000ns + + diff --git a/ipcore_dir/hdmi_clk/simulation/timing/simulate_mti.sh b/ipcore_dir/hdmi_clk/simulation/timing/simulate_mti.sh new file mode 100755 index 0000000..f5ac4e9 --- /dev/null +++ b/ipcore_dir/hdmi_clk/simulation/timing/simulate_mti.sh @@ -0,0 +1,61 @@ +#/bin/sh +# file: simulate_mti.sh +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +# set up the working directory +set work work +vlib work + +# compile all of the files +vlog -work work $XILINX/verilog/src/glbl.v +vlog -work work ../../implement/results/routed.v +vlog -work work hdmi_clk_tb.v + +# run the simulation +vsim -c -t ps +transport_int_delays -voptargs="+acc" -L secureip -L simprims_ver -sdfmax hdmi_clk_tb/dut=../../implement/results/routed.sdf +no_notifier work.hdmi_clk_tb work.glbl diff --git a/ipcore_dir/hdmi_clk/simulation/timing/simulate_ncsim.sh b/ipcore_dir/hdmi_clk/simulation/timing/simulate_ncsim.sh new file mode 100755 index 0000000..894b56f --- /dev/null +++ b/ipcore_dir/hdmi_clk/simulation/timing/simulate_ncsim.sh @@ -0,0 +1,64 @@ +#!/bin/sh +# file: simulate_ncsim.sh +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +# set up the working directory +mkdir work + +# compile all of the files +ncvlog -work work ${XILINX}/verilog/src/glbl.v +ncvlog -work work ../../implement/results/routed.v +ncvlog -work work hdmi_clk_tb.v + +# elaborate and run the simulation +ncsdfc ../../implement/results/routed.sdf + +ncelab -work work -access +wc -pulse_r 10 -nonotifier work.hdmi_clk_tb work.glbl -sdf_cmd_file sdf_cmd_file +ncsim -input "@database -open -shm nc; probe -create -database nc -all -depth all; run 50000ns; exit" work.hdmi_clk_tb + diff --git a/ipcore_dir/hdmi_clk/simulation/timing/simulate_vcs.sh b/ipcore_dir/hdmi_clk/simulation/timing/simulate_vcs.sh new file mode 100755 index 0000000..d752b65 --- /dev/null +++ b/ipcore_dir/hdmi_clk/simulation/timing/simulate_vcs.sh @@ -0,0 +1,72 @@ +#!/bin/sh +# file: simulate_vcs.sh +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +# remove old files +rm -rf simv* csrc DVEfiles AN.DB + +# compile all of the files +# Note that -sverilog is not strictly required- You can +# remove the -sverilog if you change the type of the +# localparam for the periods in the testbench file to +# [63:0] from time + vlogan -sverilog \ + hdmi_clk_tb.v \ + ../../implement/results/routed.v + + +# prepare the simulation +vcs -sdf max:hdmi_clk_exdes:../../implement/results/routed.sdf +v2k -y $XILINX/verilog/src/simprims \ + +libext+.v -debug hdmi_clk_tb.v ../../implement/results/routed.v + +# run the simulation +./simv -ucli -i ucli_commands.key + +# launch the viewer +#dve -vpd vcdplus.vpd -session vcs_session.tcl diff --git a/ipcore_dir/hdmi_clk/simulation/timing/ucli_commands.key b/ipcore_dir/hdmi_clk/simulation/timing/ucli_commands.key new file mode 100755 index 0000000..0548d17 --- /dev/null +++ b/ipcore_dir/hdmi_clk/simulation/timing/ucli_commands.key @@ -0,0 +1,5 @@ + +call {$vcdpluson} +run 50000ns +call {$vcdplusclose} +quit diff --git a/ipcore_dir/hdmi_clk/simulation/timing/vcs_session.tcl b/ipcore_dir/hdmi_clk/simulation/timing/vcs_session.tcl new file mode 100755 index 0000000..1438f6b --- /dev/null +++ b/ipcore_dir/hdmi_clk/simulation/timing/vcs_session.tcl @@ -0,0 +1 @@ +gui_open_window Wave diff --git a/ipcore_dir/hdmi_clk/simulation/timing/wave.do b/ipcore_dir/hdmi_clk/simulation/timing/wave.do new file mode 100755 index 0000000..30e0e04 --- /dev/null +++ b/ipcore_dir/hdmi_clk/simulation/timing/wave.do @@ -0,0 +1,70 @@ +# file: wave.do +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate /hdmi_clk_tb/CLK_IN1 +add wave -noupdate /hdmi_clk_tb/COUNT +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {3223025 ps} 0} +configure wave -namecolwidth 238 +configure wave -valuecolwidth 107 +configure wave -justifyvalue left +configure wave -signalnamewidth 0 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits ps +update +WaveRestoreZoom {0 ps} {74848022 ps} diff --git a/ipcore_dir/hdmi_clk_flist.txt b/ipcore_dir/hdmi_clk_flist.txt new file mode 100644 index 0000000..41c361f --- /dev/null +++ b/ipcore_dir/hdmi_clk_flist.txt @@ -0,0 +1,55 @@ +# Output products list for +_xmsgs/pn_parser.xmsgs +hdmi_clk/clk_wiz_v3_6_readme.txt +hdmi_clk/doc/clk_wiz_v3_6_readme.txt +hdmi_clk/doc/clk_wiz_v3_6_vinfo.html +hdmi_clk/doc/pg065_clk_wiz.pdf +hdmi_clk/example_design/hdmi_clk_exdes.ucf +hdmi_clk/example_design/hdmi_clk_exdes.v +hdmi_clk/example_design/hdmi_clk_exdes.xdc +hdmi_clk/implement/implement.bat +hdmi_clk/implement/implement.sh +hdmi_clk/implement/planAhead_ise.bat +hdmi_clk/implement/planAhead_ise.sh +hdmi_clk/implement/planAhead_ise.tcl +hdmi_clk/implement/planAhead_rdn.bat +hdmi_clk/implement/planAhead_rdn.sh +hdmi_clk/implement/planAhead_rdn.tcl +hdmi_clk/implement/xst.prj +hdmi_clk/implement/xst.scr +hdmi_clk/simulation/functional/simcmds.tcl +hdmi_clk/simulation/functional/simulate_isim.bat +hdmi_clk/simulation/functional/simulate_isim.sh +hdmi_clk/simulation/functional/simulate_mti.bat +hdmi_clk/simulation/functional/simulate_mti.do +hdmi_clk/simulation/functional/simulate_mti.sh +hdmi_clk/simulation/functional/simulate_ncsim.sh +hdmi_clk/simulation/functional/simulate_vcs.sh +hdmi_clk/simulation/functional/ucli_commands.key +hdmi_clk/simulation/functional/vcs_session.tcl +hdmi_clk/simulation/functional/wave.do +hdmi_clk/simulation/functional/wave.sv +hdmi_clk/simulation/hdmi_clk_tb.v +hdmi_clk/simulation/timing/hdmi_clk_tb.v +hdmi_clk/simulation/timing/sdf_cmd_file +hdmi_clk/simulation/timing/simcmds.tcl +hdmi_clk/simulation/timing/simulate_isim.sh +hdmi_clk/simulation/timing/simulate_mti.bat +hdmi_clk/simulation/timing/simulate_mti.do +hdmi_clk/simulation/timing/simulate_mti.sh +hdmi_clk/simulation/timing/simulate_ncsim.sh +hdmi_clk/simulation/timing/simulate_vcs.sh +hdmi_clk/simulation/timing/ucli_commands.key +hdmi_clk/simulation/timing/vcs_session.tcl +hdmi_clk/simulation/timing/wave.do +hdmi_clk.asy +hdmi_clk.gise +hdmi_clk.sym +hdmi_clk.ucf +hdmi_clk.v +hdmi_clk.veo +hdmi_clk.xco +hdmi_clk.xdc +hdmi_clk.xise +hdmi_clk_flist.txt +hdmi_clk_xmdf.tcl diff --git a/ipcore_dir/hdmi_clk_xmdf.tcl b/ipcore_dir/hdmi_clk_xmdf.tcl new file mode 100755 index 0000000..06f09b0 --- /dev/null +++ b/ipcore_dir/hdmi_clk_xmdf.tcl @@ -0,0 +1,140 @@ +# The package naming convention is _xmdf +package provide hdmi_clk_xmdf 1.0 + +# This includes some utilities that support common XMDF operations +package require utilities_xmdf + +# Define a namespace for this package. The name of the name space +# is _xmdf +namespace eval ::hdmi_clk_xmdf { +# Use this to define any statics +} + +# Function called by client to rebuild the params and port arrays +# Optional when the use context does not require the param or ports +# arrays to be available. +proc ::hdmi_clk_xmdf::xmdfInit { instance } { +# Variable containg name of library into which module is compiled +# Recommendation: +# Required +utilities_xmdf::xmdfSetData $instance Module Attributes Name hdmi_clk +} +# ::hdmi_clk_xmdf::xmdfInit + +# Function called by client to fill in all the xmdf* data variables +# based on the current settings of the parameters +proc ::hdmi_clk_xmdf::xmdfApplyParams { instance } { + +set fcount 0 +# Array containing libraries that are assumed to exist +# Examples include unisim and xilinxcorelib +# Optional +# In this example, we assume that the unisim library will +# be magically +# available to the simulation and synthesis tool +utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library +utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hdmi_clk/clk_wiz_readme.txt +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hdmi_clk/doc/clk_wiz_ds709.pdf +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hdmi_clk/doc/clk_wiz_gsg521.pdf +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hdmi_clk/implement/implement.bat +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hdmi_clk/implement/implement.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hdmi_clk/implement/xst.prj +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hdmi_clk/implement/xst.scr +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hdmi_clk/simulation/hdmi_clk_tb.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hdmi_clk/simulation/functional/simcmds.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hdmi_clk/simulation/functional/simulate_isim.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hdmi_clk/simulation/functional/simulate_mti.do +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hdmi_clk/simulation/functional/simulate_ncsim.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hdmi_clk/simulation/functional/simulate_vcs.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hdmi_clk/simulation/functional/ucli_commands.key +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hdmi_clk/simulation/functional/vcs_session.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hdmi_clk/simulation/functional/wave.do +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hdmi_clk/simulation/functional/wave.sv +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hdmi_clk.asy +utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hdmi_clk.ejp +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hdmi_clk.ucf +utilities_xmdf::xmdfSetData $instance FileSet $fcount type ucf +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hdmi_clk.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hdmi_clk.veo +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hdmi_clk.xco +utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hdmi_clk_xmdf.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module hdmi_clk +incr fcount + +} + +# ::gen_comp_name_xmdf::xmdfApplyParams diff --git a/ipcore_dir/mb_bootloop_le.elf b/ipcore_dir/mb_bootloop_le.elf new file mode 100644 index 0000000..d8ff6c4 Binary files /dev/null and b/ipcore_dir/mb_bootloop_le.elf differ diff --git a/ipcore_dir/microblaze_mcs.asy b/ipcore_dir/microblaze_mcs.asy new file mode 100644 index 0000000..90ece3a --- /dev/null +++ b/ipcore_dir/microblaze_mcs.asy @@ -0,0 +1,45 @@ +Version 4 +SymbolType BLOCK +TEXT 32 32 LEFT 4 microblaze_mcs +RECTANGLE Normal 32 32 736 1728 +LINE Normal 0 80 32 80 +PIN 0 80 LEFT 36 +PINATTR PinName clk +PINATTR Polarity IN +LINE Normal 0 112 32 112 +PIN 0 112 LEFT 36 +PINATTR PinName reset +PINATTR Polarity IN +LINE Normal 768 656 736 656 +PIN 768 656 RIGHT 36 +PINATTR PinName gpi2_interrupt +PINATTR Polarity OUT +LINE Wide 0 304 32 304 +PIN 0 304 LEFT 36 +PINATTR PinName gpi1[7:0] +PINATTR Polarity IN +LINE Wide 0 336 32 336 +PIN 0 336 LEFT 36 +PINATTR PinName gpi2[0:0] +PINATTR Polarity IN +LINE Wide 0 368 32 368 +PIN 0 368 LEFT 36 +PINATTR PinName gpi3[1:0] +PINATTR Polarity IN +LINE Wide 768 784 736 784 +PIN 768 784 RIGHT 36 +PINATTR PinName gpo1[15:0] +PINATTR Polarity OUT +LINE Wide 768 816 736 816 +PIN 768 816 RIGHT 36 +PINATTR PinName gpo2[15:0] +PINATTR Polarity OUT +LINE Wide 768 848 736 848 +PIN 768 848 RIGHT 36 +PINATTR PinName gpo3[0:0] +PINATTR Polarity OUT +LINE Wide 768 880 736 880 +PIN 768 880 RIGHT 36 +PINATTR PinName gpo4[5:0] +PINATTR Polarity OUT + diff --git a/ipcore_dir/microblaze_mcs.bmm b/ipcore_dir/microblaze_mcs.bmm new file mode 100644 index 0000000..b71facc --- /dev/null +++ b/ipcore_dir/microblaze_mcs.bmm @@ -0,0 +1,16 @@ +ADDRESS_MAP microblaze_mcs MICROBLAZE-LE 100 + ADDRESS_SPACE lmb_bram COMBINED [0x00000000:0x00003fff] + ADDRESS_RANGE RAMB16 + BUS_BLOCK + mcs_0/U0/lmb_bram_I/RAM_Inst/Using_B16_S4.The_BRAMs[0].RAMB16_S4_1 [31:28] INPUT = microblaze_mcs.lmb_bram_0.mem; + mcs_0/U0/lmb_bram_I/RAM_Inst/Using_B16_S4.The_BRAMs[1].RAMB16_S4_1 [27:24] INPUT = microblaze_mcs.lmb_bram_1.mem; + mcs_0/U0/lmb_bram_I/RAM_Inst/Using_B16_S4.The_BRAMs[2].RAMB16_S4_1 [23:20] INPUT = microblaze_mcs.lmb_bram_2.mem; + mcs_0/U0/lmb_bram_I/RAM_Inst/Using_B16_S4.The_BRAMs[3].RAMB16_S4_1 [19:16] INPUT = microblaze_mcs.lmb_bram_3.mem; + mcs_0/U0/lmb_bram_I/RAM_Inst/Using_B16_S4.The_BRAMs[4].RAMB16_S4_1 [15:12] INPUT = microblaze_mcs.lmb_bram_4.mem; + mcs_0/U0/lmb_bram_I/RAM_Inst/Using_B16_S4.The_BRAMs[5].RAMB16_S4_1 [11:8] INPUT = microblaze_mcs.lmb_bram_5.mem; + mcs_0/U0/lmb_bram_I/RAM_Inst/Using_B16_S4.The_BRAMs[6].RAMB16_S4_1 [7:4] INPUT = microblaze_mcs.lmb_bram_6.mem; + mcs_0/U0/lmb_bram_I/RAM_Inst/Using_B16_S4.The_BRAMs[7].RAMB16_S4_1 [3:0] INPUT = microblaze_mcs.lmb_bram_7.mem; + END_BUS_BLOCK; + END_ADDRESS_RANGE; + END_ADDRESS_SPACE; +END_ADDRESS_MAP; diff --git a/ipcore_dir/microblaze_mcs.gise b/ipcore_dir/microblaze_mcs.gise new file mode 100644 index 0000000..c088017 --- /dev/null +++ b/ipcore_dir/microblaze_mcs.gise @@ -0,0 +1,49 @@ + + + + + + + + + + + + + + + + + + + + 11.1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ipcore_dir/microblaze_mcs.ncf b/ipcore_dir/microblaze_mcs.ncf new file mode 100644 index 0000000..e69de29 diff --git a/ipcore_dir/microblaze_mcs.ngc b/ipcore_dir/microblaze_mcs.ngc new file mode 100644 index 0000000..9c33565 --- /dev/null +++ b/ipcore_dir/microblaze_mcs.ngc @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.6e 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+ + + + + + + + +

test Project Status
Project File:	test.xmp	Implementation State:	New
Module Name:	test	Errors:
Product Version:	EDK 14.7	Warnings:

XPS Reports					[-]
Report Name	Generated	Errors	Warnings	Infos
Platgen Log File
Simgen Log File
BitInit Log File
System Log File	Mon Sep 14 18:25:51 2020

Detailed Reports						[-]
Report Name	Status	Generated	Errors	Warnings	Infos
Translation Report
Map Report
Place and Route Report
Post-PAR Static Timing Report
Bitgen Report

Secondary Reports			[-]
Report Name	Status	Generated