From e8bedf9b14cdd2a4e340e89a218f1c972acd53eb Mon Sep 17 00:00:00 2001
From: Dreaded_X <tim.huizinga@gmail.com>
Date: Sat, 19 Sep 2020 22:23:51 +0200
Subject: [PATCH] Latest changes

---
 HDMI.alp           |  5 +++--
 constraint/z80.ucf |  8 ++++----
 source/mojo_top.v  |  3 +++
 source/sram.v      | 45 +++++++++++++++++++++++++--------------------
 4 files changed, 35 insertions(+), 26 deletions(-)

diff --git a/HDMI.alp b/HDMI.alp
index 681dfbe..b9ea4db 100644
--- a/HDMI.alp
+++ b/HDMI.alp
@@ -1,5 +1,5 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<project name="HDMI" board="Mojo" language="Verilog" version="2">
+<project name="HDMI" board="Mojo" language="Verilog" version="3">
   <files>
     <src>hdmi_encoder.luc</src>
     <src top="true">mojo_top.v</src>
@@ -9,9 +9,10 @@
     <component>dvi_globals.luc</component>
     <component>avr_interface.luc</component>
     <component>dvi_encoder.luc</component>
-    <component>spi_slave.luc</component>
+    <component>spi_peripheral.luc</component>
     <component>uart_tx.luc</component>
     <component>serdes_n_to_1.luc</component>
+    <src>spi_slave.luc</src>
     <component>simple_dual_ram.v</component>
     <component>async_fifo.luc</component>
     <component>cclk_detector.luc</component>
diff --git a/constraint/z80.ucf b/constraint/z80.ucf
index b2632e0..75d6e5e 100644
--- a/constraint/z80.ucf
+++ b/constraint/z80.ucf
@@ -1,8 +1,8 @@
 NET "z80_clk" LOC = P23 | IOSTANDARD = LVTTL;
-NET "z80_data(2)" LOC = P114 | IOSTANDARD = LVTTL;
-NET "z80_data(3)" LOC = P115 | IOSTANDARD = LVTTL;
-NET "z80_data(1)" LOC = P116 | IOSTANDARD = LVTTL;
-NET "z80_data(0)" LOC = P117 | IOSTANDARD = LVTTL;
+NET "z80_data(1)" LOC = P114 | IOSTANDARD = LVTTL;
+NET "z80_data(0)" LOC = P115 | IOSTANDARD = LVTTL;
+NET "z80_data(2)" LOC = P116 | IOSTANDARD = LVTTL;
+NET "z80_data(3)" LOC = P117 | IOSTANDARD = LVTTL;
 NET "z80_data(4)" LOC = P118 | IOSTANDARD = LVTTL;
 NET "z80_data(5)" LOC = P119 | IOSTANDARD = LVTTL;
 NET "z80_data(6)" LOC = P120 | IOSTANDARD = LVTTL;
diff --git a/source/mojo_top.v b/source/mojo_top.v
index 90c3af1..8f61d12 100644
--- a/source/mojo_top.v
+++ b/source/mojo_top.v
@@ -210,6 +210,7 @@ reg write_enable, write_enable_c_q, write_enable_c_d;
 wire[7:0] sram_read_data;
 sram #(.SIZE(8), .DEPTH(CHAR_HMAX*CHAR_VMAX)) sram(
 	.clk(hdmi_clk),
+	.rst(rst),
 	.read_address(char_index_q),
 	.write_address(addr_q-1),
 	.read_data(sram_read_data),
@@ -306,6 +307,7 @@ always @(negedge z80_ioreq) begin
 		bottom_t = 1;
 		scroll_t = scroll_q + 1;
 	end else if ((bottom_q == 1) && ((addr_t >= (scroll_q*CHAR_HMAX)) || (addr_n >= (scroll_q*CHAR_HMAX)) || (addr_r >= (scroll_q*CHAR_HMAX)))) begin
+		// Reset line
 		scroll_t = scroll_q + 1;
 	end
 
@@ -317,6 +319,7 @@ always @(negedge z80_ioreq) begin
 		addr_b = addr_b - 1;
 	end
 
+	// @todo If we underflow (-1) we do not end up in the right spot (makes sense)
 	addr_t = addr_t % (CHAR_HMAX*CHAR_VMAX);
 	addr_n = addr_n % (CHAR_HMAX*CHAR_VMAX);
 	addr_r = addr_r % (CHAR_HMAX*CHAR_VMAX);
diff --git a/source/sram.v b/source/sram.v
index d84a9f9..9f78149 100644
--- a/source/sram.v
+++ b/source/sram.v
@@ -1,22 +1,27 @@
 module sram #(
-    parameter SIZE = 1,
-    parameter DEPTH = 1
-  )(
-    input clk,
-    input [$clog2(DEPTH)-1:0] read_address,
-    input [$clog2(DEPTH)-1:0] write_address,
-    output reg [SIZE-1:0] read_data,
-    input [SIZE-1:0] write_data,
-    input write_en
-  );
- 
-  reg [SIZE-1:0] ram [DEPTH-1:0];
- 
-  always @(posedge clk) begin
-    read_data <= ram[read_address];
- 
-    if (write_en)
-      ram[write_address] <= write_data;
-  end
- 
+	parameter SIZE = 1,
+	parameter DEPTH = 1
+)(
+	input clk,
+	input rst,
+	input [$clog2(DEPTH)-1:0] read_address,
+	input [$clog2(DEPTH)-1:0] write_address,
+	output reg [SIZE-1:0] read_data,
+	input [SIZE-1:0] write_data,
+	input write_en
+);
+
+reg [SIZE-1:0] ram [DEPTH-1:0];
+
+reg [DEPTH-1:0] valid;
+
+always @(posedge clk) begin
+	read_data <= ram[read_address] * valid[read_address];
+
+	if (write_en) begin
+		valid[write_address] <= 1;
+		ram[write_address] <= write_data;
+	end
+end
+
 endmodule