xilinx.com project coregen 1.0 hdmi_clk hdmi_clk true false false false false No_Jitter false false 50 Units_MHz Units_UI REL_PRIMARY 100.000 UI 0.010 0.010 0.010 0.010 200.0 100.0 true false false false false false 2 false false false false false false false CLK_IN1 CLK_OUT1 CLK_OUT2 CLK_OUT3 CLK_OUT4 CLK_OUT5 CLK_OUT6 CLK_OUT7 DADDR DCLK DRDY DWE DIN DOUT DEN PSCLK PSEN PSINCDEC PSDONE 75 0.000 50.000 150 0.000 50.000 100.000 0.000 50.000 100.000 0.000 50.000 100.000 0.000 50.000 100.000 0.000 50.000 100.000 0.000 50.000 false false Single_ended_clock_capable_pin false CLK_IN2 Single_ended_clock_capable_pin BUFG BUFG BUFG BUFG BUFG BUFG BUFG FDBK_AUTO SINGLE CLKFB_IN CLKFB_IN_P CLKFB_IN_N CLKFB_OUT CLKFB_OUT_P CLKFB_OUT_N lin64 empty false DONE false false false false false false false RESET LOCKED POWER_DOWN CLK_VALID STATUS CLK_IN_SEL INPUT_CLK_STOPPED CLKFB_STOPPED false None 1 OPTIMIZED 4.000 0.000 false 10.000 10.000 false false ZHOLD 0.010 0.010 false 4.000 0.500 0.000 false 1 0.500 0.000 false 1 0.500 0.000 false 1 0.500 0.000 false 1 0.500 0.000 false 1 0.500 0.000 false 1 0.500 0.000 false false None 2.0 2 3 false 20.000 NONE SYSTEM_SYNCHRONOUS 0 NONE false CLKFX CLK0 CLK0 CLK0 CLK0 CLK0 false None 1 4 2 0.000 false 10.000 NONE CLKFX CLKFX CLKFX false None OPTIMIZED 9 0.000 CLKFBOUT 1 20.000 INTERNAL 0.010 6 0.500 0.000 3 0.500 0.000 1 0.500 0.000 1 0.500 0.000 1 0.500 0.000 1 0.500 0.000 NONE AUTO PLL_BASE MMCM CENTER_HIGH 250 hdmi_clk coregen ./ ./tmp/ ./tmp/_cg/ xc6slx9 spartan6 tqg144 -2 BusFormatAngleBracketNotRipped Verilog true Other false false false Ngc false Behavioral Verilog false 2012-05-10+12:44 microblaze_mcs USER2 microblaze_mcs_v1_4 mcs_0 150 false false 16KB false false false 9600 false 8 false Even false false false false 6216 false false 6216 false false 6216 false false 6216 false false 32 true None false false 32 true None false false 32 true None false false 32 true None false true 8 0x00000000 true 16 0x00000000 true 2 0x00000000 true 6 0x00000000 true 8 None true 1 Falling_Edge true 2 None false 32 None false 1 0x0000 0xFFFF microblaze_mcs coregen ./ ./tmp/ ./tmp/_cg/ xc6slx9 spartan6 tqg144 -2 BusFormatAngleBracketNotRipped Verilog true Other false false false Ngc false Behavioral Verilog false 2012-11-21+08:11 coregen ./ ./tmp/ ./tmp/_cg/ xc6slx9 spartan6 tqg144 -2 BusFormatAngleBracketNotRipped Verilog true Other false false false Ngc false Behavioral Verilog false