Generating IP... Verilog simulation file type 'Behavioral' is not valid for this core. Overriding with simulation file type 'Structural'. A core named 'microblaze_mcs' already exists in the project. Output products for this core may be overwritten. Verilog simulation file type 'Behavioral' is not valid for this core. Overriding with simulation file type 'Structural'. A core named 'microblaze_mcs' already exists in the project. Output products for this core may be overwritten. Pre-processing HDL files for 'microblaze_mcs'... Running microblaze_mcs_gen_script.tcl Please source the "microblaze_mcs_setup.tcl" script in the Tcl Console to complete MicroBlaze MCS core generation Verilog simulation file type 'Behavioral' is not valid for this core. Overriding with simulation file type 'Structural'. Verilog simulation file type 'Behavioral' is not valid for this core. Overriding with simulation file type 'Structural'. Running microblaze_mcs_sim_script.tcl C_MICROBLAZE_INSTANCE = microblaze_mcs Netlist filename = ./_cg/microblaze_mcs.v Setting INIT_FILE = "microblaze_mcs.lmb_bram_7.mem" for BRAM 7 Setting INIT_FILE = "microblaze_mcs.lmb_bram_6.mem" for BRAM 6 Setting INIT_FILE = "microblaze_mcs.lmb_bram_5.mem" for BRAM 5 Setting INIT_FILE = "microblaze_mcs.lmb_bram_4.mem" for BRAM 4 Setting INIT_FILE = "microblaze_mcs.lmb_bram_3.mem" for BRAM 3 Setting INIT_FILE = "microblaze_mcs.lmb_bram_2.mem" for BRAM 2 Setting INIT_FILE = "microblaze_mcs.lmb_bram_1.mem" for BRAM 1 Setting INIT_FILE = "microblaze_mcs.lmb_bram_0.mem" for BRAM 0 Finished generation of ASY schematic symbol. Finished FLIST file generation.