Enable Fault Tolerance Support Select implementation to optimize area (with lower instruction throughput) Select Bus Interfaces Select Stream Interfaces Enable Additional Machine Status Register Instructions Enable Pattern Comparator Enable Barrel Shifter Enable Integer Divider Enable Integer Multiplier Enable Floating Point Unit Enable Reversed Load/Store and Swap Instructions Enable Unaligned Data Exception Enable Illegal Instruction Exception Enable Instruction-side AXI Exception Enable Data-side AXI Exception Enable Instruction-side PLB Exception Enable Data-side PLB Exception Enable Integer Divide Exception Enable Floating Point Unit Exceptions Enable Stream Exception <qt>Enable stack protection</qt> Specifies Processor Version Register Specify USER1 Bits in Processor Version Register Specify USER2 Bits in Processor Version Registers Enable MicroBlaze Debug Module Interface Number of PC Breakpoints Number of Read Address Watchpoints Number of Write Address Watchpoints Sense Interrupt on Edge vs. Level Sense Interrupt on Rising vs. Falling Edge Specify Reset Value for Select MSR Bits <qt>Generate Illegal Instruction Exception for NULL Instruction</qt> Number of Stream Links Enable Additional Stream Instructions Base Address High Address Enable Instruction Cache Enable Writes Size in Bytes Line Length Use Cache Links for All Memory Accesses Number of Victims Number of Streams Use Distributed RAM for Tags Data Width Base Address High Address Enable Data Cache Enable Writes Size in Bytes Line Length Use Cache Links for All Memory Accesses Enable Write-back Storage Policy Number of Victims Use Distributed RAM for Tags Data Width Memory Management Data Shadow Translation Look-Aside Buffer Size Instruction Shadow Translation Look-Aside Buffer Size Enable Access to Memory Management Special Registers Number of Memory Protection Zones Privileged Instructions Enable Branch Target Cache Branch Target Cache Size Local Memory Bus (LMB) 1.0 'The LMB is a fast, local bus for connecting MicroBlaze I and D ports to peripherals and BRAM' Number of Bus Slaves LMB Address Bus Width LMB Data Bus Width Active High External Reset Local Memory Bus (LMB) 1.0 'The LMB is a fast, local bus for connecting MicroBlaze I and D ports to peripherals and BRAM' Number of Bus Slaves LMB Address Bus Width LMB Data Bus Width Active High External Reset LMB BRAM Base Address LMB BRAM High Address SLMB Address Decode Mask SLMB1 Address Decode Mask SLMB2 Address Decode Mask SLMB3 Address Decode Mask LMB Address Bus Width LMB Data Bus Width Error Correction Code Select Interconnect Fault Inject Registers Correctable Error First Failing Register Uncorrectable Error First Failing Register ECC Status and Control Register ECC On/Off Register ECC On/Off Reset Value Correctable Error Counter Register Width Write Access setting Number of LMB ports Base Address for PLB Interface High Address for PLB Interface PLB Address Bus Width PLB Data Bus Width PLB Slave Uses P2P Topology Master ID Bus Width of PLB Number of PLB Masters PLB Slave is Capable of Bursts Native Data Bus Width of PLB Slave Frequency of PLB Slave S_AXI_CTRL Clock Frequency S_AXI_CTRL Base Address S_AXI_CTRL High Address S_AXI_CTRL Address Width S_AXI_CTRL Data Width S_AXI_CTRL Protocol LMB BRAM Base Address LMB BRAM High Address SLMB Address Decode Mask SLMB1 Address Decode Mask SLMB2 Address Decode Mask SLMB3 Address Decode Mask LMB Address Bus Width LMB Data Bus Width Error Correction Code Select Interconnect Fault Inject Registers Correctable Error First Failing Register Uncorrectable Error First Failing Register ECC Status and Control Register ECC On/Off Register ECC On/Off Reset Value Correctable Error Counter Register Width Write Access setting Number of LMB ports Base Address for PLB Interface High Address for PLB Interface PLB Address Bus Width PLB Data Bus Width PLB Slave Uses P2P Topology Master ID Bus Width of PLB Number of PLB Masters PLB Slave is Capable of Bursts Native Data Bus Width of PLB Slave Frequency of PLB Slave S_AXI_CTRL Clock Frequency S_AXI_CTRL Base Address S_AXI_CTRL High Address S_AXI_CTRL Address Width S_AXI_CTRL Data Width S_AXI_CTRL Protocol Block RAM (BRAM) Block The BRAM Block is a configurable memory module that attaches to a variety of BRAM Interface Controllers. Size of BRAM(s) in Bytes Data Width of Port A and B Address Width of Port A and B Number of Byte Write Enables Device Family LMB I/O Module LMB module which includes plenty of I/O peripherals I/O Module Register Base Address I/O Module Register High Address I/O Module Register Address Decode Mask I/O Module IO Bus Base Address I/O Module IO Bus High Address I/O Module IO Bus Address Decode Mask LMB Address Bus Width LMB Data Bus Width Enable IO Bus Enable Receiver Enable Transmitter Define Baud Rate Number of Data Bits Use Parity Even or Odd Parity Implement Receive Interrupt Implement Transmit Interrupt Implement Error Interrupt Programmable Baud Rate Use FIT Number of Clocks Between Strobes Generate Interrupt Use FIT Number of Clocks Between Strobes Generate Interrupt Use FIT Number of Clocks Between Strobes Generate Interrupt Use FIT Number of Clocks Between Strobes Generate Interrupt Use PIT Number of Bits for Timer Shall Counter Value Be Readable Define Prescaler Generate Interrupt Use PIT Number of Bits for Timer Shall Counter Value Be Readable Define Prescaler Generate Interrupt Use PIT Number of Bits for Timer Shall Counter Value be Readable Define Prescaler Generate Interrupt Use PIT Number of Bits for Timer Shall Counter Value Be Readable Define Prescaler Generate Interrupt Use GPO Number of Bits Initial Value of GPO Use GPO Number of Bits Initial Value of GPO Use GPO Number of Bits Initial Value of GPO Use GPO Number of Bits Initial Value of GPO Use GPI Number of Bits Generate Interrupt Use GPI Number of Bits Generate Interrupt Use GPI Number of Bits Generate Interrupt Use GPI Number of Bits Generate Interrupt Use External Interrupts Number of External Inputs Use Low-latency Interrupt Handling Serial Data In Serial Data Out Interrupt Inputs Interrupt Request Output Interrupt Vector Address Output Interrupt Acknowledgement Input