xilinx.com CoreGen coregen 1.0 clk_wiz_v3_6 clk_wiz_v3_6 true false false false false No_Jitter false false 50.000 Units_MHz Units_UI REL_PRIMARY 100.000 UI 0.010 0.010 0.010 0.010 200.0 100.0 false false false false false false 1 false false false false false false false CLK_IN1 CLK_OUT1 CLK_OUT2 CLK_OUT3 CLK_OUT4 CLK_OUT5 CLK_OUT6 CLK_OUT7 DADDR DCLK DRDY DWE DIN DOUT DEN PSCLK PSEN PSINCDEC PSDONE 75.000 0.000 50.000 100.000 0.000 50.000 100.000 0.000 50.000 100.000 0.000 50.000 100.000 0.000 50.000 100.000 0.000 50.000 100.000 0.000 50.000 false false Single_ended_clock_capable_pin false CLK_IN2 Single_ended_clock_capable_pin BUFG BUFG BUFG BUFG BUFG BUFG BUFG FDBK_AUTO SINGLE CLKFB_IN CLKFB_IN_P CLKFB_IN_N CLKFB_OUT CLKFB_OUT_P CLKFB_OUT_N nt empty false DONE false false false false false false false RESET LOCKED POWER_DOWN CLK_VALID STATUS CLK_IN_SEL INPUT_CLK_STOPPED CLKFB_STOPPED false None 1 OPTIMIZED 4.000 0.000 false 10.000 10.000 false false ZHOLD 0.010 0.010 false 4.000 0.500 0.000 false 1 0.500 0.000 false 1 0.500 0.000 false 1 0.500 0.000 false 1 0.500 0.000 false 1 0.500 0.000 false 1 0.500 0.000 false false None 2.0 2 3 false 20.000 NONE SYSTEM_SYNCHRONOUS 0 NONE false CLKFX CLK0 CLK0 CLK0 CLK0 CLK0 false None 1 4 2 0.000 false 10.000 NONE CLKFX CLKFX CLKFX false None OPTIMIZED 8 0.000 CLKFBOUT 1 20.0 INTERNAL 0.010 128 0.500 0.000 1 0.500 0.000 1 0.500 0.000 1 0.500 0.000 1 0.500 0.000 1 0.500 0.000 NONE AUTO PLL_BASE MMCM CENTER_HIGH 250 0 0 0 0 0 0 clk_wiz_v3_6 nt 1 0 0.010 0.010 No_Jitter 0 0 0 0 0 0 0 0 DCM_SP 0 50.000 Units_MHz 100.000 FDBK_AUTO Single_ended_clock_capable_pin Single_ended_clock_capable_pin SINGLE 0 0 0 0 0 0 0 1 BUFG BUFG BUFG BUFG BUFG BUFG BUFG __primary__________50.000____________0.010 no_secondary_input_clock CLK_OUT1____75.000______0.000______50.0______466.667____150.000 no_CLK_OUT2_output no_CLK_OUT3_output no_CLK_OUT4_output no_CLK_OUT5_output no_CLK_OUT6_output no_CLK_OUT7_output 75.000 100.000 100.000 100.000 100.000 100.000 100.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 50.000 50.000 50.000 50.000 50.000 50.000 50.000 75.000 N/A N/A N/A N/A N/A N/A 0.000 N/A N/A N/A N/A N/A N/A 50.0 N/A N/A N/A N/A N/A N/A None OPTIMIZED 4.000 10.000 10.000 FALSE FALSE ZHOLD 1 0.010 0.010 FALSE 4.000 1 1 1 1 1 1 0.500 0.500 0.500 0.500 0.500 0.500 0.500 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE None OPTIMIZED CLKFBOUT 8 20.0 INTERNAL 1 0.010 128 1 1 1 1 1 0.500 0.500 0.500 0.500 0.500 0.500 0.000 0.000 0.000 0.000 0.000 0.000 0.000 None 2.000 2 3 FALSE 20.0 NONE NONE NONE SYSTEM_SYNCHRONOUS 0 FALSE CLKFX NONE NONE NONE NONE NONE None 2 1 4 20.0 0.000 NONE FALSE CLKFX NONE NONE AUTO 0 0 0 0 NONE CLK_IN1 CLK_IN2 CLK_OUT1 CLK_OUT2 CLK_OUT3 CLK_OUT4 CLK_OUT5 CLK_OUT6 CLK_OUT7 RESET LOCKED CLKFB_IN CLKFB_IN_P CLKFB_IN_N CLKFB_OUT CLKFB_OUT_P CLKFB_OUT_N POWER_DOWN DADDR DCLK DRDY DWE DIN DOUT DEN PSCLK PSEN PSINCDEC PSDONE CLK_VALID STATUS CLK_IN_SEL INPUT_CLK_STOPPED CLKFB_STOPPED 200.0 100.0 MMCM CENTER_HIGH 4000 coregen ./ C:/Program Files/Alchitry/Alchitry Labs/ C:/Program Files/Alchitry/Alchitry Labs/_cg/ xc6slx9 spartan6 tqg144 -2 BusFormatAngleBracketNotRipped Verilog true Other false false false Ngc false Behavioral Verilog false 2012-05-10+12:44 apply_current_project_options_generator customization_generator model_parameter_resolution_generator ip_xco_generator ./clk_wiz_v3_6.xco xco Fri Feb 28 22:02:23 GMT 2020 0x8939EF15 generationID_1879581046 tcl_flow_generator ./clk_wiz_v3_6/example_design/clk_wiz_v3_6_exdes.ucf ignore ucf Fri Feb 28 22:02:34 GMT 2020 0x19A045DD generationID_1879581046 ./clk_wiz_v3_6/example_design/clk_wiz_v3_6_exdes.v ignore verilog Fri Feb 28 22:02:24 GMT 2020 0xAC64F57E generationID_1879581046 ./clk_wiz_v3_6/example_design/clk_wiz_v3_6_exdes.xdc ignore xdc Fri Feb 28 22:02:34 GMT 2020 0x38870E64 generationID_1879581046 ./clk_wiz_v3_6/implement/implement.bat ignore unknown Fri Feb 28 22:02:33 GMT 2020 0x4ED49AF9 generationID_1879581046 ./clk_wiz_v3_6/implement/implement.sh ignore unknown Fri Feb 28 22:02:33 GMT 2020 0xEFECD5E5 generationID_1879581046 ./clk_wiz_v3_6/implement/planAhead_ise.bat ignore unknown Fri Feb 28 22:02:31 GMT 2020 0x6966A508 generationID_1879581046 ./clk_wiz_v3_6/implement/planAhead_ise.sh ignore unknown Fri Feb 28 22:02:32 GMT 2020 0x7F8B5943 generationID_1879581046 ./clk_wiz_v3_6/implement/planAhead_ise.tcl ignore tcl Fri Feb 28 22:02:32 GMT 2020 0x0F692296 generationID_1879581046 ./clk_wiz_v3_6/implement/planAhead_rdn.bat ignore unknown Fri Feb 28 22:02:32 GMT 2020 0xB9373CFA generationID_1879581046 ./clk_wiz_v3_6/implement/planAhead_rdn.sh ignore unknown Fri Feb 28 22:02:32 GMT 2020 0xDCE9D96C generationID_1879581046 ./clk_wiz_v3_6/implement/planAhead_rdn.tcl ignore tcl Fri Feb 28 22:02:33 GMT 2020 0xA3D65585 generationID_1879581046 ./clk_wiz_v3_6/implement/xst.prj ignore unknown Fri Feb 28 22:02:34 GMT 2020 0x49D219A7 generationID_1879581046 ./clk_wiz_v3_6/implement/xst.scr ignore unknown Fri Feb 28 22:02:35 GMT 2020 0x316C95E2 generationID_1879581046 ./clk_wiz_v3_6/simulation/clk_wiz_v3_6_tb.v ignore verilog Fri Feb 28 22:02:25 GMT 2020 0x747CB764 generationID_1879581046 ./clk_wiz_v3_6/simulation/functional/simcmds.tcl ignore tcl Fri Feb 28 22:02:30 GMT 2020 0x18DD8E59 generationID_1879581046 ./clk_wiz_v3_6/simulation/functional/simulate_isim.bat ignore unknown Fri Feb 28 22:02:29 GMT 2020 0x2B81F5D5 generationID_1879581046 ./clk_wiz_v3_6/simulation/functional/simulate_isim.sh ignore unknown Fri Feb 28 22:02:29 GMT 2020 0x9FCFD1F7 generationID_1879581046 ./clk_wiz_v3_6/simulation/functional/simulate_mti.bat ignore unknown Fri Feb 28 22:02:27 GMT 2020 0xFD2E9ECE generationID_1879581046 ./clk_wiz_v3_6/simulation/functional/simulate_mti.do ignore unknown Fri Feb 28 22:02:27 GMT 2020 0xA4A47524 generationID_1879581046 ./clk_wiz_v3_6/simulation/functional/simulate_mti.sh ignore unknown Fri Feb 28 22:02:27 GMT 2020 0xC9A4E9E6 generationID_1879581046 ./clk_wiz_v3_6/simulation/functional/simulate_ncsim.sh ignore unknown Fri Feb 28 22:02:28 GMT 2020 0x2901E532 generationID_1879581046 ./clk_wiz_v3_6/simulation/functional/simulate_vcs.sh ignore unknown Fri Feb 28 22:02:30 GMT 2020 0x52343BF0 generationID_1879581046 ./clk_wiz_v3_6/simulation/functional/ucli_commands.key ignore unknown Fri Feb 28 22:02:31 GMT 2020 0x8C15B41F generationID_1879581046 ./clk_wiz_v3_6/simulation/functional/vcs_session.tcl ignore tcl Fri Feb 28 22:02:31 GMT 2020 0xDBAB8E4B generationID_1879581046 ./clk_wiz_v3_6/simulation/functional/wave.do ignore unknown Fri Feb 28 22:02:28 GMT 2020 0x87ADB985 generationID_1879581046 ./clk_wiz_v3_6/simulation/functional/wave.sv ignore unknown Fri Feb 28 22:02:29 GMT 2020 0x71E0D404 generationID_1879581046 ./clk_wiz_v3_6/simulation/timing/clk_wiz_v3_6_tb.v ignore verilog Fri Feb 28 22:02:25 GMT 2020 0xF4B97746 generationID_1879581046 ./clk_wiz_v3_6/simulation/timing/sdf_cmd_file ignore unknown Fri Feb 28 22:02:29 GMT 2020 0x3E480C11 generationID_1879581046 ./clk_wiz_v3_6/simulation/timing/simcmds.tcl ignore tcl Fri Feb 28 22:02:30 GMT 2020 0x84642126 generationID_1879581046 ./clk_wiz_v3_6/simulation/timing/simulate_isim.sh ignore unknown Fri Feb 28 22:02:30 GMT 2020 0xF857D9E0 generationID_1879581046 ./clk_wiz_v3_6/simulation/timing/simulate_mti.bat ignore unknown Fri Feb 28 22:02:27 GMT 2020 0x559888D5 generationID_1879581046 ./clk_wiz_v3_6/simulation/timing/simulate_mti.do ignore unknown Fri Feb 28 22:02:28 GMT 2020 0xA99E36D0 generationID_1879581046 ./clk_wiz_v3_6/simulation/timing/simulate_mti.sh ignore unknown Fri Feb 28 22:02:27 GMT 2020 0x94E2B7E1 generationID_1879581046 ./clk_wiz_v3_6/simulation/timing/simulate_ncsim.sh ignore unknown Fri Feb 28 22:02:29 GMT 2020 0x400C9C0D generationID_1879581046 ./clk_wiz_v3_6/simulation/timing/simulate_vcs.sh ignore unknown Fri Feb 28 22:02:31 GMT 2020 0x5F8F9F1C generationID_1879581046 ./clk_wiz_v3_6/simulation/timing/ucli_commands.key ignore unknown Fri Feb 28 22:02:31 GMT 2020 0x9DC0E037 generationID_1879581046 ./clk_wiz_v3_6/simulation/timing/vcs_session.tcl ignore tcl Fri Feb 28 22:02:31 GMT 2020 0x28340249 generationID_1879581046 ./clk_wiz_v3_6/simulation/timing/wave.do ignore unknown Fri Feb 28 22:02:28 GMT 2020 0xEDE0E39F generationID_1879581046 ./clk_wiz_v3_6.ucf ucf Fri Feb 28 22:02:34 GMT 2020 0x8BA05682 generationID_1879581046 ./clk_wiz_v3_6.v verilog Fri Feb 28 22:02:24 GMT 2020 0xF90EB239 generationID_1879581046 ./clk_wiz_v3_6.veo veo Fri Feb 28 22:02:26 GMT 2020 0x7B4DCC20 generationID_1879581046 ./clk_wiz_v3_6.xdc ignore xdc Fri Feb 28 22:02:34 GMT 2020 0xDB639994 generationID_1879581046 ./clk_wiz_v3_6_xmdf.tcl tcl Fri Feb 28 22:02:26 GMT 2020 0xF1D6EDD0 generationID_1879581046 associated_files_generator ./clk_wiz_v3_6/clk_wiz_v3_6_readme.txt ignore txt Sun Oct 13 18:34:18 GMT 2013 0x5B63DA78 generationID_1879581046 ejava_generator ./clk_wiz_v3_6/example_design/clk_wiz_v3_6_exdes.ucf ignore ucf Fri Feb 28 22:02:37 GMT 2020 0x19A045DD generationID_1879581046 ./clk_wiz_v3_6/example_design/clk_wiz_v3_6_exdes.v ignore verilog Fri Feb 28 22:02:37 GMT 2020 0xAC64F57E generationID_1879581046 ./clk_wiz_v3_6/example_design/clk_wiz_v3_6_exdes.xdc ignore xdc Fri Feb 28 22:02:37 GMT 2020 0x38870E64 generationID_1879581046 ./clk_wiz_v3_6/implement/implement.bat ignore unknown Fri Feb 28 22:02:37 GMT 2020 0x4ED49AF9 generationID_1879581046 ./clk_wiz_v3_6/implement/implement.sh ignore unknown Fri Feb 28 22:02:37 GMT 2020 0xEFECD5E5 generationID_1879581046 ./clk_wiz_v3_6/implement/planAhead_ise.bat ignore unknown Fri Feb 28 22:02:37 GMT 2020 0x6966A508 generationID_1879581046 ./clk_wiz_v3_6/implement/planAhead_ise.sh ignore unknown Fri Feb 28 22:02:37 GMT 2020 0x7F8B5943 generationID_1879581046 ./clk_wiz_v3_6/implement/planAhead_ise.tcl ignore tcl Fri Feb 28 22:02:37 GMT 2020 0x0F692296 generationID_1879581046 ./clk_wiz_v3_6/implement/planAhead_rdn.bat ignore unknown Fri Feb 28 22:02:37 GMT 2020 0xB9373CFA generationID_1879581046 ./clk_wiz_v3_6/implement/planAhead_rdn.sh ignore unknown Fri Feb 28 22:02:37 GMT 2020 0xDCE9D96C generationID_1879581046 ./clk_wiz_v3_6/implement/planAhead_rdn.tcl ignore tcl Fri Feb 28 22:02:37 GMT 2020 0xA3D65585 generationID_1879581046 ./clk_wiz_v3_6/implement/xst.prj ignore unknown Fri Feb 28 22:02:37 GMT 2020 0x49D219A7 generationID_1879581046 ./clk_wiz_v3_6/implement/xst.scr ignore unknown Fri Feb 28 22:02:37 GMT 2020 0x316C95E2 generationID_1879581046 ./clk_wiz_v3_6/simulation/clk_wiz_v3_6_tb.v ignore verilog Fri Feb 28 22:02:37 GMT 2020 0x747CB764 generationID_1879581046 ./clk_wiz_v3_6/simulation/functional/simcmds.tcl ignore tcl Fri Feb 28 22:02:37 GMT 2020 0x18DD8E59 generationID_1879581046 ./clk_wiz_v3_6/simulation/functional/simulate_isim.bat ignore unknown Fri Feb 28 22:02:37 GMT 2020 0x2B81F5D5 generationID_1879581046 ./clk_wiz_v3_6/simulation/functional/simulate_isim.sh ignore unknown Fri Feb 28 22:02:37 GMT 2020 0x9FCFD1F7 generationID_1879581046 ./clk_wiz_v3_6/simulation/functional/simulate_mti.bat ignore unknown Fri Feb 28 22:02:37 GMT 2020 0xFD2E9ECE generationID_1879581046 ./clk_wiz_v3_6/simulation/functional/simulate_mti.do ignore unknown Fri Feb 28 22:02:37 GMT 2020 0xA4A47524 generationID_1879581046 ./clk_wiz_v3_6/simulation/functional/simulate_mti.sh ignore unknown Fri Feb 28 22:02:37 GMT 2020 0xC9A4E9E6 generationID_1879581046 ./clk_wiz_v3_6/simulation/functional/simulate_ncsim.sh ignore unknown Fri Feb 28 22:02:37 GMT 2020 0x2901E532 generationID_1879581046 ./clk_wiz_v3_6/simulation/functional/simulate_vcs.sh ignore unknown Fri Feb 28 22:02:37 GMT 2020 0x52343BF0 generationID_1879581046 ./clk_wiz_v3_6/simulation/functional/ucli_commands.key ignore unknown Fri Feb 28 22:02:37 GMT 2020 0x8C15B41F generationID_1879581046 ./clk_wiz_v3_6/simulation/functional/vcs_session.tcl ignore tcl Fri Feb 28 22:02:37 GMT 2020 0xDBAB8E4B generationID_1879581046 ./clk_wiz_v3_6/simulation/functional/wave.do ignore unknown Fri Feb 28 22:02:37 GMT 2020 0x87ADB985 generationID_1879581046 ./clk_wiz_v3_6/simulation/functional/wave.sv ignore unknown Fri Feb 28 22:02:37 GMT 2020 0x71E0D404 generationID_1879581046 ./clk_wiz_v3_6/simulation/timing/clk_wiz_v3_6_tb.v ignore verilog Fri Feb 28 22:02:37 GMT 2020 0xF4B97746 generationID_1879581046 ./clk_wiz_v3_6/simulation/timing/sdf_cmd_file ignore unknown Fri Feb 28 22:02:37 GMT 2020 0x3E480C11 generationID_1879581046 ./clk_wiz_v3_6/simulation/timing/simcmds.tcl ignore tcl Fri Feb 28 22:02:37 GMT 2020 0x84642126 generationID_1879581046 ./clk_wiz_v3_6/simulation/timing/simulate_isim.sh ignore unknown Fri Feb 28 22:02:37 GMT 2020 0xF857D9E0 generationID_1879581046 ./clk_wiz_v3_6/simulation/timing/simulate_mti.bat ignore unknown Fri Feb 28 22:02:37 GMT 2020 0x559888D5 generationID_1879581046 ./clk_wiz_v3_6/simulation/timing/simulate_mti.do ignore unknown Fri Feb 28 22:02:37 GMT 2020 0xA99E36D0 generationID_1879581046 ./clk_wiz_v3_6/simulation/timing/simulate_mti.sh ignore unknown Fri Feb 28 22:02:37 GMT 2020 0x94E2B7E1 generationID_1879581046 ./clk_wiz_v3_6/simulation/timing/simulate_ncsim.sh ignore unknown Fri Feb 28 22:02:37 GMT 2020 0x400C9C0D generationID_1879581046 ./clk_wiz_v3_6/simulation/timing/simulate_vcs.sh ignore unknown Fri Feb 28 22:02:37 GMT 2020 0x5F8F9F1C generationID_1879581046 ./clk_wiz_v3_6/simulation/timing/ucli_commands.key ignore unknown Fri Feb 28 22:02:37 GMT 2020 0x9DC0E037 generationID_1879581046 ./clk_wiz_v3_6/simulation/timing/vcs_session.tcl ignore tcl Fri Feb 28 22:02:37 GMT 2020 0x28340249 generationID_1879581046 ./clk_wiz_v3_6/simulation/timing/wave.do ignore unknown Fri Feb 28 22:02:37 GMT 2020 0xEDE0E39F generationID_1879581046 ./clk_wiz_v3_6.ucf ucf Fri Feb 28 22:02:37 GMT 2020 0x8BA05682 generationID_1879581046 ./clk_wiz_v3_6.v verilog Fri Feb 28 22:02:37 GMT 2020 0xF90EB239 generationID_1879581046 ./clk_wiz_v3_6.veo veo Fri Feb 28 22:02:37 GMT 2020 0x7B4DCC20 generationID_1879581046 ./clk_wiz_v3_6.xdc ignore xdc Fri Feb 28 22:02:37 GMT 2020 0xDB639994 generationID_1879581046 ./clk_wiz_v3_6_xmdf.tcl tcl Fri Feb 28 22:02:37 GMT 2020 0xF1D6EDD0 generationID_1879581046 all_documents_generator ./clk_wiz_v3_6/doc/clk_wiz_v3_6_readme.txt ignore txt Fri Feb 28 22:02:42 GMT 2020 0x5B63DA78 generationID_1879581046 ./clk_wiz_v3_6/doc/clk_wiz_v3_6_vinfo.html ignore unknown Fri Feb 28 22:02:42 GMT 2020 0xF2E77607 generationID_1879581046 ./clk_wiz_v3_6/doc/pg065_clk_wiz.pdf ignore pdf Fri Feb 28 22:02:42 GMT 2020 0x2F883891 generationID_1879581046 readme_documents_generator asy_generator ./clk_wiz_v3_6.asy asy Fri Feb 28 22:02:49 GMT 2020 0xB3495C04 generationID_1879581046 ise_generator ./clk_wiz_v3_6.gise ignore gise Fri Feb 28 22:02:52 GMT 2020 0xDC71B9A6 generationID_1879581046 ./clk_wiz_v3_6.xise ignore xise Fri Feb 28 22:02:52 GMT 2020 0x97B6FAE0 generationID_1879581046 deliver_readme_generator flist_generator ./clk_wiz_v3_6_flist.txt ignore txtFlist txt Fri Feb 28 22:02:52 GMT 2020 0x33F5EAC3 generationID_1879581046 view_readme_generator coregen ./ C:/Program Files/Alchitry/Alchitry Labs/ C:/Program Files/Alchitry/Alchitry Labs/_cg/ xc6slx9 spartan6 tqg144 -2 BusFormatAngleBracketNotRipped Verilog true Other false false false Ngc false Behavioral Verilog false