28 lines
498 B
Verilog
28 lines
498 B
Verilog
module sram #(
|
|
parameter SIZE = 1,
|
|
parameter DEPTH = 1
|
|
)(
|
|
input clk,
|
|
input rst,
|
|
input [$clog2(DEPTH)-1:0] read_address,
|
|
input [$clog2(DEPTH)-1:0] write_address,
|
|
output reg [SIZE-1:0] read_data,
|
|
input [SIZE-1:0] write_data,
|
|
input write_en
|
|
);
|
|
|
|
reg [SIZE-1:0] ram [DEPTH-1:0];
|
|
|
|
reg [DEPTH-1:0] valid;
|
|
|
|
always @(posedge clk) begin
|
|
read_data <= ram[read_address] * valid[read_address];
|
|
|
|
if (write_en) begin
|
|
valid[write_address] <= 1;
|
|
ram[write_address] <= write_data;
|
|
end
|
|
end
|
|
|
|
endmodule
|