146 lines
3.7 KiB
Verilog
146 lines
3.7 KiB
Verilog
`timescale 1ns / 1ps
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/*
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This file was generated automatically by Alchitry Labs version 1.2.0.
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Do not edit this file directly. Instead edit the original Lucid source.
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This is a temporary file and any changes made to it will be destroyed.
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*/
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/*
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Parameters:
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PCLK_DIV = 1
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Y_RES = HEIGHT
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X_RES = WIDTH
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Y_FRAME = HEIGHT+30
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X_FRAME = WIDTH+387
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*/
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module hdmi_encoder #(parameter Y_RES = 720, parameter X_RES = 1280, parameter Y_FRAME = Y_RES+30, parameter X_FRAME = X_RES+387) (
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input clk,
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input rst,
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output reg pclk,
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output reg [3:0] tmds,
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output reg [3:0] tmdsb,
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output reg active,
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output reg [11:0] x,
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output reg [10:0] y,
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input [7:0] red,
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input [7:0] green,
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input [7:0] blue
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);
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localparam PCLK_DIV = 1'h1;
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reg clkfbin;
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wire [1-1:0] M_pll_oserdes_CLKOUT0;
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wire [1-1:0] M_pll_oserdes_CLKOUT1;
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wire [1-1:0] M_pll_oserdes_CLKOUT2;
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wire [1-1:0] M_pll_oserdes_CLKOUT3;
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wire [1-1:0] M_pll_oserdes_CLKOUT4;
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wire [1-1:0] M_pll_oserdes_CLKOUT5;
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wire [1-1:0] M_pll_oserdes_CLKFBOUT;
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wire [1-1:0] M_pll_oserdes_LOCKED;
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PLL_BASE #(.CLKIN_PERIOD(10), .CLKFBOUT_MULT(10), .CLKOUT0_DIVIDE(1), .CLKOUT1_DIVIDE(10), .CLKOUT2_DIVIDE(5), .COMPENSATION("SOURCE_SYNCHRONOUS")) pll_oserdes (
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.CLKFBIN(clkfbin),
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.CLKIN(clk),
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.RST(1'h0),
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.CLKOUT0(M_pll_oserdes_CLKOUT0),
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.CLKOUT1(M_pll_oserdes_CLKOUT1),
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.CLKOUT2(M_pll_oserdes_CLKOUT2),
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.CLKOUT3(M_pll_oserdes_CLKOUT3),
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.CLKOUT4(M_pll_oserdes_CLKOUT4),
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.CLKOUT5(M_pll_oserdes_CLKOUT5),
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.CLKFBOUT(M_pll_oserdes_CLKFBOUT),
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.LOCKED(M_pll_oserdes_LOCKED)
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);
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wire [1-1:0] M_clkfb_buf_O;
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BUFG clkfb_buf (
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.I(M_pll_oserdes_CLKFBOUT),
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.O(M_clkfb_buf_O)
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);
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always @* begin
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clkfbin = M_clkfb_buf_O;
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end
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wire [1-1:0] M_pclkx2_buf_O;
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BUFG pclkx2_buf (
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.I(M_pll_oserdes_CLKOUT2),
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.O(M_pclkx2_buf_O)
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);
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wire [1-1:0] M_pclk_buf_O;
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BUFG pclk_buf (
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.I(M_pll_oserdes_CLKOUT1),
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.O(M_pclk_buf_O)
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);
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wire [1-1:0] M_ioclk_buf_IOCLK;
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wire [1-1:0] M_ioclk_buf_SERDESSTROBE;
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wire [1-1:0] M_ioclk_buf_LOCK;
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BUFPLL #(.DIVIDE(5)) ioclk_buf (
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.PLLIN(M_pll_oserdes_CLKOUT0),
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.GCLK(M_pclkx2_buf_O),
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.LOCKED(M_pll_oserdes_LOCKED),
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.IOCLK(M_ioclk_buf_IOCLK),
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.SERDESSTROBE(M_ioclk_buf_SERDESSTROBE),
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.LOCK(M_ioclk_buf_LOCK)
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);
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reg [11:0] M_ctrX_d, M_ctrX_q = 1'h0;
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reg [10:0] M_ctrY_d, M_ctrY_q = 1'h0;
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reg hSync;
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reg vSync;
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reg drawArea;
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wire [4-1:0] M_dvi_tmds;
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wire [4-1:0] M_dvi_tmdsb;
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dvi_encoder dvi (
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.pclk(M_pclk_buf_O),
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.pclkx2(M_pclkx2_buf_O),
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.pclkx10(M_ioclk_buf_IOCLK),
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.strobe(M_ioclk_buf_SERDESSTROBE),
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.rst(~M_ioclk_buf_LOCK),
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.blue(blue),
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.green(green),
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.red(red),
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.hsync(hSync),
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.vsync(vSync),
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.de(drawArea),
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.tmds(M_dvi_tmds),
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.tmdsb(M_dvi_tmdsb)
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);
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always @* begin
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M_ctrY_d = M_ctrY_q;
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M_ctrX_d = M_ctrX_q;
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M_ctrX_d = (M_ctrX_q == 13'h0682) ? 1'h0 : M_ctrX_q + 1'h1;
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if (M_ctrX_q == 13'h0682) begin
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M_ctrY_d = (M_ctrY_q == 12'h2ed) ? 1'h0 : M_ctrY_q + 1'h1;
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end
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pclk = M_pclk_buf_O;
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hSync = (M_ctrX_q >= 12'h50a) && (M_ctrX_q < 12'h514);
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vSync = (M_ctrY_q >= 11'h2da) && (M_ctrY_q < 11'h2dc);
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drawArea = (M_ctrX_q < 11'h500) && (M_ctrY_q < 10'h2d0);
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active = drawArea;
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x = M_ctrX_q;
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y = M_ctrY_q;
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tmds = M_dvi_tmds;
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tmdsb = M_dvi_tmdsb;
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end
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always @(posedge M_pclk_buf_O) begin
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if (rst == 1'b1) begin
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M_ctrX_q <= 1'h0;
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M_ctrY_q <= 1'h0;
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end else begin
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M_ctrX_q <= M_ctrX_d;
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M_ctrY_q <= M_ctrY_d;
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end
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end
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endmodule |