23 lines
554 B
Plaintext
23 lines
554 B
Plaintext
# Date: Fri Feb 28 22:01:30 2020
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SET addpads = false
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SET asysymbol = true
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SET busformat = BusFormatAngleBracketNotRipped
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SET createndf = false
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SET designentry = Verilog
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SET device = xc6slx9
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SET devicefamily = spartan6
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SET flowvendor = Other
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SET formalverification = false
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SET foundationsym = false
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SET implementationfiletype = Ngc
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SET package = tqg144
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SET removerpms = false
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SET simulationfiles = Behavioral
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SET speedgrade = -2
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SET verilogsim = true
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SET vhdlsim = false
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SET workingdirectory = "C:\Program Files\Alchitry\Alchitry Labs\"
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# CRC: 38e944ea
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