Whole project can now be build using make

2021-01-28 22:47:06 +01:00
parent c661c10757
commit 12b49eff1c
10 changed files with 635 additions and 8 deletions
--- a/scripts/build.tcl
+++ b/scripts/build.tcl
@@ -0,0 +1,137 @@
+set out_dir ./.build
+set top_module dvi_top
+set part_num xc7a35tftg256-1
+
+set_part $part_num
+
+file mkdir $out_dir
+foreach fname [glob -nocomplain -type f $out_dir/*] {
+	file delete $fname
+}
+
+set step 0_ip
+if { [file isdirectory ${out_dir}/ip] } {
+	read_ip ${out_dir}/ip/clk_wiz_0/clk_wiz_0.xci
+	read_ip ${out_dir}/ip/microblaze_mcs_0/microblaze_mcs_0.xci
+} else {
+	file mkdir ${out_dir}/ip
+
+	create_project -in_memory
+
+	create_ip -name clk_wiz -vendor xilinx.com -library ip \
+	    -version 6.0 -module_name clk_wiz_0 \
+	    -dir ${out_dir}/ip
+
+	set_property -dict [list \
+	    CONFIG.PRIMARY_PORT {clk_in} \
+	    CONFIG.CLKOUT2_USED {true} \
+	    CONFIG.CLKOUT3_USED {true} \
+	    CONFIG.CLKOUT4_USED {true} \
+	    CONFIG.CLK_OUT1_PORT {clk_dvi} \
+	    CONFIG.CLK_OUT2_PORT {clk_dvin} \
+	    CONFIG.CLK_OUT3_PORT {clk_pix} \
+	    CONFIG.CLK_OUT4_PORT {clk_mcu} \
+	    CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {375} \
+	    CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {375} \
+	    CONFIG.CLKOUT2_REQUESTED_PHASE {180} \
+	    CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {75} \
+	    CONFIG.CLKOUT4_REQUESTED_OUT_FREQ {150} \
+	    CONFIG.CLKOUT1_DRIVES {BUFG} \
+	    CONFIG.FEEDBACK_SOURCE {FDBK_AUTO} \
+	    CONFIG.MMCM_DIVCLK_DIVIDE {1} \
+	    CONFIG.MMCM_CLKFBOUT_MULT_F {7.500} \
+	    CONFIG.MMCM_CLKOUT0_DIVIDE_F {2.000} \
+	    CONFIG.MMCM_CLKOUT1_DIVIDE {2} \
+	    CONFIG.MMCM_CLKOUT1_PHASE {180.000} \
+	    CONFIG.MMCM_CLKOUT2_DIVIDE {10} \
+	    CONFIG.MMCM_CLKOUT3_DIVIDE {5} \
+	    CONFIG.NUM_OUT_CLKS {4} \
+	    CONFIG.CLKOUT1_JITTER {111.604} \
+	    CONFIG.CLKOUT1_PHASE_ERROR {116.405} \
+	    CONFIG.CLKOUT2_JITTER {111.604} \
+	    CONFIG.CLKOUT2_PHASE_ERROR {116.405} \
+	    CONFIG.CLKOUT3_JITTER {152.549} \
+	    CONFIG.CLKOUT3_PHASE_ERROR {116.405} \
+	    CONFIG.CLKOUT4_JITTER {132.464} \
+	    CONFIG.CLKOUT4_PHASE_ERROR {116.405} \
+	] [get_ips clk_wiz_0]
+
+	create_ip -name microblaze_mcs -vendor xilinx.com -library ip \
+	    -version 3.0 -module_name microblaze_mcs_0 \
+	    -dir ${out_dir}/ip
+
+	set_property -dict [list \
+	    CONFIG.FREQ {150} \
+	    CONFIG.MEMSIZE {131072} \
+	    CONFIG.USE_GPO1 {1} \
+	    CONFIG.GPO1_SIZE {16} \
+	    CONFIG.USE_GPO2 {1} \
+	    CONFIG.GPO2_SIZE {16} \
+	    CONFIG.USE_GPO3 {1} \
+	    CONFIG.GPO3_SIZE {2} \
+	    CONFIG.USE_GPO4 {1} \
+	    CONFIG.GPO4_SIZE {6} \
+	    CONFIG.USE_GPI1 {1} \
+	    CONFIG.GPI1_SIZE {8} \
+	    CONFIG.USE_GPI2 {1} \
+	    CONFIG.GPI2_SIZE {1} \
+	    CONFIG.GPI2_INTERRUPT {3} \
+	    CONFIG.USE_GPI3 {1} \
+	    CONFIG.GPI3_SIZE {1} \
+	] [get_ips microblaze_mcs_0]
+
+	generate_target all [get_ips]
+
+	synth_ip [get_ips] > $out_dir/${step}.log
+}
+
+read_verilog [glob ./src/*.v]
+read_xdc [glob ./src/*.xdc]
+
+set step 1_synth
+synth_design -top $top_module -part $part_num -retiming -fanout_limit 1000 -gated_clock_conversion on > $out_dir/${step}.log
+write_checkpoint -force $out_dir/$step
+report_timing_summary -file $out_dir/${step}_timing_summary.rpt
+report_utilization -file $out_dir/${step}_util.rpt
+report_power -file $out_dir/${step}_power.rpt
+
+set step 2_opt
+opt_design -directive Explore > $out_dir/${step}.log
+write_checkpoint -force $out_dir/$step
+report_timing_summary -file $out_dir/${step}_timing_summary.rpt
+report_utilization -file $out_dir/${step}_util.rpt
+
+set step 3_place
+place_design -directive ExtraPostPlacementOpt > $out_dir/${step}.log
+write_checkpoint -force $out_dir/$step
+report_timing_summary -file $out_dir/${step}_timing_summary.rpt
+report_utilization -file $out_dir/${step}_util.rpt
+
+set step 4_phys_opt
+set WNS [ get_property SLACK [get_timing_paths -max_paths 1 -nworst 1 -setup] ]
+if {$WNS < 0.000} {
+	for {set i 0} {$i < 5} {incr i} {
+		phys_opt_design -directive AggressiveExplore > $out_dir/${step}_explore_${i}.log
+		phys_opt_design -directive AggressiveFanoutOpt > $out_dir/${step}_fanout_${i}.log
+		phys_opt_design -directive AlternateReplication > $out_dir/${step}_replication_${i}.log
+	}
+}
+write_checkpoint -force $out_dir/$step
+report_timing_summary -file $out_dir/${step}_timing_summary.rpt
+report_utilization -file $out_dir/${step}_util.rpt
+
+set step 5_route
+route_design -directive Explore > $out_dir/${step}.log
+write_checkpoint -force $out_dir/$step
+
+report_timing_summary -file $out_dir/${step}_timing_summary.rpt
+report_timing -sort_by group -max_paths 100 -path_type summary -file $out_dir/${step}_timing.rpt
+report_clock_utilization -file $out_dir/${step}_clock_util.rpt
+report_utilization -file $out_dir/${step}_util.rpt
+report_power -file $out_dir/${step}_power.rpt
+report_drc -file $out_dir/${step}_drc.rpt
+
+write_verilog -force $out_dir/imp_netlist.v
+write_xdc -no_fixed_only -force $out_dir/imp.xdc
+
+write_hwdef -force  -file ${out_dir}/system.hdf
--- a/scripts/clk_wiz_0.tcl
+++ b/scripts/clk_wiz_0.tcl
@@ -0,0 +1,50 @@
+set out_dir ./.build
+set part_num xc7a35tftg256-1
+
+set_part $part_num
+
+file delete -force $out_dir/ip/clk_wiz_0
+
+create_project -in_memory
+
+create_ip -name clk_wiz -vendor xilinx.com -library ip \
+	-version 6.0 -module_name clk_wiz_0 \
+	-dir ${out_dir}/ip
+
+set_property -dict [list \
+	CONFIG.PRIMARY_PORT {clk_in} \
+	CONFIG.CLKOUT2_USED {true} \
+	CONFIG.CLKOUT3_USED {true} \
+	CONFIG.CLKOUT4_USED {true} \
+	CONFIG.CLK_OUT1_PORT {clk_dvi} \
+	CONFIG.CLK_OUT2_PORT {clk_dvin} \
+	CONFIG.CLK_OUT3_PORT {clk_pix} \
+	CONFIG.CLK_OUT4_PORT {clk_mcu} \
+	CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {375} \
+	CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {375} \
+	CONFIG.CLKOUT2_REQUESTED_PHASE {180} \
+	CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {75} \
+	CONFIG.CLKOUT4_REQUESTED_OUT_FREQ {150} \
+	CONFIG.CLKOUT1_DRIVES {BUFG} \
+	CONFIG.FEEDBACK_SOURCE {FDBK_AUTO} \
+	CONFIG.MMCM_DIVCLK_DIVIDE {1} \
+	CONFIG.MMCM_CLKFBOUT_MULT_F {7.500} \
+	CONFIG.MMCM_CLKOUT0_DIVIDE_F {2.000} \
+	CONFIG.MMCM_CLKOUT1_DIVIDE {2} \
+	CONFIG.MMCM_CLKOUT1_PHASE {180.000} \
+	CONFIG.MMCM_CLKOUT2_DIVIDE {10} \
+	CONFIG.MMCM_CLKOUT3_DIVIDE {5} \
+	CONFIG.NUM_OUT_CLKS {4} \
+	CONFIG.CLKOUT1_JITTER {111.604} \
+	CONFIG.CLKOUT1_PHASE_ERROR {116.405} \
+	CONFIG.CLKOUT2_JITTER {111.604} \
+	CONFIG.CLKOUT2_PHASE_ERROR {116.405} \
+	CONFIG.CLKOUT3_JITTER {152.549} \
+	CONFIG.CLKOUT3_PHASE_ERROR {116.405} \
+	CONFIG.CLKOUT4_JITTER {132.464} \
+	CONFIG.CLKOUT4_PHASE_ERROR {116.405} \
+] [get_ips clk_wiz_0]
+
+generate_target all [get_ips]
+
+synth_ip [get_ips] > $out_dir/clk_wiz_0.log
--- a/scripts/microblaze_mcs_0.tcl
+++ b/scripts/microblaze_mcs_0.tcl
@@ -0,0 +1,36 @@
+set out_dir ./.build
+set part_num xc7a35tftg256-1
+
+set_part $part_num
+
+file delete -force $out_dir/ip/microblaze_mcs_0
+
+create_project -in_memory
+
+create_ip -name microblaze_mcs -vendor xilinx.com -library ip \
+	-version 3.0 -module_name microblaze_mcs_0 \
+	-dir ${out_dir}/ip
+
+set_property -dict [list \
+	CONFIG.FREQ {150} \
+	CONFIG.MEMSIZE {131072} \
+	CONFIG.USE_GPO1 {1} \
+	CONFIG.GPO1_SIZE {16} \
+	CONFIG.USE_GPO2 {1} \
+	CONFIG.GPO2_SIZE {16} \
+	CONFIG.USE_GPO3 {1} \
+	CONFIG.GPO3_SIZE {2} \
+	CONFIG.USE_GPO4 {1} \
+	CONFIG.GPO4_SIZE {6} \
+	CONFIG.USE_GPI1 {1} \
+	CONFIG.GPI1_SIZE {8} \
+	CONFIG.USE_GPI2 {1} \
+	CONFIG.GPI2_SIZE {1} \
+	CONFIG.GPI2_INTERRUPT {3} \
+	CONFIG.USE_GPI3 {1} \
+	CONFIG.GPI3_SIZE {1} \
+] [get_ips microblaze_mcs_0]
+
+generate_target all [get_ips]
+
+synth_ip [get_ips] > $out_dir/microblaze_mcs_0.log
--- a/scripts/sdk.tcl
+++ b/scripts/sdk.tcl
@@ -0,0 +1,9 @@
+set out_dir ./.build
+
+file delete -force ${out_dir}/.metadata
+file delete -force ${out_dir}/hw_platform
+file delete -force ${out_dir}/bsp
+
+setws .build
+createhw -name hw_platform -hwspec .build/system.hdf
+createbsp -name bsp -hwproject hw_platform -os standalone -proc microblaze_I
--- a/scripts/write.tcl
+++ b/scripts/write.tcl
@@ -0,0 +1,10 @@
+set out_dir ./.build
+
+open_checkpoint .build/5_route.dcp
+
+add_files -norecurse ./controller.elf
+set_property used_in_simulation 0 [get_files ./controller.elf]
+set_property SCOPED_TO_REF microblaze_mcs_0 [get_files -all -of_objects [get_fileset sources_1] {./controller.elf}]
+set_property SCOPED_TO_CELLS { inst/microblaze_I } [get_files -all -of_objects [get_fileset sources_1] {./controller.elf}]
+
+write_bitstream -force $out_dir/impl.bit -bin_file