From cca21dfea2d0ad581928f65018da38df44632391 Mon Sep 17 00:00:00 2001 From: Dreaded_X Date: Thu, 21 Jan 2021 21:09:36 +0100 Subject: [PATCH] Converted Vivado project to non-project mode, still working on the software side of the project --- .gitignore | 3 + build.tcl | 137 ++++++++++++++++++++ controller.elf | Bin 0 -> 15556 bytes src/char_map.v | 290 ++++++++++++++++++++++++++++++++++++++++++ src/color_map.v | 54 ++++++++ src/dvi_top.v | 165 ++++++++++++++++++++++++ src/dvid.v | 70 ++++++++++ src/encode.v | 190 +++++++++++++++++++++++++++ src/hdmi.xdc | 107 ++++++++++++++++ src/simple_dual_ram.v | 78 ++++++++++++ write.tcl | 10 ++ 11 files changed, 1104 insertions(+) create mode 100644 .gitignore create mode 100644 build.tcl create mode 100755 controller.elf create mode 100644 src/char_map.v create mode 100644 src/color_map.v create mode 100644 src/dvi_top.v create mode 100644 src/dvid.v create mode 100644 src/encode.v create mode 100644 src/hdmi.xdc create mode 100644 src/simple_dual_ram.v create mode 100644 write.tcl diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..eab3b43 --- /dev/null +++ b/.gitignore @@ -0,0 +1,3 @@ +.build +.Xil +hdmi.sdk diff --git a/build.tcl b/build.tcl new file mode 100644 index 0000000..fad523d --- /dev/null +++ b/build.tcl @@ -0,0 +1,137 @@ +set out_dir ./.build +set top_module dvi_top +set part_num xc7a35tftg256-1 + +set_part $part_num + +file mkdir $out_dir +foreach fname [glob -nocomplain -type f $out_dir/*] { + file delete $fname +} + +set step 0_ip +if { [file isdirectory ./.build/ip] } { + read_ip ./.build/ip/clk_wiz_0/clk_wiz_0.xci + read_ip ./.build/ip/microblaze_mcs_0/microblaze_mcs_0.xci +} else { + file mkdir ./.build/ip + + create_project -in_memory + + create_ip -name clk_wiz -vendor xilinx.com -library ip \ + -version 6.0 -module_name clk_wiz_0 \ + -dir ./.build/ip + + set_property -dict [list \ + CONFIG.PRIMARY_PORT {clk_in} \ + CONFIG.CLKOUT2_USED {true} \ + CONFIG.CLKOUT3_USED {true} \ + CONFIG.CLKOUT4_USED {true} \ + CONFIG.CLK_OUT1_PORT {clk_dvi} \ + CONFIG.CLK_OUT2_PORT {clk_dvin} \ + CONFIG.CLK_OUT3_PORT {clk_pix} \ + CONFIG.CLK_OUT4_PORT {clk_mcu} \ + CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {375} \ + CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {375} \ + CONFIG.CLKOUT2_REQUESTED_PHASE {180} \ + CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {75} \ + CONFIG.CLKOUT4_REQUESTED_OUT_FREQ {150} \ + CONFIG.CLKOUT1_DRIVES {BUFG} \ + CONFIG.FEEDBACK_SOURCE {FDBK_AUTO} \ + CONFIG.MMCM_DIVCLK_DIVIDE {1} \ + CONFIG.MMCM_CLKFBOUT_MULT_F {7.500} \ + CONFIG.MMCM_CLKOUT0_DIVIDE_F {2.000} \ + CONFIG.MMCM_CLKOUT1_DIVIDE {2} \ + CONFIG.MMCM_CLKOUT1_PHASE {180.000} \ + CONFIG.MMCM_CLKOUT2_DIVIDE {10} \ + CONFIG.MMCM_CLKOUT3_DIVIDE {5} \ + CONFIG.NUM_OUT_CLKS {4} \ + CONFIG.CLKOUT1_JITTER {111.604} \ + CONFIG.CLKOUT1_PHASE_ERROR {116.405} \ + CONFIG.CLKOUT2_JITTER {111.604} \ + CONFIG.CLKOUT2_PHASE_ERROR {116.405} \ + CONFIG.CLKOUT3_JITTER {152.549} \ + CONFIG.CLKOUT3_PHASE_ERROR {116.405} \ + CONFIG.CLKOUT4_JITTER {132.464} \ + CONFIG.CLKOUT4_PHASE_ERROR {116.405} \ + ] [get_ips clk_wiz_0] + + create_ip -name microblaze_mcs -vendor xilinx.com -library ip \ + -version 3.0 -module_name microblaze_mcs_0 \ + -dir ./.build/ip + + set_property -dict [list \ + CONFIG.FREQ {150} \ + CONFIG.MEMSIZE {131072} \ + CONFIG.USE_GPO1 {1} \ + CONFIG.GPO1_SIZE {16} \ + CONFIG.USE_GPO2 {1} \ + CONFIG.GPO2_SIZE {16} \ + CONFIG.USE_GPO3 {1} \ + CONFIG.GPO3_SIZE {2} \ + CONFIG.USE_GPO4 {1} \ + CONFIG.GPO4_SIZE {6} \ + CONFIG.USE_GPI1 {1} \ + CONFIG.GPI1_SIZE {8} \ + CONFIG.USE_GPI2 {1} \ + CONFIG.GPI2_SIZE {1} \ + CONFIG.GPI2_INTERRUPT {3} \ + CONFIG.USE_GPI3 {1} \ + CONFIG.GPI3_SIZE {1} \ + ] [get_ips microblaze_mcs_0] + + generate_target all [get_ips] + + synth_ip [get_ips] > $out_dir/${step}.log +} + +read_verilog [glob ./src/*.v] +read_xdc [glob ./src/*.xdc] + +set step 1_synth +synth_design -top $top_module -part $part_num -retiming -fanout_limit 1000 -gated_clock_conversion on > $out_dir/${step}.log +write_checkpoint -force $out_dir/$step +report_timing_summary -file $out_dir/${step}_timing_summary.rpt +report_utilization -file $out_dir/${step}_util.rpt +report_power -file $out_dir/${step}_power.rpt + +set step 2_opt +opt_design -directive Explore > $out_dir/${step}.log +write_checkpoint -force $out_dir/$step +report_timing_summary -file $out_dir/${step}_timing_summary.rpt +report_utilization -file $out_dir/${step}_util.rpt + +set step 3_place +place_design -directive ExtraPostPlacementOpt > $out_dir/${step}.log +write_checkpoint -force $out_dir/$step +report_timing_summary -file $out_dir/${step}_timing_summary.rpt +report_utilization -file $out_dir/${step}_util.rpt + +set step 4_phys_opt +set WNS [ get_property SLACK [get_timing_paths -max_paths 1 -nworst 1 -setup] ] +if {$WNS < 0.000} { + for {set i 0} {$i < 5} {incr i} { + phys_opt_design -directive AggressiveExplore > $out_dir/${step}_explore_${i}.log + phys_opt_design -directive AggressiveFanoutOpt > $out_dir/${step}_fanout_${i}.log + phys_opt_design -directive AlternateReplication > $out_dir/${step}_replication_${i}.log + } +} +write_checkpoint -force $out_dir/$step +report_timing_summary -file $out_dir/${step}_timing_summary.rpt +report_utilization -file $out_dir/${step}_util.rpt + +set step 5_route +route_design -directive Explore > $out_dir/${step}.log +write_checkpoint -force $out_dir/$step + +report_timing_summary -file $out_dir/${step}_timing_summary.rpt +report_timing -sort_by group -max_paths 100 -path_type summary -file $out_dir/${step}_timing.rpt +report_clock_utilization -file $out_dir/${step}_clock_util.rpt +report_utilization -file $out_dir/${step}_util.rpt +report_power -file $out_dir/${step}_power.rpt +report_drc -file $out_dir/${step}_drc.rpt + +write_verilog -force $out_dir/imp_netlist.v +write_xdc -no_fixed_only -force $out_dir/imp.xdc + +source write.tcl diff --git a/controller.elf b/controller.elf new file mode 100755 index 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+////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 20:18:41 09/13/2020 +// Design Name: +// Module Name: char_map +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + module char_map( + input clk, + input [7:0] index, + output reg [255:0] char +); + +wire [255:0] char_data [255:0]; + +always @(posedge clk) begin + char <= char_data[index]; +end + +assign char_data[ 0] = 256'h0000000000000000000000000000000000000000000000000000000000000000; +assign char_data[ 1] = 256'h00001ffc380e30063636363630063006300637f63006380e1ffc000000000000; +assign char_data[ 2] = 256'h00001ffc3ffe3ffe39ce39ce3ffe3ffe3ffe380e3ffe3ffe0ff8000000000000; +assign char_data[ 3] = 256'h000000000c301e783ffc3ffc3ffc3ffc3ffc1ff80ff007e003c0018000000000; +assign char_data[ 4] = 256'h0000018003c007e00ff01ff83ffc7ffe7ffe3ffc1ff80ff007e003c001800000; +assign char_data[ 5] = 256'h000003c007e007e007e003c0399c7dbe7ffe7ffe7dbe399c018003c00ff00000; +assign char_data[ 6] = 256'h0000018003c007e00ff01ff81ff83ffc3ffc3ffc1db80180018003c00ff00000; +assign char_data[ 7] = 256'h000000000000000003c007e00ff00ff00ff00ff007e003c00000000000000000; +assign char_data[ 8] = 256'hfffffffffffffffffc3ff81ff00ff00ff00ff00ff81ffc3fffffffffffffffff; +assign char_data[ 9] = 256'h0000000007e00ff01ff81818100810081008100818181ff80ff007e000000000; +assign char_data[ 10] = 256'hfffffffff81ff00fe007e7e7eff7eff7eff7eff7e7e7e007f00ff81fffffffff; +assign char_data[ 11] = 256'h000007f8007801e807c80f081fc038e038e038e038e038e01fc0000000000000; +assign char_data[ 12] = 256'h000007f00e380e380e380e380e3807f001c001c00ff801c001c0000000000000; +assign char_data[ 13] = 256'h000001fc01c601c001fc01c601c001c001c01fc03fc03fc01f80000000000000; +assign char_data[ 14] = 256'h00000ffe0e0e0e0e0ffe0e0e0e0e0e0e0e0e0e3e3e7e7e7e7e3c3c0000000000; +assign char_data[ 15] = 256'h000003c03bdc3bdc3ffc0ff07c3e7c3e7c3e7c3e0ff03ffc3bdc3bdc03c00000; +assign char_data[ 16] = 256'h0000600078007e007f807fe07ff87ffe7ffe7ff87fe07f807e00780060000000; +assign char_data[ 17] = 256'h00000006001e007e01fe07fe1ffe7ffe7ffe1ffe07fe01fe007e001e00060000; +assign char_data[ 18] = 256'h0000008001c003e007f00ff801c001c001c001c00ff807f003e001c000800000; +assign char_data[ 19] = 256'h000000000e700e700e700e700e700e700e70000000000e700e700e7000000000; +assign char_data[ 20] = 256'h00001ffc3ffc339c339c339c339c3f9c1f9c039c039c039c039c039c039c0000; +assign char_data[ 21] = 256'h00000ff81e0c1c040f800ff01c381c381c381c380ff001f0203830781ff00000; +assign char_data[ 22] = 256'h0000000000000000000000000000000000001ffc1ffc1ffc1ffc1ffc1ffc0000; +assign char_data[ 23] = 256'h0000008001c003e007f00ff801c001c001c001c00ff807f003e001c00ff81ffc; +assign char_data[ 24] = 256'h00000100038007c00fe01ff03ff83ff803800380038003800380038000000000; +assign char_data[ 25] = 256'h00000380038003800380038003803ff83ff81ff00fe007c00380010000000000; +assign char_data[ 26] = 256'h00000000000000c000e000f000f83ffc3ffe3ffc00f800f000e000c000000000; +assign char_data[ 27] = 256'h0000000000000180038007800f801ffe3ffe1ffe0f8007800380018000000000; +assign char_data[ 28] = 256'h0000000000000000000030003000300030003ff83ff800000000000000000000; +assign char_data[ 29] = 256'h000000000000000004200c301c383ffc7ffe3ffc1c380c300420000000000000; +assign char_data[ 30] = 256'h00000180018003c003c007e007e00ff00ff01ff81ff83ffc3ffc7ffe7ffe0000; +assign char_data[ 31] = 256'h00007ffe7ffe3ffc3ffc1ff81ff80ff00ff007e007e003c003c0018001800000; +assign char_data[ 32] = 256'h0000000000000000000000000000000000000000000000000000000000000000; // +assign char_data[ 33] = 256'h0000000007000f800f800f800f800f8007000700000000000700070007000000; // ! +assign char_data[ 34] = 256'h00000e380e380e380e3806300000000000000000000000000000000000000000; // " +assign char_data[ 35] = 256'h00000c300c300c307ffe7ffe0c300c300c300c307ffe7ffe0c300c300c300000; // # +assign char_data[ 36] = 256'h0000024002400ff81ff81a401a401ff00ff8025802581ff81ff0024002400000; // $ +assign char_data[ 37] = 256'h0000000000000e100e300e7000e001c0038007000e700c700870000000000000; // % +assign char_data[ 38] = 256'h000000000f001980198019800f000f080f9819f818f018e019f00f9800000000; // & +assign char_data[ 39] = 256'h000000000700070007000e000000000000000000000000000000000000000000; // ' +assign char_data[ 40] = 256'h0000000000f001c0038007000e000e000e000e000700038001c000f000000000; // ( +assign char_data[ 41] = 256'h000000000f00038001c000e0007000700070007000e001c003800f0000000000; // ) +assign char_data[ 42] = 256'h0000000000000180018019981db807e007e01db8199801800180000000000000; // * +assign char_data[ 43] = 256'h00000000000001800180018001801ff81ff80180018001800180000000000000; // + +assign char_data[ 44] = 256'h000000000000000000000000000000000000000000000700070007000e000000; // , +assign char_data[ 45] = 256'h00000000000000000000000000001ff81ff80000000000000000000000000000; // - +assign char_data[ 46] = 256'h0000000000000000000000000000000000000000000007000700070000000000; // . +assign char_data[ 47] = 256'h0000000000020006000e001c0038007000e001c0038007000e001c0000000000; // / +assign char_data[ 48] = 256'h000000000ff01c381c781cf81cf81db81db81f381f381e381c380ff000000000; // 0 +assign char_data[ 49] = 256'h000000000180018003801f801f800380038003800380038003801ff000000000; // 1 +assign char_data[ 50] = 256'h000000000fe01c701c380038007000e001c0038007000e381c381ff800000000; // 2 +assign char_data[ 51] = 256'h000000000fe01c701c380038007003e003e0007000381c381c700fe000000000; // 3 +assign char_data[ 52] = 256'h0000000000e001e003e006e00ce018e01ff81ff800e000e000e003f800000000; // 4 +assign char_data[ 53] = 256'h000000001ff81c001c001c001c001fe01ff0007800381c381c700fe000000000; // 5 +assign char_data[ 54] = 256'h0000000003e007000e001c001c001ff01ff81c381c381c381c380ff000000000; // 6 +assign char_data[ 55] = 256'h000000001ffc1c1c1c1c1c1c001c0038007000e001c003800380038000000000; // 7 +assign char_data[ 56] = 256'h000000000ff01c381c381c381f3807e007e01cf81c381c381c380ff000000000; // 8 +assign char_data[ 57] = 256'h000000000ff01c381c381c381c381ff80ff800380038007000e007c000000000; // 9 +assign char_data[ 58] = 256'h0000000000000000038003800380000000000380038003800000000000000000; // : +assign char_data[ 59] = 256'h0000000000000000070007000700000000000700070007000e00000000000000; // ; +assign char_data[ 60] = 256'h0000007000e001c0038007000e001c001c000e000700038001c000e000700000; // < +assign char_data[ 61] = 256'h000000000000000000003ffc3ffc000000003ffc3ffc00000000000000000000; // = +assign char_data[ 62] = 256'h00001c000e000700038001c000e00070007000e001c0038007000e001c000000; // > +assign char_data[ 63] = 256'h000003c00ff01e7818380038007000e001c001c00000000001c001c001c00000; // ? +assign char_data[ 64] = 256'h000007f81c1c1c1c1c1c1c1c1cfc1cfc1cfc1cfc1c001c001c001c0007f80000; // @ +assign char_data[ 65] = 256'h0000000003c007e00e701c381c381c381c381ff81c381c381c381c3800000000; // A +assign char_data[ 66] = 256'h000000001ff00e380e380e380e380ff00ff00e380e380e380e381ff000000000; // B +assign char_data[ 67] = 256'h0000000007f00e381c381c001c001c001c001c001c001c380e3807f000000000; // C +assign char_data[ 68] = 256'h000000001fe00e700e380e380e380e380e380e380e380e380e701fe000000000; // D +assign char_data[ 69] = 256'h000000001ff80e180e080e000e300ff00ff00e300e000e080e181ff800000000; // E +assign char_data[ 70] = 256'h000000001ff80e180e080e000e300ff00ff00e300e000e000e001f0000000000; // F +assign char_data[ 71] = 256'h0000000007f00e381c381c381c001c001c001cf81c381c380e3807f800000000; // G +assign char_data[ 72] = 256'h000000001c701c701c701c701c701ff01ff01c701c701c701c701c7000000000; // H +assign char_data[ 73] = 256'h000000001fc007000700070007000700070007000700070007001fc000000000; // I +assign char_data[ 74] = 256'h0000000001fc0070007000700070007000701c701c701c701c700fe000000000; // J +assign char_data[ 75] = 256'h000000001e380e380e700ee00fc00f800f800fc00ee00e700e381e3800000000; // K +assign char_data[ 76] = 256'h000000001f000e000e000e000e000e000e000e000e080e180e381ff800000000; // L +assign char_data[ 77] = 256'h000000001c1c1e3c1f7c1ffc1ffc1ddc1c9c1c1c1c1c1c1c1c1c1c1c00000000; // M +assign char_data[ 78] = 256'h000000001c1c1c1c1e1c1f1c1f9c1ddc1cfc1c7c1c3c1c1c1c1c1c1c00000000; // N +assign char_data[ 79] = 256'h0000000003e007700e381c1c1c1c1c1c1c1c1c1c1c1c0e38077003e000000000; // O +assign char_data[ 80] = 256'h000000001ff00e380e380e380e380ff00ff00e000e000e000e001f0000000000; // P +assign char_data[ 81] = 256'h0000000003e00f780e381c1c1c1c1c1c1c1c1c7c1cfc0ff80ff8003800fc0000; // Q +assign char_data[ 82] = 256'h000000001ff00e380e380e380e380ff00ff00e700e380e380e381e3800000000; // R +assign char_data[ 83] = 256'h000000000ff01c381c381c381c000fe007f000381c381c381c380ff000000000; // S +assign char_data[ 84] = 256'h000000001ffc19cc11c401c001c001c001c001c001c001c001c007f000000000; // T +assign char_data[ 85] = 256'h000000001c701c701c701c701c701c701c701c701c701c701c700fe000000000; // U +assign char_data[ 86] = 256'h000000001c701c701c701c701c701c701c701c701c700ee007c0038000000000; // V +assign char_data[ 87] = 256'h000000001c1c1c1c1c1c1c1c1c1c1c9c1c9c1c9c0ff80f780770077000000000; // W +assign char_data[ 88] = 256'h000000001c701c701c700ee007c00380038007c00ee01c701c701c7000000000; // X +assign char_data[ 89] = 256'h000000001c701c701c701c701c700ee007c003800380038003800fe000000000; // Y +assign char_data[ 90] = 256'h000000001ff81c381838107000e001c0038007000e081c181c381ff800000000; // Z +assign char_data[ 91] = 256'h0000000007f0070007000700070007000700070007000700070007f000000000; // [ +assign char_data[ 92] = 256'h00000000100018001c000e000700038001c000e000700038001c000e00000000; // \ +assign char_data[ 93] = 256'h0000000007f0007000700070007000700070007000700070007007f000000000; // ] +assign char_data[ 94] = 256'h0000018003c007e00e701c380000000000000000000000000000000000000000; // ^ +assign char_data[ 95] = 256'h00000000000000000000000000000000000000000000000000000000ffffffff; // _ +assign char_data[ 96] = 256'h000000001c001c00070007000000000000000000000000000000000000000000; // ` +assign char_data[ 97] = 256'h0000000000000000000000000fe0007000700ff01c701c701c700f9800000000; // a +assign char_data[ 98] = 256'h000000001e000e000e000e000ff00e380e380e380e380e380e3819f000000000; // b +assign char_data[ 99] = 256'h0000000000000000000000000fe01c701c701c001c001c701c700fe000000000; // c +assign char_data[100] = 256'h0000000000f80070007000700ff01c701c701c701c701c701c700f9800000000; // d +assign char_data[101] = 256'h0000000000000000000000000fe01c701c701ff01c001c701c700fe000000000; // e +assign char_data[102] = 256'h0000000003e007700770070007001fe01fe007000700070007001fc000000000; // f +assign char_data[103] = 256'h0000000000000000000000000f981c701c701c701c700ff007f000701c700fe0; // g +assign char_data[104] = 256'h000000001e000e000e000e000ef00f380f380e380e380e380e381e3800000000; // h +assign char_data[105] = 256'h0000000001c001c001c000000fc001c001c001c001c001c001c00ff800000000; // i +assign char_data[106] = 256'h00000000007000700070000003f00070007000700070007000701c701c7007e0; // j +assign char_data[107] = 256'h000000001e000e000e000e000e380e700ee00fc00ee00e700e381e3800000000; // k +assign char_data[108] = 256'h000000000fc001c001c001c001c001c001c001c001c001c001c00ff800000000; // l +assign char_data[109] = 256'h0000000000000000000000001ff81c9c1c9c1c9c1c9c1c9c1c9c1c1c00000000; // m +assign char_data[110] = 256'h0000000000000000000000001fe01c701c701c701c701c701c701c7000000000; // n +assign char_data[111] = 256'h0000000000000000000000000fe01c701c701c701c701c701c700fe000000000; // o +assign char_data[112] = 256'h00000000000000000000000019f00e380e380e380e380e380ff00e000e001f00; // p +assign char_data[113] = 256'h0000000000000000000000001f3038e038e038e038e038e01fe000e000e001f0; // q +assign char_data[114] = 256'h0000000000000000000000001e700ff80f380e000e000e000e001f0000000000; // r +assign char_data[115] = 256'h0000000000000000000000000fe01c301c300f8003e0187018700fe000000000; // s +assign char_data[116] = 256'h0000000000000100030007001ff007000700070007000770077003e000000000; // t +assign char_data[117] = 256'h0000000000000000000000001c701c701c701c701c701c701c700f9800000000; // u +assign char_data[118] = 256'h0000000000000000000000001c701c701c701c701c700ee007c0038000000000; // v +assign char_data[119] = 256'h0000000000000000000000001c1c1c1c1c1c1c9c1c9c0f780770077000000000; // w +assign char_data[120] = 256'h0000000000000000000000001ce01ce00fc0078007800fc01ce01ce000000000; // x +assign char_data[121] = 256'h0000000000000000000000000e380e380e380e380e3807f003e000e001c01f80; // y +assign char_data[122] = 256'h0000000000000000000000001fe018e011c0038007000e201c601fe000000000; // z +assign char_data[123] = 256'h0000000001f803800380038007001c001c00070003800380038001f800000000; // { +assign char_data[124] = 256'h0000000003c003c003c003c003c00000000003c003c003c003c003c000000000; // | +assign char_data[125] = 256'h000000001f8001c001c001c000e00038003800e001c001c001c01f8000000000; // } +assign char_data[126] = 256'h000000001f1c3b9c39dc38f80000000000000000000000000000000000000000; // ~ +assign char_data[127] = 256'h00000000018003c007e00e701c38181818181818181818181ff81ff800000000; +assign char_data[128] = 256'h000007f00e381c381c001c001c001c001c001c001c380e3807f001c00fc00fc0; +assign char_data[129] = 256'h00001c701c701c70000000001c701c701c701c701c701c701c70079800000000; +assign char_data[130] = 256'h000001c003800700000000000fe01c701c701ff01c001c701c700fe000000000; +assign char_data[131] = 256'h0000038006c00c60000000000fe0007000700ff01c701c701c700f9800000000; +assign char_data[132] = 256'h00001c701c701c70000000000fe0007000700ff01c701c701c700f9800000000; +assign char_data[133] = 256'h00000700038001c0000000000fe0007000700ff01c701c701c700f9800000000; +assign char_data[134] = 256'h0180024002400180000000000fe0007000700ff01c701c701c700f9800000000; +assign char_data[135] = 256'h0000000000000000000000000fe01c701c701c001c001c701c700fe003801f80; +assign char_data[136] = 256'h0000038006c00c60000000000fe01c701c701ff01c001c701c700fe000000000; +assign char_data[137] = 256'h00001c701c701c70000000000fe01c701c701ff01c001c701c700fe000000000; +assign char_data[138] = 256'h00000700038001c0000000000fe01c701c701ff01c001c701c700fe000000000; +assign char_data[139] = 256'h00001c701c701c70000000000fc001c001c001c001c001c001c00ff800000000; +assign char_data[140] = 256'h0000038006c00c60000000000fc001c001c001c001c001c001c00ff800000000; +assign char_data[141] = 256'h00000700038001c0000000000fc001c001c001c001c001c001c00ff800000000; +assign char_data[142] = 256'h00000e700e70000003c007e00e701c381c381c381ff81c381c381c3800000000; +assign char_data[143] = 256'h018002400180000003c007e00e701c381c381c381ff81c381c381c3800000000; +assign char_data[144] = 256'h000000e0038000001ff80e180e080e200fe00fe00e200e080e181ff800000000; +assign char_data[145] = 256'h0000000000000000000000000ff0019801980ff81980199819980ef000000000; +assign char_data[146] = 256'h0000000007f80ff81d80398031803ff83ff831803180318031f831f800000000; +assign char_data[147] = 256'h0000038006c00c60000000000fe01c701c701c701c701c701c700fe000000000; +assign char_data[148] = 256'h00001c701c701c70000000000fe01c701c701c701c701c701c700fe000000000; +assign char_data[149] = 256'h00000700038001c0000000000fe01c701c701c701c701c701c700fe000000000; +assign char_data[150] = 256'h0000038006c00c60000000001c701c701c701c701c701c701c700f9800000000; +assign char_data[151] = 256'h00000700038001c0000000001c701c701c701c701c701c701c700f9800000000; +assign char_data[152] = 256'h00000e380e380e38000000000e380e380e380e380e3807f003e000e001c01f80; +assign char_data[153] = 256'h00000e700e70000007e00e701c381c381c381c381c381c380e7007e000000000; +assign char_data[154] = 256'h00001c701c7000001c701c701c701c701c701c701c701c701c700fe000000000; +assign char_data[155] = 256'h00000380038003800fe01c701c701c001c001c701c700fe00380038003800000; +assign char_data[156] = 256'h000001e003f0071807000700070007001fe01fe0070007000e080e180ff80000; +assign char_data[157] = 256'h00000e700e700e700e700e7003c001800ff001800ff001800180018001800000; +assign char_data[158] = 256'h00003f8030c030c030c030c030c03f003080308031cc3084309c309430da0000; +assign char_data[159] = 256'h00fc01ce01ce01c001c00ff801c001c001c001c039c039c01f80000000000000; +assign char_data[160] = 256'h000001c0038007000000000007e0007000700ff01c701c701c700f9800000000; +assign char_data[161] = 256'h000001c003800700000000000fc001c001c001c001c001c001c00ff800000000; +assign char_data[162] = 256'h000001c003800700000000000fe01c701c701c701c701c701c700fe000000000; +assign char_data[163] = 256'h000001c003800700000000001c701c701c701c701c701c701c700f9800000000; +assign char_data[164] = 256'h00000e383bb838e0000000001fe01c701c701c701c701c701c701c7000000000; +assign char_data[165] = 256'h0000079c1cf000001c1c1e1c1f1c1f9c1ddc1cfc1c7c1c3c1c1c1c1c00000000; +assign char_data[166] = 256'h0000000007c0006003e00c600c6003b000001ff8000000000000000000000000; +assign char_data[167] = 256'h0000000003c00e700c300c300e7003c000001ff8000000000000000000000000; +assign char_data[168] = 256'h0000038003800380000000000380038007000e001c001c181e780ff003c00000; +assign char_data[169] = 256'h0000000000000000000000003ff03ff030003000300030000000000000000000; +assign char_data[170] = 256'h0000000000000000000000003ff03ff000300030003000300000000000000000; +assign char_data[171] = 256'h000000000c0e1c1c1c380c700ce00ddc03b607060e0c1c181830103e00000000; +assign char_data[172] = 256'h000000000c0e1c1c1c380c700ce60dce039e07360e661c7e1806100600000000; +assign char_data[173] = 256'h00000000038003800380000000000380038007c007c007c007c007c003800000; +assign char_data[174] = 256'h000000000000000000000000038e071c0e381c701c700e38071c038e00000000; +assign char_data[175] = 256'h0000000000000000000000001c700e38071c038e038e071c0e381c7000000000; +assign char_data[176] = 256'hcccc666633339999cccc666633339999cccc666633339999cccc666633339999; +assign char_data[177] = 256'haaaa77777777aaaaaaaa77777777aaaaaaaa77777777aaaaaaaa77777777aaaa; +assign char_data[178] = 256'haaaadddd7777bbbbaaaadddd7777bbbbaaaadddd7777bbbbaaaadddd7777bbbb; +assign char_data[179] = 256'h0180018001800180018001800180018001800180018001800180018001800180; +assign char_data[180] = 256'h0180018001800180018001800180ff80ff800180018001800180018001800180; +assign char_data[181] = 256'h01800180018001800180ff80ff8001800180ff80ff8001800180018001800180; +assign char_data[182] = 256'h0660066006600660066006600660fe60fe600660066006600660066006600660; +assign char_data[183] = 256'h0000000000000000000000000000ffe0ffe00660066006600660066006600660; +assign char_data[184] = 256'h00000000000000000000ff80ff8001800180ff80ff8001800180018001800180; +assign char_data[185] = 256'h06600660066006600660fe60fe6000600060fe60fe6006600660066006600660; +assign char_data[186] = 256'h0660066006600660066006600660066006600660066006600660066006600660; +assign char_data[187] = 256'h00000000000000000000ffe0ffe000600060fe60fe6006600660066006600660; +assign char_data[188] = 256'h06600660066006600660fe60fe6000600060ffe0ffe000000000000000000000; +assign char_data[189] = 256'h0660066006600660066006600660ffe0ffe00000000000000000000000000000; +assign char_data[190] = 256'h01800180018001800180ff80ff8001800180ff80ff8000000000000000000000; +assign char_data[191] = 256'h0000000000000000000000000000ff80ff800180018001800180018001800180; +assign char_data[192] = 256'h018001800180018001800180018001ff01ff0000000000000000000000000000; +assign char_data[193] = 256'h0180018001800180018001800180ffffffff0000000000000000000000000000; +assign char_data[194] = 256'h0000000000000000000000000000ffffffff0180018001800180018001800180; +assign char_data[195] = 256'h018001800180018001800180018001ff01ff0180018001800180018001800180; +assign char_data[196] = 256'h0000000000000000000000000000ffffffff0000000000000000000000000000; +assign char_data[197] = 256'h0180018001800180018001800180ffffffff0180018001800180018001800180; +assign char_data[198] = 256'h0180018001800180018001ff01ff0180018001ff01ff01800180018001800180; +assign char_data[199] = 256'h0660066006600660066006600660067f067f0660066006600660066006600660; +assign char_data[200] = 256'h06600660066006600660067f067f0600060007ff07ff00000000000000000000; +assign char_data[201] = 256'h0000000000000000000007ff07ff06000600067f067f06600660066006600660; +assign char_data[202] = 256'h06600660066006600660fe7ffe7f00000000ffffffff00000000000000000000; +assign char_data[203] = 256'h00000000000000000000ffffffff00000000fe7ffe7f06600660066006600660; +assign char_data[204] = 256'h06600660066006600660067f067f06000600067f067f06600660066006600660; +assign char_data[205] = 256'h00000000000000000000ffffffff00000000ffffffff00000000000000000000; +assign char_data[206] = 256'h06600660066006600660fe7ffe7f00000000fe7ffe7f06600660066006600660; +assign char_data[207] = 256'h01800180018001800180ffffffff00000000ffffffff00000000000000000000; +assign char_data[208] = 256'h0660066006600660066006600660ffffffff0000000000000000000000000000; +assign char_data[209] = 256'h00000000000000000000ffffffff00000000ffffffff01800180018001800180; +assign char_data[210] = 256'h0000000000000000000000000000ffffffff0660066006600660066006600660; +assign char_data[211] = 256'h066006600660066006600660066007ff07ff0000000000000000000000000000; +assign char_data[212] = 256'h0180018001800180018001ff01ff0180018001ff01ff00000000000000000000; +assign char_data[213] = 256'h0000000000000000000001ff01ff0180018001ff01ff01800180018001800180; +assign char_data[214] = 256'h000000000000000000000000000007ff07ff0660066006600660066006600660; +assign char_data[215] = 256'h0660066006600660066006600660fe7ffe7f0660066006600660066006600660; +assign char_data[216] = 256'h01800180018001800180ffffffff00000000ffffffff01800180018001800180; +assign char_data[217] = 256'h0180018001800180018001800180ff80ff800000000000000000000000000000; +assign char_data[218] = 256'h000000000000000000000000000001ff01ff0180018001800180018001800180; +assign char_data[219] = 256'hffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff; +assign char_data[220] = 256'h00000000000000000000000000000000ffffffffffffffffffffffffffffffff; +assign char_data[221] = 256'hffc0ffc0ffc0ffc0ffc0ffc0ffc0ffc0ffc0ffc0ffc0ffc0ffc0ffc0ffc0ffc0; +assign char_data[222] = 256'h00ff00ff00ff00ff00ff00ff00ff00ff00ff00ff00ff00ff00ff00ff00ff00ff; +assign char_data[223] = 256'hffffffffffffffffffffffffffffffff00000000000000000000000000000000; +assign char_data[224] = 256'h0000000000000000000000000f8c1fdc18f81870187018f81fdc0f8c00000000; +assign char_data[225] = 256'h000000000ff01e381c381c701ce01ce01c701c381c381c381c381cf000000000; +assign char_data[226] = 256'hff00ff00ff00ff00ff00ff00ff00ff0000000000000000000000000000000000; +assign char_data[227] = 256'h00ff00ff00ff00ff00ff00ff00ff00ff00000000000000000000000000000000; +assign char_data[228] = 256'hffffffffffffffffffffffffffffffff00000000000000000000000000000000; +assign char_data[229] = 256'h0000000000000000000000000000000000ff00ff00ff00ff00ff00ff00ff00ff; +assign char_data[230] = 256'hff00ff00ff00ff00ff00ff00ff00ff0000ff00ff00ff00ff00ff00ff00ff00ff; +assign char_data[231] = 256'h00ff00ff00ff00ff00ff00ff00ff00ff00ff00ff00ff00ff00ff00ff00ff00ff; +assign char_data[232] = 256'h00000000000000000000000000000000ff00ff00ff00ff00ff00ff00ff00ff00; +assign char_data[233] = 256'h000007e00ff01ff83c3c381c381c3ffc3ffc381c381c3c3c1ff80ff007e00000; +assign char_data[234] = 256'h00000ff01ff83c3c381c381c381c381c381c3c3c1e780e702e743e7c3e7c0000; +assign char_data[235] = 256'h0000000007f00e000e0007800fc01ce03870387038701ce00fc0078000000000; +assign char_data[236] = 256'h000000000000000000000f3839ce39ce39ce39ce0e7800000000000000000000; +assign char_data[237] = 256'h000000000000000803d007e00c700cb00d300e3007e00bc01000000000000000; +assign char_data[238] = 256'h0000000007f00e000c00180018001ff01ff0180018000c000e0007f000000000; +assign char_data[239] = 256'h0000000000000fe01ff03c783c783c783c783c783c783c783c783c7800000000; +assign char_data[240] = 256'h0000000000001ff81ff8000000001ff81ff8000000001ff81ff8000000000000; +assign char_data[241] = 256'h0000000001800180018001801ff81ff8018001800180018000001ff81ff80000; +assign char_data[242] = 256'h000000000700038001c000e00070007000e001c00380070000001ff81ff80000; +assign char_data[243] = 256'h00000000007000e001c0038007000700038001c000e0007000001ff81ff80000; +assign char_data[244] = 256'h0000000000f801fc01ce01ce01c001c001c001c001c001c001c001c001c001c0; +assign char_data[245] = 256'h01c001c001c001c001c001c001c001c001c001c039c039c01fc00f8000000000; +assign char_data[246] = 256'h00000000038003800380000000003ff83ff80000000003800380038000000000; +assign char_data[247] = 256'h0000000000001f1c3b9c39dc38f80000000000001f1c3b9c39dc38f800000000; +assign char_data[248] = 256'h000003c007e00e700c300c300e7007e003c00000000000000000000000000000; +assign char_data[249] = 256'h000000000000000000000000018003c003c00180000000000000000000000000; +assign char_data[250] = 256'h0000000000000000000000000000018001800000000000000000000000000000; +assign char_data[251] = 256'h00000000003c002000200020002038203c200e20072003e001e000e000000000; +assign char_data[252] = 256'h00000ef007380738073807380738073807380000000000000000000000000000; +assign char_data[253] = 256'h000007f007f80038003800f003c007f807f80000000000000000000000000000; +assign char_data[254] = 256'h0000000001f801f801f801f801f801f801f801f801f801f801f8000000000000; +assign char_data[255] = 256'h0000000000000000000000000000000000000000000000000000000000000000; + +endmodule diff --git a/src/color_map.v b/src/color_map.v new file mode 100644 index 0000000..f336ff2 --- /dev/null +++ b/src/color_map.v @@ -0,0 +1,54 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 22:16:37 09/18/2020 +// Design Name: +// Module Name: color_map +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module color_map( + input clk, + input[3:0] colorcode, + output reg[23:0] color +); + +wire [23:0] colors [15:0]; + +always @(posedge clk) begin + color <= colors[colorcode]; +end + +// VGA Colors +// Normal colors +assign colors[0] = 24'h000000; +assign colors[1] = 24'hAA0000; +assign colors[2] = 24'h00AA00; +assign colors[3] = 24'hAA5500; +assign colors[4] = 24'h0000AA; +assign colors[5] = 24'hAA00AA; +assign colors[6] = 24'h00AAAA; +assign colors[7] = 24'hAAAAAA; + +// Bright colors +assign colors[8] = 24'h555555; +assign colors[9] = 24'hFF5555; +assign colors[10] = 24'h55FF55; +assign colors[11] = 24'hFFFF55; +assign colors[12] = 24'h5555FF; +assign colors[13] = 24'hFF55FF; +assign colors[14] = 24'h55FFFF; +assign colors[15] = 24'hFFFFFF; + +endmodule diff --git a/src/dvi_top.v b/src/dvi_top.v new file mode 100644 index 0000000..5e112b2 --- /dev/null +++ b/src/dvi_top.v @@ -0,0 +1,165 @@ +module dvi_top ( + input clk, + input rst, + output [3:0] tmds, + output [3:0] tmdsb, + + output [7:0] LED, + + inout [7:0] zdata, + input [7:0] zaddr, + input zclk, + input zioreq, + input zm1, + input zwr, + input zrd +); + +// Generate all the required clocks +wire clk_dvi, clk_dvin, clk_pix, clk_mcu; +clk_wiz_0 clocking( + .reset(rst), + .clk_in(clk), + .clk_dvi(clk_dvi), // 5x pix clock + .clk_dvin(clk_dvin), // 5x pix clock (inv) + .clk_pix(clk_pix), + .clk_mcu(clk_mcu) +); + +// Position counters +reg [10:0] counter_x; +reg [9:0] counter_y; +always @(posedge clk_pix) begin + counter_x <= (counter_x == 1663) ? 0 : counter_x + 1; + if (counter_x == 1663) begin + counter_y <= (counter_y == 747) ? 0 : counter_y + 1; + end +end + +// Sync signals +wire hsync = (counter_x >= (1280+64)) && (counter_x < (1280+64+128)); +wire vsync = (counter_y >= (720+3)) && (counter_y < (720+3+5)); + +// Blank signals +wire de = (counter_x < 1280) && (counter_y < 720); +wire blank = ~de; + +wire [15:0] write_data; +wire [15:0] read_data; +wire write_enable; + +wire [3:0] char_x = counter_x % 16; +wire [3:0] char_y = counter_y % 16; + +wire [7:0] screen_x, screen_y; +wire [5:0] scroll; +wire ready; + +wire [13:0] waddr = (screen_x % (80+24)) + (80+24)*((screen_y + scroll) % (45+2)); +wire [13:0] raddr = (((counter_x+2) >> 4) % (80+24)) + (80+24)*((( (counter_x > 1280) ? ((counter_y+1) >> 4) : (counter_y >> 4)) + scroll) % (45+2)); + +wire [255:0] char; + +wire io_write = (zioreq == 0 && zm1 == 1 && zwr == 0 && zaddr == 8'h02); +wire io_read = (zioreq == 0 && zm1 == 1 && zrd == 0 && zaddr == 8'h03); + +assign zdata[7:0] = io_read ? {7'b0, ready} : 8'bZ; + +assign LED[7:0] = 8'b11000011; + +wire cursor = (((counter_x >> 4) == screen_x) && ((counter_y >> 4) == screen_y)); + + +wire [23:0] foreground, background; + +// Calculate the colors +reg [7:0] red, green, blue; +always @(*) begin + if (char[255 - char_x - 16*char_y] == 1) begin + red = cursor ? 8'h00 : foreground[23:16]; + green = cursor ? 8'h00 : foreground[15:8]; + blue = cursor ? 8'h00 : foreground[7:0]; + end else begin + red = cursor ? 8'hAA : background[23:16]; + green = cursor ? 8'hAA : background[15:8]; + blue = cursor ? 8'h99 : background[7:0]; + end +end + +microblaze_mcs_0 mcs( + .Clk(clk_mcu), + .Reset(rst), + .GPIO1_tri_o(write_data), + .GPIO2_tri_o({screen_y, screen_x}), + .GPIO3_tri_o({ready, write_enable}), + .GPIO4_tri_o(scroll), + .GPIO1_tri_i(zdata), + .GPIO2_tri_i(zclk), + .GPI2_Interrupt(), + .GPIO3_tri_i(io_write), + .INTC_IRQ() +); + +simple_dual_ram #(.SIZE(16), .DEPTH((80+24)*(45+2))) vram ( + .wclk(clk_mcu), + .waddr(waddr), + .write_data(write_data), + .write_en(write_enable), + .rclk(clk_pix), + .raddr(raddr), + .read_data(read_data) +); + +char_map char_map( + .clk(clk_pix), + .index(read_data[7:0]), + .char(char) +); + +color_map foreground_map( + .clk(clk_pix), + .colorcode(read_data[11:8]), + .color(foreground) +); + +color_map background_map( + .clk(clk_pix), + .colorcode(read_data[15:12]), + .color(background) +); + +// Generate the actual signal we output +wire blue_s, green_s, red_s, clock_s; + +OBUFDS OBUFDS_blue (.O(tmds[0]), .OB(tmdsb[0]), .I(blue_s)); +OBUFDS OBUFDS_green (.O(tmds[1]), .OB(tmdsb[1]), .I(green_s)); +OBUFDS OBUFDS_red (.O(tmds[2]), .OB(tmdsb[2]), .I(red_s)); +OBUFDS OBUFDS_clock (.O(tmds[3]), .OB(tmdsb[3]), .I(clock_s)); + +dvid dvid ( + .clk (clk_dvi), + .clk_n (clk_dvin), + .clk_pixel (clk_pix), + .rst (rst), + + // input rgb data + .red_p (red), + .green_p (green), + .blue_p (blue), + + // vga timing signals + .de (de), + .blank (blank), + .hsync (hsync), + .vsync (vsync), + + // serialized data ready for differential output buffer + .red_s (red_s), + .green_s (green_s), + .blue_s (blue_s), + + // Forwarded clock for differential output buffer + .clock_s (clock_s) +); + +endmodule // dvi \ No newline at end of file diff --git a/src/dvid.v b/src/dvid.v new file mode 100644 index 0000000..bd1972f --- /dev/null +++ b/src/dvid.v @@ -0,0 +1,70 @@ +module dvid ( + input clk, + input clk_n, + input clk_pixel, + input rst, + + input [7:0] red_p, + input [7:0] green_p, + input [7:0] blue_p, + + input blank, + input de, + input hsync, + input vsync, + + output red_s, + output green_s, + output blue_s, + output clock_s +); + +wire [9:0] encoded_red, encoded_green, encoded_blue; +reg [9:0] latched_red = 0, latched_green = 0, latched_blue = 0; +reg [9:0] shift_red = 0, shift_green = 0, shift_blue = 0; +reg [9:0] shift_clock = 10'b0000011111; + +//dvi_encoder dvi_encoder_red (.clk(clk_pixel), .rst(rst), .c0(0), .c1(0), .de(de), .d(red_p), .q_out(encoded_red)); +//dvi_encoder dvi_encoder_green (.clk(clk_pixel), .rst(rst), .c0(0), .c1(0), .de(de), .d(green_p), .q_out(encoded_green)); +//dvi_encoder dvi_encoder_blue (.clk(clk_pixel), .rst(rst), .c0(hsync), .c1(vsync), .de(de), .d(blue_p), .q_out(encoded_blue)); + +encode dvi_encoder_red (.clkin(clk_pixel), .rstin(rst), .c0(0), .c1(0), .de(de), .din(red_p), .dout(encoded_red)); +encode dvi_encoder_green (.clkin(clk_pixel), .rstin(rst), .c0(0), .c1(0), .de(de), .din(green_p), .dout(encoded_green)); +encode dvi_encoder_blue (.clkin(clk_pixel), .rstin(rst), .c0(hsync), .c1(vsync), .de(de), .din(blue_p), .dout(encoded_blue)); + + +ODDR2 #(.DDR_ALIGNMENT("C0"), .INIT(0), .SRTYPE("ASYNC")) + ODDR_red(.Q(red_s), .D0(shift_red[0]), .D1(shift_red[1]), .C0(clk), .C1(clk_n), .CE(1), .R(0), .S(0)); + +ODDR2 #(.DDR_ALIGNMENT("C0"), .INIT(0), .SRTYPE("ASYNC")) + ODDR_green(.Q(green_s), .D0(~shift_green[0]), .D1(~shift_green[1]), .C0(clk), .C1(clk_n), .CE(1), .R(0), .S(0)); + +ODDR2 #(.DDR_ALIGNMENT("C0"), .INIT(0), .SRTYPE("ASYNC")) + ODDR_blue(.Q(blue_s), .D0(shift_blue[0]), .D1(shift_blue[1]), .C0(clk), .C1(clk_n), .CE(1), .R(0), .S(0)); + +// ODDR2 #(.DDR_ALIGNMENT("C0"), .INIT(0), .SRTYPE("ASYNC")) +// ODDR_clock(.Q(clock_s), .D0(shift_clock[0]), .D1(shift_clock[1]), .C0(clk), .C1(clk_n), .CE(1), .R(0), .S(0)); + +ODDR2 #(.DDR_ALIGNMENT("C0"), .INIT(0), .SRTYPE("ASYNC")) + ODDR_clock(.Q(clock_s), .D0(0), .D1(1), .C0(clk_pixel), .C1(~clk_pixel), .CE(1), .R(0), .S(0)); + +always @ ( posedge clk_pixel ) begin + latched_red <= encoded_red; + latched_green <= encoded_green; + latched_blue <= encoded_blue; +end + +always @ ( posedge clk ) begin + if (shift_clock == 10'b0000011111) begin + shift_red <= latched_red; + shift_green <= latched_green; + shift_blue <= latched_blue; + end else begin + shift_red <= { 2'b00, shift_red[9:2] }; + shift_green <= { 2'b00, shift_green[9:2] }; + shift_blue <= { 2'b00, shift_blue[9:2] }; + end + shift_clock <= { shift_clock[1:0], shift_clock[9:2] }; +end + +endmodule // dvid diff --git a/src/encode.v b/src/encode.v new file mode 100644 index 0000000..696b57c --- /dev/null +++ b/src/encode.v @@ -0,0 +1,190 @@ +////////////////////////////////////////////////////////////////////////////// +// +// Xilinx, Inc. 2008 www.xilinx.com +// +////////////////////////////////////////////////////////////////////////////// +// +// File name : encode.v +// +// Description : TMDS encoder +// +// Date - revision : Jan. 2008 - v 1.0 +// +// Author : Bob Feng +// +// Disclaimer: LIMITED WARRANTY AND DISCLAMER. These designs are +// provided to you "as is". Xilinx and its licensors make and you +// receive no warranties or conditions, express, implied, +// statutory or otherwise, and Xilinx specifically disclaims any +// implied warranties of merchantability, non-infringement,or +// fitness for a particular purpose. Xilinx does not warrant that +// the functions contained in these designs will meet your +// requirements, or that the operation of these designs will be +// uninterrupted or error free, or that defects in the Designs +// will be corrected. Furthermore, Xilinx does not warrantor +// make any representations regarding use or the results of the +// use of the designs in terms of correctness, accuracy, +// reliability, or otherwise. +// +// LIMITATION OF LIABILITY. In no event will Xilinx or its +// licensors be liable for any loss of data, lost profits,cost +// or procurement of substitute goods or services, or for any +// special, incidental, consequential, or indirect damages +// arising from the use or operation of the designs or +// accompanying documentation, however caused and on any theory +// of liability. This limitation will apply even if Xilinx +// has been advised of the possibility of such damage. This +// limitation shall apply not-withstanding the failure of the +// essential purpose of any limited remedies herein. +// +// Copyright © 2006 Xilinx, Inc. +// All rights reserved +// +////////////////////////////////////////////////////////////////////////////// + +module encode ( + input clkin, // pixel clock input + input rstin, // async. reset input (active high) + input [7:0] din, // data inputs: expect registered + input c0, // c0 input + input c1, // c1 input + input de, // de input + output reg [9:0] dout // data outputs +); + + //////////////////////////////////////////////////////////// + // Counting number of 1s and 0s for each incoming pixel + // component. Pipe line the result. + // Register Data Input so it matches the pipe lined adder + // output + //////////////////////////////////////////////////////////// + reg [3:0] n1d; //number of 1s in din + reg [7:0] din_q; + + always @ (posedge clkin) begin + n1d <=#1 din[0] + din[1] + din[2] + din[3] + din[4] + din[5] + din[6] + din[7]; + + din_q <=#1 din; + end + + /////////////////////////////////////////////////////// + // Stage 1: 8 bit -> 9 bit + // Refer to DVI 1.0 Specification, page 29, Figure 3-5 + /////////////////////////////////////////////////////// + wire decision1; + + assign decision1 = (n1d > 4'h4) | ((n1d == 4'h4) & (din_q[0] == 1'b0)); +/* + reg [8:0] q_m; + always @ (posedge clkin) begin + q_m[0] <=#1 din_q[0]; + q_m[1] <=#1 (decision1) ? (q_m[0] ^~ din_q[1]) : (q_m[0] ^ din_q[1]); + q_m[2] <=#1 (decision1) ? (q_m[1] ^~ din_q[2]) : (q_m[1] ^ din_q[2]); + q_m[3] <=#1 (decision1) ? (q_m[2] ^~ din_q[3]) : (q_m[2] ^ din_q[3]); + q_m[4] <=#1 (decision1) ? (q_m[3] ^~ din_q[4]) : (q_m[3] ^ din_q[4]); + q_m[5] <=#1 (decision1) ? (q_m[4] ^~ din_q[5]) : (q_m[4] ^ din_q[5]); + q_m[6] <=#1 (decision1) ? (q_m[5] ^~ din_q[6]) : (q_m[5] ^ din_q[6]); + q_m[7] <=#1 (decision1) ? (q_m[6] ^~ din_q[7]) : (q_m[6] ^ din_q[7]); + q_m[8] <=#1 (decision1) ? 1'b0 : 1'b1; + end +*/ + wire [8:0] q_m; + assign q_m[0] = din_q[0]; + assign q_m[1] = (decision1) ? (q_m[0] ^~ din_q[1]) : (q_m[0] ^ din_q[1]); + assign q_m[2] = (decision1) ? (q_m[1] ^~ din_q[2]) : (q_m[1] ^ din_q[2]); + assign q_m[3] = (decision1) ? (q_m[2] ^~ din_q[3]) : (q_m[2] ^ din_q[3]); + assign q_m[4] = (decision1) ? (q_m[3] ^~ din_q[4]) : (q_m[3] ^ din_q[4]); + assign q_m[5] = (decision1) ? (q_m[4] ^~ din_q[5]) : (q_m[4] ^ din_q[5]); + assign q_m[6] = (decision1) ? (q_m[5] ^~ din_q[6]) : (q_m[5] ^ din_q[6]); + assign q_m[7] = (decision1) ? (q_m[6] ^~ din_q[7]) : (q_m[6] ^ din_q[7]); + assign q_m[8] = (decision1) ? 1'b0 : 1'b1; + + ///////////////////////////////////////////////////////// + // Stage 2: 9 bit -> 10 bit + // Refer to DVI 1.0 Specification, page 29, Figure 3-5 + ///////////////////////////////////////////////////////// + reg [3:0] n1q_m, n0q_m; // number of 1s and 0s for q_m + always @ (posedge clkin) begin + n1q_m <=#1 q_m[0] + q_m[1] + q_m[2] + q_m[3] + q_m[4] + q_m[5] + q_m[6] + q_m[7]; + n0q_m <=#1 4'h8 - (q_m[0] + q_m[1] + q_m[2] + q_m[3] + q_m[4] + q_m[5] + q_m[6] + q_m[7]); + end + + parameter CTRLTOKEN0 = 10'b1101010100; + parameter CTRLTOKEN1 = 10'b0010101011; + parameter CTRLTOKEN2 = 10'b0101010100; + parameter CTRLTOKEN3 = 10'b1010101011; + + reg [4:0] cnt; //disparity counter, MSB is the sign bit + wire decision2, decision3; + + assign decision2 = (cnt == 5'h0) | (n1q_m == n0q_m); + ///////////////////////////////////////////////////////////////////////// + // [(cnt > 0) and (N1q_m > N0q_m)] or [(cnt < 0) and (N0q_m > N1q_m)] + ///////////////////////////////////////////////////////////////////////// + assign decision3 = (~cnt[4] & (n1q_m > n0q_m)) | (cnt[4] & (n0q_m > n1q_m)); + + //////////////////////////////////// + // pipe line alignment + //////////////////////////////////// + reg de_q, de_reg; + reg c0_q, c1_q; + reg c0_reg, c1_reg; + reg [8:0] q_m_reg; + + always @ (posedge clkin) begin + de_q <=#1 de; + de_reg <=#1 de_q; + + c0_q <=#1 c0; + c0_reg <=#1 c0_q; + c1_q <=#1 c1; + c1_reg <=#1 c1_q; + + q_m_reg <=#1 q_m; + end + + /////////////////////////////// + // 10-bit out + // disparity counter + /////////////////////////////// + always @ (posedge clkin or posedge rstin) begin + if(rstin) begin + dout <= 10'h0; + cnt <= 5'h0; + end else begin + if (de_reg) begin + if(decision2) begin + dout[9] <=#1 ~q_m_reg[8]; + dout[8] <=#1 q_m_reg[8]; + dout[7:0] <=#1 (q_m_reg[8]) ? q_m_reg[7:0] : ~q_m_reg[7:0]; + + cnt <=#1 (~q_m_reg[8]) ? (cnt + n0q_m - n1q_m) : (cnt + n1q_m - n0q_m); + end else begin + if(decision3) begin + dout[9] <=#1 1'b1; + dout[8] <=#1 q_m_reg[8]; + dout[7:0] <=#1 ~q_m_reg; + + cnt <=#1 cnt + {q_m_reg[8], 1'b0} + (n0q_m - n1q_m); + end else begin + dout[9] <=#1 1'b0; + dout[8] <=#1 q_m_reg[8]; + dout[7:0] <=#1 q_m_reg[7:0]; + + cnt <=#1 cnt - {~q_m_reg[8], 1'b0} + (n1q_m - n0q_m); + end + end + end else begin + case ({c1_reg, c0_reg}) + 2'b00: dout <=#1 CTRLTOKEN0; + 2'b01: dout <=#1 CTRLTOKEN1; + 2'b10: dout <=#1 CTRLTOKEN2; + default: dout <=#1 CTRLTOKEN3; + endcase + + cnt <=#1 5'h0; + end + end + end + +endmodule diff --git a/src/hdmi.xdc b/src/hdmi.xdc new file mode 100644 index 0000000..f533cee --- /dev/null +++ b/src/hdmi.xdc @@ -0,0 +1,107 @@ +#set_property CFGBVS VCCO [current_design] +#set_property CONFIG_VOLTAGE 3.3 [current_design] +## CLOCK 100MHz and Reset # +##################################################################################################################### +#set_property -dict { PACKAGE_PIN "N11" IOSTANDARD LVCMOS33} [get_ports { clk }]; +#set_property -dict { PACKAGE_PIN "N6" IOSTANDARD LVCMOS33} [get_ports { rst }]; +##################################################################################################################### +## LEDs # +##################################################################################################################### +#set_property -dict { PACKAGE_PIN "K12" IOSTANDARD LVCMOS33 SLEW FAST} [get_ports { LED[0] }]; +#set_property -dict { PACKAGE_PIN "K13" IOSTANDARD LVCMOS33 SLEW FAST} [get_ports { LED[1] }]; +#set_property -dict { PACKAGE_PIN "R10" IOSTANDARD LVCMOS33 SLEW FAST} [get_ports { LED[2] }]; +#set_property -dict { PACKAGE_PIN "R13" IOSTANDARD LVCMOS33 SLEW FAST} [get_ports { LED[3] }]; +#set_property -dict { PACKAGE_PIN "T13" IOSTANDARD LVCMOS33 SLEW FAST} [get_ports { LED[4] }]; +#set_property -dict { PACKAGE_PIN "R12" IOSTANDARD LVCMOS33 SLEW FAST} [get_ports { LED[5] }]; +#set_property -dict { PACKAGE_PIN "T12" IOSTANDARD LVCMOS33 SLEW FAST} [get_ports { LED[6] }]; +#set_property -dict { PACKAGE_PIN "R11" IOSTANDARD LVCMOS33 SLEW FAST} [get_ports { LED[7] }]; +##################################################################################################################### +## TDMS # +##################################################################################################################### +#set_property -dict { PACKAGE_PIN "F15" IOSTANDARD TMDS_33} [get_ports { tmds[0] }]; # Blue +#set_property -dict { PACKAGE_PIN "E15" IOSTANDARD TMDS_33} [get_ports { tmdsb[0] }]; +#set_property -dict { PACKAGE_PIN "G14" IOSTANDARD TMDS_33} [get_ports { tmds[1] }]; # Green +#set_property -dict { PACKAGE_PIN "F14" IOSTANDARD TMDS_33} [get_ports { tmdsb[1] }]; +#set_property -dict { PACKAGE_PIN "J15" IOSTANDARD TMDS_33} [get_ports { tmds[2] }]; # Red +#set_property -dict { PACKAGE_PIN "J16" IOSTANDARD TMDS_33} [get_ports { tmdsb[2] }]; +#set_property -dict { PACKAGE_PIN "H14" IOSTANDARD TMDS_33} [get_ports { tmds[3] }]; # Clock +#set_property -dict { PACKAGE_PIN "G15" IOSTANDARD TMDS_33} [get_ports { tmdsb[3] }]; +##################################################################################################################### +## Z80 # +##################################################################################################################### +#set_property -dict { PACKAGE_PIN "C12" IOSTANDARD LVCMOS33} [get_ports { zdata[0] }]; +#set_property -dict { PACKAGE_PIN "C11" IOSTANDARD LVCMOS33} [get_ports { zdata[1] }]; +#set_property -dict { PACKAGE_PIN "C13" IOSTANDARD LVCMOS33} [get_ports { zdata[2] }]; +#set_property -dict { PACKAGE_PIN "D13" IOSTANDARD LVCMOS33} [get_ports { zdata[3] }]; +#set_property -dict { PACKAGE_PIN "B14" IOSTANDARD LVCMOS33} [get_ports { zdata[4] }]; +#set_property -dict { PACKAGE_PIN "C14" IOSTANDARD LVCMOS33} [get_ports { zdata[5] }]; +#set_property -dict { PACKAGE_PIN "D15" IOSTANDARD LVCMOS33} [get_ports { zdata[6] }]; +#set_property -dict { PACKAGE_PIN "D14" IOSTANDARD LVCMOS33} [get_ports { zdata[7] }]; + +#set_property -dict { PACKAGE_PIN "C16" IOSTANDARD LVCMOS33} [get_ports { zaddr[0] }]; +#set_property -dict { PACKAGE_PIN "B16" IOSTANDARD LVCMOS33} [get_ports { zaddr[1] }]; +#set_property -dict { PACKAGE_PIN "B15" IOSTANDARD LVCMOS33} [get_ports { zaddr[2] }]; +#set_property -dict { PACKAGE_PIN "A15" IOSTANDARD LVCMOS33} [get_ports { zaddr[3] }]; + +#set_property -dict { PACKAGE_PIN "C8" IOSTANDARD LVCMOS33} [get_ports { zclk }]; +#set_property -dict { PACKAGE_PIN "B11" IOSTANDARD LVCMOS33} [get_ports { zioreq }]; +#set_property -dict { PACKAGE_PIN "B10" IOSTANDARD LVCMOS33} [get_ports { zwr }]; +##set_property -dict { PACKAGE_PIN "" IOSTANDARD LVCMOS33} [get_ports { zrd }]; +#set_property -dict { PACKAGE_PIN "C9" IOSTANDARD LVCMOS33} [get_ports { zm1 }]; + + +set_property CFGBVS VCCO [current_design] +set_property CONFIG_VOLTAGE 3.3 [current_design] +# CLOCK 100MHz and Reset # +#################################################################################################################### +set_property -dict { PACKAGE_PIN "N11" IOSTANDARD LVCMOS33} [get_ports { clk }]; +set_property -dict { PACKAGE_PIN "N6" IOSTANDARD LVCMOS33} [get_ports { rst }]; +#################################################################################################################### +# LEDs # +#################################################################################################################### +set_property -dict { PACKAGE_PIN "K12" IOSTANDARD LVCMOS33 SLEW FAST} [get_ports { LED[0] }]; +set_property -dict { PACKAGE_PIN "K13" IOSTANDARD LVCMOS33 SLEW FAST} [get_ports { LED[1] }]; +set_property -dict { PACKAGE_PIN "R10" IOSTANDARD LVCMOS33 SLEW FAST} [get_ports { LED[2] }]; +set_property -dict { PACKAGE_PIN "R13" IOSTANDARD LVCMOS33 SLEW FAST} [get_ports { LED[3] }]; +set_property -dict { PACKAGE_PIN "T13" IOSTANDARD LVCMOS33 SLEW FAST} [get_ports { LED[4] }]; +set_property -dict { PACKAGE_PIN "R12" IOSTANDARD LVCMOS33 SLEW FAST} [get_ports { LED[5] }]; +set_property -dict { PACKAGE_PIN "T12" IOSTANDARD LVCMOS33 SLEW FAST} [get_ports { LED[6] }]; +set_property -dict { PACKAGE_PIN "R11" IOSTANDARD LVCMOS33 SLEW FAST} [get_ports { LED[7] }]; +#################################################################################################################### +# TDMS # +#################################################################################################################### +set_property -dict { PACKAGE_PIN "R2" IOSTANDARD TMDS_33} [get_ports { tmds[0] }]; # Blue +set_property -dict { PACKAGE_PIN "R1" IOSTANDARD TMDS_33} [get_ports { tmdsb[0] }]; +set_property -dict { PACKAGE_PIN "P3" IOSTANDARD TMDS_33} [get_ports { tmdsb[1] }]; # Green +set_property -dict { PACKAGE_PIN "P4" IOSTANDARD TMDS_33} [get_ports { tmds[1] }]; +set_property -dict { PACKAGE_PIN "T4" IOSTANDARD TMDS_33} [get_ports { tmds[2] }]; # Red +set_property -dict { PACKAGE_PIN "T3" IOSTANDARD TMDS_33} [get_ports { tmdsb[2] }]; +set_property -dict { PACKAGE_PIN "M1" IOSTANDARD TMDS_33} [get_ports { tmdsb[3] }]; # Clock +set_property -dict { PACKAGE_PIN "M2" IOSTANDARD TMDS_33} [get_ports { tmds[3] }]; +#################################################################################################################### +# Z80 # +#################################################################################################################### +set_property -dict { PACKAGE_PIN "R3" IOSTANDARD LVCMOS33} [get_ports { zdata[0] }]; +set_property -dict { PACKAGE_PIN "T2" IOSTANDARD LVCMOS33} [get_ports { zdata[1] }]; +set_property -dict { PACKAGE_PIN "M5" IOSTANDARD LVCMOS33} [get_ports { zdata[2] }]; +set_property -dict { PACKAGE_PIN "N4" IOSTANDARD LVCMOS33} [get_ports { zdata[3] }]; +set_property -dict { PACKAGE_PIN "H11" IOSTANDARD LVCMOS33} [get_ports { zdata[4] }]; +set_property -dict { PACKAGE_PIN "G12" IOSTANDARD LVCMOS33} [get_ports { zdata[5] }]; +set_property -dict { PACKAGE_PIN "D9" IOSTANDARD LVCMOS33} [get_ports { zdata[6] }]; +set_property -dict { PACKAGE_PIN "D8" IOSTANDARD LVCMOS33} [get_ports { zdata[7] }]; + +set_property -dict { PACKAGE_PIN "A8" IOSTANDARD LVCMOS33} [get_ports { zaddr[0] }]; +set_property -dict { PACKAGE_PIN "A10" IOSTANDARD LVCMOS33} [get_ports { zaddr[1] }]; +set_property -dict { PACKAGE_PIN "B9" IOSTANDARD LVCMOS33} [get_ports { zaddr[2] }]; +set_property -dict { PACKAGE_PIN "A12" IOSTANDARD LVCMOS33} [get_ports { zaddr[3] }]; +set_property -dict { PACKAGE_PIN "B12" IOSTANDARD LVCMOS33} [get_ports { zaddr[4] }]; +set_property -dict { PACKAGE_PIN "N2" IOSTANDARD LVCMOS33} [get_ports { zaddr[5] }]; +set_property -dict { PACKAGE_PIN "N3" IOSTANDARD LVCMOS33} [get_ports { zaddr[6] }]; +set_property -dict { PACKAGE_PIN "L4" IOSTANDARD LVCMOS33} [get_ports { zaddr[7] }]; + +set_property -dict { PACKAGE_PIN "A9" IOSTANDARD LVCMOS33} [get_ports { zclk }]; +set_property -dict { PACKAGE_PIN "H13" IOSTANDARD LVCMOS33} [get_ports { zioreq }]; +set_property -dict { PACKAGE_PIN "H12" IOSTANDARD LVCMOS33} [get_ports { zwr }]; +set_property -dict { PACKAGE_PIN "A15" IOSTANDARD LVCMOS33} [get_ports { zrd }]; +set_property -dict { PACKAGE_PIN "L5" IOSTANDARD LVCMOS33} [get_ports { zm1 }]; +#set_property -dict { PACKAGE_PIN "P5" IOSTANDARD LVCMOS33} [get_ports { zrst }]; \ No newline at end of file diff --git a/src/simple_dual_ram.v b/src/simple_dual_ram.v new file mode 100644 index 0000000..58f35cb --- /dev/null +++ b/src/simple_dual_ram.v @@ -0,0 +1,78 @@ +`timescale 1ns / 1ps +/****************************************************************************** + + The MIT License (MIT) + + Copyright (c) 2019 Alchitry + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to deal + in the Software without restriction, including without limitation the rights + to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + THE SOFTWARE. + + ***************************************************************************** + + This module is a simple dual port RAM. This RAM is implemented in such a + way that Xilinx's tools will recognize it as a RAM and implement large + instances in block RAM instead of flip-flops. + + The parameter SIZE is used to specify the word size. That is the size of + each entry in the RAM. + + The parameter DEPTH is used to specify how many entries are in the RAM. + + read_data outputs the value of the entry pointed to by raddr in the previous + clock cycle. That means to read address 10, you would set address to be 10 + and wait one cycle for its value to show up. The RAM is always reading whatever + address is. If you don't need to read, just ignore this value. + + To write, set write_en to 1, write_data to the value to write, and waddr to + the address you want to write. + + You should avoid reading and writing to the same address simultaneously. The + value read in this case is undefined. +*/ + +module simple_dual_ram #( + parameter SIZE = 8, // size of each entry + parameter DEPTH = 8 // number of entries + )( + // write interface + input wclk, // write clock + input [$clog2(DEPTH)-1:0] waddr, // write address + input [SIZE-1:0] write_data, // write data + input write_en, // write enable (1 = write) + + // read interface + input rclk, // read clock + input [$clog2(DEPTH)-1:0] raddr, // read address + output reg [SIZE-1:0] read_data // read data + ); + + reg [SIZE-1:0] mem [DEPTH-1:0]; // memory array + + // write clock domain + always @(posedge wclk) begin + if (write_en) // if write enable + mem[waddr] <= write_data; // write memory + end + + // read clock domain + always @(posedge rclk) begin + read_data <= mem[raddr]; // read memory + end + +endmodule \ No newline at end of file diff --git a/write.tcl b/write.tcl new file mode 100644 index 0000000..c3a22b4 --- /dev/null +++ b/write.tcl @@ -0,0 +1,10 @@ +set out_dir ./.build + +open_checkpoint .build/5_route.dcp + +add_files -norecurse ./controller.elf +set_property used_in_simulation 0 [get_files ./controller.elf] +set_property SCOPED_TO_REF microblaze_mcs_0 [get_files -all -of_objects [get_fileset sources_1] {./controller.elf}] +set_property SCOPED_TO_CELLS { inst/microblaze_I } [get_files -all -of_objects [get_fileset sources_1] {./controller.elf}] + +write_bitstream -force $out_dir/impl.bit -bin_file