#
# Numato Mimas A7 Mini - Artix 7 FPGA Board
#
# https://numato.com/product/mimas-a7-mini-fpga-development-board
#

interface ftdi
ftdi_device_desc "Mimas A7 Mini FPGA Module"
ftdi_vid_pid 0x2a19 0x100e

# channel 0 is for custom purpose by users (like uart, fifo etc)
# channel 1 is reserved for JTAG (by-default) or SPI (possible via changing solder jumpers)
ftdi_channel 1
ftdi_tdo_sample_edge falling


# FTDI Pin Layout
#
# +--------+-------+-------+-------+-------+-------+-------+-------+
# | DBUS7  | DBUS6 | DBUS5 | DBUS4 | DBUS3 | DBUS2 | DBUS1 | DBUS0 |
# +--------+-------+-------+-------+-------+-------+-------+-------+
# | PROG_B | OE_N  |  NC   |  NC   |  TMS  |  TDO  |  TDI  |  TCK  |
# +--------+-------+-------+-------+-------+-------+-------+-------+
#
# OE_N is JTAG buffer output enable signal (active-low)
# PROG_B is not used, so left as input to FTDI.
#
ftdi_layout_init 0x0008 0x004b
reset_config none
adapter_khz 30000

source [find cpld/xilinx-xc7.cfg]
source [find cpld/jtagspi.cfg]

proc fpga_program {} {
    global _CHIPNAME
    xc7_program $_CHIPNAME.tap
}