Worked on schematics and added some parts

This commit is contained in:
Dreaded_X 2022-05-22 21:00:50 +02:00
parent ecae5f4718
commit 7c66935cb9
14 changed files with 77289 additions and 242 deletions

4
hardware/fp-lib-table Normal file
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(fp_lib_table
(lib (name "RCJ-013")(type "KiCad")(uri "${KIPRJMOD}/library/RCJ-013")(options "")(descr ""))
(lib (name "31-M-12")(type "KiCad")(uri "${KIPRJMOD}/library/31-M-12")(options "")(descr ""))
)

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(module HRO_TYPE-C-31-M-12 (layer F.Cu) (tedit 628A6491)
(descr "")
(fp_text reference REF** (at -1.825 -7.435 0) (layer F.SilkS)
(effects (font (size 1.0 1.0) (thickness 0.15)))
)
(fp_text value HRO_TYPE-C-31-M-12 (at 6.43 4.135 0) (layer F.Fab)
(effects (font (size 1.0 1.0) (thickness 0.15)))
)
(pad A1B12 smd rect (at -3.25 -5.095) (size 0.6 1.45) (layers F.Cu F.Mask F.Paste))
(pad A4B9 smd rect (at -2.45 -5.095) (size 0.6 1.45) (layers F.Cu F.Mask F.Paste))
(pad A6 smd rect (at -0.25 -5.095) (size 0.3 1.45) (layers F.Cu F.Mask F.Paste))
(pad B7 smd rect (at -0.75 -5.095) (size 0.3 1.45) (layers F.Cu F.Mask F.Paste))
(pad A5 smd rect (at -1.25 -5.095) (size 0.3 1.45) (layers F.Cu F.Mask F.Paste))
(pad B8 smd rect (at -1.75 -5.095) (size 0.3 1.45) (layers F.Cu F.Mask F.Paste))
(pad A7 smd rect (at 0.25 -5.095) (size 0.3 1.45) (layers F.Cu F.Mask F.Paste))
(pad B6 smd rect (at 0.75 -5.095) (size 0.3 1.45) (layers F.Cu F.Mask F.Paste))
(pad A8 smd rect (at 1.25 -5.095) (size 0.3 1.45) (layers F.Cu F.Mask F.Paste))
(pad B5 smd rect (at 1.75 -5.095) (size 0.3 1.45) (layers F.Cu F.Mask F.Paste))
(pad B4A9 smd rect (at 2.45 -5.095) (size 0.6 1.45) (layers F.Cu F.Mask F.Paste))
(pad B1A12 smd rect (at 3.25 -5.095) (size 0.6 1.45) (layers F.Cu F.Mask F.Paste))
(pad S1 thru_hole oval (at -4.32 -4.18) (size 1.05 2.1) (drill oval 0.65 1.75) (layers *.Cu *.Mask))
(pad S2 thru_hole oval (at 4.32 -4.18) (size 1.05 2.1) (drill oval 0.65 1.75) (layers *.Cu *.Mask))
(pad S3 thru_hole oval (at -4.32 0.0) (size 1.05 2.1) (drill oval 0.65 1.25) (layers *.Cu *.Mask))
(pad S4 thru_hole oval (at 4.32 0.0) (size 1.05 2.1) (drill oval 0.65 1.25) (layers *.Cu *.Mask))
(pad None np_thru_hole circle (at -2.89 -3.65) (size 0.7 0.7) (drill 0.7) (layers *.Cu *.Mask))
(pad None np_thru_hole circle (at 2.89 -3.65) (size 0.7 0.7) (drill 0.7) (layers *.Cu *.Mask))
(fp_line (start -4.47 2.6) (end 4.47 2.6) (layer F.Fab) (width 0.127))
(fp_line (start 4.47 2.6) (end 4.47 -4.7) (layer F.Fab) (width 0.127))
(fp_line (start 4.47 -4.7) (end -4.47 -4.7) (layer F.Fab) (width 0.127))
(fp_line (start -4.47 -4.7) (end -4.47 2.6) (layer F.Fab) (width 0.127))
(fp_line (start -4.47 -2.81) (end -4.47 -1.37) (layer F.SilkS) (width 0.127))
(fp_line (start 4.47 -2.81) (end 4.47 -1.37) (layer F.SilkS) (width 0.127))
(fp_line (start 4.47 1.37) (end 4.47 2.6) (layer F.SilkS) (width 0.127))
(fp_line (start 4.47 2.6) (end -4.47 2.6) (layer F.SilkS) (width 0.127))
(fp_line (start -4.47 2.6) (end -4.47 1.37) (layer F.SilkS) (width 0.127))
(fp_line (start -5.095 2.85) (end 5.095 2.85) (layer F.CrtYd) (width 0.05))
(fp_line (start 5.095 2.85) (end 5.095 -6.07) (layer F.CrtYd) (width 0.05))
(fp_line (start 5.095 -6.07) (end -5.095 -6.07) (layer F.CrtYd) (width 0.05))
(fp_line (start -5.095 -6.07) (end -5.095 2.85) (layer F.CrtYd) (width 0.05))
(fp_circle (center -3.4 -6.4) (end -3.3 -6.4) (layer F.Fab) (width 0.2))
(fp_circle (center -3.4 -6.4) (end -3.3 -6.4) (layer F.SilkS) (width 0.2))
)

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BY ACCESSING OR USING THESE SYMBOLS & FOOTPRINTS ("MODELS"), YOU ARE ACKNOWLEDGING THAT YOU HAVE READ, FULLY UNDERSTAND AND AGREE TO THESE TERMS AND CONDITIONS (the "Agreement"), WHICH CONSTITUTE A BINDING AGREEMENT BETWEEN YOU AND SNAPEDA, INC., ENTERED INTO ON THE DATE OF SUCH OCCURRENCE (the "Effective Date"). IF YOU ARE ACCESSING OR USING THESE FILES ON BEHALF OF AN ENTITY, YOU REPRESENT THAT YOU HAVE THE RIGHT, AUTHORITY, AND CAPACITY TO BIND SUCH ENTITY TO THIS AGREEMENT AND HEREBY DO SO. IF YOU DO NOT AGREE WITH ANY OF THE TERMS OR CONDITIONS OF THIS AGREEMENT, YOU MUST NOT USE ANY PART OF THESE MODELS.
1. Design License
You and your sub-licensees are hereby licensed to design, manufacture, use and distribute, circuit board designs and circuit boards formed by combining Models provided by SnapEDA with other circuit elements of your choosing. You may then convey such combinations under licensing terms of your choice. 
Individual Models remain the intellectual property of SnapEDA, Inc. You shall not (and shall not permit or encourage any third party to) to do any of the following :
(a) sell, assign, lease, lend, rent, issue, sublicense, make available, or otherwise distribute to any third party, or publicly perform, display or communicate, the Models (for example, by uploading Models to another website or software application);
(b) remove, alter, or conceal, any copyright, trademark, or other proprietary rights notice or legend displayed or contained in the individual Models.
For further clarity, once integrated into a schematic design or PCB layout, Models may be modified freely for the purpose of designing a circuit board. 
2. Limitation of Liability
IN NO EVENT WILL SNAPEDA OR OUR SUBSIDIARIES, AGENTS, SUCCESSORS, THIRD PARTY PROVIDERS, AND/OR ANY OF THE FOREGOING ENTITIES' RESPECTIVE DIRECTORS, OFFICERS, EMPLOYEES, AGENTS, REPRESENTATIVES, CUSTOMERS, SUPPLIERS, OR LICENSORS BE RESPONSIBLE OR LIABLE UNDER, OR OTHERWISE IN CONNECTION WITH THIS AGREEMENT, FOR:
(a) ANY CONSEQUENTIAL, INDIRECT, SPECIAL, INCIDENTAL, OR PUNITIVE DAMAGES;
(b) ANY LOSS OF PROFITS, LOSS OF BUSINESS, LOSS OF REVENUE, OR LOSS OF ANTICIPATED SAVINGS;
(c) ANY LOSS OF, OR DAMAGE TO, DATA, REPUTATION, OR GOODWILL; AND/OR
(d) THE COST OF PROCURING ANY SUBSTITUTE GOODS OR SERVICES.
THE COMBINED AGGREGATE LIABILITY OF SNAPEDA AND ALL SNAPEDA CONTENT AFFILIATES UNDER, OR OTHERWISE IN CONNECTION WITH, THIS AGREEMENT SHALL NOT EXCEED THE TOTAL AMOUNT OF FEES RECEIVED BY SNAPEDA FROM YOU IN THE PREVIOUS TWELVE (12) MONTHS. THE FOREGOING EXCLUSIONS AND LIMITATIONS SHALL APPLY: (a) EVEN IF SNAPEDA OR ANY SNAPEDA CONTENT AFFILIATE HAS BEEN ADVISED, OR SHOULD HAVE BEEN AWARE, OF THE POSSIBILITY OF LOSSES, DAMAGES, OR COSTS; (b) EVEN IF ANY REMEDY IN THIS AGREEMENT FAILS OF ITS ESSENTIAL PURPOSE; AND (c) REGARDLESS OF THE THEORY OR BASIS OF LIABILITY (INCLUDING WITHOUT LIMITATION BREACH OF CONTRACT, TORT, NEGLIGENCE, AND STRICT LIABILITY).

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EESchema-LIBRARY Version 2.3
#encoding utf-8
#(c) SnapEDA 2016 (snapeda.com)
#This work is licensed under a Creative Commons Attribution-ShareAlike 4.0 International License (CC BY-SA) with Design Exception 1.0
#
# TYPE-C-31-M-12
#
DEF TYPE-C-31-M-12 J 0 40 Y Y 1 L N
F0 "J" -500 530 50 H V L BNN
F1 "TYPE-C-31-M-12" -500 -530 50 H V L BNN
F2 "HRO_TYPE-C-31-M-12" 0 0 50 H I L BNN
F3 "" 0 0 50 H I L BNN
F4 "Manufacturer Recommendations" 0 0 50 H I L BNN "STANDARD"
F5 "A" 0 0 50 H I L BNN "PARTREV"
F6 "HRO Electronics" 0 0 50 H I L BNN "MANUFACTURER"
F7 "3.31mm" 0 0 50 H I L BNN "MAXIMUM_PACKAGE_HEIGHT"
DRAW
S -500 -500 500 500 0 0 10 f
X DP1 A6 -700 100 200 R 40 40 0 0 B
X CC1 A5 -700 200 200 R 40 40 0 0 B
X SBU1 A8 -700 -100 200 R 40 40 0 0 B
X DN1 A7 -700 0 200 R 40 40 0 0 B
X SHIELD S1 700 -300 200 L 40 40 0 0 P
X SHIELD S2 700 -300 200 L 40 40 0 0 P
X SHIELD S3 700 -300 200 L 40 40 0 0 P
X SHIELD S4 700 -300 200 L 40 40 0 0 P
X GND A1B12 700 -400 200 L 40 40 0 0 W
X GND B1A12 700 -400 200 L 40 40 0 0 W
X VBUS A4B9 700 400 200 L 40 40 0 0 W
X VBUS B4A9 700 400 200 L 40 40 0 0 W
X DP2 B6 700 0 200 L 40 40 0 0 B
X CC2 B5 700 -100 200 L 40 40 0 0 B
X SBU2 B8 700 200 200 L 40 40 0 0 B
X DN2 B7 700 100 200 L 40 40 0 0 B
ENDDRAW
ENDDEF
#
# End Library

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(module CUI_RCJ-013 (layer F.Cu) (tedit 628A527C)
(descr "<b>DC POWER JACK</b><p>Source: DCJ0202.pdf")
(fp_text reference REF** (at -4.03065 -5.76308 0) (layer F.SilkS)
(effects (font (size 1.0014015748 1.0014015748) (thickness 0.15)))
)
(fp_text value CUI_RCJ-013 (at 0.065075 5.499085 0) (layer F.Fab)
(effects (font (size 1.0007480315 1.0007480315) (thickness 0.15)))
)
(pad 2 thru_hole circle (at 5.95 0.0) (size 2.55 2.55) (drill 1.7) (layers *.Cu *.Mask))
(pad 1A thru_hole circle (at 5.95 -5.0) (size 3.616 3.616) (drill 2.6) (layers *.Cu *.Mask))
(pad 1B thru_hole circle (at 5.95 5.0) (size 3.616 3.616) (drill 2.6) (layers *.Cu *.Mask))
(pad 1C thru_hole circle (at 1.45 0.0) (size 3.616 3.616) (drill 2.6) (layers *.Cu *.Mask))
(fp_line (start 0.75 -4.15) (end -7.25 -4.15) (layer F.Fab) (width 0.127))
(fp_line (start -7.25 -4.15) (end -7.25 4.15) (layer F.Fab) (width 0.127))
(fp_line (start -7.25 4.15) (end 0.75 4.15) (layer F.Fab) (width 0.127))
(fp_line (start 0.75 4.15) (end 0.75 5.3) (layer F.Fab) (width 0.127))
(fp_line (start 0.75 5.3) (end 7.25 5.3) (layer F.Fab) (width 0.127))
(fp_line (start 7.25 5.3) (end 7.25 -5.3) (layer F.Fab) (width 0.127))
(fp_line (start 7.25 -5.3) (end 0.75 -5.3) (layer F.Fab) (width 0.127))
(fp_line (start 0.75 -5.3) (end 0.75 -4.15) (layer F.Fab) (width 0.127))
(fp_line (start 0.75 -4.15) (end -7.25 -4.15) (layer F.SilkS) (width 0.127))
(fp_line (start -7.25 -4.15) (end -7.25 4.15) (layer F.SilkS) (width 0.127))
(fp_line (start -7.25 4.15) (end 0.75 4.15) (layer F.SilkS) (width 0.127))
(fp_line (start 0.75 4.15) (end 0.75 5.3) (layer F.SilkS) (width 0.127))
(fp_line (start 0.75 5.3) (end 3.85 5.3) (layer F.SilkS) (width 0.127))
(fp_line (start 0.75 -5.3) (end 0.75 -4.15) (layer F.SilkS) (width 0.127))
(fp_line (start 0.5 -4.4) (end -7.5 -4.4) (layer F.CrtYd) (width 0.05))
(fp_line (start -7.5 -4.4) (end -7.5 4.4) (layer F.CrtYd) (width 0.05))
(fp_line (start -7.5 4.4) (end 0.5 4.4) (layer F.CrtYd) (width 0.05))
(fp_line (start 0.5 4.4) (end 0.5 5.55) (layer F.CrtYd) (width 0.05))
(fp_line (start 0.5 5.55) (end 3.9 5.55) (layer F.CrtYd) (width 0.05))
(fp_line (start 8.1 7.15) (end 8.1 3.55) (layer F.CrtYd) (width 0.05))
(fp_line (start 3.9 -5.75) (end 0.5 -5.75) (layer F.CrtYd) (width 0.05))
(fp_line (start 0.5 -5.75) (end 0.5 -4.4) (layer F.CrtYd) (width 0.05))
(fp_line (start 3.9 -5.75) (end 3.9 -7.05) (layer F.CrtYd) (width 0.05))
(fp_line (start 3.9 -7.05) (end 8.1 -7.05) (layer F.CrtYd) (width 0.05))
(fp_line (start 8.1 -7.05) (end 8.1 -3.65) (layer F.CrtYd) (width 0.05))
(fp_line (start 8.1 -3.65) (end 7.6 -3.65) (layer F.CrtYd) (width 0.05))
(fp_line (start 7.6 -3.65) (end 7.6 3.55) (layer F.CrtYd) (width 0.05))
(fp_line (start 7.6 3.55) (end 8.1 3.55) (layer F.CrtYd) (width 0.05))
(fp_line (start 8.1 7.15) (end 3.9 7.15) (layer F.CrtYd) (width 0.05))
(fp_line (start 3.9 7.15) (end 3.9 5.55) (layer F.CrtYd) (width 0.05))
(fp_line (start 3.95 -5.3) (end 0.75 -5.3) (layer F.SilkS) (width 0.127))
(fp_line (start 7.25 3.35) (end 7.25 0.8) (layer F.SilkS) (width 0.127))
(fp_line (start 7.25 -0.9) (end 7.25 -3.4) (layer F.SilkS) (width 0.127))
(fp_circle (center 8.8 -5.2) (end 9.0 -5.2) (layer F.SilkS) (width 0.4))
)

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BY ACCESSING OR USING THESE SYMBOLS & FOOTPRINTS ("MODELS"), YOU ARE ACKNOWLEDGING THAT YOU HAVE READ, FULLY UNDERSTAND AND AGREE TO THESE TERMS AND CONDITIONS (the "Agreement"), WHICH CONSTITUTE A BINDING AGREEMENT BETWEEN YOU AND SNAPEDA, INC., ENTERED INTO ON THE DATE OF SUCH OCCURRENCE (the "Effective Date"). IF YOU ARE ACCESSING OR USING THESE FILES ON BEHALF OF AN ENTITY, YOU REPRESENT THAT YOU HAVE THE RIGHT, AUTHORITY, AND CAPACITY TO BIND SUCH ENTITY TO THIS AGREEMENT AND HEREBY DO SO. IF YOU DO NOT AGREE WITH ANY OF THE TERMS OR CONDITIONS OF THIS AGREEMENT, YOU MUST NOT USE ANY PART OF THESE MODELS.
1. Design License
You and your sub-licensees are hereby licensed to design, manufacture, use and distribute, circuit board designs and circuit boards formed by combining Models provided by SnapEDA with other circuit elements of your choosing. You may then convey such combinations under licensing terms of your choice. 
Individual Models remain the intellectual property of SnapEDA, Inc. You shall not (and shall not permit or encourage any third party to) to do any of the following :
(a) sell, assign, lease, lend, rent, issue, sublicense, make available, or otherwise distribute to any third party, or publicly perform, display or communicate, the Models (for example, by uploading Models to another website or software application);
(b) remove, alter, or conceal, any copyright, trademark, or other proprietary rights notice or legend displayed or contained in the individual Models.
For further clarity, once integrated into a schematic design or PCB layout, Models may be modified freely for the purpose of designing a circuit board. 
2. Limitation of Liability
IN NO EVENT WILL SNAPEDA, CUI, OR OUR SUBSIDIARIES, AGENTS, SUCCESSORS, THIRD PARTY PROVIDERS, AND/OR ANY OF THE FOREGOING ENTITIES' RESPECTIVE DIRECTORS, OFFICERS, EMPLOYEES, AGENTS, REPRESENTATIVES, CUSTOMERS, SUPPLIERS, OR LICENSORS BE RESPONSIBLE OR LIABLE UNDER, OR OTHERWISE IN CONNECTION WITH THIS AGREEMENT, FOR:
(a) ANY CONSEQUENTIAL, INDIRECT, SPECIAL, INCIDENTAL, OR PUNITIVE DAMAGES;
(b) ANY LOSS OF PROFITS, LOSS OF BUSINESS, LOSS OF REVENUE, OR LOSS OF ANTICIPATED SAVINGS;
(c) ANY LOSS OF, OR DAMAGE TO, DATA, REPUTATION, OR GOODWILL; AND/OR
(d) THE COST OF PROCURING ANY SUBSTITUTE GOODS OR SERVICES.
THE COMBINED AGGREGATE LIABILITY OF SNAPEDA AND ALL SNAPEDA CONTENT AFFILIATES UNDER, OR OTHERWISE IN CONNECTION WITH, THIS AGREEMENT SHALL NOT EXCEED THE TOTAL AMOUNT OF FEES RECEIVED BY SNAPEDA FROM YOU IN THE PREVIOUS TWELVE (12) MONTHS. THE FOREGOING EXCLUSIONS AND LIMITATIONS SHALL APPLY: (a) EVEN IF SNAPEDA OR ANY SNAPEDA CONTENT AFFILIATE HAS BEEN ADVISED, OR SHOULD HAVE BEEN AWARE, OF THE POSSIBILITY OF LOSSES, DAMAGES, OR COSTS; (b) EVEN IF ANY REMEDY IN THIS AGREEMENT FAILS OF ITS ESSENTIAL PURPOSE; AND (c) REGARDLESS OF THE THEORY OR BASIS OF LIABILITY (INCLUDING WITHOUT LIMITATION BREACH OF CONTRACT, TORT, NEGLIGENCE, AND STRICT LIABILITY).

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EESchema-LIBRARY Version 2.3
#encoding utf-8
#(c) SnapEDA 2016 (snapeda.com)
#This work is licensed under a Creative Commons Attribution-ShareAlike 4.0 International License (CC BY-SA) with Design Exception 1.0
#
# RCJ-013
#
DEF RCJ-013 J 0 40 Y Y 1 L N
F0 "J" -100 150 50 H V L BNN
F1 "RCJ-013" -100 -250 50 H V L BNN
F2 "CUI_RCJ-013" 0 0 50 H I L BNN
F3 "" 0 0 50 H I L BNN
F4 "B" 0 0 50 H I L BNN "PART_REV"
F5 "Manufacturer recommendations" 0 0 50 H I L BNN "STANDARD"
F6 "CUI Inc" 0 0 50 H I L BNN "MANUFACTURER"
DRAW
P 2 0 0 6 200 100 -100 100 N
P 2 0 0 6 -100 100 -100 50 N
P 2 0 0 6 200 -100 100 -100 N
P 2 0 0 6 100 -100 30 -100 N
P 2 0 0 6 30 -100 0 -40 N
P 2 0 0 6 0 -40 -30 -100 N
S -130 -100 -70 50 0 0 0 F
X 1 1A 300 100 100 L 40 40 0 0 P
X 1 1B 300 100 100 L 40 40 0 0 P
X 1 1C 300 100 100 L 40 40 0 0 P
X 2 2 300 -100 100 L 40 40 0 0 P
ENDDRAW
ENDDEF
#
# End Library

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hardware/sym-lib-table Normal file
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(sym_lib_table
(lib (name "RCJ-013")(type "Legacy")(uri "${KIPRJMOD}/library/RCJ-013/RCJ-013.lib")(options "")(descr ""))
(lib (name "TYPE-C-31-M-12")(type "Legacy")(uri "${KIPRJMOD}/library/31-M-12/TYPE-C-31-M-12.lib")(options "")(descr ""))
)