Removed unnecessary files
This commit is contained in:
parent
0f312b8085
commit
58dd1a72a5
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@ -1,78 +0,0 @@
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<?xml version="1.0" encoding="UTF-8"?>
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||||
<!-- IMPORTANT: This is an internal file that has been generated
|
||||
by the Xilinx ISE software. Any direct editing or
|
||||
changes made to this file may result in unpredictable
|
||||
behavior or data corruption. It is strongly advised that
|
||||
users do not edit the contents of this file. -->
|
||||
<messages>
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||||
<msg type="info" file="sim" num="172" delta="old" >Generating IP...
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</msg>
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<msg type="warning" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">Verilog simulation file type 'Behavioral' is not valid for this core. Overriding with simulation file type 'Structural'.</arg>
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</msg>
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<msg type="warning" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">A core named 'microblaze_mcs' already exists in the project. Output products for this core may be overwritten.</arg>
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</msg>
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<msg type="warning" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">Verilog simulation file type 'Behavioral' is not valid for this core. Overriding with simulation file type 'Structural'.</arg>
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</msg>
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<msg type="warning" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">A core named 'microblaze_mcs' already exists in the project. Output products for this core may be overwritten.</arg>
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</msg>
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<msg type="info" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">Pre-processing HDL files for 'microblaze_mcs'...</arg>
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</msg>
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<msg type="info" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">Running microblaze_mcs_gen_script.tcl</arg>
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</msg>
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<msg type="info" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">Please source the "microblaze_mcs_setup.tcl" script in the Tcl Console to complete MicroBlaze MCS core generation</arg>
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</msg>
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<msg type="warning" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">Verilog simulation file type 'Behavioral' is not valid for this core. Overriding with simulation file type 'Structural'.</arg>
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</msg>
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<msg type="warning" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">Verilog simulation file type 'Behavioral' is not valid for this core. Overriding with simulation file type 'Structural'.</arg>
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</msg>
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<msg type="info" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">Running microblaze_mcs_sim_script.tcl</arg>
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</msg>
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<msg type="info" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">C_MICROBLAZE_INSTANCE = microblaze_mcs</arg>
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</msg>
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<msg type="info" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">Netlist filename = ./_cg/microblaze_mcs.v</arg>
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</msg>
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<msg type="info" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">Setting INIT_FILE = "microblaze_mcs.lmb_bram_7.mem" for BRAM 7</arg>
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</msg>
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<msg type="info" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">Setting INIT_FILE = "microblaze_mcs.lmb_bram_6.mem" for BRAM 6</arg>
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</msg>
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<msg type="info" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">Setting INIT_FILE = "microblaze_mcs.lmb_bram_5.mem" for BRAM 5</arg>
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</msg>
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<msg type="info" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">Setting INIT_FILE = "microblaze_mcs.lmb_bram_4.mem" for BRAM 4</arg>
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</msg>
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<msg type="info" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">Setting INIT_FILE = "microblaze_mcs.lmb_bram_3.mem" for BRAM 3</arg>
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</msg>
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<msg type="info" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">Setting INIT_FILE = "microblaze_mcs.lmb_bram_2.mem" for BRAM 2</arg>
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</msg>
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<msg type="info" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">Setting INIT_FILE = "microblaze_mcs.lmb_bram_1.mem" for BRAM 1</arg>
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</msg>
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<msg type="info" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">Setting INIT_FILE = "microblaze_mcs.lmb_bram_0.mem" for BRAM 0</arg>
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</msg>
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<msg type="info" file="sim" num="949" delta="old" >Finished generation of ASY schematic symbol.
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</msg>
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<msg type="info" file="sim" num="948" delta="old" >Finished FLIST file generation.
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</msg>
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</messages>
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@ -1,15 +0,0 @@
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<?xml version="1.0" encoding="UTF-8"?>
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<!-- IMPORTANT: This is an internal file that has been generated -->
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<!-- by the Xilinx ISE software. Any direct editing or -->
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||||
<!-- changes made to this file may result in unpredictable -->
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||||
<!-- behavior or data corruption. It is strongly advised that -->
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||||
<!-- users do not edit the contents of this file. -->
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<!-- -->
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<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
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<messages>
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<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file "/home/tim/Projects/z80/hdmi/ipcore_dir/hdmi_clk.v" into library work</arg>
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</msg>
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</messages>
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@ -1,52 +0,0 @@
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
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<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
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<!-- -->
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<!-- For tool use only. Do not edit. -->
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<!-- -->
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<!-- ProjectNavigator created generated project file. -->
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<!-- For use in tracking generated file and other information -->
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<!-- allowing preservation of process status. -->
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<!-- -->
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<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
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<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
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<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="hdmi_clk.xise"/>
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<files xmlns="http://www.xilinx.com/XMLSchema">
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<file xil_pn:fileType="FILE_ASY" xil_pn:name="hdmi_clk.asy" xil_pn:origination="imported"/>
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<file xil_pn:fileType="FILE_VEO" xil_pn:name="hdmi_clk.veo" xil_pn:origination="imported"/>
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</files>
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<transforms xmlns="http://www.xilinx.com/XMLSchema">
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<transform xil_pn:end_ts="1600022764" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1600022764">
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="ReadyToRun"/>
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</transform>
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<transform xil_pn:end_ts="1600550220" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-8597742380004556400" xil_pn:start_ts="1600550220">
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="ReadyToRun"/>
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</transform>
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<transform xil_pn:end_ts="1600550220" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-1825882304215661665" xil_pn:start_ts="1600550220">
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="ReadyToRun"/>
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</transform>
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<transform xil_pn:end_ts="1600550220" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1600550220">
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="ReadyToRun"/>
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</transform>
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<transform xil_pn:end_ts="1600550220" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="1294299709957645202" xil_pn:start_ts="1600550220">
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="ReadyToRun"/>
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</transform>
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</transforms>
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</generated_project>
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@ -1,2 +0,0 @@
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verilog work ../../hdmi_clk.v
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verilog work ../example_design/hdmi_clk_exdes.v
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@ -1,49 +0,0 @@
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
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<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
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<!-- -->
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||||
|
||||
<!-- For tool use only. Do not edit. -->
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<!-- -->
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||||
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<!-- ProjectNavigator created generated project file. -->
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<!-- For use in tracking generated file and other information -->
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<!-- allowing preservation of process status. -->
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<!-- -->
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<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
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<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
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<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="microblaze_mcs.xise"/>
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<files xmlns="http://www.xilinx.com/XMLSchema"/>
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<transforms xmlns="http://www.xilinx.com/XMLSchema">
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<transform xil_pn:end_ts="1599953511" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1599953511">
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="ReadyToRun"/>
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</transform>
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<transform xil_pn:end_ts="1600550220" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="7354168592165971327" xil_pn:start_ts="1600550220">
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="ReadyToRun"/>
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</transform>
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<transform xil_pn:end_ts="1600550220" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-5659800160767749842" xil_pn:start_ts="1600550220">
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="ReadyToRun"/>
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</transform>
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<transform xil_pn:end_ts="1600550220" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1600550220">
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="ReadyToRun"/>
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</transform>
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<transform xil_pn:end_ts="1600550220" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="2694950640116957441" xil_pn:start_ts="1600550220">
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="ReadyToRun"/>
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</transform>
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</transforms>
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</generated_project>
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File diff suppressed because one or more lines are too long
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@ -1,12 +0,0 @@
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<?xml version="1.0" encoding="UTF-8"?>
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||||
<!-- IMPORTANT: This is an internal file that has been generated
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||||
by the Xilinx ISE software. Any direct editing or
|
||||
changes made to this file may result in unpredictable
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||||
behavior or data corruption. It is strongly advised that
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||||
users do not edit the contents of this file. -->
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<messages>
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<msg type="info" file="NetListWriters" num="633" delta="old" >The generated Verilog netlist contains Xilinx <arg fmt="%s" index="1">UNISIM</arg> simulation primitives and has to be used with <arg fmt="%s" index="2">UNISIM</arg> simulation library for correct compilation and simulation.
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</msg>
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</messages>
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|
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@ -1,12 +0,0 @@
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<?xml version="1.0" encoding="UTF-8"?>
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||||
<!-- IMPORTANT: This is an internal file that has been generated -->
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||||
<!-- by the Xilinx ISE software. Any direct editing or -->
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||||
<!-- changes made to this file may result in unpredictable -->
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||||
<!-- behavior or data corruption. It is strongly advised that -->
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<!-- users do not edit the contents of this file. -->
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||||
<!-- -->
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<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
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<messages>
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</messages>
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File diff suppressed because it is too large
Load Diff
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@ -1 +0,0 @@
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work
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@ -1,121 +0,0 @@
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<?xml version='1.0' encoding='utf-8'?>
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<!--This is an ISE project configuration file.-->
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<!--It holds project specific layout data for the projectmgr plugin.-->
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<!--Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.-->
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<Project version="2" owner="projectmgr" name="Mojo-Base" >
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<!--This is an ISE project configuration file.-->
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<ItemView engineview="SynthesisOnly" guiview="Source" compilemode="AutoCompile" >
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<ClosedNodes>
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<ClosedNodesVersion>2</ClosedNodesVersion>
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<ClosedNode>/avr_interface |home|justin|workspace|Mojo-Tutorials|Mojo-Base|src|avr_interface.v</ClosedNode>
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</ClosedNodes>
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<SelectedItems>
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<SelectedItem>mojo_top (/home/tim/Projects/z80/hdmi/src/mojo_top.v)</SelectedItem>
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</SelectedItems>
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<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
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<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
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||||
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000202000000010000000100000064000001c9000000020000000000000000000000000200000064ffffffff000000810000000300000002000001c90000000100000003000000000000000100000003</ViewHeaderState>
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<UserChangedColumnWidths orientation="horizontal" >true</UserChangedColumnWidths>
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<CurrentItem>mojo_top (/home/tim/Projects/z80/hdmi/src/mojo_top.v)</CurrentItem>
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</ItemView>
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<ItemView engineview="SynthesisOnly" sourcetype="DESUT_VERILOG" guiview="Process" >
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<ClosedNodes>
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<ClosedNodesVersion>1</ClosedNodesVersion>
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<ClosedNode>Configure Target Device</ClosedNode>
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<ClosedNode>Design Utilities/Compile HDL Simulation Libraries</ClosedNode>
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<ClosedNode>Implement Design/Map/Generate Post-Map Static Timing</ClosedNode>
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<ClosedNode>Implement Design/Place & Route/Back-annotate Pin Locations</ClosedNode>
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<ClosedNode>Implement Design/Place & Route/Generate IBIS Model</ClosedNode>
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<ClosedNode>Implement Design/Place & Route/Generate Post-Place & Route Static Timing</ClosedNode>
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<ClosedNode>Synthesize - XST</ClosedNode>
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<ClosedNode>User Constraints</ClosedNode>
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</ClosedNodes>
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<SelectedItems>
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<SelectedItem>Generate Programming File</SelectedItem>
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</SelectedItems>
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<ScrollbarPosition orientation="vertical" >5</ScrollbarPosition>
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<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
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||||
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000001cb000000010000000100000000000000000000000064ffffffff000000810000000000000001000001cb0000000100000000</ViewHeaderState>
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<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
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<CurrentItem>Generate Programming File</CurrentItem>
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</ItemView>
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<ItemView guiview="File" >
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<ClosedNodes>
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<ClosedNodesVersion>1</ClosedNodesVersion>
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</ClosedNodes>
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||||
<SelectedItems>
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||||
<SelectedItem>mojo_top.v</SelectedItem>
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||||
</SelectedItems>
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||||
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
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||||
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
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<ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000000000000010000000000000000000000000000000000000ab8000000040101000100000000000000000000000064ffffffff000000810000000000000004000000770000000100000000000000c50000000100000000000000790000000100000000000009030000000100000000</ViewHeaderState>
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||||
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
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||||
<CurrentItem>mojo_top.v</CurrentItem>
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||||
</ItemView>
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||||
<ItemView guiview="Library" >
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||||
<ClosedNodes>
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||||
<ClosedNodesVersion>1</ClosedNodesVersion>
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<ClosedNode>work</ClosedNode>
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</ClosedNodes>
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||||
<SelectedItems/>
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||||
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
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||||
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
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<ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000000000000010000000000000000000000000000000000000125000000010001000100000000000000000000000064ffffffff000000810000000000000001000001250000000100000000</ViewHeaderState>
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<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
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<CurrentItem>work</CurrentItem>
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</ItemView>
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<SourceProcessView>000000ff0000000000000002000001380000011b01000000040100000002</SourceProcessView>
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<CurrentView>Implementation</CurrentView>
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<ItemView engineview="SynthesisOnly" sourcetype="" guiview="Process" >
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<ClosedNodes>
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<ClosedNodesVersion>1</ClosedNodesVersion>
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||||
<ClosedNode>Design Utilities/Compile HDL Simulation Libraries</ClosedNode>
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||||
</ClosedNodes>
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<SelectedItems>
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||||
<SelectedItem/>
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||||
</SelectedItems>
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||||
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
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||||
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
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||||
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000001db000000010000000100000000000000000000000064ffffffff000000810000000000000001000001db0000000100000000</ViewHeaderState>
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||||
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
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||||
<CurrentItem/>
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||||
</ItemView>
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||||
<ItemView engineview="SynthesisOnly" sourcetype="DESUT_UCF" guiview="Process" >
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||||
<ClosedNodes>
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<ClosedNodesVersion>1</ClosedNodesVersion>
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||||
<ClosedNode>User Constraints</ClosedNode>
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</ClosedNodes>
|
||||
<SelectedItems>
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||||
<SelectedItem/>
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||||
</SelectedItems>
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||||
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
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||||
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
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||||
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000001db000000010000000100000000000000000000000064ffffffff000000810000000000000001000001db0000000100000000</ViewHeaderState>
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<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
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<CurrentItem/>
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||||
</ItemView>
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||||
<ItemView engineview="SynthesisOnly" sourcetype="DESUT_XCO" guiview="Process" >
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<ClosedNodes>
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<ClosedNodesVersion>1</ClosedNodesVersion>
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</ClosedNodes>
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||||
<SelectedItems>
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<SelectedItem></SelectedItem>
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</SelectedItems>
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||||
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
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||||
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
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||||
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000001db000000010000000100000000000000000000000064ffffffff000000810000000000000001000001db0000000100000000</ViewHeaderState>
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||||
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
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<CurrentItem></CurrentItem>
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||||
</ItemView>
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||||
<ItemView engineview="SynthesisOnly" sourcetype="DESUT_XPS" guiview="Process" >
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<ClosedNodes>
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<ClosedNodesVersion>1</ClosedNodesVersion>
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</ClosedNodes>
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<SelectedItems/>
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||||
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
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||||
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
|
||||
<ViewHeaderState orientation="horizontal" />
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||||
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
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<CurrentItem/>
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</ItemView>
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</Project>
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@ -1,215 +0,0 @@
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<?xml version='1.0' encoding='UTF-8'?>
|
||||
<report-views version="2.0" >
|
||||
<header>
|
||||
<DateModified>2020-09-20T21:06:16</DateModified>
|
||||
<ModuleName>mojo_top</ModuleName>
|
||||
<SummaryTimeStamp>2013-04-16T10:54:27</SummaryTimeStamp>
|
||||
<SavedFilePath>/home/tim/Projects/z80/hdmi/iseconfig/mojo_top.xreport</SavedFilePath>
|
||||
<ImplementationReportsDirectory>/home/tim/Projects/z80/hdmi/syn/</ImplementationReportsDirectory>
|
||||
<DateInitialized>2012-11-08T12:38:20</DateInitialized>
|
||||
<EnableMessageFiltering>false</EnableMessageFiltering>
|
||||
</header>
|
||||
<body>
|
||||
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|
||||
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|
||||
<toc-item title="Design Overview" target="Design Overview" />
|
||||
<toc-item title="Design Utilization Summary" target="Design Utilization Summary" />
|
||||
<toc-item title="Performance Summary" target="Performance Summary" />
|
||||
<toc-item title="Failing Constraints" target="Failing Constraints" />
|
||||
<toc-item title="Detailed Reports" target="Detailed Reports" />
|
||||
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|
||||
<view inputState="Unknown" program="implementation" contextTags="FPGA_ONLY" hidden="true" type="HTML" file="mojo_top_envsettings.html" label="System Settings" />
|
||||
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|
||||
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|
||||
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|
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|
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|
||||
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||||
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|
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|
||||
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|
||||
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|
||||
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||||
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|
||||
<view program="simgen" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/simgen.xmsgs" label="Simgen Messages" />
|
||||
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|
||||
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|
||||
<viewgroup label="XPS Reports" >
|
||||
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|
||||
<view inputState="PreSynthesized" program="simgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="simgen.log" label="Simgen Log File" />
|
||||
<view inputState="PreSynthesized" program="bitinit" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="bitinit.log" label="BitInit Log File" />
|
||||
<view inputState="PreSynthesized" program="system" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="mojo_top.log" label="System Log File" />
|
||||
</viewgroup>
|
||||
<viewgroup label="Errors and Warnings" >
|
||||
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|
||||
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|
||||
<view inputState="Synthesized" program="ngdbuild" WrapMessages="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/ngdbuild.xmsgs" label="Translation Messages" />
|
||||
<view inputState="Translated" program="map" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/map.xmsgs" label="Map Messages" />
|
||||
<view inputState="Mapped" program="par" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/par.xmsgs" label="Place and Route Messages" />
|
||||
<view inputState="Routed" program="trce" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/trce.xmsgs" label="Timing Messages" />
|
||||
<view inputState="Routed" program="xpwr" WrapMessages="true" contextTags="EDK_OFF" hidden="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/xpwr.xmsgs" label="Power Messages" />
|
||||
<view inputState="Routed" program="bitgen" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/bitgen.xmsgs" label="Bitgen Messages" />
|
||||
<view inputState="Translated" program="cpldfit" WrapMessages="true" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/cpldfit.xmsgs" label="Fitter Messages" />
|
||||
<view inputState="Current" program="implementation" WrapMessages="true" fileList="_xmsgs/xst.xmsgs,_xmsgs/ngdbuild.xmsgs,_xmsgs/map.xmsgs,_xmsgs/par.xmsgs,_xmsgs/trce.xmsgs,_xmsgs/xpwr.xmsgs,_xmsgs/bitgen.xmsgs" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/*.xmsgs" label="All Implementation Messages" />
|
||||
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|
||||
</viewgroup>
|
||||
<viewgroup label="Detailed Reports" >
|
||||
<view program="xst" contextTags="XST_ONLY,EDK_OFF" hidden="false" type="Report" file="mojo_top.syr" label="Synthesis Report" >
|
||||
<toc-item title="Top of Report" target="Copyright " searchDir="Forward" />
|
||||
<toc-item title="Synthesis Options Summary" target=" Synthesis Options Summary " />
|
||||
<toc-item title="HDL Compilation" target=" HDL Compilation " />
|
||||
<toc-item title="Design Hierarchy Analysis" target=" Design Hierarchy Analysis " />
|
||||
<toc-item title="HDL Analysis" target=" HDL Analysis " />
|
||||
<toc-item title="HDL Parsing" target=" HDL Parsing " />
|
||||
<toc-item title="HDL Elaboration" target=" HDL Elaboration " />
|
||||
<toc-item title="HDL Synthesis" target=" HDL Synthesis " />
|
||||
<toc-item title="HDL Synthesis Report" target="HDL Synthesis Report" searchCnt="2" searchDir="Backward" subItemLevel="1" />
|
||||
<toc-item title="Advanced HDL Synthesis" target=" Advanced HDL Synthesis " searchDir="Backward" />
|
||||
<toc-item title="Advanced HDL Synthesis Report" target="Advanced HDL Synthesis Report" subItemLevel="1" />
|
||||
<toc-item title="Low Level Synthesis" target=" Low Level Synthesis " />
|
||||
<toc-item title="Partition Report" target=" Partition Report " />
|
||||
<toc-item title="Final Report" target=" Final Report " />
|
||||
<toc-item title="Design Summary" target=" Design Summary " />
|
||||
<toc-item title="Primitive and Black Box Usage" target="Primitive and Black Box Usage:" subItemLevel="1" />
|
||||
<toc-item title="Device Utilization Summary" target="Device utilization summary:" subItemLevel="1" />
|
||||
<toc-item title="Partition Resource Summary" target="Partition Resource Summary:" subItemLevel="1" />
|
||||
<toc-item title="Timing Report" target="Timing Report" subItemLevel="1" />
|
||||
<toc-item title="Clock Information" target="Clock Information" subItemLevel="2" />
|
||||
<toc-item title="Asynchronous Control Signals Information" target="Asynchronous Control Signals Information" subItemLevel="2" />
|
||||
<toc-item title="Timing Summary" target="Timing Summary" subItemLevel="2" />
|
||||
<toc-item title="Timing Details" target="Timing Details" subItemLevel="2" />
|
||||
<toc-item title="Cross Clock Domains Report" target="Cross Clock Domains Report:" subItemLevel="2" />
|
||||
</view>
|
||||
<view program="synplify" contextTags="SYNPLIFY_ONLY,EDK_OFF" hidden="true" type="Report" file="mojo_top.srr" label="Synplify Report" />
|
||||
<view program="precision" contextTags="PRECISION_ONLY,EDK_OFF" hidden="true" type="Report" file="mojo_top.prec_log" label="Precision Report" />
|
||||
<view inputState="Synthesized" program="ngdbuild" type="Report" file="mojo_top.bld" label="Translation Report" >
|
||||
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
|
||||
<toc-item title="Command Line" target="Command Line:" />
|
||||
<toc-item title="Partition Status" target="Partition Implementation Status" />
|
||||
<toc-item title="Final Summary" target="NGDBUILD Design Results Summary:" />
|
||||
</view>
|
||||
<view inputState="Translated" program="map" contextTags="FPGA_ONLY" type="Report" file="mojo_top_map.mrp" label="Map Report" >
|
||||
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
|
||||
<toc-item title="Section 1: Errors" target="Section 1 -" searchDir="Backward" />
|
||||
<toc-item title="Section 2: Warnings" target="Section 2 -" searchDir="Backward" />
|
||||
<toc-item title="Section 3: Infos" target="Section 3 -" searchDir="Backward" />
|
||||
<toc-item title="Section 4: Removed Logic Summary" target="Section 4 -" searchDir="Backward" />
|
||||
<toc-item title="Section 5: Removed Logic" target="Section 5 -" searchDir="Backward" />
|
||||
<toc-item title="Section 6: IOB Properties" target="Section 6 -" searchDir="Backward" />
|
||||
<toc-item title="Section 7: RPMs" target="Section 7 -" searchDir="Backward" />
|
||||
<toc-item title="Section 8: Guide Report" target="Section 8 -" searchDir="Backward" />
|
||||
<toc-item title="Section 9: Area Group and Partition Summary" target="Section 9 -" searchDir="Backward" />
|
||||
<toc-item title="Section 10: Timing Report" target="Section 10 -" searchDir="Backward" />
|
||||
<toc-item title="Section 11: Configuration String Details" target="Section 11 -" searchDir="Backward" />
|
||||
<toc-item title="Section 12: Control Set Information" target="Section 12 -" searchDir="Backward" />
|
||||
<toc-item title="Section 13: Utilization by Hierarchy" target="Section 13 -" searchDir="Backward" />
|
||||
</view>
|
||||
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY" type="Report" file="mojo_top.par" label="Place and Route Report" >
|
||||
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
|
||||
<toc-item title="Device Utilization" target="Device Utilization Summary:" />
|
||||
<toc-item title="Router Information" target="Starting Router" />
|
||||
<toc-item title="Partition Status" target="Partition Implementation Status" />
|
||||
<toc-item title="Clock Report" target="Generating Clock Report" />
|
||||
<toc-item title="Timing Results" target="Timing Score:" />
|
||||
<toc-item title="Final Summary" target="Peak Memory Usage:" />
|
||||
</view>
|
||||
<view inputState="Routed" program="trce" contextTags="FPGA_ONLY" type="Report" file="mojo_top.twr" label="Post-PAR Static Timing Report" >
|
||||
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
|
||||
<toc-item title="Timing Report Description" target="Device,package,speed:" />
|
||||
<toc-item title="Informational Messages" target="INFO:" />
|
||||
<toc-item title="Warning Messages" target="WARNING:" />
|
||||
<toc-item title="Timing Constraints" target="Timing constraint:" />
|
||||
<toc-item title="Derived Constraint Report" target="Derived Constraint Report" />
|
||||
<toc-item title="Data Sheet Report" target="Data Sheet report:" />
|
||||
<toc-item title="Timing Summary" target="Timing summary:" />
|
||||
<toc-item title="Trace Settings" target="Trace Settings:" />
|
||||
</view>
|
||||
<view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="mojo_top.rpt" label="CPLD Fitter Report (Text)" >
|
||||
<toc-item title="Top of Report" target="cpldfit:" searchDir="Forward" />
|
||||
<toc-item title="Resources Summary" target="** Mapped Resource Summary **" />
|
||||
<toc-item title="Pin Resources" target="** Pin Resources **" />
|
||||
<toc-item title="Global Resources" target="** Global Control Resources **" />
|
||||
</view>
|
||||
<view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="mojo_top.tim" label="CPLD Timing Report (Text)" >
|
||||
<toc-item title="Top of Report" target="Performance Summary Report" searchDir="Forward" />
|
||||
<toc-item title="Performance Summary" target="Performance Summary:" />
|
||||
</view>
|
||||
<view inputState="Routed" program="xpwr" contextTags="EDK_OFF" type="Report" file="mojo_top.pwr" label="Power Report" >
|
||||
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
|
||||
<toc-item title="Power summary" target="Power summary" />
|
||||
<toc-item title="Thermal summary" target="Thermal summary" />
|
||||
</view>
|
||||
<view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" type="Report" file="mojo_top.bgn" label="Bitgen Report" >
|
||||
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
|
||||
<toc-item title="Bitgen Options" target="Summary of Bitgen Options:" />
|
||||
<toc-item title="Final Summary" target="DRC detected" />
|
||||
</view>
|
||||
</viewgroup>
|
||||
<viewgroup label="Secondary Reports" >
|
||||
<view inputState="PreSynthesized" program="isim" hidden="if_missing" type="Secondary_Report" file="isim.log" label="ISIM Simulator Log" />
|
||||
<view inputState="Synthesized" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/synthesis/mojo_top_synthesis.nlf" label="Post-Synthesis Simulation Model Report" >
|
||||
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
|
||||
</view>
|
||||
<view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/translate/mojo_top_translate.nlf" label="Post-Translate Simulation Model Report" >
|
||||
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
|
||||
</view>
|
||||
<view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="mojo_top_tran_fecn.nlf" label="Post-Translate Formality Netlist Report" />
|
||||
<view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="mojo_top_map.map" label="Map Log File" >
|
||||
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
|
||||
<toc-item title="Design Information" target="Design Information" />
|
||||
<toc-item title="Design Summary" target="Design Summary" />
|
||||
</view>
|
||||
<view inputState="Routed" program="smartxplorer" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="smartxplorer_results/smartxplorer.txt" label="SmartXplorer Report" />
|
||||
<view inputState="Mapped" program="trce" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="mojo_top_preroute.twr" label="Post-Map Static Timing Report" >
|
||||
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
|
||||
<toc-item title="Timing Report Description" target="Device,package,speed:" />
|
||||
<toc-item title="Informational Messages" target="INFO:" />
|
||||
<toc-item title="Warning Messages" target="WARNING:" />
|
||||
<toc-item title="Timing Constraints" target="Timing constraint:" />
|
||||
<toc-item title="Derived Constraint Report" target="Derived Constraint Report" />
|
||||
<toc-item title="Data Sheet Report" target="Data Sheet report:" />
|
||||
<toc-item title="Timing Summary" target="Timing summary:" />
|
||||
<toc-item title="Trace Settings" target="Trace Settings:" />
|
||||
</view>
|
||||
<view inputState="Mapped" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/map/mojo_top_map.nlf" label="Post-Map Simulation Model Report" />
|
||||
<view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="mojo_top_map.psr" label="Physical Synthesis Report" >
|
||||
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
|
||||
</view>
|
||||
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Pad_Report" file="mojo_top_pad.txt" label="Pad Report" >
|
||||
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
|
||||
</view>
|
||||
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="mojo_top.unroutes" label="Unroutes Report" >
|
||||
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
|
||||
</view>
|
||||
<view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="mojo_top_preroute.tsi" label="Post-Map Constraints Interaction Report" >
|
||||
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
|
||||
</view>
|
||||
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="mojo_top.grf" label="Guide Results Report" />
|
||||
<view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="mojo_top.dly" label="Asynchronous Delay Report" />
|
||||
<view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="mojo_top.clk_rgn" label="Clock Region Report" />
|
||||
<view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="mojo_top.tsi" label="Post-Place and Route Constraints Interaction Report" >
|
||||
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
|
||||
</view>
|
||||
<view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="mojo_top_par_fecn.nlf" label="Post-Place and Route Formality Netlist Report" />
|
||||
<view inputState="Routed" program="netgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="netgen/par/mojo_top_timesim.nlf" label="Post-Place and Route Simulation Model Report" />
|
||||
<view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="mojo_top_sta.nlf" label="Primetime Netlist Report" >
|
||||
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
|
||||
</view>
|
||||
<view inputState="Routed" program="ibiswriter" hidden="if_missing" type="Secondary_Report" file="mojo_top.ibs" label="IBIS Model" >
|
||||
<toc-item title="Top of Report" target="IBIS Models for" searchDir="Forward" />
|
||||
<toc-item title="Component" target="Component " />
|
||||
</view>
|
||||
<view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="mojo_top.lck" label="Back-annotate Pin Report" >
|
||||
<toc-item title="Top of Report" target="pin2ucf Report File" searchDir="Forward" />
|
||||
<toc-item title="Constraint Conflicts Information" target="Constraint Conflicts Information" />
|
||||
</view>
|
||||
<view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="mojo_top.lpc" label="Locked Pin Constraints" >
|
||||
<toc-item title="Top of Report" target="top.lpc" searchDir="Forward" />
|
||||
<toc-item title="Newly Added Constraints" target="The following constraints were newly added" />
|
||||
</view>
|
||||
<view inputState="Translated" program="netgen" contextTags="CPLD_ONLY,EDK_OFF" hidden="if_missing" type="Secondary_Report" file="netgen/fit/mojo_top_timesim.nlf" label="Post-Fit Simulation Model Report" />
|
||||
<view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="HTML" file="usage_statistics_webtalk.html" label="WebTalk Report" />
|
||||
<view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="webtalk.log" label="WebTalk Log File" />
|
||||
</viewgroup>
|
||||
</body>
|
||||
</report-views>
|
||||
|
|
@ -1,3 +0,0 @@
|
|||
-g TdoPin:PULLNONE
|
||||
-g StartUpClk:JTAGCLK
|
||||
#add other options here.
|
||||
|
|
@ -1,61 +0,0 @@
|
|||
<HTML><HEAD><TITLE>Xilinx Design Summary</TITLE></HEAD>
|
||||
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
|
||||
<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
|
||||
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
|
||||
<TD ALIGN=CENTER COLSPAN='4'><B>test Project Status</B></TD></TR>
|
||||
<TR ALIGN=LEFT>
|
||||
<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
|
||||
<TD>test.xmp</TD>
|
||||
<TD BGCOLOR='#FFFF99'><B>Implementation State:</B></TD>
|
||||
<TD>New</TD>
|
||||
</TR>
|
||||
<TR ALIGN=LEFT>
|
||||
<TD BGCOLOR='#FFFF99'><B>Module Name:</B></TD>
|
||||
<TD>test</TD>
|
||||
<TD BGCOLOR='#FFFF99'><UL><LI><B>Errors:</B></LI></UL></TD>
|
||||
<TD> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=LEFT>
|
||||
<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>EDK 14.7</TD>
|
||||
<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD>
|
||||
<TD> </TD>
|
||||
</TR>
|
||||
</TABLE>
|
||||
|
||||
|
||||
|
||||
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
|
||||
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='5'><B>XPS Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=EDKReports"><B>[-]</B></a></TD></TR>
|
||||
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Generated</B></TD>
|
||||
<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>
|
||||
<TR ALIGN=LEFT><TD>Platgen Log File</TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR>
|
||||
<TR ALIGN=LEFT><TD>Simgen Log File</TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR>
|
||||
<TR ALIGN=LEFT><TD>BitInit Log File</TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR>
|
||||
<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/tim/Projects/fpga/micro_test/test/test.log'>System Log File</A></TD><TD>Mon Sep 14 18:25:51 2020</TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR>
|
||||
</TABLE>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
|
||||
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR>
|
||||
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>
|
||||
<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>
|
||||
<TR ALIGN=LEFT><TD>Translation Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR>
|
||||
<TR ALIGN=LEFT><TD>Map Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR>
|
||||
<TR ALIGN=LEFT><TD>Place and Route Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR>
|
||||
<TR ALIGN=LEFT><TD>Post-PAR Static Timing Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR>
|
||||
<TR ALIGN=LEFT><TD>Bitgen Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR>
|
||||
</TABLE>
|
||||
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
|
||||
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR>
|
||||
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR>
|
||||
</TABLE>
|
||||
|
||||
|
||||
<br><center><b>Date Generated:</b> 09/14/2020 - 18:26:05</center>
|
||||
</BODY></HTML>
|
||||
Reference in New Issue
Block a user