Removed unnecessary files
This commit is contained in:
@@ -1,78 +0,0 @@
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<?xml version="1.0" encoding="UTF-8"?>
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<!-- IMPORTANT: This is an internal file that has been generated
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by the Xilinx ISE software. Any direct editing or
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changes made to this file may result in unpredictable
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behavior or data corruption. It is strongly advised that
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users do not edit the contents of this file. -->
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<messages>
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<msg type="info" file="sim" num="172" delta="old" >Generating IP...
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</msg>
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<msg type="warning" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">Verilog simulation file type 'Behavioral' is not valid for this core. Overriding with simulation file type 'Structural'.</arg>
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</msg>
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<msg type="warning" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">A core named 'microblaze_mcs' already exists in the project. Output products for this core may be overwritten.</arg>
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</msg>
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<msg type="warning" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">Verilog simulation file type 'Behavioral' is not valid for this core. Overriding with simulation file type 'Structural'.</arg>
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</msg>
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<msg type="warning" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">A core named 'microblaze_mcs' already exists in the project. Output products for this core may be overwritten.</arg>
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</msg>
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<msg type="info" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">Pre-processing HDL files for 'microblaze_mcs'...</arg>
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</msg>
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<msg type="info" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">Running microblaze_mcs_gen_script.tcl</arg>
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</msg>
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<msg type="info" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">Please source the "microblaze_mcs_setup.tcl" script in the Tcl Console to complete MicroBlaze MCS core generation</arg>
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</msg>
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<msg type="warning" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">Verilog simulation file type 'Behavioral' is not valid for this core. Overriding with simulation file type 'Structural'.</arg>
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</msg>
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<msg type="warning" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">Verilog simulation file type 'Behavioral' is not valid for this core. Overriding with simulation file type 'Structural'.</arg>
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</msg>
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<msg type="info" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">Running microblaze_mcs_sim_script.tcl</arg>
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</msg>
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<msg type="info" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">C_MICROBLAZE_INSTANCE = microblaze_mcs</arg>
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</msg>
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<msg type="info" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">Netlist filename = ./_cg/microblaze_mcs.v</arg>
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</msg>
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<msg type="info" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">Setting INIT_FILE = "microblaze_mcs.lmb_bram_7.mem" for BRAM 7</arg>
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</msg>
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<msg type="info" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">Setting INIT_FILE = "microblaze_mcs.lmb_bram_6.mem" for BRAM 6</arg>
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</msg>
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<msg type="info" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">Setting INIT_FILE = "microblaze_mcs.lmb_bram_5.mem" for BRAM 5</arg>
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</msg>
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<msg type="info" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">Setting INIT_FILE = "microblaze_mcs.lmb_bram_4.mem" for BRAM 4</arg>
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</msg>
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<msg type="info" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">Setting INIT_FILE = "microblaze_mcs.lmb_bram_3.mem" for BRAM 3</arg>
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</msg>
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<msg type="info" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">Setting INIT_FILE = "microblaze_mcs.lmb_bram_2.mem" for BRAM 2</arg>
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</msg>
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<msg type="info" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">Setting INIT_FILE = "microblaze_mcs.lmb_bram_1.mem" for BRAM 1</arg>
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</msg>
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<msg type="info" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">Setting INIT_FILE = "microblaze_mcs.lmb_bram_0.mem" for BRAM 0</arg>
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</msg>
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<msg type="info" file="sim" num="949" delta="old" >Finished generation of ASY schematic symbol.
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</msg>
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<msg type="info" file="sim" num="948" delta="old" >Finished FLIST file generation.
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</msg>
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</messages>
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@@ -1,15 +0,0 @@
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<?xml version="1.0" encoding="UTF-8"?>
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<!-- IMPORTANT: This is an internal file that has been generated -->
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<!-- by the Xilinx ISE software. Any direct editing or -->
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<!-- changes made to this file may result in unpredictable -->
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<!-- behavior or data corruption. It is strongly advised that -->
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<!-- users do not edit the contents of this file. -->
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<!-- -->
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<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
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<messages>
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<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file "/home/tim/Projects/z80/hdmi/ipcore_dir/hdmi_clk.v" into library work</arg>
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</msg>
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</messages>
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@@ -1,52 +0,0 @@
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
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<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
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<!-- -->
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<!-- For tool use only. Do not edit. -->
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<!-- -->
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<!-- ProjectNavigator created generated project file. -->
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<!-- For use in tracking generated file and other information -->
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<!-- allowing preservation of process status. -->
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<!-- -->
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<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
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<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
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<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="hdmi_clk.xise"/>
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<files xmlns="http://www.xilinx.com/XMLSchema">
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<file xil_pn:fileType="FILE_ASY" xil_pn:name="hdmi_clk.asy" xil_pn:origination="imported"/>
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<file xil_pn:fileType="FILE_VEO" xil_pn:name="hdmi_clk.veo" xil_pn:origination="imported"/>
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</files>
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<transforms xmlns="http://www.xilinx.com/XMLSchema">
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<transform xil_pn:end_ts="1600022764" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1600022764">
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="ReadyToRun"/>
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</transform>
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<transform xil_pn:end_ts="1600550220" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-8597742380004556400" xil_pn:start_ts="1600550220">
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="ReadyToRun"/>
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</transform>
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<transform xil_pn:end_ts="1600550220" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-1825882304215661665" xil_pn:start_ts="1600550220">
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="ReadyToRun"/>
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</transform>
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<transform xil_pn:end_ts="1600550220" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1600550220">
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="ReadyToRun"/>
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</transform>
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<transform xil_pn:end_ts="1600550220" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="1294299709957645202" xil_pn:start_ts="1600550220">
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="ReadyToRun"/>
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</transform>
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</transforms>
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</generated_project>
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@@ -1,2 +0,0 @@
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verilog work ../../hdmi_clk.v
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verilog work ../example_design/hdmi_clk_exdes.v
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@@ -1,49 +0,0 @@
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
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<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
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<!-- -->
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<!-- For tool use only. Do not edit. -->
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<!-- -->
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<!-- ProjectNavigator created generated project file. -->
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<!-- For use in tracking generated file and other information -->
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<!-- allowing preservation of process status. -->
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<!-- -->
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<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
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<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
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<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="microblaze_mcs.xise"/>
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<files xmlns="http://www.xilinx.com/XMLSchema"/>
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<transforms xmlns="http://www.xilinx.com/XMLSchema">
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<transform xil_pn:end_ts="1599953511" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1599953511">
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="ReadyToRun"/>
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</transform>
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<transform xil_pn:end_ts="1600550220" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="7354168592165971327" xil_pn:start_ts="1600550220">
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="ReadyToRun"/>
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</transform>
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<transform xil_pn:end_ts="1600550220" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-5659800160767749842" xil_pn:start_ts="1600550220">
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="ReadyToRun"/>
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</transform>
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<transform xil_pn:end_ts="1600550220" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1600550220">
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="ReadyToRun"/>
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</transform>
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<transform xil_pn:end_ts="1600550220" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="2694950640116957441" xil_pn:start_ts="1600550220">
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="ReadyToRun"/>
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</transform>
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</transforms>
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</generated_project>
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File diff suppressed because one or more lines are too long
@@ -1,12 +0,0 @@
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<?xml version="1.0" encoding="UTF-8"?>
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||||
<!-- IMPORTANT: This is an internal file that has been generated
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||||
by the Xilinx ISE software. Any direct editing or
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||||
changes made to this file may result in unpredictable
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||||
behavior or data corruption. It is strongly advised that
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||||
users do not edit the contents of this file. -->
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||||
<messages>
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<msg type="info" file="NetListWriters" num="633" delta="old" >The generated Verilog netlist contains Xilinx <arg fmt="%s" index="1">UNISIM</arg> simulation primitives and has to be used with <arg fmt="%s" index="2">UNISIM</arg> simulation library for correct compilation and simulation.
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</msg>
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</messages>
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@@ -1,12 +0,0 @@
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<?xml version="1.0" encoding="UTF-8"?>
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||||
<!-- IMPORTANT: This is an internal file that has been generated -->
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<!-- by the Xilinx ISE software. Any direct editing or -->
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<!-- changes made to this file may result in unpredictable -->
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||||
<!-- behavior or data corruption. It is strongly advised that -->
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||||
<!-- users do not edit the contents of this file. -->
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||||
<!-- -->
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||||
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
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<messages>
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</messages>
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File diff suppressed because it is too large
Load Diff
@@ -1 +0,0 @@
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work
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