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@@ -210,6 +210,7 @@ reg write_enable, write_enable_c_q, write_enable_c_d;
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wire[7:0] sram_read_data;
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sram #(.SIZE(8), .DEPTH(CHAR_HMAX*CHAR_VMAX)) sram(
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.clk(hdmi_clk),
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.rst(rst),
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.read_address(char_index_q),
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.write_address(addr_q-1),
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.read_data(sram_read_data),
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@@ -306,6 +307,7 @@ always @(negedge z80_ioreq) begin
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bottom_t = 1;
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scroll_t = scroll_q + 1;
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end else if ((bottom_q == 1) && ((addr_t >= (scroll_q*CHAR_HMAX)) || (addr_n >= (scroll_q*CHAR_HMAX)) || (addr_r >= (scroll_q*CHAR_HMAX)))) begin
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// Reset line
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scroll_t = scroll_q + 1;
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end
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@@ -317,6 +319,7 @@ always @(negedge z80_ioreq) begin
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addr_b = addr_b - 1;
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end
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// @todo If we underflow (-1) we do not end up in the right spot (makes sense)
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addr_t = addr_t % (CHAR_HMAX*CHAR_VMAX);
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addr_n = addr_n % (CHAR_HMAX*CHAR_VMAX);
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addr_r = addr_r % (CHAR_HMAX*CHAR_VMAX);
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@@ -1,22 +1,27 @@
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module sram #(
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parameter SIZE = 1,
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parameter DEPTH = 1
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)(
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input clk,
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input [$clog2(DEPTH)-1:0] read_address,
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input [$clog2(DEPTH)-1:0] write_address,
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output reg [SIZE-1:0] read_data,
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input [SIZE-1:0] write_data,
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input write_en
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);
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reg [SIZE-1:0] ram [DEPTH-1:0];
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always @(posedge clk) begin
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read_data <= ram[read_address];
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if (write_en)
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ram[write_address] <= write_data;
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end
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parameter SIZE = 1,
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parameter DEPTH = 1
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)(
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input clk,
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input rst,
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input [$clog2(DEPTH)-1:0] read_address,
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input [$clog2(DEPTH)-1:0] write_address,
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output reg [SIZE-1:0] read_data,
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input [SIZE-1:0] write_data,
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input write_en
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);
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reg [SIZE-1:0] ram [DEPTH-1:0];
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reg [DEPTH-1:0] valid;
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always @(posedge clk) begin
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read_data <= ram[read_address] * valid[read_address];
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if (write_en) begin
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valid[write_address] <= 1;
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ram[write_address] <= write_data;
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end
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end
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endmodule
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