z80/hdmi.old
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Dreaded_X 2020-09-19 22:23:51 +02:00
parent 5e1e3bbbcc
commit e8bedf9b14
4 changed files with 35 additions and 26 deletions
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5
HDMI.alp
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@ -1,5 +1,5 @@
<?xml version="1.0" encoding="UTF-8"?> <?xml version="1.0" encoding="UTF-8"?>
<project name="HDMI" board="Mojo" language="Verilog" version="2"> <project name="HDMI" board="Mojo" language="Verilog" version="3">
<files> <files>
<src>hdmi_encoder.luc</src> <src>hdmi_encoder.luc</src>
<src top="true">mojo_top.v</src> <src top="true">mojo_top.v</src>
@ -9,9 +9,10 @@
<component>dvi_globals.luc</component> <component>dvi_globals.luc</component>
<component>avr_interface.luc</component> <component>avr_interface.luc</component>
<component>dvi_encoder.luc</component> <component>dvi_encoder.luc</component>
<component>spi_slave.luc</component> <component>spi_peripheral.luc</component>
<component>uart_tx.luc</component> <component>uart_tx.luc</component>
<component>serdes_n_to_1.luc</component> <component>serdes_n_to_1.luc</component>
<src>spi_slave.luc</src>
<component>simple_dual_ram.v</component> <component>simple_dual_ram.v</component>
<component>async_fifo.luc</component> <component>async_fifo.luc</component>
<component>cclk_detector.luc</component> <component>cclk_detector.luc</component>

8
constraint/z80.ucf
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@ -1,8 +1,8 @@
NET "z80_clk" LOC = P23 | IOSTANDARD = LVTTL; NET "z80_clk" LOC = P23 | IOSTANDARD = LVTTL;
NET "z80_data(2)" LOC = P114 | IOSTANDARD = LVTTL; NET "z80_data(1)" LOC = P114 | IOSTANDARD = LVTTL;
NET "z80_data(3)" LOC = P115 | IOSTANDARD = LVTTL; NET "z80_data(0)" LOC = P115 | IOSTANDARD = LVTTL;
NET "z80_data(1)" LOC = P116 | IOSTANDARD = LVTTL; NET "z80_data(2)" LOC = P116 | IOSTANDARD = LVTTL;
NET "z80_data(0)" LOC = P117 | IOSTANDARD = LVTTL; NET "z80_data(3)" LOC = P117 | IOSTANDARD = LVTTL;
NET "z80_data(4)" LOC = P118 | IOSTANDARD = LVTTL; NET "z80_data(4)" LOC = P118 | IOSTANDARD = LVTTL;
NET "z80_data(5)" LOC = P119 | IOSTANDARD = LVTTL; NET "z80_data(5)" LOC = P119 | IOSTANDARD = LVTTL;
NET "z80_data(6)" LOC = P120 | IOSTANDARD = LVTTL; NET "z80_data(6)" LOC = P120 | IOSTANDARD = LVTTL;

3
source/mojo_top.v
View File

@ -210,6 +210,7 @@ reg write_enable, write_enable_c_q, write_enable_c_d;
wire[7:0] sram_read_data; wire[7:0] sram_read_data;
sram #(.SIZE(8), .DEPTH(CHAR_HMAX*CHAR_VMAX)) sram( sram #(.SIZE(8), .DEPTH(CHAR_HMAX*CHAR_VMAX)) sram(
.clk(hdmi_clk), .clk(hdmi_clk),
.rst(rst),
.read_address(char_index_q), .read_address(char_index_q),
.write_address(addr_q-1), .write_address(addr_q-1),
.read_data(sram_read_data), .read_data(sram_read_data),
@ -306,6 +307,7 @@ always @(negedge z80_ioreq) begin
bottom_t = 1; bottom_t = 1;
scroll_t = scroll_q + 1; scroll_t = scroll_q + 1;
end else if ((bottom_q == 1) && ((addr_t >= (scroll_q*CHAR_HMAX)) || (addr_n >= (scroll_q*CHAR_HMAX)) || (addr_r >= (scroll_q*CHAR_HMAX)))) begin end else if ((bottom_q == 1) && ((addr_t >= (scroll_q*CHAR_HMAX)) || (addr_n >= (scroll_q*CHAR_HMAX)) || (addr_r >= (scroll_q*CHAR_HMAX)))) begin
// Reset line
scroll_t = scroll_q + 1; scroll_t = scroll_q + 1;
end end
@ -317,6 +319,7 @@ always @(negedge z80_ioreq) begin
addr_b = addr_b - 1; addr_b = addr_b - 1;
end end
// @todo If we underflow (-1) we do not end up in the right spot (makes sense)
addr_t = addr_t % (CHAR_HMAX*CHAR_VMAX); addr_t = addr_t % (CHAR_HMAX*CHAR_VMAX);
addr_n = addr_n % (CHAR_HMAX*CHAR_VMAX); addr_n = addr_n % (CHAR_HMAX*CHAR_VMAX);
addr_r = addr_r % (CHAR_HMAX*CHAR_VMAX); addr_r = addr_r % (CHAR_HMAX*CHAR_VMAX);

37
source/sram.v
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@ -1,22 +1,27 @@
module sram #( module sram #(
parameter SIZE = 1, parameter SIZE = 1,
parameter DEPTH = 1 parameter DEPTH = 1
)( )(
input clk, input clk,
input [$clog2(DEPTH)-1:0] read_address, input rst,
input [$clog2(DEPTH)-1:0] write_address, input [$clog2(DEPTH)-1:0] read_address,
output reg [SIZE-1:0] read_data, input [$clog2(DEPTH)-1:0] write_address,
input [SIZE-1:0] write_data, output reg [SIZE-1:0] read_data,
input write_en input [SIZE-1:0] write_data,
); input write_en
);
reg [SIZE-1:0] ram [DEPTH-1:0]; reg [SIZE-1:0] ram [DEPTH-1:0];
always @(posedge clk) begin reg [DEPTH-1:0] valid;
read_data <= ram[read_address];
if (write_en) always @(posedge clk) begin
ram[write_address] <= write_data; read_data <= ram[read_address] * valid[read_address];
end
if (write_en) begin
valid[write_address] <= 1;
ram[write_address] <= write_data;
end
end
endmodule endmodule