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85
.gitignore vendored
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@ -1,84 +1 @@
# Created by https://www.toptal.com/developers/gitignore/api/xilinxise
# Edit at https://www.toptal.com/developers/gitignore?templates=xilinxise
### XilinxISE ###
# intermediate build files
*.bgn
*.bit
*.bld
*.cmd_log
*.drc
*.ll
*.lso
*.msd
*.msk
*.ncd
*.ngc
*.ngd
*.ngr
*.pad
*.par
*.pcf
*.prj
*.ptwx
*.rbb
*.rbd
*.stx
*.syr
*.twr
*.twx
*.unroutes
*.ut
*.xpi
*.xst
*_bitgen.xwbt
*_envsettings.html
*_map.map
*_map.mrp
*_map.ngm
*_map.xrpt
*_ngdbuild.xrpt
*_pad.csv
*_pad.txt
*_par.xrpt
*_summary.html
*_summary.xml
*_usage.xml
*_xst.xrpt
# iMPACT generated files
_impactbatch.log
impact.xsl
impact_impact.xwbt
ise_impact.cmd
webtalk_impact.xml
# Core Generator generated files
xaw2verilog.log
# project-wide generated files
*.gise
par_usage_statistics.html
usage_statistics_webtalk.html
webtalk.log
webtalk_pn.xml
# generated folders
iseconfig/
xlnx_auto_0_xdb/
xst/
_ngo/
_xmsgs/
# End of https://www.toptal.com/developers/gitignore/api/xilinxise
*.log
syn/*
!syn/main.prj
!syn/main.ut
!syn/main.xst
mb/*.elf
mb/*.d
mb/*.o
mb/Graphics_bsp/microblaze_mcs
work/

2
.vimlocal
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@ -1,2 +0,0 @@
map <silent> <F9> :Make<cr>
map <silent> <F10> :Dispatch upload --mojo syn/main.bin<cr>

27
HDMI.alp Normal file
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@ -0,0 +1,27 @@
<?xml version="1.0" encoding="UTF-8"?>
<project name="HDMI" board="Mojo" language="Verilog" version="3">
<files>
<src>hdmi_encoder.luc</src>
<src top="true">mojo_top.v</src>
<component>uart_rx.luc</component>
<src>sram.v</src>
<component>fifo_2x_reducer.luc</component>
<component>dvi_globals.luc</component>
<component>avr_interface.luc</component>
<component>dvi_encoder.luc</component>
<component>spi_peripheral.luc</component>
<component>uart_tx.luc</component>
<component>serdes_n_to_1.luc</component>
<src>spi_slave.luc</src>
<component>simple_dual_ram.v</component>
<component>async_fifo.luc</component>
<component>cclk_detector.luc</component>
<component>tmds_encoder.luc</component>
<constraint lib="true">mojo.ucf</constraint>
<constraint>hdmi2.ucf</constraint>
<constraint>z80.ucf</constraint>
<core name="clk_wiz_v3_6">
<src>..\clk_wiz_v3_6.v</src>
</core>
</files>
</project>

21
LICENSE.txt
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@ -1,21 +0,0 @@
The MIT License (MIT)
Copyright (c) 2015 Embedded Micro
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.

28
Makefile
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@ -1,28 +0,0 @@
all: syn/main.bin
syn/main.bin: syn/main.ncd mb/Graphics/Release/Graphics.elf
@cd syn && bitgen -intstyle ise -f main.ut main.ncd
syn/main.ncd: syn/main.prj syn/main.xst src/*.v ipcore_dir/*.v syn/xst/projnav.tmp/
@cd syn && xst -intstyle ise -ifn "main.xst" -ofn "main.syr"
@cd syn && ngdbuild -intstyle ise -dd _ngo -sd ../ipcore_dir -nt timestamp -uc /home/tim/Projects/z80/hdmi/src/constraints.ucf -p xc6slx9-tqg144-2 main.ngc main.ngd -bm "../ipcore_dir/microblaze_mcs.bmm"
@cd syn && map -intstyle ise -p xc6slx9-tqg144-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o main_map.ncd main.ngd main.pcf
@cd syn && par -w -intstyle ise -ol high -mt off main_map.ncd main.ncd main.pcf
@cd syn && trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf
syn/xst/projnav.tmp/:
@mkdir -p syn/xst/projnav.tmp
mb/Graphics/Release/Graphics.elf: mb
@echo
.PHONY: mb
mb:
@$(MAKE) -C mb/Graphics_bsp all
@$(MAKE) -C mb/Graphics/Release all
.PHONY: clean
clean:
@cd syn && find . ! -name 'main.prj' ! -name 'main.ut' ! -name 'main.xst' ! -name 'Makefile' ! -name '.' -exec rm -rf {} +
@$(MAKE) -C mb/Graphics_bsp clean
@$(MAKE) -C mb/Graphics/Release clean

17
cmds.sh
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@ -1,17 +0,0 @@
#!/bin/bash
# @todo We need to figure out the dependecies and turn this into a Makefile
# mkdir -p xst/projnav.tmp && \
# xst -intstyle ise -ifn "/home/tim/Projects/z80/hdmi/syn/main.xst" -ofn "/home/tim/Projects/z80/hdmi/syn/main.syr"
#
# ngdbuild -intstyle ise -dd _ngo -sd ../ipcore_dir -nt timestamp -i -p xc6slx9-tqg144-2 main.ngc main.ngd -bm "../ipcore_dir/microblaze_mcs.bmm"
#
# map -intstyle ise -p xc6slx9-tqg144-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o main_map.ncd main.ngd main.pcf
#
# par -w -intstyle ise -ol high -mt off main_map.ncd main.ncd main.pcf
#
# trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf
bitgen -intstyle ise -f main.ut main.ncd

8
constraint/hdmi2.ucf Normal file
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@ -0,0 +1,8 @@
NET "hdmi1_tmds(3)" LOC = "P144" |IOSTANDARD = TMDS_33 | CLOCK_DEDICATED_ROUTE = FALSE ; # Clock
NET "hdmi1_tmdsb(3)" LOC = "P143" |IOSTANDARD = TMDS_33 | CLOCK_DEDICATED_ROUTE = FALSE ;
NET "hdmi1_tmds(2)" LOC = "P138" |IOSTANDARD = TMDS_33 ; # Red
NET "hdmi1_tmdsb(2)" LOC = "P137" |IOSTANDARD = TMDS_33 ;
NET "hdmi1_tmds(1)" LOC = "P140" |IOSTANDARD = TMDS_33 ; # Green
NET "hdmi1_tmdsb(1)" LOC = "P139" |IOSTANDARD = TMDS_33 ;
NET "hdmi1_tmds(0)" LOC = "P142" |IOSTANDARD = TMDS_33 ; # Blue
NET "hdmi1_tmdsb(0)" LOC = "P141" |IOSTANDARD = TMDS_33 ;

20
constraint/z80.ucf Normal file
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@ -0,0 +1,20 @@
NET "z80_clk" LOC = P23 | IOSTANDARD = LVTTL;
NET "z80_data(1)" LOC = P114 | IOSTANDARD = LVTTL;
NET "z80_data(0)" LOC = P115 | IOSTANDARD = LVTTL;
NET "z80_data(2)" LOC = P116 | IOSTANDARD = LVTTL;
NET "z80_data(3)" LOC = P117 | IOSTANDARD = LVTTL;
NET "z80_data(4)" LOC = P118 | IOSTANDARD = LVTTL;
NET "z80_data(5)" LOC = P119 | IOSTANDARD = LVTTL;
NET "z80_data(6)" LOC = P120 | IOSTANDARD = LVTTL;
NET "z80_data(7)" LOC = P121 | IOSTANDARD = LVTTL;
// NET "z80_address(0)" LOC = P9 | IOSTANDARD = LVTTL;
// NET "z80_address(1)" LOC = P10 | IOSTANDARD = LVTTL;
// NET "z80_address(2)" LOC = P11 | IOSTANDARD = LVTTL;
// NET "z80_address(3)" LOC = P12 | IOSTANDARD = LVTTL;
// NET "z80_address(4)" LOC = P13 | IOSTANDARD = LVTTL;
// NET "z80_address(5)" LOC = P14 | IOSTANDARD = LVTTL;
// NET "z80_address(6)" LOC = P15 | IOSTANDARD = LVTTL;
// NET "z80_address(7)" LOC = P16 | IOSTANDARD = LVTTL;
NET "z80_ioreq" LOC = P24 | IOSTANDARD = LVTTL;
NET "z80_wr" LOC = P21 | IOSTANDARD = LVTTL;
NET "z80_m1" LOC = P22 | IOSTANDARD = LVTTL;

6
ipcore_dir/hdmi_clk.asy → cores/clk_wiz_v3_6.asy
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@ -1,6 +1,6 @@
Version 4
SymbolType BLOCK
TEXT 32 32 LEFT 4 hdmi_clk
TEXT 32 32 LEFT 4 clk_wiz_v3_6
RECTANGLE Normal 32 32 576 1088
LINE Normal 0 80 32 80
PIN 0 80 LEFT 36
@ -10,8 +10,4 @@ LINE Normal 608 80 576 80
PIN 608 80 RIGHT 36
PINATTR PinName clk_out1
PINATTR Polarity OUT
LINE Normal 608 176 576 176
PIN 608 176 RIGHT 36
PINATTR PinName clk_out2
PINATTR Polarity OUT

31
cores/clk_wiz_v3_6.gise Normal file
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@ -0,0 +1,31 @@
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<!-- -->
<!-- For tool use only. Do not edit. -->
<!-- -->
<!-- ProjectNavigator created generated project file. -->
<!-- For use in tracking generated file and other information -->
<!-- allowing preservation of process status. -->
<!-- -->
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="clk_wiz_v3_6.xise"/>
<files xmlns="http://www.xilinx.com/XMLSchema">
<file xil_pn:fileType="FILE_ASY" xil_pn:name="clk_wiz_v3_6.asy" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_VEO" xil_pn:name="clk_wiz_v3_6.veo" xil_pn:origination="imported"/>
</files>
<transforms xmlns="http://www.xilinx.com/XMLSchema"/>
</generated_project>

5
ipcore_dir/hdmi_clk.ncf → cores/clk_wiz_v3_6.ucf
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@ -1,4 +1,4 @@
# file: hdmi_clk.ucf
# file: clk_wiz_v3_6.ucf
#
# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
#
@ -51,9 +51,8 @@
# input clocks. You can use these to time your system
#----------------------------------------------------------------
NET "CLK_IN1" TNM_NET = "CLK_IN1";
TIMESPEC "TS_CLK_IN1" = PERIOD "CLK_IN1" 20.000 ns HIGH 50% INPUT_JITTER 200.0ps;
TIMESPEC "TS_CLK_IN1" = PERIOD "CLK_IN1" 20.0 ns HIGH 50% INPUT_JITTER 200.0ps;
# FALSE PATH constraints

100
ipcore_dir/hdmi_clk.v → cores/clk_wiz_v3_6.v Executable file → Normal file
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@ -1,4 +1,4 @@
// file: hdmi_clk.v
// file: clk_wiz_v3_6.v
//
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
//
@ -55,23 +55,21 @@
// "Output Output Phase Duty Pk-to-Pk Phase"
// "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
//----------------------------------------------------------------------------
// CLK_OUT1____75.000______0.000______50.0______248.869____240.171
// CLK_OUT2___150.000______0.000______50.0______216.897____240.171
// CLK_OUT1____75.000______0.000______50.0______466.667____150.000
//
//----------------------------------------------------------------------------
// "Input Clock Freq (MHz) Input Jitter (UI)"
//----------------------------------------------------------------------------
// __primary______________50____________0.010
// __primary__________50.000____________0.010
`timescale 1ps/1ps
(* CORE_GENERATION_INFO = "hdmi_clk,clk_wiz_v3_6,{component_name=hdmi_clk,use_phase_alignment=false,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=PLL_BASE,num_out_clk=2,clkin1_period=20.000,clkin2_period=20.000,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}" *)
module hdmi_clk
(* CORE_GENERATION_INFO = "clk_wiz_v3_6,clk_wiz_v3_6,{component_name=clk_wiz_v3_6,use_phase_alignment=false,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=1,clkin1_period=20.0,clkin2_period=20.0,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}" *)
module clk_wiz_v3_6
(// Clock in ports
input CLK_IN1,
// Clock out ports
output CLK_OUT1,
output CLK_OUT2
output CLK_OUT1
);
// Input buffering
@ -83,61 +81,65 @@ module hdmi_clk
// Clocking primitive
//------------------------------------
// Instantiation of the PLL primitive
// Instantiation of the DCM primitive
// * Unused inputs are tied off
// * Unused outputs are labeled unused
wire [15:0] do_unused;
wire drdy_unused;
wire locked_unused;
wire clkfbout;
wire clkout2_unused;
wire clkout3_unused;
wire clkout4_unused;
wire clkout5_unused;
wire psdone_unused;
wire locked_int;
wire [7:0] status_int;
wire clkfb;
wire clk0;
wire clkfx;
PLL_BASE
#(.BANDWIDTH ("OPTIMIZED"),
.CLK_FEEDBACK ("CLKFBOUT"),
.COMPENSATION ("INTERNAL"),
.DIVCLK_DIVIDE (1),
.CLKFBOUT_MULT (9),
.CLKFBOUT_PHASE (0.000),
.CLKOUT0_DIVIDE (6),
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT1_DIVIDE (3),
.CLKOUT1_PHASE (0.000),
.CLKOUT1_DUTY_CYCLE (0.500),
.CLKIN_PERIOD (20.000),
.REF_JITTER (0.010))
pll_base_inst
DCM_SP
#(.CLKDV_DIVIDE (2.000),
.CLKFX_DIVIDE (2),
.CLKFX_MULTIPLY (3),
.CLKIN_DIVIDE_BY_2 ("FALSE"),
.CLKIN_PERIOD (20.0),
.CLKOUT_PHASE_SHIFT ("NONE"),
.CLK_FEEDBACK ("NONE"),
.DESKEW_ADJUST ("SYSTEM_SYNCHRONOUS"),
.PHASE_SHIFT (0),
.STARTUP_WAIT ("FALSE"))
dcm_sp_inst
// Input clock
(.CLKIN (clkin1),
.CLKFB (clkfb),
// Output clocks
(.CLKFBOUT (clkfbout),
.CLKOUT0 (clkout0),
.CLKOUT1 (clkout1),
.CLKOUT2 (clkout2_unused),
.CLKOUT3 (clkout3_unused),
.CLKOUT4 (clkout4_unused),
.CLKOUT5 (clkout5_unused),
.LOCKED (locked_unused),
.CLK0 (clk0),
.CLK90 (),
.CLK180 (),
.CLK270 (),
.CLK2X (),
.CLK2X180 (),
.CLKFX (clkfx),
.CLKFX180 (),
.CLKDV (),
// Ports for dynamic phase shift
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.PSDONE (),
// Other control and status signals
.LOCKED (locked_int),
.STATUS (status_int),
.RST (1'b0),
// Input clock control
.CLKFBIN (clkfbout),
.CLKIN (clkin1));
// Unused pin- tie low
.DSSEN (1'b0));
// Output buffering
//-----------------------------------
// no phase alignment active, connect to ground
assign clkfb = 1'b0;
BUFG clkout1_buf
(.O (CLK_OUT1),
.I (clkout0));
.I (clkfx));
BUFG clkout2_buf
(.O (CLK_OUT2),
.I (clkout1));
endmodule

10
ipcore_dir/hdmi_clk.veo → cores/clk_wiz_v3_6.veo Executable file → Normal file
View File

@ -54,13 +54,12 @@
// "Output Output Phase Duty Pk-to-Pk Phase"
// "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
//----------------------------------------------------------------------------
// CLK_OUT1____75.000______0.000______50.0______248.869____240.171
// CLK_OUT2___150.000______0.000______50.0______216.897____240.171
// CLK_OUT1____75.000______0.000______50.0______466.667____150.000
//
//----------------------------------------------------------------------------
// "Input Clock Freq (MHz) Input Jitter (UI)"
//----------------------------------------------------------------------------
// __primary______________50____________0.010
// __primary__________50.000____________0.010
// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
@ -68,10 +67,9 @@
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
hdmi_clk instance_name
clk_wiz_v3_6 instance_name
(// Clock in ports
.CLK_IN1(CLK_IN1), // IN
// Clock out ports
.CLK_OUT1(CLK_OUT1), // OUT
.CLK_OUT2(CLK_OUT2)); // OUT
.CLK_OUT1(CLK_OUT1)); // OUT
// INST_TAG_END ------ End INSTANTIATION Template ---------

26
ipcore_dir/hdmi_clk.xco → cores/clk_wiz_v3_6.xco
View File

@ -1,7 +1,7 @@
##############################################################
#
# Xilinx Core Generator version 14.7
# Date: Mon Sep 21 18:02:33 2020
# Date: Fri Feb 28 22:02:23 2020
#
##############################################################
#
@ -70,13 +70,13 @@ CSET clkin2_jitter_ps=100.0
CSET clkin2_ui_jitter=0.010
CSET clkout1_drives=BUFG
CSET clkout1_requested_duty_cycle=50.000
CSET clkout1_requested_out_freq=75
CSET clkout1_requested_out_freq=75.000
CSET clkout1_requested_phase=0.000
CSET clkout2_drives=BUFG
CSET clkout2_requested_duty_cycle=50.000
CSET clkout2_requested_out_freq=150
CSET clkout2_requested_out_freq=100.000
CSET clkout2_requested_phase=0.000
CSET clkout2_used=true
CSET clkout2_used=false
CSET clkout3_drives=BUFG
CSET clkout3_requested_duty_cycle=50.000
CSET clkout3_requested_out_freq=100.000
@ -103,7 +103,7 @@ CSET clkout7_requested_out_freq=100.000
CSET clkout7_requested_phase=0.000
CSET clkout7_used=false
CSET clock_mgr_type=AUTO
CSET component_name=hdmi_clk
CSET component_name=clk_wiz_v3_6
CSET daddr_port=DADDR
CSET dclk_port=DCLK
CSET dcm_clk_feedback=NONE
@ -189,21 +189,21 @@ CSET mmcm_notes=None
CSET mmcm_ref_jitter1=0.010
CSET mmcm_ref_jitter2=0.010
CSET mmcm_startup_wait=false
CSET num_out_clks=2
CSET num_out_clks=1
CSET override_dcm=false
CSET override_dcm_clkgen=false
CSET override_mmcm=false
CSET override_pll=false
CSET platform=lin64
CSET platform=nt
CSET pll_bandwidth=OPTIMIZED
CSET pll_clk_feedback=CLKFBOUT
CSET pll_clkfbout_mult=9
CSET pll_clkfbout_mult=8
CSET pll_clkfbout_phase=0.000
CSET pll_clkin_period=20.000
CSET pll_clkout0_divide=6
CSET pll_clkin_period=20.0
CSET pll_clkout0_divide=128
CSET pll_clkout0_duty_cycle=0.500
CSET pll_clkout0_phase=0.000
CSET pll_clkout1_divide=3
CSET pll_clkout1_divide=1
CSET pll_clkout1_duty_cycle=0.500
CSET pll_clkout1_phase=0.000
CSET pll_clkout2_divide=1
@ -223,7 +223,7 @@ CSET pll_divclk_divide=1
CSET pll_notes=None
CSET pll_ref_jitter=0.010
CSET power_down_port=POWER_DOWN
CSET prim_in_freq=50
CSET prim_in_freq=50.000
CSET prim_in_jitter=0.010
CSET prim_source=Single_ended_clock_capable_pin
CSET primary_port=CLK_IN1
@ -266,4 +266,4 @@ CSET use_status=false
MISC pkg_timestamp=2012-05-10T12:44:55Z
# END Extra information
GENERATE
# CRC: 9368653d
# CRC: 78c63287

4
ipcore_dir/hdmi_clk.xdc → cores/clk_wiz_v3_6.xdc Executable file → Normal file
View File

@ -1,4 +1,4 @@
# file: hdmi_clk.xdc
# file: clk_wiz_v3_6.xdc
#
# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
#
@ -50,7 +50,7 @@
# Input clock periods. These duplicate the values entered for the
# input clocks. You can use these to time your system
#----------------------------------------------------------------
create_clock -name CLK_IN1 -period 20.000 [get_ports CLK_IN1]
create_clock -name CLK_IN1 -period 20.0 [get_ports CLK_IN1]
set_propagated_clock CLK_IN1
set_input_jitter CLK_IN1 0.2

292
hdmi.xise → cores/clk_wiz_v3_6.xise
View File

@ -15,158 +15,103 @@
<version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
<files>
<file xil_pn:name="src/constraints.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="src/main.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="12"/>
</file>
<file xil_pn:name="ipcore_dir/microblaze_mcs.xco" xil_pn:type="FILE_COREGEN">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/>
<association xil_pn:name="Implementation" xil_pn:seqID="10"/>
</file>
<file xil_pn:name="src/hdmi_encoder.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="75"/>
<association xil_pn:name="Implementation" xil_pn:seqID="7"/>
</file>
<file xil_pn:name="src/dvi_encoder.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="76"/>
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<file xil_pn:name="src/serdes_n_to_1.v" xil_pn:type="FILE_VERILOG">
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<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
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<file xil_pn:name="src/tmds_encoder.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="78"/>
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
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<file xil_pn:name="src/fifo_2x_reducer.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="79"/>
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<file xil_pn:name="src/async_fifo.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="80"/>
<file xil_pn:name="clk_wiz_v3_6.ucf" xil_pn:type="FILE_UCF">
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<file xil_pn:name="src/simple_dual_ram.v" xil_pn:type="FILE_VERILOG">
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<file xil_pn:name="ipcore_dir/hdmi_clk.xco" xil_pn:type="FILE_COREGEN">
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<file xil_pn:name="src/color_map.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="88"/>
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<file xil_pn:name="ipcore_dir/microblaze_mcs.xise" xil_pn:type="FILE_COREGENISE">
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<file xil_pn:name="ipcore_dir/hdmi_clk.xise" xil_pn:type="FILE_COREGENISE">
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<file xil_pn:name="clk_wiz_v3_6.v" xil_pn:type="FILE_VERILOG">
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<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="3"/>
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<properties>
<property xil_pn:name="AES Initial Vector spartan6" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="AES Initial Vector virtex6" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="AES Key (Hex String) spartan6" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Add File to project" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="AES Key (Hex String) virtex6" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Add I/O Pads" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Advanced FSM Optimization" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/>
<property xil_pn:name="Array Bounds Check" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Auto Constrain" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="BPI Reads Per Page" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="BPI Sync Mode" xil_pn:value="Disable" xil_pn:valueState="default"/>
<property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Baud rate" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Bus Delimiter" xil_pn:value="&lt;>" xil_pn:valueState="default"/>
<property xil_pn:name="CLB Pack Factor Percentage" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
<property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Change Device Speed To" xil_pn:value="-2" xil_pn:valueState="default"/>
<property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-2" xil_pn:valueState="default"/>
<property xil_pn:name="Clock Port" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile SmartModels (PPC, MGT) Simulation Library" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Clk (Configuration Pins)" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Name" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin HSWAPEN" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin Init" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin M0" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin M1" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin M2" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Rate" xil_pn:value="4" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Rate spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
<property xil_pn:name="Convert Tristates To Logic" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Rate virtex5" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Binary Configuration File" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create IEEE 1532 Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create IEEE 1532 Configuration File spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Cycles for First BPI Page Read" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="DCI Update Mode" xil_pn:value="As Required" xil_pn:valueState="default"/>
<property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Data Flow window" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Decoder Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Default Enum Encoding Goal" xil_pn:value="default" xil_pn:valueState="default"/>
<property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
<property xil_pn:name="Delay Values To Be Read from SDF ModelSim" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
<property xil_pn:name="Device" xil_pn:value="xc6slx9" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-2" xil_pn:valueState="default"/>
<property xil_pn:name="Disable Detailed Package Model Insertion" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Disable I/O insertion" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Display Incremental Messages" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Disable JTAG Connection" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
<property xil_pn:name="Drive Awake Pin During Suspend/Wake Sequence spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="EDIF" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Enable BitStream Compression" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Cyclic Redundancy Checking (CRC)" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Cyclic Redundancy Checking (CRC) spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Enhanced Design Summary" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Enable External Master Clock" xil_pn:value="Disable" xil_pn:valueState="default"/>
<property xil_pn:name="Enable External Master Clock spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Hardware Co-Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Multi-Threading" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Multi-Threading par spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Multi-Threading par virtex5" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Suspend/Wake Global Set/Reset spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Encrypt Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Encrypt Bitstream virtex6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Encrypt Key Select spartan6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
<property xil_pn:name="Equivalent Register Removal" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Encrypt Key Select virtex6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
<property xil_pn:name="Equivalent Register Removal Map" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Essential Bits" xil_pn:value="false" xil_pn:valueState="default"/>
@ -174,16 +119,14 @@
<property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Extra Cost Tables Map" xil_pn:value="0" xil_pn:valueState="default"/>
<property xil_pn:name="Extra Cost Tables Map virtex6" xil_pn:value="0" xil_pn:valueState="default"/>
<property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
<property xil_pn:name="FSM Encoding" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
<property xil_pn:name="Fanout Guide" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Fallback Reconfiguration virtex7" xil_pn:value="Disable" xil_pn:valueState="default"/>
<property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Frequency" xil_pn:value="0.0" xil_pn:valueState="default"/>
<property xil_pn:name="Full Case" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="Verilog" xil_pn:valueState="default"/>
@ -201,66 +144,45 @@
<property xil_pn:name="Generate Post-Place &amp; Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Post-Place &amp; Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Generate SAIF File for Power Optimization/Estimation" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate UCF from RTL Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Verbose Library Compilation Messages" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Global Clock Delay 0 (Binary String)" xil_pn:value="11111" xil_pn:valueState="default"/>
<property xil_pn:name="Global Clock Delay 1 (Binary String)" xil_pn:value="11111" xil_pn:valueState="default"/>
<property xil_pn:name="Global Clock Delay 2 (Binary String)" xil_pn:value="11111" xil_pn:valueState="default"/>
<property xil_pn:name="Global Clock Delay 3 (Binary String)" xil_pn:value="11111" xil_pn:valueState="default"/>
<property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
<property xil_pn:name="Global Optimization map" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Global Optimization map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Global Optimization map virtex5" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
<property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
<property xil_pn:name="HDL Instantiation Template Target Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="HMAC Key (Hex String)" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
<property xil_pn:name="ICAP Select" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore Pre-Compiled Library Warning Check" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore Version Check" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Implementation Start View" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Implementation Stop View" xil_pn:value="AbstractSynthesis" xil_pn:valueState="default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Module|main" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="../src/main.v" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/main" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Module|clk_wiz_v3_6" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="clk_wiz_v3_6.v" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/clk_wiz_v3_6" xil_pn:valueState="non-default"/>
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Instance Name for Simulation in Hardware" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Instantiation Template Target Language Schematic" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG to XADC Connection" xil_pn:value="Enable" xil_pn:valueState="default"/>
<property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/>
<property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked)" xil_pn:valueState="default"/>
<property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="List window" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Load Timing Specification Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Log All Signals In Behavioral Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Log All Signals In Post-Map Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Log All Signals In Post-Par Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Log All Signals In Post-Translate Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Logical Shifter Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="MAC Address for Hardware Co-Simulation" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Mask Pins for Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="0x00" xil_pn:valueState="default"/>
@ -268,100 +190,73 @@
<property xil_pn:name="Maximum Compression" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
<property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
<property xil_pn:name="Message Filter File" xil_pn:value="filter.filter" xil_pn:valueState="default"/>
<property xil_pn:name="ModelSim Post-Map UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="ModelSim Post-Par UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Insert IPROG CMD in the Bitfile spartan6" xil_pn:value="Enable" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Insert IPROG CMD in the Bitfile virtex7" xil_pn:value="Enable" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Next Configuration Mode spartan6" xil_pn:value="001" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Starting Address for Golden Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Starting Address for Next Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Use New Mode for Next Configuration spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: User-Defined Register for Failsafe Scheme spartan6" xil_pn:value="0x0000" xil_pn:valueState="default"/>
<property xil_pn:name="Multiplier Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
<property xil_pn:name="Mux Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Mux Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
<property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Clock Buffers" xil_pn:value="16" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Critical Paths" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Critical Paths Synthesis" xil_pn:value="0" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Start/End Points" xil_pn:value="0" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Summary Paths" xil_pn:value="10" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Effort" xil_pn:value="Normal" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Effort spartan6" xil_pn:value="Normal" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Effort virtex6" xil_pn:value="Normal" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Strategy (Cover Mode)" xil_pn:value="Area" xil_pn:valueState="default"/>
<property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Bitgen Command Line Options spartan6" xil_pn:value="-bd &quot;/home/tim/Projects/z80/hdmi/mb/Graphics/Release/Graphics.elf&quot; tag microblaze_mcs" xil_pn:valueState="non-default"/>
<property xil_pn:name="Other Bitgen Command Line Options spartan6" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Fit" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="-bm &quot;../ipcore_dir/microblaze_mcs.bmm&quot;" xil_pn:valueState="non-default"/>
<property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Place &amp; Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Precision Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Synplify Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Synplify Project Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other VCOM Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other VLOG Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other VSIM Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Base Name" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Name" xil_pn:value="pwm_top" xil_pn:valueState="non-default"/>
<property xil_pn:name="Output File Name" xil_pn:value="clk_wiz_v3_6" xil_pn:valueState="default"/>
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Overwrite Existing Symbol" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Package" xil_pn:value="tqg144" xil_pn:valueState="default"/>
<property xil_pn:name="Parallel Case" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Pipelining" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
<property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
<property xil_pn:name="Place MultiBoot Settings into Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Place MultiBoot Settings into Bitstream virtex7" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="pwm_top_map.v" xil_pn:valueState="non-default"/>
<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="pwm_top_timesim.v" xil_pn:valueState="non-default"/>
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="pwm_top_synthesis.v" xil_pn:valueState="non-default"/>
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="pwm_top_translate.v" xil_pn:valueState="non-default"/>
<property xil_pn:name="Power Reduction Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="clk_wiz_v3_6_map.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="clk_wiz_v3_6_timesim.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="clk_wiz_v3_6_synthesis.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="clk_wiz_v3_6_translate.v" xil_pn:valueState="default"/>
<property xil_pn:name="Power Down Device if Over Safe Temperature" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Map virtex6" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Precision Optimization Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/>
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Priority Encoder Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Process window" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Project Generator" xil_pn:value="ProjNav" xil_pn:valueState="default"/>
<property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
<property xil_pn:name="Push Tristates across Process/Block Boundaries" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Re-Use Last Bitstream File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
@ -369,110 +264,77 @@
<property xil_pn:name="Register Duplication Map" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Register Ordering spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
<property xil_pn:name="Release Set/Reset (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
<property xil_pn:name="Register Ordering virtex6" xil_pn:value="4" xil_pn:valueState="default"/>
<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Report Clock Frequencies" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Report Critical Paths" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Report Missing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Report Timing Summary" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Report Timing Violations" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
<property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
<property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Resource Sharing Precision" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Resource Sharing Synthesis" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Retiming" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Retry Configuration if CRC Error Occurs spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Revision Select" xil_pn:value="00" xil_pn:valueState="default"/>
<property xil_pn:name="Revision Select Tristate" xil_pn:value="Disable" xil_pn:valueState="default"/>
<property xil_pn:name="Router Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run Retiming" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="SPI 32-bit Addressing" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/main/spi" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.spi" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Set SPI Configuration Bus Width" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Set SPI Configuration Bus Width spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Setup External Master Clock Division spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Shift Register Minimum Size spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
<property xil_pn:name="Shift Register Minimum Size virtex6" xil_pn:value="2" xil_pn:valueState="default"/>
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Show Clock Domain Crossing" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Show Net Fan Out" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Signal window" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Model Target" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Resolution" xil_pn:value="Default (1 ps)" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Modelsim" xil_pn:value="1000ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Slice Packing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Source window" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.spi" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-2" xil_pn:valueState="non-default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Starting Address for Fallback Configuration virtex7" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100)" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100) Map spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Structure window" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Symbolic FSM Compiler" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Sysgen Instantiation Template Target Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Target Board for Hardware Co-Simulation" xil_pn:value="SP601 (JTAG)" xil_pn:valueState="default"/>
<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
<property xil_pn:name="Test Bench Module/Entity Name" xil_pn:value="testbench" xil_pn:valueState="default"/>
<property xil_pn:name="Test Bench Target Language Xps" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Timing Mode Map" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
<property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
<property xil_pn:name="Transform Set/Reset on DFFs to Latches" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Tri-state Buffer Transformation Mode" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
<property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
<property xil_pn:name="Update modelsim.ini File for Xilinx SmartModel Use" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Automatic Do File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Configuration Name" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Do File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Do File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Do File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Do File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Do File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
@ -481,45 +343,35 @@
<property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use DSP Block" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use DSP Block spartan6" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Explicit Declarations Only" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use FSM Explorer Data" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Use Safe FSM" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use SPI Falling Edge" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="User Browsed Strategy Files" xil_pn:value="/opt/Xilinx/14.7/ISE_DS/ISE/data/default.xds" xil_pn:valueState="non-default"/>
<property xil_pn:name="User Access Register Value" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
<property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/>
<property xil_pn:name="VHDL" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
<property xil_pn:name="VHDL Syntax" xil_pn:value="93" xil_pn:valueState="default"/>
<property xil_pn:name="VHDL Syntax Precision" xil_pn:value="VHDL 2002" xil_pn:valueState="default"/>
<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Variables window" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Verilog" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Verilog Standard" xil_pn:value="Verilog 2001" xil_pn:valueState="default"/>
<property xil_pn:name="Wait for DCI Match (Output Events) virtex5" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Wait for DCM and PLL Lock (Output Events) spartan6" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
<property xil_pn:name="Wait for DLL Lock (Output Events)" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
<property xil_pn:name="Wait for PLL Lock (Output Events) virtex6" xil_pn:value="No Wait" xil_pn:valueState="default"/>
<property xil_pn:name="Wakeup Clock spartan6" xil_pn:value="Startup Clock" xil_pn:valueState="default"/>
<property xil_pn:name="Watchdog Timer Mode 7-series" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Watchdog Timer Value 7-series" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
<property xil_pn:name="Watchdog Timer Value spartan6" xil_pn:value="0xFFFF" xil_pn:valueState="default"/>
<property xil_pn:name="Wave window" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Working Directory" xil_pn:value="syn" xil_pn:valueState="non-default"/>
<property xil_pn:name="Write Mapped VHDL Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Write Mapped Verilog Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="default"/>
<property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Write Vendor Constraint File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="XOR Collapsing" xil_pn:value="true" xil_pn:valueState="default"/>
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Module|spi_tb" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="PWM-Demo" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="clk_wiz_v3_6" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
@ -527,14 +379,14 @@
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2012-11-06T11:19:28" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="F04BE7BB4526104AA483BCD2B63930B5" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="UnderProjDir" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="Yes" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2020-02-28T23:02:51" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="ECCA9B4B624941A8B2D32A13ED283052" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties>
<bindings>
<binding xil_pn:location="/main" xil_pn:name="src/constraints.ucf"/>
<binding xil_pn:location="/clk_wiz_v3_6" xil_pn:name="clk_wiz_v3_6.ucf"/>
</bindings>
<libraries/>

0
ipcore_dir/hdmi_clk/clk_wiz_v3_6_readme.txt → cores/clk_wiz_v3_6/clk_wiz_v3_6_readme.txt
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0
ipcore_dir/hdmi_clk/doc/clk_wiz_v3_6_readme.txt → cores/clk_wiz_v3_6/doc/clk_wiz_v3_6_readme.txt
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0
ipcore_dir/hdmi_clk/doc/clk_wiz_v3_6_vinfo.html → cores/clk_wiz_v3_6/doc/clk_wiz_v3_6_vinfo.html
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0
ipcore_dir/hdmi_clk/doc/pg065_clk_wiz.pdf → cores/clk_wiz_v3_6/doc/pg065_clk_wiz.pdf
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4
ipcore_dir/hdmi_clk/example_design/hdmi_clk_exdes.ucf → cores/clk_wiz_v3_6/example_design/clk_wiz_v3_6_exdes.ucf Executable file → Normal file
View File

@ -1,4 +1,4 @@
# file: hdmi_clk_exdes.ucf
# file: clk_wiz_v3_6_exdes.ucf
#
# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
#
@ -51,7 +51,7 @@
# input clocks. You can use these to time your system
#----------------------------------------------------------------
NET "CLK_IN1" TNM_NET = "CLK_IN1";
TIMESPEC "TS_CLK_IN1" = PERIOD "CLK_IN1" 20.000 ns HIGH 50% INPUT_JITTER 200.0ps;
TIMESPEC "TS_CLK_IN1" = PERIOD "CLK_IN1" 20.0 ns HIGH 50% INPUT_JITTER 200.0ps;
# FALSE PATH constraints

91
ipcore_dir/hdmi_clk/example_design/hdmi_clk_exdes.v → cores/clk_wiz_v3_6/example_design/clk_wiz_v3_6_exdes.v Executable file → Normal file
View File

@ -1,4 +1,4 @@
// file: hdmi_clk_exdes.v
// file: clk_wiz_v3_6_exdes.v
//
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
//
@ -56,7 +56,7 @@
`timescale 1ps/1ps
module hdmi_clk_exdes
module clk_wiz_v3_6_exdes
#(
parameter TCQ = 100
)
@ -64,105 +64,86 @@ module hdmi_clk_exdes
input CLK_IN1,
// Reset that only drives logic in example design
input COUNTER_RESET,
output [2:1] CLK_OUT,
output [1:1] CLK_OUT,
// High bits of counters driven by clocks
output [2:1] COUNT
output COUNT
);
// Parameters for the counters
//-------------------------------
// Counter width
localparam C_W = 16;
localparam NUM_C = 2;
genvar count_gen;
// Create reset for the counters
wire reset_int = COUNTER_RESET;
reg [NUM_C:1] rst_sync;
reg [NUM_C:1] rst_sync_int;
reg [NUM_C:1] rst_sync_int1;
reg [NUM_C:1] rst_sync_int2;
reg rst_sync;
reg rst_sync_int;
reg rst_sync_int1;
reg rst_sync_int2;
// Declare the clocks and counters
wire [NUM_C:1] clk_int;
wire [NUM_C:1] clk_n;
wire [NUM_C:1] clk;
reg [C_W-1:0] counter [NUM_C:1];
// Declare the clocks and counter
wire clk_int;
wire clk_n;
wire clk;
reg [C_W-1:0] counter;
// Instantiation of the clocking network
//--------------------------------------
hdmi_clk clknetwork
clk_wiz_v3_6 clknetwork
(// Clock in ports
.CLK_IN1 (CLK_IN1),
// Clock out ports
.CLK_OUT1 (clk_int[1]),
.CLK_OUT2 (clk_int[2]));
.CLK_OUT1 (clk_int));
genvar clk_out_pins;
generate
for (clk_out_pins = 1; clk_out_pins <= NUM_C; clk_out_pins = clk_out_pins + 1)
begin: gen_outclk_oddr
assign clk_n[clk_out_pins] = ~clk[clk_out_pins];
assign clk_n = ~clk;
ODDR2 clkout_oddr
(.Q (CLK_OUT[clk_out_pins]),
.C0 (clk[clk_out_pins]),
.C1 (clk_n[clk_out_pins]),
(.Q (CLK_OUT[1]),
.C0 (clk),
.C1 (clk_n),
.CE (1'b1),
.D0 (1'b1),
.D1 (1'b0),
.R (1'b0),
.S (1'b0));
end
endgenerate
// Connect the output clocks to the design
//-----------------------------------------
assign clk[1] = clk_int[1];
assign clk[2] = clk_int[2];
assign clk = clk_int;
// Reset synchronizer
//-----------------------------------
generate for (count_gen = 1; count_gen <= NUM_C; count_gen = count_gen + 1) begin: counters_1
always @(posedge reset_int or posedge clk[count_gen]) begin
always @(posedge reset_int or posedge clk) begin
if (reset_int) begin
rst_sync[count_gen] <= 1'b1;
rst_sync_int[count_gen]<= 1'b1;
rst_sync_int1[count_gen]<= 1'b1;
rst_sync_int2[count_gen]<= 1'b1;
rst_sync <= 1'b1;
rst_sync_int <= 1'b1;
rst_sync_int1 <= 1'b1;
rst_sync_int2 <= 1'b1;
end
else begin
rst_sync[count_gen] <= 1'b0;
rst_sync_int[count_gen] <= rst_sync[count_gen];
rst_sync_int1[count_gen] <= rst_sync_int[count_gen];
rst_sync_int2[count_gen] <= rst_sync_int1[count_gen];
rst_sync <= 1'b0;
rst_sync_int <= rst_sync;
rst_sync_int1 <= rst_sync_int;
rst_sync_int2 <= rst_sync_int1;
end
end
end
endgenerate
// Output clock sampling
//-----------------------------------
generate for (count_gen = 1; count_gen <= NUM_C; count_gen = count_gen + 1) begin: counters
always @(posedge clk[count_gen] or posedge rst_sync_int2[count_gen]) begin
if (rst_sync_int2[count_gen]) begin
counter[count_gen] <= #TCQ { C_W { 1'b 0 } };
always @(posedge clk or posedge rst_sync_int2) begin
if (rst_sync_int2) begin
counter <= #TCQ { C_W { 1'b 0 } };
end else begin
counter[count_gen] <= #TCQ counter[count_gen] + 1'b 1;
counter <= #TCQ counter + 1'b 1;
end
end
// alias the high bit of each counter to the corresponding
// bit in the output bus
assign COUNT[count_gen] = counter[count_gen][C_W-1];
end
endgenerate
// alias the high bit to the output
assign COUNT = counter[C_W-1];

4
ipcore_dir/hdmi_clk/example_design/hdmi_clk_exdes.xdc → cores/clk_wiz_v3_6/example_design/clk_wiz_v3_6_exdes.xdc Executable file → Normal file
View File

@ -1,4 +1,4 @@
# file: hdmi_clk_exdes.xdc
# file: clk_wiz_v3_6_exdes.xdc
#
# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
#
@ -50,7 +50,7 @@
# Input clock periods. These duplicate the values entered for the
# input clocks. You can use these to time your system
#----------------------------------------------------------------
create_clock -name CLK_IN1 -period 20.000 [get_ports CLK_IN1]
create_clock -name CLK_IN1 -period 20.0 [get_ports CLK_IN1]
set_propagated_clock CLK_IN1
set_input_jitter CLK_IN1 0.2

10
ipcore_dir/hdmi_clk/implement/implement.bat → cores/clk_wiz_v3_6/implement/implement.bat Executable file → Normal file
View File

@ -61,19 +61,19 @@ copy %XILINX%\verilog\src\iSE\unisim_comp.v .\results\
REM Synthesize the Verilog Wrapper Files
echo 'Synthesizing Clocking Wizard design with XST'
xst -ifn xst.scr
move hdmi_clk_exdes.ngc results\
move clk_wiz_v3_6_exdes.ngc results\
REM Copy the constraints files generated by Coregen
echo 'Copying files from constraints directory to results directory'
copy ..\example_design\hdmi_clk_exdes.ucf results\
copy ..\example_design\clk_wiz_v3_6_exdes.ucf results\
cd results
echo 'Running ngdbuild'
ngdbuild -uc hdmi_clk_exdes.ucf hdmi_clk_exdes
ngdbuild -uc clk_wiz_v3_6_exdes.ucf clk_wiz_v3_6_exdes
echo 'Running map'
map -timing -pr b hdmi_clk_exdes -o mapped.ncd
map -timing -pr b clk_wiz_v3_6_exdes -o mapped.ncd
echo 'Running par'
par -w mapped.ncd routed mapped.pcf
@ -85,6 +85,6 @@ echo 'Running design through bitgen'
bitgen -w routed
echo 'Running netgen to create gate level model for the clocking wizard example design'
netgen -ofmt verilog -sim -sdf_anno false -tm hdmi_clk_exdes -w routed.ncd routed.v
netgen -ofmt verilog -sim -sdf_anno false -tm clk_wiz_v3_6_exdes -w routed.ncd routed.v
cd ..

10
ipcore_dir/hdmi_clk/implement/implement.sh → cores/clk_wiz_v3_6/implement/implement.sh Executable file → Normal file
View File

@ -62,19 +62,19 @@ cp $XILINX/verilog/src/iSE/unisim_comp.v ./results/
# Synthesize the Verilog Wrapper Files
echo 'Synthesizing Clocking Wizard design with XST'
xst -ifn xst.scr
mv hdmi_clk_exdes.ngc results/
mv clk_wiz_v3_6_exdes.ngc results/
# Copy the constraints files generated by Coregen
echo 'Copying files from constraints directory to results directory'
cp ../example_design/hdmi_clk_exdes.ucf results/
cp ../example_design/clk_wiz_v3_6_exdes.ucf results/
cd results
echo 'Running ngdbuild'
ngdbuild -uc hdmi_clk_exdes.ucf hdmi_clk_exdes
ngdbuild -uc clk_wiz_v3_6_exdes.ucf clk_wiz_v3_6_exdes
echo 'Running map'
map -timing hdmi_clk_exdes -o mapped.ncd
map -timing clk_wiz_v3_6_exdes -o mapped.ncd
echo 'Running par'
par -w mapped.ncd routed mapped.pcf
@ -86,6 +86,6 @@ echo 'Running design through bitgen'
bitgen -w routed
echo 'Running netgen to create gate level model for the clocking wizard example design'
netgen -ofmt verilog -sim -sdf_anno false -tm hdmi_clk_exdes -w routed.ncd routed.v
netgen -ofmt verilog -sim -sdf_anno false -tm clk_wiz_v3_6_exdes -w routed.ncd routed.v
cd ..

0
ipcore_dir/hdmi_clk/implement/planAhead_ise.bat → cores/clk_wiz_v3_6/implement/planAhead_ise.bat Executable file → Normal file
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0
ipcore_dir/hdmi_clk/implement/planAhead_ise.sh → cores/clk_wiz_v3_6/implement/planAhead_ise.sh Executable file → Normal file
View File

10
ipcore_dir/hdmi_clk/implement/planAhead_ise.tcl → cores/clk_wiz_v3_6/implement/planAhead_ise.tcl Executable file → Normal file
View File

@ -48,8 +48,8 @@
#
set projDir [file dirname [info script]]
set projName hdmi_clk
set topName hdmi_clk_exdes
set projName clk_wiz_v3_6
set topName clk_wiz_v3_6_exdes
set device xc6slx9tqg144-2
create_project $projName $projDir/results/$projName -part $device
@ -58,12 +58,12 @@ set_property design_mode RTL [get_filesets sources_1]
## Source files
#set verilogSources [glob $srcDir/*.v]
import_files -fileset [get_filesets sources_1] -force -norecurse ../../example_design/hdmi_clk_exdes.v
import_files -fileset [get_filesets sources_1] -force -norecurse ../../../hdmi_clk.v
import_files -fileset [get_filesets sources_1] -force -norecurse ../../example_design/clk_wiz_v3_6_exdes.v
import_files -fileset [get_filesets sources_1] -force -norecurse ../../../clk_wiz_v3_6.v
#UCF file
import_files -fileset [get_filesets constrs_1] -force -norecurse ../../example_design/hdmi_clk_exdes.ucf
import_files -fileset [get_filesets constrs_1] -force -norecurse ../../example_design/clk_wiz_v3_6_exdes.ucf
set_property top $topName [get_property srcset [current_run]]

0
ipcore_dir/hdmi_clk/implement/planAhead_rdn.bat → cores/clk_wiz_v3_6/implement/planAhead_rdn.bat Executable file → Normal file
View File

0
ipcore_dir/hdmi_clk/implement/planAhead_rdn.sh → cores/clk_wiz_v3_6/implement/planAhead_rdn.sh Executable file → Normal file
View File

18
ipcore_dir/hdmi_clk/implement/planAhead_rdn.tcl → cores/clk_wiz_v3_6/implement/planAhead_rdn.tcl Executable file → Normal file
View File

@ -48,22 +48,22 @@
#
set device xc6slx9tqg144-2
set projName hdmi_clk
set design hdmi_clk
set projName clk_wiz_v3_6
set design clk_wiz_v3_6
set projDir [file dirname [info script]]
create_project $projName $projDir/results/$projName -part $device -force
set_property design_mode RTL [current_fileset -srcset]
set top_module hdmi_clk_exdes
set_property top hdmi_clk_exdes [get_property srcset [current_run]]
add_files -norecurse {../../../hdmi_clk.v}
add_files -norecurse {../../example_design/hdmi_clk_exdes.v}
import_files -fileset [get_filesets constrs_1 ] -force -norecurse {../../example_design/hdmi_clk_exdes.xdc}
set top_module clk_wiz_v3_6_exdes
set_property top clk_wiz_v3_6_exdes [get_property srcset [current_run]]
add_files -norecurse {../../../clk_wiz_v3_6.v}
add_files -norecurse {../../example_design/clk_wiz_v3_6_exdes.v}
import_files -fileset [get_filesets constrs_1 ] -force -norecurse {../../example_design/clk_wiz_v3_6_exdes.xdc}
synth_design
opt_design
place_design
route_design
write_sdf -rename_top_module hdmi_clk_exdes -file routed.sdf
write_verilog -nolib -mode timesim -sdf_anno false -rename_top_module hdmi_clk_exdes -file routed.v
write_sdf -rename_top_module clk_wiz_v3_6_exdes -file routed.sdf
write_verilog -nolib -mode timesim -sdf_anno false -rename_top_module clk_wiz_v3_6_exdes -file routed.v
report_timing -nworst 30 -path_type full -file routed.twr
report_drc -file report.drc
write_bitstream -bitgen_options {-g UnconstrainedPins:Allow} -file routed.bit

2
cores/clk_wiz_v3_6/implement/xst.prj Normal file
View File

@ -0,0 +1,2 @@
verilog work ../../clk_wiz_v3_6.v
verilog work ../example_design/clk_wiz_v3_6_exdes.v

4
ipcore_dir/hdmi_clk/implement/xst.scr → cores/clk_wiz_v3_6/implement/xst.scr Executable file → Normal file
View File

@ -1,9 +1,9 @@
run
-ifmt MIXED
-top hdmi_clk_exdes
-top clk_wiz_v3_6_exdes
-p xc6slx9-tqg144-2
-ifn xst.prj
-ofn hdmi_clk_exdes
-ofn clk_wiz_v3_6_exdes
-keep_hierarchy soft
-equivalent_register_removal no
-max_fanout 65535

16
ipcore_dir/hdmi_clk/simulation/hdmi_clk_tb.v → cores/clk_wiz_v3_6/simulation/clk_wiz_v3_6_tb.v Executable file → Normal file
View File

@ -1,4 +1,4 @@
// file: hdmi_clk_tb.v
// file: clk_wiz_v3_6_tb.v
//
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
//
@ -57,9 +57,9 @@
`timescale 1ps/1ps
`define wait_lock @(posedge dut.clknetwork.pll_base_inst.LOCKED)
`define wait_lock @(posedge dut.clknetwork.dcm_sp_inst.LOCKED)
module hdmi_clk_tb ();
module clk_wiz_v3_6_tb ();
// Clock to Q delay of 100ps
localparam TCQ = 100;
@ -71,17 +71,17 @@ module hdmi_clk_tb ();
// how many cycles to run
localparam COUNT_PHASE = 1024;
// we'll be using the period in many locations
localparam time PER1 = 20.000*ONE_NS;
localparam time PER1 = 20.0*ONE_NS;
localparam time PER1_1 = PER1/2;
localparam time PER1_2 = PER1 - PER1/2;
// Declare the input clock signals
reg CLK_IN1 = 1;
// The high bits of the sampling counters
wire [2:1] COUNT;
// The high bit of the sampling counter
wire COUNT;
reg COUNTER_RESET = 0;
wire [2:1] CLK_OUT;
wire [1:1] CLK_OUT;
//Freq Check using the M & D values setting and actual Frequency generated
@ -116,7 +116,7 @@ wire [2:1] CLK_OUT;
// Instantiation of the example design containing the clock
// network and sampling counters
//---------------------------------------------------------
hdmi_clk_exdes
clk_wiz_v3_6_exdes
#(
.TCQ (TCQ)
) dut

2
ipcore_dir/hdmi_clk/simulation/functional/simcmds.tcl → cores/clk_wiz_v3_6/simulation/functional/simcmds.tcl Executable file → Normal file
View File

@ -2,7 +2,7 @@
# create the simulation script
vcd dumpfile isim.vcd
vcd dumpvars -m /hdmi_clk_tb -l 0
vcd dumpvars -m /clk_wiz_v3_6_tb -l 0
wave add /
run 50000ns
quit

10
ipcore_dir/hdmi_clk/simulation/functional/simulate_isim.bat → cores/clk_wiz_v3_6/simulation/functional/simulate_isim.bat Executable file → Normal file
View File

@ -48,12 +48,12 @@ REM PART OF THIS FILE AT ALL TIMES.
REM
vlogcomp -work work %XILINX%\verilog\src\glbl.v
vlogcomp -work work ..\..\..\hdmi_clk.v
vlogcomp -work work ..\..\example_design\hdmi_clk_exdes.v
vlogcomp -work work ..\hdmi_clk_tb.v
vlogcomp -work work ..\..\..\clk_wiz_v3_6.v
vlogcomp -work work ..\..\example_design\clk_wiz_v3_6_exdes.v
vlogcomp -work work ..\clk_wiz_v3_6_tb.v
REM compile the project
fuse work.hdmi_clk_tb work.glbl -L unisims_ver -o hdmi_clk_isim.exe
fuse work.clk_wiz_v3_6_tb work.glbl -L unisims_ver -o clk_wiz_v3_6_isim.exe
REM run the simulation script
.\hdmi_clk_isim.exe -gui -tclbatch simcmds.tcl
.\clk_wiz_v3_6_isim.exe -gui -tclbatch simcmds.tcl

12
ipcore_dir/hdmi_clk/simulation/functional/simulate_isim.sh → cores/clk_wiz_v3_6/simulation/functional/simulate_isim.sh Executable file → Normal file
View File

@ -47,15 +47,15 @@
# PART OF THIS FILE AT ALL TIMES.
#
# lin64
# nt
# create the project
vlogcomp -work work ${XILINX}/verilog/src/glbl.v
vlogcomp -work work ../../../hdmi_clk.v
vlogcomp -work work ../../example_design/hdmi_clk_exdes.v
vlogcomp -work work ../hdmi_clk_tb.v
vlogcomp -work work ../../../clk_wiz_v3_6.v
vlogcomp -work work ../../example_design/clk_wiz_v3_6_exdes.v
vlogcomp -work work ../clk_wiz_v3_6_tb.v
# compile the project
fuse work.hdmi_clk_tb work.glbl -L unisims_ver -o hdmi_clk_isim.exe
fuse work.clk_wiz_v3_6_tb work.glbl -L unisims_ver -o clk_wiz_v3_6_isim.exe
# run the simulation script
./hdmi_clk_isim.exe -gui -tclbatch simcmds.tcl
./clk_wiz_v3_6_isim.exe -gui -tclbatch simcmds.tcl

8
ipcore_dir/hdmi_clk/simulation/functional/simulate_mti.bat → cores/clk_wiz_v3_6/simulation/functional/simulate_mti.bat Executable file → Normal file
View File

@ -52,10 +52,10 @@ vlib work
REM compile all of the files
vlog -work work %XILINX%\verilog\src\glbl.v
vlog -work work ..\..\..\hdmi_clk.v
vlog -work work ..\..\example_design\hdmi_clk_exdes.v
vlog -work work ..\hdmi_clk_tb.v
vlog -work work ..\..\..\clk_wiz_v3_6.v
vlog -work work ..\..\example_design\clk_wiz_v3_6_exdes.v
vlog -work work ..\clk_wiz_v3_6_tb.v
REM run the simulation
vsim -c -t ps -voptargs="+acc" -L secureip -L unisims_ver work.hdmi_clk_tb work.glbl
vsim -c -t ps -voptargs="+acc" -L secureip -L unisims_ver work.clk_wiz_v3_6_tb work.glbl

10
ipcore_dir/hdmi_clk/simulation/functional/simulate_mti.do → cores/clk_wiz_v3_6/simulation/functional/simulate_mti.do Executable file → Normal file
View File

@ -53,13 +53,13 @@ vlib work
# compile all of the files
vlog -work work $env(XILINX)/verilog/src/glbl.v
vlog -work work ../../../hdmi_clk.v
vlog -work work ../../example_design/hdmi_clk_exdes.v
vlog -work work ../hdmi_clk_tb.v
vlog -work work ../../../clk_wiz_v3_6.v
vlog -work work ../../example_design/clk_wiz_v3_6_exdes.v
vlog -work work ../clk_wiz_v3_6_tb.v
# run the simulation
vsim -t ps -voptargs="+acc" -L unisims_ver work.hdmi_clk_tb work.glbl
vsim -t ps -voptargs="+acc" -L unisims_ver work.clk_wiz_v3_6_tb work.glbl
do wave.do
log hdmi_clk_tb/dut/counter
log clk_wiz_v3_6_tb/dut/counter
log -r /*
run 50000ns

8
ipcore_dir/hdmi_clk/simulation/functional/simulate_mti.sh → cores/clk_wiz_v3_6/simulation/functional/simulate_mti.sh Executable file → Normal file
View File

@ -53,9 +53,9 @@ vlib work
# compile all of the files
vlog -work work $XILINX/verilog/src/glbl.v
vlog -work work ../../../hdmi_clk.v
vlog -work work ../../example_design/hdmi_clk_exdes.v
vlog -work work ../hdmi_clk_tb.v
vlog -work work ../../../clk_wiz_v3_6.v
vlog -work work ../../example_design/clk_wiz_v3_6_exdes.v
vlog -work work ../clk_wiz_v3_6_tb.v
# run the simulation
vsim -c -t ps -voptargs="+acc" -L secureip -L unisims_ver work.hdmi_clk_tb work.glbl
vsim -c -t ps -voptargs="+acc" -L secureip -L unisims_ver work.clk_wiz_v3_6_tb work.glbl

10
ipcore_dir/hdmi_clk/simulation/functional/simulate_ncsim.sh → cores/clk_wiz_v3_6/simulation/functional/simulate_ncsim.sh Executable file → Normal file
View File

@ -53,10 +53,10 @@ mkdir work
# compile all of the files
ncvlog -work work ${XILINX}/verilog/src/glbl.v
ncvlog -work work ../../../hdmi_clk.v
ncvlog -work work ../../example_design/hdmi_clk_exdes.v
ncvlog -work work ../hdmi_clk_tb.v
ncvlog -work work ../../../clk_wiz_v3_6.v
ncvlog -work work ../../example_design/clk_wiz_v3_6_exdes.v
ncvlog -work work ../clk_wiz_v3_6_tb.v
# elaborate and run the simulation
ncelab -work work -access +wc work.hdmi_clk_tb work.glbl
ncsim -input "@database -open -shm nc; probe -create -database nc -all -depth all; probe dut.counter; run 50000ns; exit" work.hdmi_clk_tb
ncelab -work work -access +wc work.clk_wiz_v3_6_tb work.glbl
ncsim -input "@database -open -shm nc; probe -create -database nc -all -depth all; probe dut.counter; run 50000ns; exit" work.clk_wiz_v3_6_tb

8
ipcore_dir/hdmi_clk/simulation/functional/simulate_vcs.sh → cores/clk_wiz_v3_6/simulation/functional/simulate_vcs.sh Executable file → Normal file
View File

@ -58,12 +58,12 @@ rm -rf simv* csrc DVEfiles AN.DB
# [63:0] from time
vlogan -sverilog \
${XILINX}/verilog/src/glbl.v \
../../../hdmi_clk.v \
../../example_design/hdmi_clk_exdes.v \
../hdmi_clk_tb.v
../../../clk_wiz_v3_6.v \
../../example_design/clk_wiz_v3_6_exdes.v \
../clk_wiz_v3_6_tb.v
# prepare the simulation
vcs +vcs+lic+wait -debug hdmi_clk_tb glbl
vcs +vcs+lic+wait -debug clk_wiz_v3_6_tb glbl
# run the simulation
./simv -ucli -i ucli_commands.key

5
cores/clk_wiz_v3_6/simulation/functional/ucli_commands.key Normal file
View File

@ -0,0 +1,5 @@
call {$vcdpluson}
call {$vcdplusmemon(clk_wiz_v3_6_tb.dut.counter)}
run
call {$vcdplusclose}
quit

15
cores/clk_wiz_v3_6/simulation/functional/vcs_session.tcl Normal file
View File

@ -0,0 +1,15 @@
gui_open_window Wave
gui_sg_create clk_wiz_v3_6_group
gui_list_add_group -id Wave.1 {clk_wiz_v3_6_group}
gui_sg_addsignal -group clk_wiz_v3_6_group {clk_wiz_v3_6_tb.test_phase}
gui_set_radix -radix {ascii} -signals {clk_wiz_v3_6_tb.test_phase}
gui_sg_addsignal -group clk_wiz_v3_6_group {{Input_clocks}} -divider
gui_sg_addsignal -group clk_wiz_v3_6_group {clk_wiz_v3_6_tb.CLK_IN1}
gui_sg_addsignal -group clk_wiz_v3_6_group {{Output_clocks}} -divider
gui_sg_addsignal -group clk_wiz_v3_6_group {clk_wiz_v3_6_tb.dut.clk}
gui_list_expand -id Wave.1 clk_wiz_v3_6_tb.dut.clk
gui_sg_addsignal -group clk_wiz_v3_6_group {{Counters}} -divider
gui_sg_addsignal -group clk_wiz_v3_6_group {clk_wiz_v3_6_tb.COUNT}
gui_sg_addsignal -group clk_wiz_v3_6_group {clk_wiz_v3_6_tb.dut.counter}
gui_list_expand -id Wave.1 clk_wiz_v3_6_tb.dut.counter
gui_zoom -window Wave.1 -full

10
ipcore_dir/hdmi_clk/simulation/functional/wave.do → cores/clk_wiz_v3_6/simulation/functional/wave.do Executable file → Normal file
View File

@ -47,11 +47,11 @@
# PART OF THIS FILE AT ALL TIMES.
#
add wave -noupdate -format Literal -radix ascii /hdmi_clk_tb/test_phase
add wave -noupdate -format Literal -radix ascii /clk_wiz_v3_6_tb/test_phase
add wave -noupdate -divider {Input clocks}
add wave -noupdate -format Logic /hdmi_clk_tb/CLK_IN1
add wave -noupdate -format Logic /clk_wiz_v3_6_tb/CLK_IN1
add wave -noupdate -divider {Output clocks}
add wave -noupdate -format Literal -expand /hdmi_clk_tb/dut/clk
add wave -noupdate -format Logic /clk_wiz_v3_6_tb/dut/clk
add wave -noupdate -divider Counters
add wave -noupdate -format Literal -radix hexadecimal /hdmi_clk_tb/COUNT
add wave -noupdate -format Literal -radix hexadecimal -expand /hdmi_clk_tb/dut/counter
add wave -noupdate -format Literal -radix hexadecimal /clk_wiz_v3_6_tb/COUNT
add wave -noupdate -format Literal -radix hexadecimal /clk_wiz_v3_6_tb/dut/counter

18
ipcore_dir/hdmi_clk/simulation/functional/wave.sv → cores/clk_wiz_v3_6/simulation/functional/wave.sv Executable file → Normal file
View File

@ -54,8 +54,8 @@ if {[catch {window new WatchList -name "Design Browser 1" -geometry 1054x819+536
window target "Design Browser 1" on
browser using {Design Browser 1}
browser set \
-scope nc::hdmi_clk_tb
browser yview see nc::hdmi_clk_tb
-scope nc::clk_wiz_v3_6_tb
browser yview see nc::clk_wiz_v3_6_tb
browser timecontrol set -lock 0
if {[catch {window new WaveWindow -name "Waveform 1" -geometry 1010x600+0+541}] != ""} {
@ -81,7 +81,7 @@ catch {group new -name {Output clocks} -overlay 0}
catch {group new -name {Status/control} -overlay 0}
catch {group new -name {Counters} -overlay 0}
set id [waveform add -signals [list {nc::hdmi_clk_tb.CLK_IN1}]]
set id [waveform add -signals [list {nc::clk_wiz_v3_6_tb.CLK_IN1}]]
group using {Output clocks}
group set -overlay 0
@ -89,20 +89,20 @@ group set -comment {}
group clear 0 end
group insert \
{hdmi_clk_tb.dut.clk[1]} \
{hdmi_clk_tb.dut.clk[2]}
{clk_wiz_v3_6_tb.dut.clk} \
group using {Counters}
group set -overlay 0
group set -comment {}
group clear 0 end
group insert \
{hdmi_clk_tb.dut.counter[1]} \
{hdmi_clk_tb.dut.counter[2]}
{clk_wiz_v3_6_tb.dut.counter} \
set id [waveform add -signals [list {nc::hdmi_clk_tb.COUNT} ]]
set id [waveform add -signals [list {nc::hdmi_clk_tb.test_phase} ]]
set id [waveform add -signals [list {nc::clk_wiz_v3_6_tb.COUNT} ]]
set id [waveform add -signals [list {nc::clk_wiz_v3_6_tb.test_phase} ]]
waveform format $id -radix %a
set groupId [waveform add -groups {{Input clocks}}]

14
ipcore_dir/hdmi_clk/simulation/timing/hdmi_clk_tb.v → cores/clk_wiz_v3_6/simulation/timing/clk_wiz_v3_6_tb.v Executable file → Normal file
View File

@ -1,4 +1,4 @@
// file: hdmi_clk_tb.v
// file: clk_wiz_v3_6_tb.v
//
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
//
@ -58,7 +58,7 @@
`timescale 1ps/1ps
module hdmi_clk_tb ();
module clk_wiz_v3_6_tb ();
// Clock to Q delay of 100ps
localparam TCQ = 100;
@ -70,17 +70,17 @@ module hdmi_clk_tb ();
// how many cycles to run
localparam COUNT_PHASE = 1024;
// we'll be using the period in many locations
localparam time PER1 = 20.000*ONE_NS;
localparam time PER1 = 20.0*ONE_NS;
localparam time PER1_1 = PER1/2;
localparam time PER1_2 = PER1 - PER1/2;
// Declare the input clock signals
reg CLK_IN1 = 1;
// The high bits of the sampling counters
wire [2:1] COUNT;
// The high bit of the sampling counter
wire COUNT;
reg COUNTER_RESET = 0;
wire [2:1] CLK_OUT;
wire [1:1] CLK_OUT;
//Freq Check using the M & D values setting and actual Frequency generated
reg [13:0] timeout_counter = 14'b00000000000000;
@ -120,7 +120,7 @@ wire [2:1] CLK_OUT;
// Instantiation of the example design containing the clock
// network and sampling counters
//---------------------------------------------------------
hdmi_clk_exdes
clk_wiz_v3_6_exdes
dut
(// Clock in ports
.CLK_IN1 (CLK_IN1),

2
ipcore_dir/hdmi_clk/simulation/timing/sdf_cmd_file → cores/clk_wiz_v3_6/simulation/timing/sdf_cmd_file Executable file → Normal file
View File

@ -1,2 +1,2 @@
COMPILED_SDF_FILE = "../../implement/results/routed.sdf.X",
SCOPE = hdmi_clk_tb.dut;
SCOPE = clk_wiz_v3_6_tb.dut;

2
ipcore_dir/hdmi_clk/simulation/timing/simcmds.tcl → cores/clk_wiz_v3_6/simulation/timing/simcmds.tcl Executable file → Normal file
View File

@ -2,7 +2,7 @@
# create the simulation script
vcd dumpfile isim.vcd
vcd dumpvars -m /hdmi_clk_tb -l 0
vcd dumpvars -m /clk_wiz_v3_6_tb -l 0
wave add /
run 50000ns
quit

8
ipcore_dir/hdmi_clk/simulation/timing/simulate_isim.sh → cores/clk_wiz_v3_6/simulation/timing/simulate_isim.sh Executable file → Normal file
View File

@ -50,13 +50,13 @@
# create the project
vlogcomp -work work ${XILINX}/verilog/src/glbl.v
vlogcomp -work work ../../implement/results/routed.v
vlogcomp -work work hdmi_clk_tb.v
vlogcomp -work work clk_wiz_v3_6_tb.v
# compile the project
fuse work.hdmi_clk_tb work.glbl -L secureip -L simprims_ver -o hdmi_clk_isim.exe
fuse work.clk_wiz_v3_6_tb work.glbl -L secureip -L simprims_ver -o clk_wiz_v3_6_isim.exe
# run the simulation script
./hdmi_clk_isim.exe -tclbatch simcmds.tcl -sdfmax /hdmi_clk_tb/dut=../../implement/results/routed.sdf
./clk_wiz_v3_6_isim.exe -tclbatch simcmds.tcl -sdfmax /clk_wiz_v3_6_tb/dut=../../implement/results/routed.sdf
# run the simulation script
#./hdmi_clk_isim.exe -gui -tclbatch simcmds.tcl
#./clk_wiz_v3_6_isim.exe -gui -tclbatch simcmds.tcl

4
ipcore_dir/hdmi_clk/simulation/timing/simulate_mti.bat → cores/clk_wiz_v3_6/simulation/timing/simulate_mti.bat Executable file → Normal file
View File

@ -53,7 +53,7 @@ vlib work
REM compile all of the files
vlog -work work %XILINX%\verilog\src\glbl.v
vlog -work work ..\..\implement\results\routed.v
vlog -work work hdmi_clk_tb.v
vlog -work work clk_wiz_v3_6_tb.v
REM run the simulation
vsim -c -t ps +transport_int_delays -voptargs="+acc" -L secureip -L simprims_ver -sdfmax hdmi_clk_tb\dut=..\..\implement\results\routed.sdf +no_notifier work.hdmi_clk_tb work.glbl
vsim -c -t ps +transport_int_delays -voptargs="+acc" -L secureip -L simprims_ver -sdfmax clk_wiz_v3_6_tb\dut=..\..\implement\results\routed.sdf +no_notifier work.clk_wiz_v3_6_tb work.glbl

4
ipcore_dir/hdmi_clk/simulation/timing/simulate_mti.do → cores/clk_wiz_v3_6/simulation/timing/simulate_mti.do Executable file → Normal file
View File

@ -54,10 +54,10 @@ vlib work
# compile all of the files
vlog -work work $env(XILINX)/verilog/src/glbl.v
vlog -work work ../../implement/results/routed.v
vlog -work work hdmi_clk_tb.v
vlog -work work clk_wiz_v3_6_tb.v
# run the simulation
vsim -t ps +transport_int_delays -voptargs="+acc" -L secureip -L simprims_ver -sdfmax hdmi_clk_tb/dut=../../implement/results/routed.sdf +no_notifier work.hdmi_clk_tb work.glbl
vsim -t ps +transport_int_delays -voptargs="+acc" -L secureip -L simprims_ver -sdfmax clk_wiz_v3_6_tb/dut=../../implement/results/routed.sdf +no_notifier work.clk_wiz_v3_6_tb work.glbl
#do wave.do
#log -r /*
run 50000ns

4
ipcore_dir/hdmi_clk/simulation/timing/simulate_mti.sh → cores/clk_wiz_v3_6/simulation/timing/simulate_mti.sh Executable file → Normal file
View File

@ -55,7 +55,7 @@ vlib work
# compile all of the files
vlog -work work $XILINX/verilog/src/glbl.v
vlog -work work ../../implement/results/routed.v
vlog -work work hdmi_clk_tb.v
vlog -work work clk_wiz_v3_6_tb.v
# run the simulation
vsim -c -t ps +transport_int_delays -voptargs="+acc" -L secureip -L simprims_ver -sdfmax hdmi_clk_tb/dut=../../implement/results/routed.sdf +no_notifier work.hdmi_clk_tb work.glbl
vsim -c -t ps +transport_int_delays -voptargs="+acc" -L secureip -L simprims_ver -sdfmax clk_wiz_v3_6_tb/dut=../../implement/results/routed.sdf +no_notifier work.clk_wiz_v3_6_tb work.glbl

6
ipcore_dir/hdmi_clk/simulation/timing/simulate_ncsim.sh → cores/clk_wiz_v3_6/simulation/timing/simulate_ncsim.sh Executable file → Normal file
View File

@ -54,11 +54,11 @@ mkdir work
# compile all of the files
ncvlog -work work ${XILINX}/verilog/src/glbl.v
ncvlog -work work ../../implement/results/routed.v
ncvlog -work work hdmi_clk_tb.v
ncvlog -work work clk_wiz_v3_6_tb.v
# elaborate and run the simulation
ncsdfc ../../implement/results/routed.sdf
ncelab -work work -access +wc -pulse_r 10 -nonotifier work.hdmi_clk_tb work.glbl -sdf_cmd_file sdf_cmd_file
ncsim -input "@database -open -shm nc; probe -create -database nc -all -depth all; run 50000ns; exit" work.hdmi_clk_tb
ncelab -work work -access +wc -pulse_r 10 -nonotifier work.clk_wiz_v3_6_tb work.glbl -sdf_cmd_file sdf_cmd_file
ncsim -input "@database -open -shm nc; probe -create -database nc -all -depth all; run 50000ns; exit" work.clk_wiz_v3_6_tb

6
ipcore_dir/hdmi_clk/simulation/timing/simulate_vcs.sh → cores/clk_wiz_v3_6/simulation/timing/simulate_vcs.sh Executable file → Normal file
View File

@ -57,13 +57,13 @@ rm -rf simv* csrc DVEfiles AN.DB
# localparam for the periods in the testbench file to
# [63:0] from time
vlogan -sverilog \
hdmi_clk_tb.v \
clk_wiz_v3_6_tb.v \
../../implement/results/routed.v
# prepare the simulation
vcs -sdf max:hdmi_clk_exdes:../../implement/results/routed.sdf +v2k -y $XILINX/verilog/src/simprims \
+libext+.v -debug hdmi_clk_tb.v ../../implement/results/routed.v
vcs -sdf max:clk_wiz_v3_6_exdes:../../implement/results/routed.sdf +v2k -y $XILINX/verilog/src/simprims \
+libext+.v -debug clk_wiz_v3_6_tb.v ../../implement/results/routed.v
# run the simulation
./simv -ucli -i ucli_commands.key

0
ipcore_dir/hdmi_clk/simulation/timing/ucli_commands.key → cores/clk_wiz_v3_6/simulation/timing/ucli_commands.key Executable file → Normal file
View File

0
ipcore_dir/hdmi_clk/simulation/timing/vcs_session.tcl → cores/clk_wiz_v3_6/simulation/timing/vcs_session.tcl Executable file → Normal file
View File

4
ipcore_dir/hdmi_clk/simulation/timing/wave.do → cores/clk_wiz_v3_6/simulation/timing/wave.do Executable file → Normal file
View File

@ -49,8 +49,8 @@
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate /hdmi_clk_tb/CLK_IN1
add wave -noupdate /hdmi_clk_tb/COUNT
add wave -noupdate /clk_wiz_v3_6_tb/CLK_IN1
add wave -noupdate /clk_wiz_v3_6_tb/COUNT
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {3223025 ps} 0}
configure wave -namecolwidth 238

53
cores/clk_wiz_v3_6_flist.txt Normal file
View File

@ -0,0 +1,53 @@
# Output products list for <clk_wiz_v3_6>
clk_wiz_v3_6.asy
clk_wiz_v3_6.gise
clk_wiz_v3_6.ucf
clk_wiz_v3_6.v
clk_wiz_v3_6.veo
clk_wiz_v3_6.xco
clk_wiz_v3_6.xdc
clk_wiz_v3_6.xise
clk_wiz_v3_6\clk_wiz_v3_6_readme.txt
clk_wiz_v3_6\doc\clk_wiz_v3_6_readme.txt
clk_wiz_v3_6\doc\clk_wiz_v3_6_vinfo.html
clk_wiz_v3_6\doc\pg065_clk_wiz.pdf
clk_wiz_v3_6\example_design\clk_wiz_v3_6_exdes.ucf
clk_wiz_v3_6\example_design\clk_wiz_v3_6_exdes.v
clk_wiz_v3_6\example_design\clk_wiz_v3_6_exdes.xdc
clk_wiz_v3_6\implement\implement.bat
clk_wiz_v3_6\implement\implement.sh
clk_wiz_v3_6\implement\planAhead_ise.bat
clk_wiz_v3_6\implement\planAhead_ise.sh
clk_wiz_v3_6\implement\planAhead_ise.tcl
clk_wiz_v3_6\implement\planAhead_rdn.bat
clk_wiz_v3_6\implement\planAhead_rdn.sh
clk_wiz_v3_6\implement\planAhead_rdn.tcl
clk_wiz_v3_6\implement\xst.prj
clk_wiz_v3_6\implement\xst.scr
clk_wiz_v3_6\simulation\clk_wiz_v3_6_tb.v
clk_wiz_v3_6\simulation\functional\simcmds.tcl
clk_wiz_v3_6\simulation\functional\simulate_isim.bat
clk_wiz_v3_6\simulation\functional\simulate_isim.sh
clk_wiz_v3_6\simulation\functional\simulate_mti.bat
clk_wiz_v3_6\simulation\functional\simulate_mti.do
clk_wiz_v3_6\simulation\functional\simulate_mti.sh
clk_wiz_v3_6\simulation\functional\simulate_ncsim.sh
clk_wiz_v3_6\simulation\functional\simulate_vcs.sh
clk_wiz_v3_6\simulation\functional\ucli_commands.key
clk_wiz_v3_6\simulation\functional\vcs_session.tcl
clk_wiz_v3_6\simulation\functional\wave.do
clk_wiz_v3_6\simulation\functional\wave.sv
clk_wiz_v3_6\simulation\timing\clk_wiz_v3_6_tb.v
clk_wiz_v3_6\simulation\timing\sdf_cmd_file
clk_wiz_v3_6\simulation\timing\simcmds.tcl
clk_wiz_v3_6\simulation\timing\simulate_isim.sh
clk_wiz_v3_6\simulation\timing\simulate_mti.bat
clk_wiz_v3_6\simulation\timing\simulate_mti.do
clk_wiz_v3_6\simulation\timing\simulate_mti.sh
clk_wiz_v3_6\simulation\timing\simulate_ncsim.sh
clk_wiz_v3_6\simulation\timing\simulate_vcs.sh
clk_wiz_v3_6\simulation\timing\ucli_commands.key
clk_wiz_v3_6\simulation\timing\vcs_session.tcl
clk_wiz_v3_6\simulation\timing\wave.do
clk_wiz_v3_6_flist.txt
clk_wiz_v3_6_xmdf.tcl

62
ipcore_dir/hdmi_clk_xmdf.tcl → cores/clk_wiz_v3_6_xmdf.tcl Executable file → Normal file
View File

@ -1,29 +1,29 @@
# The package naming convention is <core_name>_xmdf
package provide hdmi_clk_xmdf 1.0
package provide clk_wiz_v3_6_xmdf 1.0
# This includes some utilities that support common XMDF operations
package require utilities_xmdf
# Define a namespace for this package. The name of the name space
# is <core_name>_xmdf
namespace eval ::hdmi_clk_xmdf {
namespace eval ::clk_wiz_v3_6_xmdf {
# Use this to define any statics
}
# Function called by client to rebuild the params and port arrays
# Optional when the use context does not require the param or ports
# arrays to be available.
proc ::hdmi_clk_xmdf::xmdfInit { instance } {
proc ::clk_wiz_v3_6_xmdf::xmdfInit { instance } {
# Variable containg name of library into which module is compiled
# Recommendation: <module_name>
# Required
utilities_xmdf::xmdfSetData $instance Module Attributes Name hdmi_clk
utilities_xmdf::xmdfSetData $instance Module Attributes Name clk_wiz_v3_6
}
# ::hdmi_clk_xmdf::xmdfInit
# ::clk_wiz_v3_6_xmdf::xmdfInit
# Function called by client to fill in all the xmdf* data variables
# based on the current settings of the parameters
proc ::hdmi_clk_xmdf::xmdfApplyParams { instance } {
proc ::clk_wiz_v3_6_xmdf::xmdfApplyParams { instance } {
set fcount 0
# Array containing libraries that are assumed to exist
@ -36,103 +36,103 @@ utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library
utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hdmi_clk/clk_wiz_readme.txt
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clk_wiz_v3_6/clk_wiz_readme.txt
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hdmi_clk/doc/clk_wiz_ds709.pdf
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clk_wiz_v3_6/doc/clk_wiz_ds709.pdf
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hdmi_clk/doc/clk_wiz_gsg521.pdf
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clk_wiz_v3_6/doc/clk_wiz_gsg521.pdf
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hdmi_clk/implement/implement.bat
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clk_wiz_v3_6/implement/implement.bat
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hdmi_clk/implement/implement.sh
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clk_wiz_v3_6/implement/implement.sh
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hdmi_clk/implement/xst.prj
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clk_wiz_v3_6/implement/xst.prj
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hdmi_clk/implement/xst.scr
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clk_wiz_v3_6/implement/xst.scr
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hdmi_clk/simulation/hdmi_clk_tb.v
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clk_wiz_v3_6/simulation/clk_wiz_v3_6_tb.v
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hdmi_clk/simulation/functional/simcmds.tcl
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clk_wiz_v3_6/simulation/functional/simcmds.tcl
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hdmi_clk/simulation/functional/simulate_isim.sh
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clk_wiz_v3_6/simulation/functional/simulate_isim.sh
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hdmi_clk/simulation/functional/simulate_mti.do
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clk_wiz_v3_6/simulation/functional/simulate_mti.do
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hdmi_clk/simulation/functional/simulate_ncsim.sh
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clk_wiz_v3_6/simulation/functional/simulate_ncsim.sh
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hdmi_clk/simulation/functional/simulate_vcs.sh
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clk_wiz_v3_6/simulation/functional/simulate_vcs.sh
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hdmi_clk/simulation/functional/ucli_commands.key
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clk_wiz_v3_6/simulation/functional/ucli_commands.key
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hdmi_clk/simulation/functional/vcs_session.tcl
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clk_wiz_v3_6/simulation/functional/vcs_session.tcl
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hdmi_clk/simulation/functional/wave.do
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clk_wiz_v3_6/simulation/functional/wave.do
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hdmi_clk/simulation/functional/wave.sv
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clk_wiz_v3_6/simulation/functional/wave.sv
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hdmi_clk.asy
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clk_wiz_v3_6.asy
utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hdmi_clk.ejp
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clk_wiz_v3_6.ejp
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hdmi_clk.ucf
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clk_wiz_v3_6.ucf
utilities_xmdf::xmdfSetData $instance FileSet $fcount type ucf
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hdmi_clk.v
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clk_wiz_v3_6.v
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hdmi_clk.veo
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clk_wiz_v3_6.veo
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hdmi_clk.xco
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clk_wiz_v3_6.xco
utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hdmi_clk_xmdf.tcl
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clk_wiz_v3_6_xmdf.tcl
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module hdmi_clk
utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module clk_wiz_v3_6
incr fcount
}

1339
cores/coregen.cgc Normal file
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File diff suppressed because it is too large Load Diff

22
cores/coregen.cgp Normal file
View File

@ -0,0 +1,22 @@
# Date: Fri Feb 28 22:01:30 2020
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = Verilog
SET device = xc6slx9
SET devicefamily = spartan6
SET flowvendor = Other
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = tqg144
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -2
SET verilogsim = true
SET vhdlsim = false
SET workingdirectory = "C:\Program Files\Alchitry\Alchitry Labs\"
# CRC: 38e944ea

0
ipcore_dir/.gitignore vendored
View File

426
ipcore_dir/coregen.cgc
View File

@ -1,426 +0,0 @@
<?xml version="1.0" encoding="UTF-8"?>
<spirit:design xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:xilinx="http://www.xilinx.com" >
<spirit:vendor>xilinx.com</spirit:vendor>
<spirit:library>project</spirit:library>
<spirit:name>coregen</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:componentInstances>
<spirit:componentInstance>
<spirit:instanceName>hdmi_clk</spirit:instanceName>
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="clk_wiz" spirit:version="3.6" />
<spirit:configurableElementValues>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.COMPONENT_NAME">hdmi_clk</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_FREQ_SYNTH">true</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_PHASE_ALIGNMENT">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_MIN_POWER">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_DYN_PHASE_SHIFT">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_DYN_RECONFIG">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.JITTER_SEL">No_Jitter</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_SPREAD_SPECTRUM">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_SPREAD_SPECTRUM_1">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_IN_FREQ">50</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IN_FREQ_UNITS">Units_MHz</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IN_JITTER_UNITS">Units_UI</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RELATIVE_INCLK">REL_PRIMARY</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_IN_FREQ">100.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.JITTER_OPTIONS">UI</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN1_UI_JITTER">0.010</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN2_UI_JITTER">0.010</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_IN_JITTER">0.010</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_IN_JITTER">0.010</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN1_JITTER_PS">200.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN2_JITTER_PS">100.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_USED">true</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_USED">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_USED">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_USED">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_USED">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_USED">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.NUM_OUT_CLKS">2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT1_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT2_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT3_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT4_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT5_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT6_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT7_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIMARY_PORT">CLK_IN1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT1_PORT">CLK_OUT1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT2_PORT">CLK_OUT2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT3_PORT">CLK_OUT3</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT4_PORT">CLK_OUT4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT5_PORT">CLK_OUT5</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT6_PORT">CLK_OUT6</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT7_PORT">CLK_OUT7</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DADDR_PORT">DADDR</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCLK_PORT">DCLK</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DRDY_PORT">DRDY</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DWE_PORT">DWE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DIN_PORT">DIN</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DOUT_PORT">DOUT</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DEN_PORT">DEN</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSCLK_PORT">PSCLK</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSEN_PORT">PSEN</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSINCDEC_PORT">PSINCDEC</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSDONE_PORT">PSDONE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_OUT_FREQ">75</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_OUT_FREQ">150</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_MAX_I_JITTER">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_MIN_O_JITTER">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_SOURCE">Single_ended_clock_capable_pin</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_INCLK_SWITCHOVER">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_PORT">CLK_IN2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_SOURCE">Single_ended_clock_capable_pin</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_DRIVES">BUFG</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_DRIVES">BUFG</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_DRIVES">BUFG</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_DRIVES">BUFG</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_DRIVES">BUFG</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_DRIVES">BUFG</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_DRIVES">BUFG</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FEEDBACK_SOURCE">FDBK_AUTO</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_SIGNALING">SINGLE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_PORT">CLKFB_IN</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_P_PORT">CLKFB_IN_P</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_N_PORT">CLKFB_IN_N</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_OUT_PORT">CLKFB_OUT</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_OUT_P_PORT">CLKFB_OUT_P</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_OUT_N_PORT">CLKFB_OUT_N</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLATFORM">lin64</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SUMMARY_STRINGS">empty</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_LOCKED">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CALC_DONE">DONE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_RESET">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_POWER_DOWN">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_STATUS">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_FREEZE">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_CLK_VALID">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_INCLK_STOPPED">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_CLKFB_STOPPED">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_PORT">RESET</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.LOCKED_PORT">LOCKED</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.POWER_DOWN_PORT">POWER_DOWN</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_VALID_PORT">CLK_VALID</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.STATUS_PORT">STATUS</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_IN_SEL_PORT">CLK_IN_SEL</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INPUT_CLK_STOPPED_PORT">INPUT_CLK_STOPPED</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_STOPPED_PORT">CLKFB_STOPPED</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OVERRIDE_MMCM">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_NOTES">None</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_DIVCLK_DIVIDE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_BANDWIDTH">OPTIMIZED</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_MULT_F">4.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_USE_FINE_PS">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKIN1_PERIOD">10.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKIN2_PERIOD">10.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_CASCADE">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLOCK_HOLD">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_COMPENSATION">ZHOLD</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_REF_JITTER1">0.010</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_REF_JITTER2">0.010</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_STARTUP_WAIT">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_DIVIDE_F">4.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_USE_FINE_PS">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_DIVIDE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_USE_FINE_PS">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_DIVIDE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_USE_FINE_PS">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_DIVIDE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_USE_FINE_PS">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_DIVIDE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_USE_FINE_PS">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_DIVIDE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_USE_FINE_PS">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_DIVIDE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_USE_FINE_PS">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OVERRIDE_DCM">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCM_NOTES">None</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCM_CLKDV_DIVIDE">2.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCM_CLKFX_DIVIDE">2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCM_CLKFX_MULTIPLY">3</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCM_CLKIN_DIVIDE_BY_2">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCM_CLKIN_PERIOD">20.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCM_CLKOUT_PHASE_SHIFT">NONE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCM_DESKEW_ADJUST">SYSTEM_SYNCHRONOUS</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCM_PHASE_SHIFT">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCM_CLK_FEEDBACK">NONE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCM_STARTUP_WAIT">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCM_CLK_OUT1_PORT">CLKFX</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCM_CLK_OUT2_PORT">CLK0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCM_CLK_OUT3_PORT">CLK0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCM_CLK_OUT4_PORT">CLK0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCM_CLK_OUT5_PORT">CLK0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCM_CLK_OUT6_PORT">CLK0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OVERRIDE_DCM_CLKGEN">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCM_CLKGEN_NOTES">None</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCM_CLKGEN_CLKFX_DIVIDE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCM_CLKGEN_CLKFX_MULTIPLY">4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCM_CLKGEN_CLKFXDV_DIVIDE">2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCM_CLKGEN_CLKFX_MD_MAX">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCM_CLKGEN_STARTUP_WAIT">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCM_CLKGEN_CLKIN_PERIOD">10.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCM_CLKGEN_SPREAD_SPECTRUM">NONE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCM_CLKGEN_CLK_OUT1_PORT">CLKFX</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCM_CLKGEN_CLK_OUT2_PORT">CLKFX</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCM_CLKGEN_CLK_OUT3_PORT">CLKFX</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OVERRIDE_PLL">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_NOTES">None</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_BANDWIDTH">OPTIMIZED</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKFBOUT_MULT">9</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKFBOUT_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLK_FEEDBACK">CLKFBOUT</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_DIVCLK_DIVIDE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKIN_PERIOD">20.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_COMPENSATION">INTERNAL</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_REF_JITTER">0.010</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT0_DIVIDE">6</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT0_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT1_DIVIDE">3</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT2_DIVIDE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT2_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT3_DIVIDE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT3_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT4_DIVIDE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT4_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT5_DIVIDE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT5_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCM_PLL_CASCADE">NONE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLOCK_MGR_TYPE">AUTO</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIMTYPE_SEL">PLL_BASE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIMITIVE">MMCM</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SS_MODE">CENTER_HIGH</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SS_MOD_FREQ">250</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COMPONENT_NAME">hdmi_clk</spirit:configurableElementValue>
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<spirit:vendorExtensions>
<xilinx:instanceProperties>
<xilinx:projectOptions>
<xilinx:projectName>coregen</xilinx:projectName>
<xilinx:outputDirectory>./</xilinx:outputDirectory>
<xilinx:workingDirectory>./tmp/</xilinx:workingDirectory>
<xilinx:subWorkingDirectory>./tmp/_cg/</xilinx:subWorkingDirectory>
</xilinx:projectOptions>
<xilinx:part>
<xilinx:device>xc6slx9</xilinx:device>
<xilinx:deviceFamily>spartan6</xilinx:deviceFamily>
<xilinx:package>tqg144</xilinx:package>
<xilinx:speedGrade>-2</xilinx:speedGrade>
</xilinx:part>
<xilinx:flowOptions>
<xilinx:busFormat>BusFormatAngleBracketNotRipped</xilinx:busFormat>
<xilinx:designEntry>Verilog</xilinx:designEntry>
<xilinx:asySymbol>true</xilinx:asySymbol>
<xilinx:flowVendor>Other</xilinx:flowVendor>
<xilinx:addPads>false</xilinx:addPads>
<xilinx:removeRPMs>false</xilinx:removeRPMs>
<xilinx:createNDF>false</xilinx:createNDF>
<xilinx:implementationFileType>Ngc</xilinx:implementationFileType>
<xilinx:formalVerification>false</xilinx:formalVerification>
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<xilinx:simulationOptions>
<xilinx:simulationModel>Behavioral</xilinx:simulationModel>
<xilinx:simulationLanguage>Verilog</xilinx:simulationLanguage>
<xilinx:foundationSym>false</xilinx:foundationSym>
</xilinx:simulationOptions>
<xilinx:packageInfo>
<xilinx:sourceCoreCreationDate>2012-05-10+12:44</xilinx:sourceCoreCreationDate>
</xilinx:packageInfo>
</xilinx:instanceProperties>
</spirit:vendorExtensions>
</spirit:componentInstance>
<spirit:componentInstance>
<spirit:instanceName>microblaze_mcs</spirit:instanceName>
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="microblaze_mcs" spirit:version="1.4" />
<spirit:configurableElementValues>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.JTAG_CHAIN">USER2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MICROBLAZE_INSTANCE">microblaze_mcs_v1_4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PATH">mcs_0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FREQ">150</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DEBUG_ENABLED">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TRACE">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MEMSIZE">16KB</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_IO_BUS">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_UART_RX">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_UART_TX">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.UART_BAUDRATE">9600</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.UART_PROG_BAUDRATE">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.UART_DATA_BITS">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.UART_USE_PARITY">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.UART_ODD_PARITY">Even</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.UART_RX_INTERRUPT">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.UART_TX_INTERRUPT">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.UART_ERROR_INTERRUPT">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_FIT1">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIT1_No_CLOCKS">6216</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIT1_INTERRUPT">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_FIT2">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIT2_No_CLOCKS">6216</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIT2_INTERRUPT">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_FIT3">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIT3_No_CLOCKS">6216</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIT3_INTERRUPT">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_FIT4">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIT4_No_CLOCKS">6216</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIT4_INTERRUPT">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_PIT1">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PIT1_SIZE">32</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PIT1_READABLE">true</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PIT1_PRESCALER">None</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PIT1_INTERRUPT">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_PIT2">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PIT2_SIZE">32</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PIT2_READABLE">true</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PIT2_PRESCALER">None</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PIT2_INTERRUPT">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_PIT3">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PIT3_SIZE">32</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PIT3_READABLE">true</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PIT3_PRESCALER">None</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PIT3_INTERRUPT">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_PIT4">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PIT4_SIZE">32</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PIT4_READABLE">true</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PIT4_PRESCALER">None</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PIT4_INTERRUPT">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_GPO1">true</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.GPO1_SIZE">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.GPO1_INIT">0x00000000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_GPO2">true</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.GPO2_SIZE">16</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.GPO2_INIT">0x00000000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_GPO3">true</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.GPO3_SIZE">2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.GPO3_INIT">0x00000000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_GPO4">true</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.GPO4_SIZE">6</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.GPO4_INIT">0x00000000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_GPI1">true</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.GPI1_SIZE">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.GPI1_INTERRUPT">None</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_GPI2">true</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.GPI2_SIZE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.GPI2_INTERRUPT">Falling_Edge</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_GPI3">true</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.GPI3_SIZE">2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.GPI3_INTERRUPT">None</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_GPI4">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.GPI4_SIZE">32</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.GPI4_INTERRUPT">None</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTC_USE_EXT_INTR">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTC_INTR_SIZE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTC_LEVEL_EDGE">0x0000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTC_POSITIVE">0xFFFF</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">microblaze_mcs</spirit:configurableElementValue>
</spirit:configurableElementValues>
<spirit:vendorExtensions>
<xilinx:instanceProperties>
<xilinx:projectOptions>
<xilinx:projectName>coregen</xilinx:projectName>
<xilinx:outputDirectory>./</xilinx:outputDirectory>
<xilinx:workingDirectory>./tmp/</xilinx:workingDirectory>
<xilinx:subWorkingDirectory>./tmp/_cg/</xilinx:subWorkingDirectory>
</xilinx:projectOptions>
<xilinx:part>
<xilinx:device>xc6slx9</xilinx:device>
<xilinx:deviceFamily>spartan6</xilinx:deviceFamily>
<xilinx:package>tqg144</xilinx:package>
<xilinx:speedGrade>-2</xilinx:speedGrade>
</xilinx:part>
<xilinx:flowOptions>
<xilinx:busFormat>BusFormatAngleBracketNotRipped</xilinx:busFormat>
<xilinx:designEntry>Verilog</xilinx:designEntry>
<xilinx:asySymbol>true</xilinx:asySymbol>
<xilinx:flowVendor>Other</xilinx:flowVendor>
<xilinx:addPads>false</xilinx:addPads>
<xilinx:removeRPMs>false</xilinx:removeRPMs>
<xilinx:createNDF>false</xilinx:createNDF>
<xilinx:implementationFileType>Ngc</xilinx:implementationFileType>
<xilinx:formalVerification>false</xilinx:formalVerification>
</xilinx:flowOptions>
<xilinx:simulationOptions>
<xilinx:simulationModel>Behavioral</xilinx:simulationModel>
<xilinx:simulationLanguage>Verilog</xilinx:simulationLanguage>
<xilinx:foundationSym>false</xilinx:foundationSym>
</xilinx:simulationOptions>
<xilinx:packageInfo>
<xilinx:sourceCoreCreationDate>2012-11-21+08:11</xilinx:sourceCoreCreationDate>
</xilinx:packageInfo>
</xilinx:instanceProperties>
</spirit:vendorExtensions>
</spirit:componentInstance>
</spirit:componentInstances>
<spirit:vendorExtensions>
<xilinx:instanceProperties>
<xilinx:projectOptions>
<xilinx:projectName>coregen</xilinx:projectName>
<xilinx:outputDirectory>./</xilinx:outputDirectory>
<xilinx:workingDirectory>./tmp/</xilinx:workingDirectory>
<xilinx:subWorkingDirectory>./tmp/_cg/</xilinx:subWorkingDirectory>
</xilinx:projectOptions>
<xilinx:part>
<xilinx:device>xc6slx9</xilinx:device>
<xilinx:deviceFamily>spartan6</xilinx:deviceFamily>
<xilinx:package>tqg144</xilinx:package>
<xilinx:speedGrade>-2</xilinx:speedGrade>
</xilinx:part>
<xilinx:flowOptions>
<xilinx:busFormat>BusFormatAngleBracketNotRipped</xilinx:busFormat>
<xilinx:designEntry>Verilog</xilinx:designEntry>
<xilinx:asySymbol>true</xilinx:asySymbol>
<xilinx:flowVendor>Other</xilinx:flowVendor>
<xilinx:addPads>false</xilinx:addPads>
<xilinx:removeRPMs>false</xilinx:removeRPMs>
<xilinx:createNDF>false</xilinx:createNDF>
<xilinx:implementationFileType>Ngc</xilinx:implementationFileType>
<xilinx:formalVerification>false</xilinx:formalVerification>
</xilinx:flowOptions>
<xilinx:simulationOptions>
<xilinx:simulationModel>Behavioral</xilinx:simulationModel>
<xilinx:simulationLanguage>Verilog</xilinx:simulationLanguage>
<xilinx:foundationSym>false</xilinx:foundationSym>
</xilinx:simulationOptions>
</xilinx:instanceProperties>
</spirit:vendorExtensions>
</spirit:design>

9
ipcore_dir/coregen.cgp
View File

@ -1,9 +0,0 @@
SET busformat = BusFormatAngleBracketNotRipped
SET designentry = Verilog
SET device = xc6slx9
SET devicefamily = spartan6
SET flowvendor = Other
SET package = tqg144
SET speedgrade = -2
SET verilogsim = true
SET vhdlsim = false

37
ipcore_dir/create_clk_wiz.tcl
View File

@ -1,37 +0,0 @@
##
## Core Generator Run Script, generator for Project Navigator create command
##
proc findRtfPath { relativePath } {
set xilenv ""
if { [info exists ::env(XILINX) ] } {
if { [info exists ::env(MYXILINX)] } {
set xilenv [join [list $::env(MYXILINX) $::env(XILINX)] $::xilinx::path_sep ]
} else {
set xilenv $::env(XILINX)
}
}
foreach path [ split $xilenv $::xilinx::path_sep ] {
set fullPath [ file join $path $relativePath ]
if { [ file exists $fullPath ] } {
return $fullPath
}
}
return ""
}
source [ findRtfPath "data/projnav/scripts/dpm_cgUtils.tcl" ]
set result [ run_cg_create "xilinx.com:ip:clk_wiz:3.6" "clk_wiz" "Clocking Wizard" "Clocking Wizard (xilinx.com:ip:clk_wiz:3.6) generated by Project Navigator" xc6slx9-2tqg144 Verilog ]
if { $result == 0 } {
puts "Core Generator create command completed successfully."
} elseif { $result == 1 } {
puts "Core Generator create command failed."
} elseif { $result == 3 || $result == 4 } {
# convert 'version check' result to real return range, bypassing any messages.
set result [ expr $result - 3 ]
} else {
puts "Core Generator create cancelled."
}
exit $result

37
ipcore_dir/create_hdmi_clk.tcl
View File

@ -1,37 +0,0 @@
##
## Core Generator Run Script, generator for Project Navigator create command
##
proc findRtfPath { relativePath } {
set xilenv ""
if { [info exists ::env(XILINX) ] } {
if { [info exists ::env(MYXILINX)] } {
set xilenv [join [list $::env(MYXILINX) $::env(XILINX)] $::xilinx::path_sep ]
} else {
set xilenv $::env(XILINX)
}
}
foreach path [ split $xilenv $::xilinx::path_sep ] {
set fullPath [ file join $path $relativePath ]
if { [ file exists $fullPath ] } {
return $fullPath
}
}
return ""
}
source [ findRtfPath "data/projnav/scripts/dpm_cgUtils.tcl" ]
set result [ run_cg_create "xilinx.com:ip:clk_wiz:3.6" "hdmi_clk" "Clocking Wizard" "Clocking Wizard (xilinx.com:ip:clk_wiz:3.6) generated by Project Navigator" xc6slx9-2tqg144 Verilog ]
if { $result == 0 } {
puts "Core Generator create command completed successfully."
} elseif { $result == 1 } {
puts "Core Generator create command failed."
} elseif { $result == 3 || $result == 4 } {
# convert 'version check' result to real return range, bypassing any messages.
set result [ expr $result - 3 ]
} else {
puts "Core Generator create cancelled."
}
exit $result

37
ipcore_dir/create_microblaze_mcs.tcl
View File

@ -1,37 +0,0 @@
##
## Core Generator Run Script, generator for Project Navigator create command
##
proc findRtfPath { relativePath } {
set xilenv ""
if { [info exists ::env(XILINX) ] } {
if { [info exists ::env(MYXILINX)] } {
set xilenv [join [list $::env(MYXILINX) $::env(XILINX)] $::xilinx::path_sep ]
} else {
set xilenv $::env(XILINX)
}
}
foreach path [ split $xilenv $::xilinx::path_sep ] {
set fullPath [ file join $path $relativePath ]
if { [ file exists $fullPath ] } {
return $fullPath
}
}
return ""
}
source [ findRtfPath "data/projnav/scripts/dpm_cgUtils.tcl" ]
set result [ run_cg_create "xilinx.com:ip:microblaze_mcs:1.4" "microblaze_mcs" "MicroBlaze MCS" "MicroBlaze MCS (xilinx.com:ip:microblaze_mcs:1.4) generated by Project Navigator" xc6slx9-2tqg144 Verilog ]
if { $result == 0 } {
puts "Core Generator create command completed successfully."
} elseif { $result == 1 } {
puts "Core Generator create command failed."
} elseif { $result == 3 || $result == 4 } {
# convert 'version check' result to real return range, bypassing any messages.
set result [ expr $result - 3 ]
} else {
puts "Core Generator create cancelled."
}
exit $result

37
ipcore_dir/edit_hdmi_clk.tcl
View File

@ -1,37 +0,0 @@
##
## Core Generator Run Script, generator for Project Navigator edit command
##
proc findRtfPath { relativePath } {
set xilenv ""
if { [info exists ::env(XILINX) ] } {
if { [info exists ::env(MYXILINX)] } {
set xilenv [join [list $::env(MYXILINX) $::env(XILINX)] $::xilinx::path_sep ]
} else {
set xilenv $::env(XILINX)
}
}
foreach path [ split $xilenv $::xilinx::path_sep ] {
set fullPath [ file join $path $relativePath ]
if { [ file exists $fullPath ] } {
return $fullPath
}
}
return ""
}
source [ findRtfPath "data/projnav/scripts/dpm_cgUtils.tcl" ]
set result [ run_cg_edit "hdmi_clk" xc6slx9-2tqg144 Verilog ]
if { $result == 0 } {
puts "Core Generator edit command completed successfully."
} elseif { $result == 1 } {
puts "Core Generator edit command failed."
} elseif { $result == 3 || $result == 4 } {
# convert 'version check' result to real return range, bypassing any messages.
set result [ expr $result - 3 ]
} else {
puts "Core Generator edit cancelled."
}
exit $result

37
ipcore_dir/edit_microblaze_mcs.tcl
View File

@ -1,37 +0,0 @@
##
## Core Generator Run Script, generator for Project Navigator edit command
##
proc findRtfPath { relativePath } {
set xilenv ""
if { [info exists ::env(XILINX) ] } {
if { [info exists ::env(MYXILINX)] } {
set xilenv [join [list $::env(MYXILINX) $::env(XILINX)] $::xilinx::path_sep ]
} else {
set xilenv $::env(XILINX)
}
}
foreach path [ split $xilenv $::xilinx::path_sep ] {
set fullPath [ file join $path $relativePath ]
if { [ file exists $fullPath ] } {
return $fullPath
}
}
return ""
}
source [ findRtfPath "data/projnav/scripts/dpm_cgUtils.tcl" ]
set result [ run_cg_edit "microblaze_mcs" xc6slx9-2tqg144 Verilog ]
if { $result == 0 } {
puts "Core Generator edit command completed successfully."
} elseif { $result == 1 } {
puts "Core Generator edit command failed."
} elseif { $result == 3 || $result == 4 } {
# convert 'version check' result to real return range, bypassing any messages.
set result [ expr $result - 3 ]
} else {
puts "Core Generator edit cancelled."
}
exit $result

37
ipcore_dir/gen_hdmi_clk.tcl
View File

@ -1,37 +0,0 @@
##
## Core Generator Run Script, generator for Project Navigator regen command
##
proc findRtfPath { relativePath } {
set xilenv ""
if { [info exists ::env(XILINX) ] } {
if { [info exists ::env(MYXILINX)] } {
set xilenv [join [list $::env(MYXILINX) $::env(XILINX)] $::xilinx::path_sep ]
} else {
set xilenv $::env(XILINX)
}
}
foreach path [ split $xilenv $::xilinx::path_sep ] {
set fullPath [ file join $path $relativePath ]
if { [ file exists $fullPath ] } {
return $fullPath
}
}
return ""
}
source [ findRtfPath "data/projnav/scripts/dpm_cgUtils.tcl" ]
set result [ run_cg_regen "hdmi_clk" xc6slx9-2tqg144 Verilog CURRENT ]
if { $result == 0 } {
puts "Core Generator regen command completed successfully."
} elseif { $result == 1 } {
puts "Core Generator regen command failed."
} elseif { $result == 3 || $result == 4 } {
# convert 'version check' result to real return range, bypassing any messages.
set result [ expr $result - 3 ]
} else {
puts "Core Generator regen cancelled."
}
exit $result

37
ipcore_dir/gen_microblaze_mcs.tcl
View File

@ -1,37 +0,0 @@
##
## Core Generator Run Script, generator for Project Navigator regen command
##
proc findRtfPath { relativePath } {
set xilenv ""
if { [info exists ::env(XILINX) ] } {
if { [info exists ::env(MYXILINX)] } {
set xilenv [join [list $::env(MYXILINX) $::env(XILINX)] $::xilinx::path_sep ]
} else {
set xilenv $::env(XILINX)
}
}
foreach path [ split $xilenv $::xilinx::path_sep ] {
set fullPath [ file join $path $relativePath ]
if { [ file exists $fullPath ] } {
return $fullPath
}
}
return ""
}
source [ findRtfPath "data/projnav/scripts/dpm_cgUtils.tcl" ]
set result [ run_cg_regen "microblaze_mcs" xc6slx9-2tqg144 Verilog CURRENT ]
if { $result == 0 } {
puts "Core Generator regen command completed successfully."
} elseif { $result == 1 } {
puts "Core Generator regen command failed."
} elseif { $result == 3 || $result == 4 } {
# convert 'version check' result to real return range, bypassing any messages.
set result [ expr $result - 3 ]
} else {
puts "Core Generator regen cancelled."
}
exit $result

18
ipcore_dir/hdmi_clk.sym
View File

@ -1,18 +0,0 @@
<?xml version="1.0" encoding="UTF-8"?>
<symbol version="7" name="hdmi_clk">
<symboltype>BLOCK</symboltype>
<timestamp>2020-9-21T18:2:44</timestamp>
<pin polarity="Input" x="0" y="80" name="clk_in1" />
<pin polarity="Output" x="608" y="80" name="clk_out1" />
<pin polarity="Output" x="608" y="176" name="clk_out2" />
<graph>
<text style="fontsize:40;fontname:Arial" x="32" y="32">hdmi_clk</text>
<rect width="544" x="32" y="32" height="1056" />
<line x2="32" y1="80" y2="80" x1="0" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="80" type="pin clk_in1" />
<line x2="576" y1="80" y2="80" x1="608" />
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="572" y="80" type="pin clk_out1" />
<line x2="576" y1="176" y2="176" x1="608" />
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="572" y="176" type="pin clk_out2" />
</graph>
</symbol>

58
ipcore_dir/hdmi_clk.ucf
View File

@ -1,58 +0,0 @@
# file: hdmi_clk.ucf
#
# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
#
# This file contains confidential and proprietary information
# of Xilinx, Inc. and is protected under U.S. and
# international copyright and other intellectual property
# laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# Xilinx, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
# (2) Xilinx shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
# materials, including for any direct, or any indirect,
# special, incidental, or consequential loss or damage
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or Xilinx had been advised of the
# possibility of the same.
#
# CRITICAL APPLICATIONS
# Xilinx products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
# other applications that could lead to death, personal
# injury, or severe property or environmental damage
# (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and
# liability of any use of Xilinx products in Critical
# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
#
# Input clock periods. These duplicate the values entered for the
# input clocks. You can use these to time your system
#----------------------------------------------------------------
NET "CLK_IN1" TNM_NET = "CLK_IN1";
TIMESPEC "TS_CLK_IN1" = PERIOD "CLK_IN1" 20.000 ns HIGH 50% INPUT_JITTER 200.0ps;
# FALSE PATH constraints

74
ipcore_dir/hdmi_clk.xise
View File

@ -1,74 +0,0 @@
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<header>
<!-- ISE source project file created by Project Navigator. -->
<!-- -->
<!-- This file contains project source information including a list of -->
<!-- project source files, project and process properties. This file, -->
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
</header>
<version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
<files>
<file xil_pn:name="hdmi_clk.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="hdmi_clk.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="3"/>
</file>
</files>
<properties>
<property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device" xil_pn:value="xc6slx9" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Module|hdmi_clk" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="hdmi_clk.v" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/hdmi_clk" xil_pn:valueState="non-default"/>
<property xil_pn:name="Package" xil_pn:value="tqg144" xil_pn:valueState="default"/>
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-2" xil_pn:valueState="non-default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_DesignName" xil_pn:value="hdmi_clk" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2020-09-21T20:02:45" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="3F469F5C71C64704824888D979DF0B8F" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties>
<bindings>
<binding xil_pn:location="/hdmi_clk" xil_pn:name="hdmi_clk.ucf"/>
</bindings>
<libraries/>
<autoManagedFiles>
<!-- The following files are identified by `include statements in verilog -->
<!-- source files and are automatically managed by Project Navigator. -->
<!-- -->
<!-- Do not hand-edit this section, as it will be overwritten when the -->
<!-- project is analyzed based on files automatically identified as -->
<!-- include files. -->
</autoManagedFiles>
</project>

5
ipcore_dir/hdmi_clk/simulation/functional/ucli_commands.key
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@ -1,5 +0,0 @@
call {$vcdpluson}
call {$vcdplusmemon(hdmi_clk_tb.dut.counter)}
run
call {$vcdplusclose}
quit

15
ipcore_dir/hdmi_clk/simulation/functional/vcs_session.tcl
View File

@ -1,15 +0,0 @@
gui_open_window Wave
gui_sg_create hdmi_clk_group
gui_list_add_group -id Wave.1 {hdmi_clk_group}
gui_sg_addsignal -group hdmi_clk_group {hdmi_clk_tb.test_phase}
gui_set_radix -radix {ascii} -signals {hdmi_clk_tb.test_phase}
gui_sg_addsignal -group hdmi_clk_group {{Input_clocks}} -divider
gui_sg_addsignal -group hdmi_clk_group {hdmi_clk_tb.CLK_IN1}
gui_sg_addsignal -group hdmi_clk_group {{Output_clocks}} -divider
gui_sg_addsignal -group hdmi_clk_group {hdmi_clk_tb.dut.clk}
gui_list_expand -id Wave.1 hdmi_clk_tb.dut.clk
gui_sg_addsignal -group hdmi_clk_group {{Counters}} -divider
gui_sg_addsignal -group hdmi_clk_group {hdmi_clk_tb.COUNT}
gui_sg_addsignal -group hdmi_clk_group {hdmi_clk_tb.dut.counter}
gui_list_expand -id Wave.1 hdmi_clk_tb.dut.counter
gui_zoom -window Wave.1 -full

55
ipcore_dir/hdmi_clk_flist.txt
View File

@ -1,55 +0,0 @@
# Output products list for <hdmi_clk>
_xmsgs/pn_parser.xmsgs
hdmi_clk/clk_wiz_v3_6_readme.txt
hdmi_clk/doc/clk_wiz_v3_6_readme.txt
hdmi_clk/doc/clk_wiz_v3_6_vinfo.html
hdmi_clk/doc/pg065_clk_wiz.pdf
hdmi_clk/example_design/hdmi_clk_exdes.ucf
hdmi_clk/example_design/hdmi_clk_exdes.v
hdmi_clk/example_design/hdmi_clk_exdes.xdc
hdmi_clk/implement/implement.bat
hdmi_clk/implement/implement.sh
hdmi_clk/implement/planAhead_ise.bat
hdmi_clk/implement/planAhead_ise.sh
hdmi_clk/implement/planAhead_ise.tcl
hdmi_clk/implement/planAhead_rdn.bat
hdmi_clk/implement/planAhead_rdn.sh
hdmi_clk/implement/planAhead_rdn.tcl
hdmi_clk/implement/xst.prj
hdmi_clk/implement/xst.scr
hdmi_clk/simulation/functional/simcmds.tcl
hdmi_clk/simulation/functional/simulate_isim.bat
hdmi_clk/simulation/functional/simulate_isim.sh
hdmi_clk/simulation/functional/simulate_mti.bat
hdmi_clk/simulation/functional/simulate_mti.do
hdmi_clk/simulation/functional/simulate_mti.sh
hdmi_clk/simulation/functional/simulate_ncsim.sh
hdmi_clk/simulation/functional/simulate_vcs.sh
hdmi_clk/simulation/functional/ucli_commands.key
hdmi_clk/simulation/functional/vcs_session.tcl
hdmi_clk/simulation/functional/wave.do
hdmi_clk/simulation/functional/wave.sv
hdmi_clk/simulation/hdmi_clk_tb.v
hdmi_clk/simulation/timing/hdmi_clk_tb.v
hdmi_clk/simulation/timing/sdf_cmd_file
hdmi_clk/simulation/timing/simcmds.tcl
hdmi_clk/simulation/timing/simulate_isim.sh
hdmi_clk/simulation/timing/simulate_mti.bat
hdmi_clk/simulation/timing/simulate_mti.do
hdmi_clk/simulation/timing/simulate_mti.sh
hdmi_clk/simulation/timing/simulate_ncsim.sh
hdmi_clk/simulation/timing/simulate_vcs.sh
hdmi_clk/simulation/timing/ucli_commands.key
hdmi_clk/simulation/timing/vcs_session.tcl
hdmi_clk/simulation/timing/wave.do
hdmi_clk.asy
hdmi_clk.gise
hdmi_clk.sym
hdmi_clk.ucf
hdmi_clk.v
hdmi_clk.veo
hdmi_clk.xco
hdmi_clk.xdc
hdmi_clk.xise
hdmi_clk_flist.txt
hdmi_clk_xmdf.tcl

BIN
ipcore_dir/mb_bootloop_le.elf
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Binary file not shown.

45
ipcore_dir/microblaze_mcs.asy
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@ -1,45 +0,0 @@
Version 4
SymbolType BLOCK
TEXT 32 32 LEFT 4 microblaze_mcs
RECTANGLE Normal 32 32 736 1728
LINE Normal 0 80 32 80
PIN 0 80 LEFT 36
PINATTR PinName clk
PINATTR Polarity IN
LINE Normal 0 112 32 112
PIN 0 112 LEFT 36
PINATTR PinName reset
PINATTR Polarity IN
LINE Normal 768 656 736 656
PIN 768 656 RIGHT 36
PINATTR PinName gpi2_interrupt
PINATTR Polarity OUT
LINE Wide 0 304 32 304
PIN 0 304 LEFT 36
PINATTR PinName gpi1[7:0]
PINATTR Polarity IN
LINE Wide 0 336 32 336
PIN 0 336 LEFT 36
PINATTR PinName gpi2[0:0]
PINATTR Polarity IN
LINE Wide 0 368 32 368
PIN 0 368 LEFT 36
PINATTR PinName gpi3[1:0]
PINATTR Polarity IN
LINE Wide 768 784 736 784
PIN 768 784 RIGHT 36
PINATTR PinName gpo1[15:0]
PINATTR Polarity OUT
LINE Wide 768 816 736 816
PIN 768 816 RIGHT 36
PINATTR PinName gpo2[15:0]
PINATTR Polarity OUT
LINE Wide 768 848 736 848
PIN 768 848 RIGHT 36
PINATTR PinName gpo3[0:0]
PINATTR Polarity OUT
LINE Wide 768 880 736 880
PIN 768 880 RIGHT 36
PINATTR PinName gpo4[5:0]
PINATTR Polarity OUT

16
ipcore_dir/microblaze_mcs.bmm
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@ -1,16 +0,0 @@
ADDRESS_MAP microblaze_mcs MICROBLAZE-LE 100
ADDRESS_SPACE lmb_bram COMBINED [0x00000000:0x00003fff]
ADDRESS_RANGE RAMB16
BUS_BLOCK
mcs_0/U0/lmb_bram_I/RAM_Inst/Using_B16_S4.The_BRAMs[0].RAMB16_S4_1 [31:28] INPUT = microblaze_mcs.lmb_bram_0.mem;
mcs_0/U0/lmb_bram_I/RAM_Inst/Using_B16_S4.The_BRAMs[1].RAMB16_S4_1 [27:24] INPUT = microblaze_mcs.lmb_bram_1.mem;
mcs_0/U0/lmb_bram_I/RAM_Inst/Using_B16_S4.The_BRAMs[2].RAMB16_S4_1 [23:20] INPUT = microblaze_mcs.lmb_bram_2.mem;
mcs_0/U0/lmb_bram_I/RAM_Inst/Using_B16_S4.The_BRAMs[3].RAMB16_S4_1 [19:16] INPUT = microblaze_mcs.lmb_bram_3.mem;
mcs_0/U0/lmb_bram_I/RAM_Inst/Using_B16_S4.The_BRAMs[4].RAMB16_S4_1 [15:12] INPUT = microblaze_mcs.lmb_bram_4.mem;
mcs_0/U0/lmb_bram_I/RAM_Inst/Using_B16_S4.The_BRAMs[5].RAMB16_S4_1 [11:8] INPUT = microblaze_mcs.lmb_bram_5.mem;
mcs_0/U0/lmb_bram_I/RAM_Inst/Using_B16_S4.The_BRAMs[6].RAMB16_S4_1 [7:4] INPUT = microblaze_mcs.lmb_bram_6.mem;
mcs_0/U0/lmb_bram_I/RAM_Inst/Using_B16_S4.The_BRAMs[7].RAMB16_S4_1 [3:0] INPUT = microblaze_mcs.lmb_bram_7.mem;
END_BUS_BLOCK;
END_ADDRESS_RANGE;
END_ADDRESS_SPACE;
END_ADDRESS_MAP;

0
ipcore_dir/microblaze_mcs.ncf
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39
ipcore_dir/microblaze_mcs.sym
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@ -1,39 +0,0 @@
<?xml version="1.0" encoding="UTF-8"?>
<symbol version="7" name="microblaze_mcs">
<symboltype>BLOCK</symboltype>
<timestamp>2020-9-21T18:2:10</timestamp>
<pin polarity="Input" x="0" y="80" name="clk" />
<pin polarity="Input" x="0" y="112" name="reset" />
<pin polarity="Output" x="768" y="656" name="gpi2_interrupt" />
<pin polarity="Input" x="0" y="304" name="gpi1[7:0]" />
<pin polarity="Input" x="0" y="336" name="gpi2[0:0]" />
<pin polarity="Input" x="0" y="368" name="gpi3[1:0]" />
<pin polarity="Output" x="768" y="784" name="gpo1[15:0]" />
<pin polarity="Output" x="768" y="816" name="gpo2[15:0]" />
<pin polarity="Output" x="768" y="848" name="gpo3[0:0]" />
<pin polarity="Output" x="768" y="880" name="gpo4[5:0]" />
<graph>
<text style="fontsize:40;fontname:Arial" x="32" y="32">microblaze_mcs</text>
<rect width="704" x="32" y="32" height="1696" />
<line x2="32" y1="80" y2="80" x1="0" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="80" type="pin clk" />
<line x2="32" y1="112" y2="112" x1="0" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="112" type="pin reset" />
<line x2="736" y1="656" y2="656" x1="768" />
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="732" y="656" type="pin gpi2_interrupt" />
<line x2="32" y1="304" y2="304" style="linewidth:W" x1="0" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="304" type="pin gpi1[7:0]" />
<line x2="32" y1="336" y2="336" style="linewidth:W" x1="0" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="336" type="pin gpi2[0:0]" />
<line x2="32" y1="368" y2="368" style="linewidth:W" x1="0" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="368" type="pin gpi3[1:0]" />
<line x2="736" y1="784" y2="784" style="linewidth:W" x1="768" />
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="732" y="784" type="pin gpo1[15:0]" />
<line x2="736" y1="816" y2="816" style="linewidth:W" x1="768" />
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="732" y="816" type="pin gpo2[15:0]" />
<line x2="736" y1="848" y2="848" style="linewidth:W" x1="768" />
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="732" y="848" type="pin gpo3[0:0]" />
<line x2="736" y1="880" y2="880" style="linewidth:W" x1="768" />
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="732" y="880" type="pin gpo4[5:0]" />
</graph>
</symbol>

16200
ipcore_dir/microblaze_mcs.v
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File diff suppressed because it is too large Load Diff

81
ipcore_dir/microblaze_mcs.veo
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@ -1,81 +0,0 @@
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2020 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
/*******************************************************************************
* Generated from core with identifier: xilinx.com:ip:microblaze_mcs:1.4 *
* *
* MicroBlaze Micro Controller System (MCS) is a light-weight general *
* purpose micro controller system, based on the MicroBlaze processor. *
* It is primarily intended for simple control applications, where a *
* hardware solution would be less flexible and more difficult to *
* implement. Software development with the Xilinx Software Development *
* Kit (SDK) is supported, including a software driver for the *
* peripherals. Debugging is available either via SDK or directly with *
* the Xilinx Microprocessor Debugger. *
* *
* The MCS consists of the processor itself, local memory with sizes *
* ranging from 4KB to 64KB, up to 4 Fixed Interval Timers, up to 4 *
* Programmable Interval Timers, up to 4 32-bit General Purpose Output *
* ports, up to 4 32-bit General Purpose Input ports, and an Interrupt *
* Controller with up to 16 external interrupt inputs. *
* *
*******************************************************************************/
// Interfaces:
// IO_BUS
// MicroBlaze MCS IO Bus Interface
// TRACE
// MicroBlaze MCS Trace Interface
// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
microblaze_mcs your_instance_name (
.Clk(Clk), // input Clk
.Reset(Reset), // input Reset
.GPO1(GPO1), // output [15 : 0] GPO1
.GPO2(GPO2), // output [15 : 0] GPO2
.GPO3(GPO3), // output [0 : 0] GPO3
.GPO4(GPO4), // output [5 : 0] GPO4
.GPI1(GPI1), // input [7 : 0] GPI1
.GPI1_Interrupt(GPI1_Interrupt), // output GPI1_Interrupt
.GPI2(GPI2), // input [0 : 0] GPI2
.GPI2_Interrupt(GPI2_Interrupt), // output GPI2_Interrupt
.GPI3(GPI3), // input [1 : 0] GPI3
.GPI3_Interrupt(GPI3_Interrupt), // output GPI3_Interrupt
.INTC_IRQ(INTC_IRQ) // output INTC_IRQ
);
// INST_TAG_END ------ End INSTANTIATION Template ---------
// You must compile the wrapper file microblaze_mcs.v when simulating
// the core, microblaze_mcs. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".

126
ipcore_dir/microblaze_mcs.xco
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@ -1,126 +0,0 @@
##############################################################
#
# Xilinx Core Generator version 14.7
# Date: Mon Sep 21 18:00:15 2020
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# Generated from component: xilinx.com:ip:microblaze_mcs:1.4
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = Verilog
SET device = xc6slx9
SET devicefamily = spartan6
SET flowvendor = Other
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = tqg144
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -2
SET verilogsim = true
SET vhdlsim = false
# END Project Options
# BEGIN Select
SELECT MicroBlaze_MCS xilinx.com:ip:microblaze_mcs:1.4
# END Select
# BEGIN Parameters
CSET component_name=microblaze_mcs
CSET debug_enabled=false
CSET fit1_interrupt=false
CSET fit1_no_clocks=6216
CSET fit2_interrupt=false
CSET fit2_no_clocks=6216
CSET fit3_interrupt=false
CSET fit3_no_clocks=6216
CSET fit4_interrupt=false
CSET fit4_no_clocks=6216
CSET freq=150
CSET gpi1_interrupt=None
CSET gpi1_size=8
CSET gpi2_interrupt=Falling_Edge
CSET gpi2_size=1
CSET gpi3_interrupt=None
CSET gpi3_size=2
CSET gpi4_interrupt=None
CSET gpi4_size=32
CSET gpo1_init=0x00000000
CSET gpo1_size=16
CSET gpo2_init=0x00000000
CSET gpo2_size=16
CSET gpo3_init=0x00000000
CSET gpo3_size=1
CSET gpo4_init=0x00000000
CSET gpo4_size=6
CSET intc_intr_size=1
CSET intc_level_edge=0x0000
CSET intc_positive=0xFFFF
CSET intc_use_ext_intr=false
CSET jtag_chain=USER2
CSET memsize=16KB
CSET microblaze_instance=microblaze_mcs_v1_4
CSET path=mcs_0
CSET pit1_interrupt=false
CSET pit1_prescaler=None
CSET pit1_readable=true
CSET pit1_size=32
CSET pit2_interrupt=false
CSET pit2_prescaler=None
CSET pit2_readable=true
CSET pit2_size=32
CSET pit3_interrupt=false
CSET pit3_prescaler=None
CSET pit3_readable=true
CSET pit3_size=32
CSET pit4_interrupt=false
CSET pit4_prescaler=None
CSET pit4_readable=true
CSET pit4_size=32
CSET trace=false
CSET uart_baudrate=9600
CSET uart_data_bits=8
CSET uart_error_interrupt=false
CSET uart_odd_parity=Even
CSET uart_prog_baudrate=false
CSET uart_rx_interrupt=false
CSET uart_tx_interrupt=false
CSET uart_use_parity=false
CSET use_fit1=false
CSET use_fit2=false
CSET use_fit3=false
CSET use_fit4=false
CSET use_gpi1=true
CSET use_gpi2=true
CSET use_gpi3=true
CSET use_gpi4=false
CSET use_gpo1=true
CSET use_gpo2=true
CSET use_gpo3=true
CSET use_gpo4=true
CSET use_io_bus=false
CSET use_pit1=false
CSET use_pit2=false
CSET use_pit3=false
CSET use_pit4=false
CSET use_uart_rx=false
CSET use_uart_tx=false
# END Parameters
# BEGIN Extra information
MISC pkg_timestamp=2012-11-21T08:11:43Z
# END Extra information
GENERATE
# CRC: d8973b25

88
ipcore_dir/microblaze_mcs.xise
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@ -1,88 +0,0 @@
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<header>
<!-- ISE source project file created by Project Navigator. -->
<!-- -->
<!-- This file contains project source information including a list of -->
<!-- project source files, project and process properties. This file, -->
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
</header>
<version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
<files>
<file xil_pn:name="microblaze_mcs/mb_bootloop_le.elf" xil_pn:type="FILE_ELF">
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file>
<file xil_pn:name="microblaze_mcs/system_template.tcl" xil_pn:type="FILE_TCL"/>
<file xil_pn:name="microblaze_mcs/microblaze_mcs_setup.tcl" xil_pn:type="FILE_TCL"/>
<file xil_pn:name="microblaze_mcs.ngc" xil_pn:type="FILE_NGC">
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
</file>
<file xil_pn:name="mb_bootloop_le.elf" xil_pn:type="FILE_ELF">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
</file>
<file xil_pn:name="microblaze_mcs.bmm" xil_pn:type="FILE_BMM">
<association xil_pn:name="Implementation" xil_pn:seqID="6"/>
</file>
<file xil_pn:name="microblaze_mcs_sdk.xml" xil_pn:type="FILE_FITTER_REPORT"/>
<file xil_pn:name="microblaze_mcs_setup.tcl" xil_pn:type="FILE_TCL"/>
<file xil_pn:name="microblaze_mcs.veo" xil_pn:type="FILE_VEO"/>
<file xil_pn:name="microblaze_mcs.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/>
<association xil_pn:name="Implementation" xil_pn:seqID="10"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="10"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="10"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="10"/>
</file>
</files>
<properties>
<property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device" xil_pn:value="xc6slx9" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Module|microblaze_mcs" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/microblaze_mcs" xil_pn:valueState="non-default"/>
<property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Package" xil_pn:value="tqg144" xil_pn:valueState="default"/>
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-2" xil_pn:valueState="non-default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_DesignName" xil_pn:value="microblaze_mcs" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2020-09-21T20:02:11" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="534E782F69499841CE64BF2098D784B5" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties>
<bindings/>
<libraries/>
<autoManagedFiles>
<!-- The following files are identified by `include statements in verilog -->
<!-- source files and are automatically managed by Project Navigator. -->
<!-- -->
<!-- Do not hand-edit this section, as it will be overwritten when the -->
<!-- project is analyzed based on files automatically identified as -->
<!-- include files. -->
</autoManagedFiles>
</project>

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###############################################################################
##
## (c) Copyright 2012 Xilinx, Inc. All rights reserved.
##
## This file contains confidential and proprietary information
## of Xilinx, Inc. and is protected under U.S. and
## international copyright and other intellectual property
## laws.
##
## DISCLAIMER
## This disclaimer is not a license and does not grant any
## rights to the materials distributed herewith. Except as
## otherwise provided in a valid license issued to you by
## Xilinx, and to the maximum extent permitted by applicable
## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
## (2) Xilinx shall not be liable (whether in contract or tort,
## including negligence, or under any other theory of
## liability) for any loss or damage of any kind or nature
## related to, arising under or in connection with these
## materials, including for any direct, or any indirect,
## special, incidental, or consequential loss or damage
## (including loss of data, profits, goodwill, or any type of
## loss or damage suffered as a result of any action brought
## by a third party) even if such damage or loss was
## reasonably foreseeable or Xilinx had been advised of the
## possibility of the same.
##
## CRITICAL APPLICATIONS
## Xilinx products are not designed or intended to be fail-
## safe, or for use in any application requiring fail-safe
## performance, such as life-support or safety devices or
## systems, Class III medical devices, nuclear facilities,
## applications related to the deployment of airbags, or any
## other applications that could lead to death, personal
## injury, or severe property or environmental damage
## (individually and collectively, "Critical
## Applications"). Customer assumes the sole risk and
## liability of any use of Xilinx products in Critical
## Applications, subject only to applicable laws and
## regulations governing limitations on product liability.
##
## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
## PART OF THIS FILE AT ALL TIMES.
##
###############################################################################
##
## microblaze_mcs_setup.tcl
##
###############################################################################
#
# This script should be sourced after CORE Generator has been used to generate
# a MicroBlaze MCS instance, either when creating a new or changing an existing
# instance.
#
# Run the script in the PlanAhead Tcl Console by typically using:
#
# source -notrace \
# project_1.srcs/sources_1/ip/microblaze_mcs_v1_4_0/microblaze_mcs_setup.tcl
#
# Run the script in the Project Navigator Tcl Console by typically using:
#
# Command> source ipcore_dir/microblaze_mcs_setup.tcl
#
# Use the menu command "View -> Panels -> Tcl Console" to show the Tcl Console
# in the Project Navigator, if it is not visible.
#
###############################################################################
#
# This script contains two exported Tcl procedures:
#
# o The first, "microblaze_mcs_setup", is used to create a merged BMM file,
# which defines the local memory of all MicroBlaze MCS instances in the
# project (if more than one instance), and set Translate process properties
# to add the "-bm" option indicating the used BMM file.
#
# The procedure is automatically invoked when sourcing this script, but
# can also subsequently be invoked with "microblaze_mcs_setup".
#
# The procedure should be invoked before running implementation, but after
# the MicroBlaze MCS instance has been generated.
#
# o The second, "microblaze_mcs_data2mem", is used to update the bit stream
# with one or more ELF files (software programs) given as arguments, generate
# corresponding MEM files for simulation, and set Bitgen process properties
# to add the "-bd" option indicating the ELF files.
#
# If no argument is given, the bit stream is updated with the microblaze
# boot loop ELF file, which ensures that the processor executes an infinite
# loop.
#
# The procedure should be invoked after the system has been implemented. It
# must also be invoked again when an ELF file name is changed, or when the
# content of an ELF file is changed. If the system is reimplemented without
# changing the software, the procedure need not be invoked again, due to the
# Bitgen "-bd" option.
#
###############################################################################
namespace eval microblaze_mcs {
# Determine if using planAhead or Project Navigator
proc mcs_using_planahead {} {
return [expr [string first "planAhead" [info nameofexecutable]] != -1]
}
# Find all MicroBlaze MCS instances in the project
# Return a list of lists with instance name and file name
proc mcs_find_instances {} {
set mcs_instances {}
set xco_filenames {}
if {[mcs_using_planahead]} {
set found [get_files -quiet -filter {IS_ENABLED==1} "*.xci"]
if {$found == ""} {
set found [get_files -quiet -filter {IS_ENABLED==1} "*.xco"]
if {[string first ".xco" $found] + 4 == [string length $found]} {
lappend xco_filenames "$found"
} else {
set xco_filenames $found
}
} elseif {[string first ".xci" $found] + 4 == [string length $found]} {
lappend xco_filenames [string map {.xci .xco} $found]
} else {
foreach item $found {
lappend xco_filenames [string map {.xci .xco} $item]
}
}
} else {
set found [search "*.xco"]
collection foreach item $found {
lappend xco_filenames [object name $item]
}
}
for {set index 0} {$index < [llength $xco_filenames]} {incr index} {
set xco_filename [lindex $xco_filenames $index]
# Check if the xco file is a MicroBlaze MCS IP Core
set xco_file [open $xco_filename "r"]
set xco_data [read $xco_file]
close $xco_file
if {[regexp {microblaze_mcs} $xco_data]} {
regexp {CSET component_name=([A-Za-z0-9_]*)} $xco_data match inst
lappend mcs_instances [list $xco_filename $inst]
}
}
return $mcs_instances
}
# Get current options
proc mcs_get_options {step} {
if {[mcs_using_planahead]} {
set dir [get_property directory [current_project]]
set name [get_property name [current_project]]
set run [current_run -quiet]
set psg_filename "[file join ${dir} ${name}.data runs ${run}.psg]"
if {[file exist $psg_filename]} {
set psg_file [open $psg_filename "r"]
set psg_data [read $psg_file]
close $psg_file
set search "<Step Id=\"[string tolower $step]\">"
append search {[\n\t ]*<Option Id="MoreOptsStr"><\!\[CDATA\[([^[]*)\]\]>}
if {[regexp $search $psg_data match option]} {
return $option
}
}
return ""
} else {
return [project get "Other $step Command Line Options"]
}
}
# Handle MicroBlaze BMM files: Create merged file and set ngdbuild options
proc microblaze_mcs_setup {} {
set procname "microblaze_mcs_setup"
# Find all MicroBlaze MCS instances in the project
set mcs_instances [mcs_find_instances]
set mcs_instances_length [llength $mcs_instances]
set cores "cores"
if {$mcs_instances_length == 1} { set cores "core" }
puts "$procname: Found $mcs_instances_length MicroBlaze MCS ${cores}."
if {$mcs_instances_length == 0} {
return
}
# Determine project directory
if {[mcs_using_planahead]} {
set projdir [get_property "directory" [current_project]]
} else {
set projdir [pwd]
}
# Handle BMM files: create merged file if more than one instance
if {$mcs_instances_length > 1} {
# Read all MicroBlaze MCS BMM files and merge the data
# Assign unique IDs (last number on ADDRESS_MAP line)
set bmm_data ""
set bmm_missing ""
set index 0
set bmm_id 100
foreach mcs_instance $mcs_instances {
set mcs_xco_filename [lindex $mcs_instance 0]
set mcs_instance_name [lindex $mcs_instance 1]
set dir "[file dirname $mcs_xco_filename]"
set bmm_filename "[file join $dir "${mcs_instance_name}.bmm"]"
if {[file exist $bmm_filename]} {
set bmm_file [open $bmm_filename "r"]
set bmm_file_data [read $bmm_file]
append bmm_data \
[regsub {MICROBLAZE-LE 100} $bmm_file_data "MICROBLAZE-LE $bmm_id"]
set bmm_id [expr $bmm_id + 100]
close $bmm_file
} else {
append bmm_missing "${mcs_instance_name}, "
}
incr index
}
if {[string length $bmm_missing] != 0} {
set bmm_missing [string trimright $bmm_missing ", "]
puts "$procname: ERROR: Could not find a BMM file for ${bmm_missing}. Please regenerate the MicroBlaze MCS instances."
return
}
# Determine merged BMM file name
set mcs_bmm_basename "microblaze_mcs_merged"
set mcs_bmm_filepath "[file join $projdir ${mcs_bmm_basename}.bmm]"
# Check if merged BMM file already exists
set bmm_file_data ""
if {[file exist $mcs_bmm_filepath]} {
set bmm_file [open $mcs_bmm_filepath "r"]
gets $bmm_file
set bmm_file_data [read $bmm_file]
close $bmm_file
}
# Output merged data on project directory level, if not found or changed
if {$bmm_file_data != $bmm_data} {
set bmm_file [open $mcs_bmm_filepath "w"]
set date [clock format [clock seconds]]
puts $bmm_file "// Automatically generated by \"microblaze_mcs_setup.tcl\" on $date"
puts -nonewline $bmm_file $bmm_data
close $bmm_file
if {[file exist $mcs_bmm_filepath]} {
puts "$procname: Modified \"${mcs_bmm_basename}.bmm\"."
} else {
puts "$procname: Created \"${mcs_bmm_basename}.bmm\"."
}
} else {
puts "$procname: Existing \"${mcs_bmm_basename}.bmm\" unchanged."
}
} else {
# Determine BMM file name for single instance
set mcs_xco_filename [lindex [lindex $mcs_instances 0] 0]
set mcs_bmm_basename [lindex [lindex $mcs_instances 0] 1]
set dir "[file dirname $mcs_xco_filename]"
set mcs_bmm_filepath "[file join $dir "${mcs_bmm_basename}.bmm"]"
if {! [file exist $mcs_bmm_filepath]} {
puts "$procname: ERROR: Could not find a BMM file for ${mcs_bmm_basename}. Please regenerate the MicroBlaze MCS instance."
return
}
}
# Determine new ngdbuild "-bm" option
if {[mcs_using_planahead]} {
set new_option "-bm \"$mcs_bmm_filepath\""
} else {
set mcs_bmm_relpath [regsub "${projdir}\[\\\/\]" "$mcs_bmm_filepath" {}]
set new_option "-bm \"$mcs_bmm_relpath\""
}
# Get current ngdbuild options
set options [mcs_get_options "Ngdbuild"]
# Strip and extract current ngdbuild "-bm" option
regsub {\-bm[^-]*} $options {} stripped_options
regsub {.*?(-bm[^-]).*} $options {\1} bm_option
# Set the ngdbuild "-bm" option if it has been modified
if {$new_option != $bm_option} {
set options [string trim "$stripped_options $new_option"]
if {[mcs_using_planahead]} {
set run [current_run -quiet]
config_run $run \
-quiet -program ngdbuild -option {More Options} -value $options
} else {
project set {Other Ngdbuild Command Line Options} $options
}
puts "$procname: Added \"-bm\" option for \"${mcs_bmm_basename}.bmm\" to ngdbuild command line options."
} else {
puts "$procname: Existing ngdbuild \"-bm\" option unchanged."
}
puts "$procname: Done."
}
# Handle MicroBlaze MCS ELF files: Run data2mem and set bitgen options
proc microblaze_mcs_data2mem {args} {
set procname "microblaze_mcs_data2mem"
# Find all MicroBlaze MCS instances in the project
set mcs_instances [mcs_find_instances]
set mcs_instances_length [llength $mcs_instances]
set cores "cores"
if {$mcs_instances_length == 1} { set cores "core" }
puts "$procname: Found $mcs_instances_length MicroBlaze MCS ${cores}."
if {$mcs_instances_length == 0} {
return
}
# Check arguments
if {[llength $args] > $mcs_instances_length} {
puts "$procname: ERROR: Too many arguments. At most $mcs_instances_length ELF files should be given."
return
}
# Determine device name
if {[mcs_using_planahead]} {
set device_name [get_property "part" [current_project]]
} else {
set device [project get "Device"]
set pack [project get "Package"]
set speed [project get "Speed"]
set device_name "${device}${pack}${speed}"
}
# Determine project directory
if {[mcs_using_planahead]} {
set projdir [get_property "directory" [current_project]]
} else {
set projdir [pwd]
}
# Find BMM file
if {$mcs_instances_length > 1} {
set mcs_bmm_basename "microblaze_mcs_merged"
set mcs_bmm_filepath "[file join $projdir ${mcs_bmm_basename}.bmm]"
set mcs_bd_bmm_filepath "[file join $projdir ${mcs_bmm_basename}_bd.bmm]"
if {! [file exist $mcs_bmm_filepath]} {
puts "$procname: ERROR: Could not find $mcs_bmm_basename.bmm. Please invoke \"microblaze_mcs_setup\" and implement the design."
return
}
} else {
set mcs_xco_filename [lindex [lindex $mcs_instances 0] 0]
set mcs_bmm_basename [lindex [lindex $mcs_instances 0] 1]
set dir "[file dirname $mcs_xco_filename]"
set mcs_bmm_filepath "[file join $dir "${mcs_bmm_basename}.bmm"]"
set mcs_bd_bmm_filepath "[file join $dir ${mcs_bmm_basename}_bd.bmm]"
if {! [file exist $mcs_bmm_filepath]} {
puts "$procname: ERROR: Could not find $mcs_bmm_basename.bmm. Please regenerate the MicroBlaze MCS instance."
return
}
}
# Create data2mem commands and bitgen "-bd" options
set bootloop_elf "mb_bootloop_le.elf"
set data2mem_cmd "-p $device_name"
set data2mem_bit "$data2mem_cmd -bm \"${mcs_bd_bmm_filepath}\""
set data2mem_sim "$data2mem_cmd -bm \"${mcs_bmm_filepath}\""
set msg_list {}
set new_options ""
foreach mcs_instance $mcs_instances arg $args {
set mcs_xco_filename [lindex $mcs_instance 0]
set mcs_instance_name [lindex $mcs_instance 1]
set mcs_xco_dir "[file dirname $mcs_xco_filename]"
set bmm_filename "[file join $mcs_xco_dir "${mcs_instance_name}.bmm"]"
# Use boot loop if no ELF file argument given
if {$arg == ""} {
set arg "[file join $mcs_xco_dir $bootloop_elf]"
}
# Check if ELF file exists
if {! [file exists $arg]} {
puts "$procname: ERROR: Could not find \"$arg\". Please make sure the file exists."
return
}
# Check if file is an ELF file (only allow .elf extension)
if {[file extension $arg] != ".elf"} {
puts "$procname: ERROR: \"$arg\" is not an ELF file."
return
}
# Must use absolute paths
if {[mcs_using_planahead] && [file pathtype $arg] == "relative"} {
set arg "[file join [pwd] $arg]"
}
# Add message
set tail [file tail $arg]
if {$tail == $bootloop_elf} {
lappend msg_list "$procname: Using bootloop for ${mcs_instance_name}"
} else {
lappend msg_list "$procname: Using \"$tail\" for ${mcs_instance_name}"
}
append new_options " -bd \"$arg\" tag $mcs_instance_name"
}
append data2mem_bit $new_options
append data2mem_sim $new_options
set new_options [string trimleft $new_options]
foreach msg $msg_list {
puts $msg
}
if {[mcs_using_planahead]} {
set run [current_run -quiet]
set rundir [get_property directory $run]
set top [get_property top [current_fileset] -quiet]
set bit_basename "[file join $rundir ${top}]"
# Create default project_1.sim/sim_1 simulation directory
set name [get_property name [current_project]]
set simdir "[file join ${projdir} ${name}.sim sim_1 behav]"
file mkdir $simdir
append data2mem_sim " -bx \"$simdir\""
} else {
set bit_basename "[project get {Output File Name}]"
append data2mem_sim " -bx ."
}
set bit_filename "${bit_basename}.bit"
set bitout_filename "${bit_basename}_out.bit"
append data2mem_bit " -bt \"$bit_filename\" -o b \"$bitout_filename\""
append data2mem_sim " -u"
# Get current bitgen options
set options [mcs_get_options "Bitgen"]
# Strip and extract current bitgen "-bd" options
regsub -all {\-bd[^-]*} $options {} stripped_options
regsub {.*?(-bd[^-])} $options {\1} bd_options
# Set the bitgen "-bd" options if they have changed
set bitfile_exists [file exists $bit_filename]
if {$new_options != $bd_options} {
set options [string trim "$stripped_options $new_options"]
if {[mcs_using_planahead]} {
if {! $bitfile_exists} {
set_property -quiet add_step Bitgen $run
}
config_run $run \
-quiet -program bitgen -option {More Options} -value $options
} else {
project set {Other Bitgen Command Line Options} $options
}
puts "$procname: Added \"-bd\" options to bitgen command line."
} else {
puts "$procname: Existing bitgen \"-bd\" options unchanged."
}
# Run data2mem to generate simulation files
set data2mem_exe [auto_execok "data2mem"]
puts "$procname: Running \"data2mem\" to create simulation files."
eval exec $data2mem_exe $data2mem_sim
# Run data2mem if bitstream and updated BMM exist
if {! $bitfile_exists} {
puts "$procname: Bitstream does not exist. Not running \"data2mem\" to update bitstream."
} elseif {! [file exist $mcs_bd_bmm_filepath]} {
puts "$procname: The file \"${mcs_bmm_basename}_bd.bmm\" does not exist. Not running \"data2mem\" to update bitstream."
} else {
puts "$procname: Running \"data2mem\" to update bitstream with software."
eval exec $data2mem_exe $data2mem_bit
# Replace original bitstream with data2mem output bitstream
if {[file exists ${bitout_filename}]} {
file copy -force "${bitout_filename}" "${bit_filename}"
file delete -force "${bitout_filename}"
}
}
puts "$procname: Done."
}
# Add help for Project Navigator
if {! [mcs_using_planahead]} {
if {[array names ::xilinx::short_help microblaze_mcs] == ""} {
set ::xilinx::short_help(microblaze_mcs) {Information about MicroBlaze MCS IP specific commands}
set ::xilinx::task_lib(microblaze_mcs) libTclTaskObject
proc ::xilinx::microblaze_mcs {args} {
set hlp ""
if {[llength $args] == 1 && [lindex $args 0] == "-help"} {
set hlp "
Tcl command: microblaze_mcs_setup \(perform MicroBlaze MCS specific setup\):
The microblaze_mcs_setup command is used to create a merged BMM file,
which defines the local memory of all MicroBlaze MCS instances in the
project \(if more than one instance), and set Translate process properties
to add the \"-bm\" option indicating the used BMM file.
The command should be invoked before running implementation, but after
the MicroBlaze MCS instance has been generated. It is automatically
invoked when sourcing the \"microblaze_mcs_setup.tcl\" script.
Tcl command: microblaze_mcs_data2mem \(update bit stream with software\):
The microblaze_mcs_data2mem command is used to update the bit stream
with one or more ELF files \(software programs\) given as arguments,
generate corresponding MEM files for simulation, and set Bitgen process
properties to add the \"-bd\" option indicating the ELF files.
If no argument is given, the bit stream is updated with the microblaze
boot loop ELF file, which ensures that the processor executes an infinite
loop.
The procedure should be invoked after the system has been implemented. It
must also be invoked again when an ELF file name is changed, or when the
content of an ELF file is changed. If the system is reimplemented without
changing the software, the procedure need not be invoked again, due to the
Bitgen \"-bd\" option.
"
}
set hlp
}
}
}
namespace export microblaze_mcs_setup microblaze_mcs_data2mem
}
namespace import microblaze_mcs::microblaze_mcs_setup microblaze_mcs::microblaze_mcs_data2mem
# Call the microblaze_mcs_setup procedure
microblaze_mcs_setup

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// BMM LOC annotation file.
//
// Release 14.6 - P.20131013, build 3.0.10 Apr 3, 2013
// Copyright (c) 1995-2020 Xilinx, Inc. All rights reserved.
///////////////////////////////////////////////////////////////////////////////
//
// Processor 'microblaze_mcs', ID 100, memory map.
//
///////////////////////////////////////////////////////////////////////////////
ADDRESS_MAP microblaze_mcs MICROBLAZE-LE 100
///////////////////////////////////////////////////////////////////////////////
//
// Processor 'microblaze_mcs' address space 'lmb_bram' 0x00000000:0x00003FFF (16 KBytes).
//
///////////////////////////////////////////////////////////////////////////////
ADDRESS_SPACE lmb_bram RAMB16 [0x00000000:0x00003FFF]
BUS_BLOCK
mcs_0/U0/lmb_bram_I/RAM_Inst/Using_B16_S4.The_BRAMs[0].RAMB16_S4_1 RAMB16 [31:28] [0:4095] INPUT = microblaze_mcs.lmb_bram_0.mem PLACED = X0Y26;
mcs_0/U0/lmb_bram_I/RAM_Inst/Using_B16_S4.The_BRAMs[1].RAMB16_S4_1 RAMB16 [27:24] [0:4095] INPUT = microblaze_mcs.lmb_bram_1.mem PLACED = X0Y20;
mcs_0/U0/lmb_bram_I/RAM_Inst/Using_B16_S4.The_BRAMs[2].RAMB16_S4_1 RAMB16 [23:20] [0:4095] INPUT = microblaze_mcs.lmb_bram_2.mem PLACED = X0Y24;
mcs_0/U0/lmb_bram_I/RAM_Inst/Using_B16_S4.The_BRAMs[3].RAMB16_S4_1 RAMB16 [19:16] [0:4095] INPUT = microblaze_mcs.lmb_bram_3.mem PLACED = X0Y18;
mcs_0/U0/lmb_bram_I/RAM_Inst/Using_B16_S4.The_BRAMs[4].RAMB16_S4_1 RAMB16 [15:12] [0:4095] INPUT = microblaze_mcs.lmb_bram_4.mem PLACED = X0Y30;
mcs_0/U0/lmb_bram_I/RAM_Inst/Using_B16_S4.The_BRAMs[5].RAMB16_S4_1 RAMB16 [11:8] [0:4095] INPUT = microblaze_mcs.lmb_bram_5.mem PLACED = X0Y22;
mcs_0/U0/lmb_bram_I/RAM_Inst/Using_B16_S4.The_BRAMs[6].RAMB16_S4_1 RAMB16 [7:4] [0:4095] INPUT = microblaze_mcs.lmb_bram_6.mem PLACED = X0Y28;
mcs_0/U0/lmb_bram_I/RAM_Inst/Using_B16_S4.The_BRAMs[7].RAMB16_S4_1 RAMB16 [3:0] [0:4095] INPUT = microblaze_mcs.lmb_bram_7.mem PLACED = X0Y16;
END_BUS_BLOCK;
END_ADDRESS_SPACE;
END_ADDRESS_MAP;

18
ipcore_dir/microblaze_mcs_flist.txt
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@ -1,18 +0,0 @@
# Output products list for <microblaze_mcs>
mb_bootloop_le.elf
microblaze_mcs/mb_bootloop_le.elf
microblaze_mcs/microblaze_mcs_setup.tcl
microblaze_mcs/system_template.tcl
microblaze_mcs.asy
microblaze_mcs.bmm
microblaze_mcs.gise
microblaze_mcs.ngc
microblaze_mcs.sym
microblaze_mcs.v
microblaze_mcs.veo
microblaze_mcs.xco
microblaze_mcs.xise
microblaze_mcs_flist.txt
microblaze_mcs_readme.txt
microblaze_mcs_sdk.xml
microblaze_mcs_setup.tcl

78
ipcore_dir/microblaze_mcs_readme.txt
View File

@ -1,78 +0,0 @@
The following files were generated for 'microblaze_mcs' in directory
/home/tim/Projects/z80/hdmi/ipcore_dir/
Generate XCO file:
CORE Generator input file containing the parameters used to generate a core.
* microblaze_mcs.xco
Generate Implementation Netlist:
Binary Xilinx implementation netlist files containing the information
required to implement the module in a Xilinx (R) FPGA.
* microblaze_mcs.ngc
Misc Files Generator:
Please see the core data sheet.
* microblaze_mcs/mb_bootloop_le.elf
* microblaze_mcs/microblaze_mcs_setup.tcl
* microblaze_mcs/system_template.tcl
Generate Script:
Execute microblaze_mcs_gen_script.tcl for generating bmm files and SDK HW
import file.
* mb_bootloop_le.elf
* microblaze_mcs.bmm
* microblaze_mcs_sdk.xml
* microblaze_mcs_setup.tcl
Generate Instantiation Templates:
Template files containing code that can be used as a model for instantiating
a CORE Generator module in an HDL design.
* microblaze_mcs.veo
RTL Simulation Model Generator:
Please see the core data sheet.
* microblaze_mcs.v
Simulation Netlist Update Script:
Execute microblaze_mcs_sim_script.tcl to add INIT_FILE filenames to
simulation netlist.
* microblaze_mcs.v
Deliver IP Symbol:
Graphical symbol information file. Used by the ISE tools and some third party
tools to create a symbol representing the core.
* microblaze_mcs.asy
SYM file generator:
Generate a SYM file for compatibility with legacy flows
* microblaze_mcs.sym
Synthesis ISE Generator:
Please see the core data sheet.
* microblaze_mcs.gise
* microblaze_mcs.xise
Deliver Readme:
Readme file for the IP.
* microblaze_mcs_readme.txt
Generate FLIST file:
Text file listing all of the output files produced when a customized core was
generated in the CORE Generator.
* microblaze_mcs_flist.txt
Please see the Xilinx CORE Generator online help for further details on
generated files and how to use them.

5833
ipcore_dir/microblaze_mcs_sdk.xml
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File diff suppressed because it is too large Load Diff

539
ipcore_dir/microblaze_mcs_setup.tcl
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@ -1,539 +0,0 @@
###############################################################################
##
## (c) Copyright 2012 Xilinx, Inc. All rights reserved.
##
## This file contains confidential and proprietary information
## of Xilinx, Inc. and is protected under U.S. and
## international copyright and other intellectual property
## laws.
##
## DISCLAIMER
## This disclaimer is not a license and does not grant any
## rights to the materials distributed herewith. Except as
## otherwise provided in a valid license issued to you by
## Xilinx, and to the maximum extent permitted by applicable
## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
## (2) Xilinx shall not be liable (whether in contract or tort,
## including negligence, or under any other theory of
## liability) for any loss or damage of any kind or nature
## related to, arising under or in connection with these
## materials, including for any direct, or any indirect,
## special, incidental, or consequential loss or damage
## (including loss of data, profits, goodwill, or any type of
## loss or damage suffered as a result of any action brought
## by a third party) even if such damage or loss was
## reasonably foreseeable or Xilinx had been advised of the
## possibility of the same.
##
## CRITICAL APPLICATIONS
## Xilinx products are not designed or intended to be fail-
## safe, or for use in any application requiring fail-safe
## performance, such as life-support or safety devices or
## systems, Class III medical devices, nuclear facilities,
## applications related to the deployment of airbags, or any
## other applications that could lead to death, personal
## injury, or severe property or environmental damage
## (individually and collectively, "Critical
## Applications"). Customer assumes the sole risk and
## liability of any use of Xilinx products in Critical
## Applications, subject only to applicable laws and
## regulations governing limitations on product liability.
##
## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
## PART OF THIS FILE AT ALL TIMES.
##
###############################################################################
##
## microblaze_mcs_setup.tcl
##
###############################################################################
#
# This script should be sourced after CORE Generator has been used to generate
# a MicroBlaze MCS instance, either when creating a new or changing an existing
# instance.
#
# Run the script in the PlanAhead Tcl Console by typically using:
#
# source -notrace \
# project_1.srcs/sources_1/ip/microblaze_mcs_v1_4_0/microblaze_mcs_setup.tcl
#
# Run the script in the Project Navigator Tcl Console by typically using:
#
# Command> source ipcore_dir/microblaze_mcs_setup.tcl
#
# Use the menu command "View -> Panels -> Tcl Console" to show the Tcl Console
# in the Project Navigator, if it is not visible.
#
###############################################################################
#
# This script contains two exported Tcl procedures:
#
# o The first, "microblaze_mcs_setup", is used to create a merged BMM file,
# which defines the local memory of all MicroBlaze MCS instances in the
# project (if more than one instance), and set Translate process properties
# to add the "-bm" option indicating the used BMM file.
#
# The procedure is automatically invoked when sourcing this script, but
# can also subsequently be invoked with "microblaze_mcs_setup".
#
# The procedure should be invoked before running implementation, but after
# the MicroBlaze MCS instance has been generated.
#
# o The second, "microblaze_mcs_data2mem", is used to update the bit stream
# with one or more ELF files (software programs) given as arguments, generate
# corresponding MEM files for simulation, and set Bitgen process properties
# to add the "-bd" option indicating the ELF files.
#
# If no argument is given, the bit stream is updated with the microblaze
# boot loop ELF file, which ensures that the processor executes an infinite
# loop.
#
# The procedure should be invoked after the system has been implemented. It
# must also be invoked again when an ELF file name is changed, or when the
# content of an ELF file is changed. If the system is reimplemented without
# changing the software, the procedure need not be invoked again, due to the
# Bitgen "-bd" option.
#
###############################################################################
namespace eval microblaze_mcs {
# Determine if using planAhead or Project Navigator
proc mcs_using_planahead {} {
return [expr [string first "planAhead" [info nameofexecutable]] != -1]
}
# Find all MicroBlaze MCS instances in the project
# Return a list of lists with instance name and file name
proc mcs_find_instances {} {
set mcs_instances {}
set xco_filenames {}
if {[mcs_using_planahead]} {
set found [get_files -quiet -filter {IS_ENABLED==1} "*.xci"]
if {$found == ""} {
set found [get_files -quiet -filter {IS_ENABLED==1} "*.xco"]
if {[string first ".xco" $found] + 4 == [string length $found]} {
lappend xco_filenames "$found"
} else {
set xco_filenames $found
}
} elseif {[string first ".xci" $found] + 4 == [string length $found]} {
lappend xco_filenames [string map {.xci .xco} $found]
} else {
foreach item $found {
lappend xco_filenames [string map {.xci .xco} $item]
}
}
} else {
set found [search "*.xco"]
collection foreach item $found {
lappend xco_filenames [object name $item]
}
}
for {set index 0} {$index < [llength $xco_filenames]} {incr index} {
set xco_filename [lindex $xco_filenames $index]
# Check if the xco file is a MicroBlaze MCS IP Core
set xco_file [open $xco_filename "r"]
set xco_data [read $xco_file]
close $xco_file
if {[regexp {microblaze_mcs} $xco_data]} {
regexp {CSET component_name=([A-Za-z0-9_]*)} $xco_data match inst
lappend mcs_instances [list $xco_filename $inst]
}
}
return $mcs_instances
}
# Get current options
proc mcs_get_options {step} {
if {[mcs_using_planahead]} {
set dir [get_property directory [current_project]]
set name [get_property name [current_project]]
set run [current_run -quiet]
set psg_filename "[file join ${dir} ${name}.data runs ${run}.psg]"
if {[file exist $psg_filename]} {
set psg_file [open $psg_filename "r"]
set psg_data [read $psg_file]
close $psg_file
set search "<Step Id=\"[string tolower $step]\">"
append search {[\n\t ]*<Option Id="MoreOptsStr"><\!\[CDATA\[([^[]*)\]\]>}
if {[regexp $search $psg_data match option]} {
return $option
}
}
return ""
} else {
return [project get "Other $step Command Line Options"]
}
}
# Handle MicroBlaze BMM files: Create merged file and set ngdbuild options
proc microblaze_mcs_setup {} {
set procname "microblaze_mcs_setup"
# Find all MicroBlaze MCS instances in the project
set mcs_instances [mcs_find_instances]
set mcs_instances_length [llength $mcs_instances]
set cores "cores"
if {$mcs_instances_length == 1} { set cores "core" }
puts "$procname: Found $mcs_instances_length MicroBlaze MCS ${cores}."
if {$mcs_instances_length == 0} {
return
}
# Determine project directory
if {[mcs_using_planahead]} {
set projdir [get_property "directory" [current_project]]
} else {
set projdir [pwd]
}
# Handle BMM files: create merged file if more than one instance
if {$mcs_instances_length > 1} {
# Read all MicroBlaze MCS BMM files and merge the data
# Assign unique IDs (last number on ADDRESS_MAP line)
set bmm_data ""
set bmm_missing ""
set index 0
set bmm_id 100
foreach mcs_instance $mcs_instances {
set mcs_xco_filename [lindex $mcs_instance 0]
set mcs_instance_name [lindex $mcs_instance 1]
set dir "[file dirname $mcs_xco_filename]"
set bmm_filename "[file join $dir "${mcs_instance_name}.bmm"]"
if {[file exist $bmm_filename]} {
set bmm_file [open $bmm_filename "r"]
set bmm_file_data [read $bmm_file]
append bmm_data \
[regsub {MICROBLAZE-LE 100} $bmm_file_data "MICROBLAZE-LE $bmm_id"]
set bmm_id [expr $bmm_id + 100]
close $bmm_file
} else {
append bmm_missing "${mcs_instance_name}, "
}
incr index
}
if {[string length $bmm_missing] != 0} {
set bmm_missing [string trimright $bmm_missing ", "]
puts "$procname: ERROR: Could not find a BMM file for ${bmm_missing}. Please regenerate the MicroBlaze MCS instances."
return
}
# Determine merged BMM file name
set mcs_bmm_basename "microblaze_mcs_merged"
set mcs_bmm_filepath "[file join $projdir ${mcs_bmm_basename}.bmm]"
# Check if merged BMM file already exists
set bmm_file_data ""
if {[file exist $mcs_bmm_filepath]} {
set bmm_file [open $mcs_bmm_filepath "r"]
gets $bmm_file
set bmm_file_data [read $bmm_file]
close $bmm_file
}
# Output merged data on project directory level, if not found or changed
if {$bmm_file_data != $bmm_data} {
set bmm_file [open $mcs_bmm_filepath "w"]
set date [clock format [clock seconds]]
puts $bmm_file "// Automatically generated by \"microblaze_mcs_setup.tcl\" on $date"
puts -nonewline $bmm_file $bmm_data
close $bmm_file
if {[file exist $mcs_bmm_filepath]} {
puts "$procname: Modified \"${mcs_bmm_basename}.bmm\"."
} else {
puts "$procname: Created \"${mcs_bmm_basename}.bmm\"."
}
} else {
puts "$procname: Existing \"${mcs_bmm_basename}.bmm\" unchanged."
}
} else {
# Determine BMM file name for single instance
set mcs_xco_filename [lindex [lindex $mcs_instances 0] 0]
set mcs_bmm_basename [lindex [lindex $mcs_instances 0] 1]
set dir "[file dirname $mcs_xco_filename]"
set mcs_bmm_filepath "[file join $dir "${mcs_bmm_basename}.bmm"]"
if {! [file exist $mcs_bmm_filepath]} {
puts "$procname: ERROR: Could not find a BMM file for ${mcs_bmm_basename}. Please regenerate the MicroBlaze MCS instance."
return
}
}
# Determine new ngdbuild "-bm" option
if {[mcs_using_planahead]} {
set new_option "-bm \"$mcs_bmm_filepath\""
} else {
set mcs_bmm_relpath [regsub "${projdir}\[\\\/\]" "$mcs_bmm_filepath" {}]
set new_option "-bm \"$mcs_bmm_relpath\""
}
# Get current ngdbuild options
set options [mcs_get_options "Ngdbuild"]
# Strip and extract current ngdbuild "-bm" option
regsub {\-bm[^-]*} $options {} stripped_options
regsub {.*?(-bm[^-]).*} $options {\1} bm_option
# Set the ngdbuild "-bm" option if it has been modified
if {$new_option != $bm_option} {
set options [string trim "$stripped_options $new_option"]
if {[mcs_using_planahead]} {
set run [current_run -quiet]
config_run $run \
-quiet -program ngdbuild -option {More Options} -value $options
} else {
project set {Other Ngdbuild Command Line Options} $options
}
puts "$procname: Added \"-bm\" option for \"${mcs_bmm_basename}.bmm\" to ngdbuild command line options."
} else {
puts "$procname: Existing ngdbuild \"-bm\" option unchanged."
}
puts "$procname: Done."
}
# Handle MicroBlaze MCS ELF files: Run data2mem and set bitgen options
proc microblaze_mcs_data2mem {args} {
set procname "microblaze_mcs_data2mem"
# Find all MicroBlaze MCS instances in the project
set mcs_instances [mcs_find_instances]
set mcs_instances_length [llength $mcs_instances]
set cores "cores"
if {$mcs_instances_length == 1} { set cores "core" }
puts "$procname: Found $mcs_instances_length MicroBlaze MCS ${cores}."
if {$mcs_instances_length == 0} {
return
}
# Check arguments
if {[llength $args] > $mcs_instances_length} {
puts "$procname: ERROR: Too many arguments. At most $mcs_instances_length ELF files should be given."
return
}
# Determine device name
if {[mcs_using_planahead]} {
set device_name [get_property "part" [current_project]]
} else {
set device [project get "Device"]
set pack [project get "Package"]
set speed [project get "Speed"]
set device_name "${device}${pack}${speed}"
}
# Determine project directory
if {[mcs_using_planahead]} {
set projdir [get_property "directory" [current_project]]
} else {
set projdir [pwd]
}
# Find BMM file
if {$mcs_instances_length > 1} {
set mcs_bmm_basename "microblaze_mcs_merged"
set mcs_bmm_filepath "[file join $projdir ${mcs_bmm_basename}.bmm]"
set mcs_bd_bmm_filepath "[file join $projdir ${mcs_bmm_basename}_bd.bmm]"
if {! [file exist $mcs_bmm_filepath]} {
puts "$procname: ERROR: Could not find $mcs_bmm_basename.bmm. Please invoke \"microblaze_mcs_setup\" and implement the design."
return
}
} else {
set mcs_xco_filename [lindex [lindex $mcs_instances 0] 0]
set mcs_bmm_basename [lindex [lindex $mcs_instances 0] 1]
set dir "[file dirname $mcs_xco_filename]"
set mcs_bmm_filepath "[file join $dir "${mcs_bmm_basename}.bmm"]"
set mcs_bd_bmm_filepath "[file join $dir ${mcs_bmm_basename}_bd.bmm]"
if {! [file exist $mcs_bmm_filepath]} {
puts "$procname: ERROR: Could not find $mcs_bmm_basename.bmm. Please regenerate the MicroBlaze MCS instance."
return
}
}
# Create data2mem commands and bitgen "-bd" options
set bootloop_elf "mb_bootloop_le.elf"
set data2mem_cmd "-p $device_name"
set data2mem_bit "$data2mem_cmd -bm \"${mcs_bd_bmm_filepath}\""
set data2mem_sim "$data2mem_cmd -bm \"${mcs_bmm_filepath}\""
set msg_list {}
set new_options ""
foreach mcs_instance $mcs_instances arg $args {
set mcs_xco_filename [lindex $mcs_instance 0]
set mcs_instance_name [lindex $mcs_instance 1]
set mcs_xco_dir "[file dirname $mcs_xco_filename]"
set bmm_filename "[file join $mcs_xco_dir "${mcs_instance_name}.bmm"]"
# Use boot loop if no ELF file argument given
if {$arg == ""} {
set arg "[file join $mcs_xco_dir $bootloop_elf]"
}
# Check if ELF file exists
if {! [file exists $arg]} {
puts "$procname: ERROR: Could not find \"$arg\". Please make sure the file exists."
return
}
# Check if file is an ELF file (only allow .elf extension)
if {[file extension $arg] != ".elf"} {
puts "$procname: ERROR: \"$arg\" is not an ELF file."
return
}
# Must use absolute paths
if {[mcs_using_planahead] && [file pathtype $arg] == "relative"} {
set arg "[file join [pwd] $arg]"
}
# Add message
set tail [file tail $arg]
if {$tail == $bootloop_elf} {
lappend msg_list "$procname: Using bootloop for ${mcs_instance_name}"
} else {
lappend msg_list "$procname: Using \"$tail\" for ${mcs_instance_name}"
}
append new_options " -bd \"$arg\" tag $mcs_instance_name"
}
append data2mem_bit $new_options
append data2mem_sim $new_options
set new_options [string trimleft $new_options]
foreach msg $msg_list {
puts $msg
}
if {[mcs_using_planahead]} {
set run [current_run -quiet]
set rundir [get_property directory $run]
set top [get_property top [current_fileset] -quiet]
set bit_basename "[file join $rundir ${top}]"
# Create default project_1.sim/sim_1 simulation directory
set name [get_property name [current_project]]
set simdir "[file join ${projdir} ${name}.sim sim_1 behav]"
file mkdir $simdir
append data2mem_sim " -bx \"$simdir\""
} else {
set bit_basename "[project get {Output File Name}]"
append data2mem_sim " -bx ."
}
set bit_filename "${bit_basename}.bit"
set bitout_filename "${bit_basename}_out.bit"
append data2mem_bit " -bt \"$bit_filename\" -o b \"$bitout_filename\""
append data2mem_sim " -u"
# Get current bitgen options
set options [mcs_get_options "Bitgen"]
# Strip and extract current bitgen "-bd" options
regsub -all {\-bd[^-]*} $options {} stripped_options
regsub {.*?(-bd[^-])} $options {\1} bd_options
# Set the bitgen "-bd" options if they have changed
set bitfile_exists [file exists $bit_filename]
if {$new_options != $bd_options} {
set options [string trim "$stripped_options $new_options"]
if {[mcs_using_planahead]} {
if {! $bitfile_exists} {
set_property -quiet add_step Bitgen $run
}
config_run $run \
-quiet -program bitgen -option {More Options} -value $options
} else {
project set {Other Bitgen Command Line Options} $options
}
puts "$procname: Added \"-bd\" options to bitgen command line."
} else {
puts "$procname: Existing bitgen \"-bd\" options unchanged."
}
# Run data2mem to generate simulation files
set data2mem_exe [auto_execok "data2mem"]
puts "$procname: Running \"data2mem\" to create simulation files."
eval exec $data2mem_exe $data2mem_sim
# Run data2mem if bitstream and updated BMM exist
if {! $bitfile_exists} {
puts "$procname: Bitstream does not exist. Not running \"data2mem\" to update bitstream."
} elseif {! [file exist $mcs_bd_bmm_filepath]} {
puts "$procname: The file \"${mcs_bmm_basename}_bd.bmm\" does not exist. Not running \"data2mem\" to update bitstream."
} else {
puts "$procname: Running \"data2mem\" to update bitstream with software."
eval exec $data2mem_exe $data2mem_bit
# Replace original bitstream with data2mem output bitstream
if {[file exists ${bitout_filename}]} {
file copy -force "${bitout_filename}" "${bit_filename}"
file delete -force "${bitout_filename}"
}
}
puts "$procname: Done."
}
# Add help for Project Navigator
if {! [mcs_using_planahead]} {
if {[array names ::xilinx::short_help microblaze_mcs] == ""} {
set ::xilinx::short_help(microblaze_mcs) {Information about MicroBlaze MCS IP specific commands}
set ::xilinx::task_lib(microblaze_mcs) libTclTaskObject
proc ::xilinx::microblaze_mcs {args} {
set hlp ""
if {[llength $args] == 1 && [lindex $args 0] == "-help"} {
set hlp "
Tcl command: microblaze_mcs_setup \(perform MicroBlaze MCS specific setup\):
The microblaze_mcs_setup command is used to create a merged BMM file,
which defines the local memory of all MicroBlaze MCS instances in the
project \(if more than one instance), and set Translate process properties
to add the \"-bm\" option indicating the used BMM file.
The command should be invoked before running implementation, but after
the MicroBlaze MCS instance has been generated. It is automatically
invoked when sourcing the \"microblaze_mcs_setup.tcl\" script.
Tcl command: microblaze_mcs_data2mem \(update bit stream with software\):
The microblaze_mcs_data2mem command is used to update the bit stream
with one or more ELF files \(software programs\) given as arguments,
generate corresponding MEM files for simulation, and set Bitgen process
properties to add the \"-bd\" option indicating the ELF files.
If no argument is given, the bit stream is updated with the microblaze
boot loop ELF file, which ensures that the processor executes an infinite
loop.
The procedure should be invoked after the system has been implemented. It
must also be invoked again when an ELF file name is changed, or when the
content of an ELF file is changed. If the system is reimplemented without
changing the software, the procedure need not be invoked again, due to the
Bitgen \"-bd\" option.
"
}
set hlp
}
}
}
namespace export microblaze_mcs_setup microblaze_mcs_data2mem
}
namespace import microblaze_mcs::microblaze_mcs_setup microblaze_mcs::microblaze_mcs_data2mem
# Call the microblaze_mcs_setup procedure
microblaze_mcs_setup

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ipcore_dir/tmp/customization_gui.0.015686198145.out
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SET_FLAG DEBUG FALSE
SET_FLAG MODE BATCH
SET_FLAG STANDALONE_MODE FALSE
SET_PREFERENCE devicefamily spartan6
SET_PREFERENCE device xc6slx9
SET_PREFERENCE speedgrade -2
SET_PREFERENCE package tqg144
SET_PREFERENCE verilogsim true
SET_PREFERENCE vhdlsim false
SET_PREFERENCE simulationfiles Behavioral
SET_PREFERENCE busformat BusFormatAngleBracketNotRipped
SET_PREFERENCE outputdirectory /home/tim/Projects/fpga/micro_test/ipcore_dir/
SET_PREFERENCE workingdirectory /home/tim/Projects/fpga/micro_test/ipcore_dir/tmp/
SET_PREFERENCE subworkingdirectory /home/tim/Projects/fpga/micro_test/ipcore_dir/tmp/_cg/
SET_PREFERENCE transientdirectory /home/tim/Projects/fpga/micro_test/ipcore_dir/tmp/_cg/_dbg/
SET_PREFERENCE designentry Verilog
SET_PREFERENCE flowvendor Other
SET_PREFERENCE addpads false
SET_PREFERENCE projectname coregen
SET_PREFERENCE formalverification false
SET_PREFERENCE asysymbol false
SET_PREFERENCE implementationfiletype Ngc
SET_PREFERENCE foundationsym false
SET_PREFERENCE createndf false
SET_PREFERENCE removerpms false
SET_PARAMETER Component_Name hdmi_clk
SET_PARAMETER Use_Freq_Synth true
SET_PARAMETER Use_Phase_Alignment false
SET_PARAMETER Use_Min_Power false
SET_PARAMETER Use_Dyn_Phase_Shift false
SET_PARAMETER Use_Dyn_Reconfig false
SET_PARAMETER Jitter_Sel No_Jitter
SET_PARAMETER Use_Spread_Spectrum false
SET_PARAMETER Use_Spread_Spectrum_1 false
SET_PARAMETER Prim_In_Freq 50
SET_PARAMETER In_Freq_Units Units_MHz
SET_PARAMETER In_Jitter_Units Units_UI
SET_PARAMETER Relative_Inclk REL_PRIMARY
SET_PARAMETER Secondary_In_Freq 100.000
SET_PARAMETER Jitter_Options UI
SET_PARAMETER Clkin1_UI_Jitter 0.010
SET_PARAMETER Clkin2_UI_Jitter 0.010
SET_PARAMETER Prim_In_Jitter 0.010
SET_PARAMETER Secondary_In_Jitter 0.010
SET_PARAMETER Clkin1_Jitter_Ps 200.0
SET_PARAMETER Clkin2_Jitter_Ps 100.0
SET_PARAMETER Clkout2_Used true
SET_PARAMETER Clkout3_Used false
SET_PARAMETER Clkout4_Used false
SET_PARAMETER Clkout5_Used false
SET_PARAMETER Clkout6_Used false
SET_PARAMETER Clkout7_Used false
SET_PARAMETER Num_Out_Clks 2
SET_PARAMETER Clk_Out1_Use_Fine_Ps_GUI false
SET_PARAMETER Clk_Out2_Use_Fine_Ps_GUI false
SET_PARAMETER Clk_Out3_Use_Fine_Ps_GUI false
SET_PARAMETER Clk_Out4_Use_Fine_Ps_GUI false
SET_PARAMETER Clk_Out5_Use_Fine_Ps_GUI false
SET_PARAMETER Clk_Out6_Use_Fine_Ps_GUI false
SET_PARAMETER Clk_Out7_Use_Fine_Ps_GUI false
SET_PARAMETER primary_port CLK_IN1
SET_PARAMETER CLK_OUT1_port CLK_OUT1
SET_PARAMETER CLK_OUT2_port CLK_OUT2
SET_PARAMETER CLK_OUT3_port CLK_OUT3
SET_PARAMETER CLK_OUT4_port CLK_OUT4
SET_PARAMETER CLK_OUT5_port CLK_OUT5
SET_PARAMETER CLK_OUT6_port CLK_OUT6
SET_PARAMETER CLK_OUT7_port CLK_OUT7
SET_PARAMETER DADDR_port DADDR
SET_PARAMETER DCLK_port DCLK
SET_PARAMETER DRDY_port DRDY
SET_PARAMETER DWE_port DWE
SET_PARAMETER DIN_port DIN
SET_PARAMETER DOUT_port DOUT
SET_PARAMETER DEN_port DEN
SET_PARAMETER PSCLK_port PSCLK
SET_PARAMETER PSEN_port PSEN
SET_PARAMETER PSINCDEC_port PSINCDEC
SET_PARAMETER PSDONE_port PSDONE
SET_PARAMETER Clkout1_Requested_Out_Freq 75
SET_PARAMETER Clkout1_Requested_Phase 0.000
SET_PARAMETER Clkout1_Requested_Duty_Cycle 50.000
SET_PARAMETER Clkout2_Requested_Out_Freq 150
SET_PARAMETER Clkout2_Requested_Phase 0.000
SET_PARAMETER Clkout2_Requested_Duty_Cycle 50.000
SET_PARAMETER Clkout3_Requested_Out_Freq 100.000
SET_PARAMETER Clkout3_Requested_Phase 0.000
SET_PARAMETER Clkout3_Requested_Duty_Cycle 50.000
SET_PARAMETER Clkout4_Requested_Out_Freq 100.000
SET_PARAMETER Clkout4_Requested_Phase 0.000
SET_PARAMETER Clkout4_Requested_Duty_Cycle 50.000
SET_PARAMETER Clkout5_Requested_Out_Freq 100.000
SET_PARAMETER Clkout5_Requested_Phase 0.000
SET_PARAMETER Clkout5_Requested_Duty_Cycle 50.000
SET_PARAMETER Clkout6_Requested_Out_Freq 100.000
SET_PARAMETER Clkout6_Requested_Phase 0.000
SET_PARAMETER Clkout6_Requested_Duty_Cycle 50.000
SET_PARAMETER Clkout7_Requested_Out_Freq 100.000
SET_PARAMETER Clkout7_Requested_Phase 0.000
SET_PARAMETER Clkout7_Requested_Duty_Cycle 50.000
SET_PARAMETER Use_Max_I_Jitter false
SET_PARAMETER Use_Min_O_Jitter false
SET_PARAMETER Prim_Source Single_ended_clock_capable_pin
SET_PARAMETER Use_Inclk_Switchover false
SET_PARAMETER secondary_port CLK_IN2
SET_PARAMETER Secondary_Source Single_ended_clock_capable_pin
SET_PARAMETER Clkout1_Drives BUFG
SET_PARAMETER Clkout2_Drives BUFG
SET_PARAMETER Clkout3_Drives BUFG
SET_PARAMETER Clkout4_Drives BUFG
SET_PARAMETER Clkout5_Drives BUFG
SET_PARAMETER Clkout6_Drives BUFG
SET_PARAMETER Clkout7_Drives BUFG
SET_PARAMETER Feedback_Source FDBK_AUTO
SET_PARAMETER Clkfb_In_Signaling SINGLE
SET_PARAMETER CLKFB_IN_port CLKFB_IN
SET_PARAMETER CLKFB_IN_P_port CLKFB_IN_P
SET_PARAMETER CLKFB_IN_N_port CLKFB_IN_N
SET_PARAMETER CLKFB_OUT_port CLKFB_OUT
SET_PARAMETER CLKFB_OUT_P_port CLKFB_OUT_P
SET_PARAMETER CLKFB_OUT_N_port CLKFB_OUT_N
SET_PARAMETER Platform lin64
SET_PARAMETER Summary_Strings empty
SET_PARAMETER Use_Locked false
SET_PARAMETER calc_done DONE
SET_PARAMETER Use_Reset false
SET_PARAMETER Use_Power_Down false
SET_PARAMETER Use_Status false
SET_PARAMETER Use_Freeze false
SET_PARAMETER Use_Clk_Valid false
SET_PARAMETER Use_Inclk_Stopped false
SET_PARAMETER Use_Clkfb_Stopped false
SET_PARAMETER RESET_port RESET
SET_PARAMETER LOCKED_port LOCKED
SET_PARAMETER Power_Down_port POWER_DOWN
SET_PARAMETER CLK_VALID_port CLK_VALID
SET_PARAMETER STATUS_port STATUS
SET_PARAMETER CLK_IN_SEL_port CLK_IN_SEL
SET_PARAMETER INPUT_CLK_STOPPED_port INPUT_CLK_STOPPED
SET_PARAMETER CLKFB_STOPPED_port CLKFB_STOPPED
SET_PARAMETER Override_Mmcm false
SET_PARAMETER Mmcm_Notes None
SET_PARAMETER Mmcm_Divclk_Divide 1
SET_PARAMETER Mmcm_Bandwidth OPTIMIZED
SET_PARAMETER Mmcm_Clkfbout_Mult_F 4.000
SET_PARAMETER Mmcm_Clkfbout_Phase 0.000
SET_PARAMETER Mmcm_Clkfbout_Use_Fine_Ps false
SET_PARAMETER Mmcm_Clkin1_Period 10.000
SET_PARAMETER Mmcm_Clkin2_Period 10.000
SET_PARAMETER Mmcm_Clkout4_Cascade false
SET_PARAMETER Mmcm_Clock_Hold false
SET_PARAMETER Mmcm_Compensation ZHOLD
SET_PARAMETER Mmcm_Ref_Jitter1 0.010
SET_PARAMETER Mmcm_Ref_Jitter2 0.010
SET_PARAMETER Mmcm_Startup_Wait false
SET_PARAMETER Mmcm_Clkout0_Divide_F 4.000
SET_PARAMETER Mmcm_Clkout0_Duty_Cycle 0.500
SET_PARAMETER Mmcm_Clkout0_Phase 0.000
SET_PARAMETER Mmcm_Clkout0_Use_Fine_Ps false
SET_PARAMETER Mmcm_Clkout1_Divide 1
SET_PARAMETER Mmcm_Clkout1_Duty_Cycle 0.500
SET_PARAMETER Mmcm_Clkout1_Phase 0.000
SET_PARAMETER Mmcm_Clkout1_Use_Fine_Ps false
SET_PARAMETER Mmcm_Clkout2_Divide 1
SET_PARAMETER Mmcm_Clkout2_Duty_Cycle 0.500
SET_PARAMETER Mmcm_Clkout2_Phase 0.000
SET_PARAMETER Mmcm_Clkout2_Use_Fine_Ps false
SET_PARAMETER Mmcm_Clkout3_Divide 1
SET_PARAMETER Mmcm_Clkout3_Duty_Cycle 0.500
SET_PARAMETER Mmcm_Clkout3_Phase 0.000
SET_PARAMETER Mmcm_Clkout3_Use_Fine_Ps false
SET_PARAMETER Mmcm_Clkout4_Divide 1
SET_PARAMETER Mmcm_Clkout4_Duty_Cycle 0.500
SET_PARAMETER Mmcm_Clkout4_Phase 0.000
SET_PARAMETER Mmcm_Clkout4_Use_Fine_Ps false
SET_PARAMETER Mmcm_Clkout5_Divide 1
SET_PARAMETER Mmcm_Clkout5_Duty_Cycle 0.500
SET_PARAMETER Mmcm_Clkout5_Phase 0.000
SET_PARAMETER Mmcm_Clkout5_Use_Fine_Ps false
SET_PARAMETER Mmcm_Clkout6_Divide 1
SET_PARAMETER Mmcm_Clkout6_Duty_Cycle 0.500
SET_PARAMETER Mmcm_Clkout6_Phase 0.000
SET_PARAMETER Mmcm_Clkout6_Use_Fine_Ps false
SET_PARAMETER Override_Dcm false
SET_PARAMETER Dcm_Notes None
SET_PARAMETER Dcm_Clkdv_Divide 2.0
SET_PARAMETER Dcm_Clkfx_Divide 2
SET_PARAMETER Dcm_Clkfx_Multiply 3
SET_PARAMETER Dcm_Clkin_Divide_By_2 false
SET_PARAMETER Dcm_Clkin_Period 20.000
SET_PARAMETER Dcm_Clkout_Phase_Shift NONE
SET_PARAMETER Dcm_Deskew_Adjust SYSTEM_SYNCHRONOUS
SET_PARAMETER Dcm_Phase_Shift 0
SET_PARAMETER Dcm_Clk_Feedback NONE
SET_PARAMETER Dcm_Startup_Wait false
SET_PARAMETER Dcm_Clk_Out1_Port CLKFX
SET_PARAMETER Dcm_Clk_Out2_Port CLK0
SET_PARAMETER Dcm_Clk_Out3_Port CLK0
SET_PARAMETER Dcm_Clk_Out4_Port CLK0
SET_PARAMETER Dcm_Clk_Out5_Port CLK0
SET_PARAMETER Dcm_Clk_Out6_Port CLK0
SET_PARAMETER Override_Dcm_Clkgen false
SET_PARAMETER Dcm_Clkgen_Notes None
SET_PARAMETER Dcm_Clkgen_Clkfx_Divide 1
SET_PARAMETER Dcm_Clkgen_Clkfx_Multiply 4
SET_PARAMETER Dcm_Clkgen_Clkfxdv_Divide 2
SET_PARAMETER Dcm_Clkgen_Clkfx_Md_Max 0.000
SET_PARAMETER Dcm_Clkgen_Startup_Wait false
SET_PARAMETER Dcm_Clkgen_Clkin_Period 10.000
SET_PARAMETER Dcm_Clkgen_Spread_Spectrum NONE
SET_PARAMETER Dcm_Clkgen_Clk_Out1_Port CLKFX
SET_PARAMETER Dcm_Clkgen_Clk_Out2_Port CLKFX
SET_PARAMETER Dcm_Clkgen_Clk_Out3_Port CLKFX
SET_PARAMETER Override_Pll false
SET_PARAMETER Pll_Notes None
SET_PARAMETER Pll_Bandwidth OPTIMIZED
SET_PARAMETER Pll_Clkfbout_Mult 9
SET_PARAMETER Pll_Clkfbout_Phase 0.000
SET_PARAMETER Pll_Clk_Feedback CLKFBOUT
SET_PARAMETER Pll_Divclk_Divide 1
SET_PARAMETER Pll_Clkin_Period 20.000
SET_PARAMETER Pll_Compensation INTERNAL
SET_PARAMETER Pll_Ref_Jitter 0.010
SET_PARAMETER Pll_Clkout0_Divide 6
SET_PARAMETER Pll_Clkout0_Duty_Cycle 0.500
SET_PARAMETER Pll_Clkout0_Phase 0.000
SET_PARAMETER Pll_Clkout1_Divide 3
SET_PARAMETER Pll_Clkout1_Duty_Cycle 0.500
SET_PARAMETER Pll_Clkout1_Phase 0.000
SET_PARAMETER Pll_Clkout2_Divide 1
SET_PARAMETER Pll_Clkout2_Duty_Cycle 0.500
SET_PARAMETER Pll_Clkout2_Phase 0.000
SET_PARAMETER Pll_Clkout3_Divide 1
SET_PARAMETER Pll_Clkout3_Duty_Cycle 0.500
SET_PARAMETER Pll_Clkout3_Phase 0.000
SET_PARAMETER Pll_Clkout4_Divide 1
SET_PARAMETER Pll_Clkout4_Duty_Cycle 0.500
SET_PARAMETER Pll_Clkout4_Phase 0.000
SET_PARAMETER Pll_Clkout5_Divide 1
SET_PARAMETER Pll_Clkout5_Duty_Cycle 0.500
SET_PARAMETER Pll_Clkout5_Phase 0.000
SET_PARAMETER dcm_pll_cascade NONE
SET_PARAMETER clock_mgr_type AUTO
SET_PARAMETER primtype_sel PLL_BASE
SET_PARAMETER primitive MMCM
SET_PARAMETER SS_Mode CENTER_HIGH
SET_PARAMETER SS_Mod_Freq 250
SET_SIM_PARAMETER c_clkout2_used 1
SET_SIM_PARAMETER c_clkout3_used 0
SET_SIM_PARAMETER c_clkout4_used 0
SET_SIM_PARAMETER c_clkout5_used 0
SET_SIM_PARAMETER c_clkout6_used 0
SET_SIM_PARAMETER c_clkout7_used 0
SET_SIM_PARAMETER c_use_clkout1_bar 0
SET_SIM_PARAMETER c_use_clkout2_bar 0
SET_SIM_PARAMETER c_use_clkout3_bar 0
SET_SIM_PARAMETER c_use_clkout4_bar 0
SET_SIM_PARAMETER c_component_name hdmi_clk
SET_SIM_PARAMETER c_platform lin64
SET_SIM_PARAMETER c_use_freq_synth 1
SET_SIM_PARAMETER c_use_phase_alignment 0
SET_SIM_PARAMETER c_prim_in_jitter 0.010
SET_SIM_PARAMETER c_secondary_in_jitter 0.010
SET_SIM_PARAMETER c_jitter_sel No_Jitter
SET_SIM_PARAMETER c_use_min_power 0
SET_SIM_PARAMETER c_use_min_o_jitter 0
SET_SIM_PARAMETER c_use_max_i_jitter 0
SET_SIM_PARAMETER c_use_dyn_phase_shift 0
SET_SIM_PARAMETER c_use_inclk_switchover 0
SET_SIM_PARAMETER c_use_dyn_reconfig 0
SET_SIM_PARAMETER c_use_spread_spectrum 0
SET_SIM_PARAMETER c_use_spread_spectrum_1 0
SET_SIM_PARAMETER c_primtype_sel PLL_BASE
SET_SIM_PARAMETER c_use_clk_valid 0
SET_SIM_PARAMETER c_prim_in_freq 50
SET_SIM_PARAMETER c_in_freq_units Units_MHz
SET_SIM_PARAMETER c_secondary_in_freq 100.000
SET_SIM_PARAMETER c_feedback_source FDBK_AUTO
SET_SIM_PARAMETER c_prim_source Single_ended_clock_capable_pin
SET_SIM_PARAMETER c_secondary_source Single_ended_clock_capable_pin
SET_SIM_PARAMETER c_clkfb_in_signaling SINGLE
SET_SIM_PARAMETER c_use_reset 0
SET_SIM_PARAMETER c_use_locked 0
SET_SIM_PARAMETER c_use_inclk_stopped 0
SET_SIM_PARAMETER c_use_clkfb_stopped 0
SET_SIM_PARAMETER c_use_power_down 0
SET_SIM_PARAMETER c_use_status 0
SET_SIM_PARAMETER c_use_freeze 0
SET_SIM_PARAMETER c_num_out_clks 2
SET_SIM_PARAMETER c_clkout1_drives BUFG
SET_SIM_PARAMETER c_clkout2_drives BUFG
SET_SIM_PARAMETER c_clkout3_drives BUFG
SET_SIM_PARAMETER c_clkout4_drives BUFG
SET_SIM_PARAMETER c_clkout5_drives BUFG
SET_SIM_PARAMETER c_clkout6_drives BUFG
SET_SIM_PARAMETER c_clkout7_drives BUFG
SET_SIM_PARAMETER c_inclk_sum_row0 "Input Clock Freq (MHz) Input Jitter (UI)"
SET_SIM_PARAMETER c_inclk_sum_row1 __primary______________50____________0.010
SET_SIM_PARAMETER c_inclk_sum_row2 no_secondary_input_clock
SET_SIM_PARAMETER c_outclk_sum_row0a "Output Output Phase Duty Pk-to-Pk Phase"
SET_SIM_PARAMETER c_outclk_sum_row0b "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
SET_SIM_PARAMETER c_outclk_sum_row1 CLK_OUT1____75.000______0.000______50.0______248.869____240.171
SET_SIM_PARAMETER c_outclk_sum_row2 CLK_OUT2___150.000______0.000______50.0______216.897____240.171
SET_SIM_PARAMETER c_outclk_sum_row3 no_CLK_OUT3_output
SET_SIM_PARAMETER c_outclk_sum_row4 no_CLK_OUT4_output
SET_SIM_PARAMETER c_outclk_sum_row5 no_CLK_OUT5_output
SET_SIM_PARAMETER c_outclk_sum_row6 no_CLK_OUT6_output
SET_SIM_PARAMETER c_outclk_sum_row7 no_CLK_OUT7_output
SET_SIM_PARAMETER c_clkout1_requested_out_freq 75
SET_SIM_PARAMETER c_clkout2_requested_out_freq 150
SET_SIM_PARAMETER c_clkout3_requested_out_freq 100.000
SET_SIM_PARAMETER c_clkout4_requested_out_freq 100.000
SET_SIM_PARAMETER c_clkout5_requested_out_freq 100.000
SET_SIM_PARAMETER c_clkout6_requested_out_freq 100.000
SET_SIM_PARAMETER c_clkout7_requested_out_freq 100.000
SET_SIM_PARAMETER c_clkout1_requested_phase 0.000
SET_SIM_PARAMETER c_clkout2_requested_phase 0.000
SET_SIM_PARAMETER c_clkout3_requested_phase 0.000
SET_SIM_PARAMETER c_clkout4_requested_phase 0.000
SET_SIM_PARAMETER c_clkout5_requested_phase 0.000
SET_SIM_PARAMETER c_clkout6_requested_phase 0.000
SET_SIM_PARAMETER c_clkout7_requested_phase 0.000
SET_SIM_PARAMETER c_clkout1_requested_duty_cycle 50.000
SET_SIM_PARAMETER c_clkout2_requested_duty_cycle 50.000
SET_SIM_PARAMETER c_clkout3_requested_duty_cycle 50.000
SET_SIM_PARAMETER c_clkout4_requested_duty_cycle 50.000
SET_SIM_PARAMETER c_clkout5_requested_duty_cycle 50.000
SET_SIM_PARAMETER c_clkout6_requested_duty_cycle 50.000
SET_SIM_PARAMETER c_clkout7_requested_duty_cycle 50.000
SET_SIM_PARAMETER c_clkout1_out_freq 75.000
SET_SIM_PARAMETER c_clkout2_out_freq 150.000
SET_SIM_PARAMETER c_clkout3_out_freq N/A
SET_SIM_PARAMETER c_clkout4_out_freq N/A
SET_SIM_PARAMETER c_clkout5_out_freq N/A
SET_SIM_PARAMETER c_clkout6_out_freq N/A
SET_SIM_PARAMETER c_clkout7_out_freq N/A
SET_SIM_PARAMETER c_clkout1_phase 0.000
SET_SIM_PARAMETER c_clkout2_phase 0.000
SET_SIM_PARAMETER c_clkout3_phase N/A
SET_SIM_PARAMETER c_clkout4_phase N/A
SET_SIM_PARAMETER c_clkout5_phase N/A
SET_SIM_PARAMETER c_clkout6_phase N/A
SET_SIM_PARAMETER c_clkout7_phase N/A
SET_SIM_PARAMETER c_clkout1_duty_cycle 50.0
SET_SIM_PARAMETER c_clkout2_duty_cycle 50.0
SET_SIM_PARAMETER c_clkout3_duty_cycle N/A
SET_SIM_PARAMETER c_clkout4_duty_cycle N/A
SET_SIM_PARAMETER c_clkout5_duty_cycle N/A
SET_SIM_PARAMETER c_clkout6_duty_cycle N/A
SET_SIM_PARAMETER c_clkout7_duty_cycle N/A
SET_SIM_PARAMETER c_mmcm_notes None
SET_SIM_PARAMETER c_mmcm_bandwidth OPTIMIZED
SET_SIM_PARAMETER c_mmcm_clkfbout_mult_f 4.000
SET_SIM_PARAMETER c_mmcm_clkin1_period 10.000
SET_SIM_PARAMETER c_mmcm_clkin2_period 10.000
SET_SIM_PARAMETER c_mmcm_clkout4_cascade FALSE
SET_SIM_PARAMETER c_mmcm_clock_hold FALSE
SET_SIM_PARAMETER c_mmcm_compensation ZHOLD
SET_SIM_PARAMETER c_mmcm_divclk_divide 1
SET_SIM_PARAMETER c_mmcm_ref_jitter1 0.010
SET_SIM_PARAMETER c_mmcm_ref_jitter2 0.010
SET_SIM_PARAMETER c_mmcm_startup_wait FALSE
SET_SIM_PARAMETER c_mmcm_clkout0_divide_f 4.000
SET_SIM_PARAMETER c_mmcm_clkout1_divide 1
SET_SIM_PARAMETER c_mmcm_clkout2_divide 1
SET_SIM_PARAMETER c_mmcm_clkout3_divide 1
SET_SIM_PARAMETER c_mmcm_clkout4_divide 1
SET_SIM_PARAMETER c_mmcm_clkout5_divide 1
SET_SIM_PARAMETER c_mmcm_clkout6_divide 1
SET_SIM_PARAMETER c_mmcm_clkout0_duty_cycle 0.500
SET_SIM_PARAMETER c_mmcm_clkout1_duty_cycle 0.500
SET_SIM_PARAMETER c_mmcm_clkout2_duty_cycle 0.500
SET_SIM_PARAMETER c_mmcm_clkout3_duty_cycle 0.500
SET_SIM_PARAMETER c_mmcm_clkout4_duty_cycle 0.500
SET_SIM_PARAMETER c_mmcm_clkout5_duty_cycle 0.500
SET_SIM_PARAMETER c_mmcm_clkout6_duty_cycle 0.500
SET_SIM_PARAMETER c_mmcm_clkfbout_phase 0.000
SET_SIM_PARAMETER c_mmcm_clkout0_phase 0.000
SET_SIM_PARAMETER c_mmcm_clkout1_phase 0.000
SET_SIM_PARAMETER c_mmcm_clkout2_phase 0.000
SET_SIM_PARAMETER c_mmcm_clkout3_phase 0.000
SET_SIM_PARAMETER c_mmcm_clkout4_phase 0.000
SET_SIM_PARAMETER c_mmcm_clkout5_phase 0.000
SET_SIM_PARAMETER c_mmcm_clkout6_phase 0.000
SET_SIM_PARAMETER c_mmcm_clkfbout_use_fine_ps FALSE
SET_SIM_PARAMETER c_mmcm_clkout0_use_fine_ps FALSE
SET_SIM_PARAMETER c_mmcm_clkout1_use_fine_ps FALSE
SET_SIM_PARAMETER c_mmcm_clkout2_use_fine_ps FALSE
SET_SIM_PARAMETER c_mmcm_clkout3_use_fine_ps FALSE
SET_SIM_PARAMETER c_mmcm_clkout4_use_fine_ps FALSE
SET_SIM_PARAMETER c_mmcm_clkout5_use_fine_ps FALSE
SET_SIM_PARAMETER c_mmcm_clkout6_use_fine_ps FALSE
SET_SIM_PARAMETER c_pll_notes None
SET_SIM_PARAMETER c_pll_bandwidth OPTIMIZED
SET_SIM_PARAMETER c_pll_clk_feedback CLKFBOUT
SET_SIM_PARAMETER c_pll_clkfbout_mult 9
SET_SIM_PARAMETER c_pll_clkin_period 20.000
SET_SIM_PARAMETER c_pll_compensation INTERNAL
SET_SIM_PARAMETER c_pll_divclk_divide 1
SET_SIM_PARAMETER c_pll_ref_jitter 0.010
SET_SIM_PARAMETER c_pll_clkout0_divide 6
SET_SIM_PARAMETER c_pll_clkout1_divide 3
SET_SIM_PARAMETER c_pll_clkout2_divide 1
SET_SIM_PARAMETER c_pll_clkout3_divide 1
SET_SIM_PARAMETER c_pll_clkout4_divide 1
SET_SIM_PARAMETER c_pll_clkout5_divide 1
SET_SIM_PARAMETER c_pll_clkout0_duty_cycle 0.500
SET_SIM_PARAMETER c_pll_clkout1_duty_cycle 0.500
SET_SIM_PARAMETER c_pll_clkout2_duty_cycle 0.500
SET_SIM_PARAMETER c_pll_clkout3_duty_cycle 0.500
SET_SIM_PARAMETER c_pll_clkout4_duty_cycle 0.500
SET_SIM_PARAMETER c_pll_clkout5_duty_cycle 0.500
SET_SIM_PARAMETER c_pll_clkfbout_phase 0.000
SET_SIM_PARAMETER c_pll_clkout0_phase 0.000
SET_SIM_PARAMETER c_pll_clkout1_phase 0.000
SET_SIM_PARAMETER c_pll_clkout2_phase 0.000
SET_SIM_PARAMETER c_pll_clkout3_phase 0.000
SET_SIM_PARAMETER c_pll_clkout4_phase 0.000
SET_SIM_PARAMETER c_pll_clkout5_phase 0.000
SET_SIM_PARAMETER c_dcm_notes None
SET_SIM_PARAMETER c_dcm_clkdv_divide 2.000
SET_SIM_PARAMETER c_dcm_clkfx_divide 2
SET_SIM_PARAMETER c_dcm_clkfx_multiply 3
SET_SIM_PARAMETER c_dcm_clkin_divide_by_2 FALSE
SET_SIM_PARAMETER c_dcm_clkin_period 20.0
SET_SIM_PARAMETER c_dcm_clkout_phase_shift NONE
SET_SIM_PARAMETER c_dcm_clk_feedback NONE
SET_SIM_PARAMETER c_dcm_clk_feedback_port NONE
SET_SIM_PARAMETER c_dcm_deskew_adjust SYSTEM_SYNCHRONOUS
SET_SIM_PARAMETER c_dcm_phase_shift 0
SET_SIM_PARAMETER c_dcm_startup_wait FALSE
SET_SIM_PARAMETER c_dcm_clk_out1_port CLKFX
SET_SIM_PARAMETER c_dcm_clk_out2_port CLK0
SET_SIM_PARAMETER c_dcm_clk_out3_port NONE
SET_SIM_PARAMETER c_dcm_clk_out4_port NONE
SET_SIM_PARAMETER c_dcm_clk_out5_port NONE
SET_SIM_PARAMETER c_dcm_clk_out6_port NONE
SET_SIM_PARAMETER c_dcm_clkgen_notes None
SET_SIM_PARAMETER c_dcm_clkgen_clkfxdv_divide 2
SET_SIM_PARAMETER c_dcm_clkgen_clkfx_divide 1
SET_SIM_PARAMETER c_dcm_clkgen_clkfx_multiply 4
SET_SIM_PARAMETER c_dcm_clkgen_dfs_bandwidth OPTIMIZED
SET_SIM_PARAMETER c_dcm_clkgen_prog_md_bandwidth OPTIMIZED
SET_SIM_PARAMETER c_dcm_clkgen_clkin_period 20.0
SET_SIM_PARAMETER c_dcm_clkgen_clkfx_md_max 0.000
SET_SIM_PARAMETER c_dcm_clkgen_spread_spectrum NONE
SET_SIM_PARAMETER c_dcm_clkgen_startup_wait FALSE
SET_SIM_PARAMETER c_dcm_clkgen_clk_out1_port CLKFX
SET_SIM_PARAMETER c_dcm_clkgen_clk_out2_port CLKFX
SET_SIM_PARAMETER c_dcm_clkgen_clk_out3_port NONE
SET_SIM_PARAMETER c_clock_mgr_type AUTO
SET_SIM_PARAMETER c_override_mmcm 0
SET_SIM_PARAMETER c_override_pll 0
SET_SIM_PARAMETER c_override_dcm 0
SET_SIM_PARAMETER c_override_dcm_clkgen 0
SET_SIM_PARAMETER c_dcm_pll_cascade NONE
SET_SIM_PARAMETER c_primary_port CLK_IN1
SET_SIM_PARAMETER c_secondary_port CLK_IN2
SET_SIM_PARAMETER c_clk_out1_port CLK_OUT1
SET_SIM_PARAMETER c_clk_out2_port CLK_OUT2
SET_SIM_PARAMETER c_clk_out3_port CLK_OUT3
SET_SIM_PARAMETER c_clk_out4_port CLK_OUT4
SET_SIM_PARAMETER c_clk_out5_port CLK_OUT5
SET_SIM_PARAMETER c_clk_out6_port CLK_OUT6
SET_SIM_PARAMETER c_clk_out7_port CLK_OUT7
SET_SIM_PARAMETER c_reset_port RESET
SET_SIM_PARAMETER c_locked_port LOCKED
SET_SIM_PARAMETER c_clkfb_in_port CLKFB_IN
SET_SIM_PARAMETER c_clkfb_in_p_port CLKFB_IN_P
SET_SIM_PARAMETER c_clkfb_in_n_port CLKFB_IN_N
SET_SIM_PARAMETER c_clkfb_out_port CLKFB_OUT
SET_SIM_PARAMETER c_clkfb_out_p_port CLKFB_OUT_P
SET_SIM_PARAMETER c_clkfb_out_n_port CLKFB_OUT_N
SET_SIM_PARAMETER c_power_down_port POWER_DOWN
SET_SIM_PARAMETER c_daddr_port DADDR
SET_SIM_PARAMETER c_dclk_port DCLK
SET_SIM_PARAMETER c_drdy_port DRDY
SET_SIM_PARAMETER c_dwe_port DWE
SET_SIM_PARAMETER c_din_port DIN
SET_SIM_PARAMETER c_dout_port DOUT
SET_SIM_PARAMETER c_den_port DEN
SET_SIM_PARAMETER c_psclk_port PSCLK
SET_SIM_PARAMETER c_psen_port PSEN
SET_SIM_PARAMETER c_psincdec_port PSINCDEC
SET_SIM_PARAMETER c_psdone_port PSDONE
SET_SIM_PARAMETER c_clk_valid_port CLK_VALID
SET_SIM_PARAMETER c_status_port STATUS
SET_SIM_PARAMETER c_clk_in_sel_port CLK_IN_SEL
SET_SIM_PARAMETER c_input_clk_stopped_port INPUT_CLK_STOPPED
SET_SIM_PARAMETER c_clkfb_stopped_port CLKFB_STOPPED
SET_SIM_PARAMETER c_clkin1_jitter_ps 200.0
SET_SIM_PARAMETER c_clkin2_jitter_ps 100.0
SET_SIM_PARAMETER c_primitive MMCM
SET_SIM_PARAMETER c_ss_mode CENTER_HIGH
SET_SIM_PARAMETER c_ss_mod_period 4000
SET_CORE_NAME Clocking Wizard
SET_CORE_VERSION 3.6
SET_CORE_VLNV xilinx.com:ip:clk_wiz:3.6
SET_CORE_CLASS com.xilinx.ip.clk_wiz_v3_6.clk_wiz_v3_6
SET_CORE_PATH /opt/Xilinx/14.7/ISE_DS/ISE/coregen/ip/xilinx/primary/com/xilinx/ip/clk_wiz_v3_6
SET_CORE_GUIPATH /opt/Xilinx/14.7/ISE_DS/ISE/coregen/ip/xilinx/primary/com/xilinx/ip/clk_wiz_v3_6/gui/clk_wiz_v3_6.tcl
SET_CORE_DATASHEET /opt/Xilinx/14.7/ISE_DS/ISE/coregen/ip/xilinx/primary/com/xilinx/ip/clk_wiz_v3_6/doc/pg065_clk_wiz.pdf
ADD_CORE_DOCUMENT </opt/Xilinx/14.7/ISE_DS/ISE/coregen/ip/xilinx/primary/com/xilinx/ip/clk_wiz_v3_6/doc/pg065_clk_wiz.pdf><pg065_clk_wiz.pdf>
ADD_CORE_DOCUMENT </opt/Xilinx/14.7/ISE_DS/ISE/coregen/ip/xilinx/primary/com/xilinx/ip/clk_wiz_v3_6/doc/clk_wiz_v3_6_readme.txt><clk_wiz_v3_6_readme.txt>
ADD_CORE_DOCUMENT </opt/Xilinx/14.7/ISE_DS/ISE/coregen/ip/xilinx/primary/com/xilinx/ip/clk_wiz_v3_6/doc/clk_wiz_v3_6_vinfo.html><clk_wiz_v3_6_vinfo.html>

505
ipcore_dir/tmp/customization_gui.0.194277189762.out
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@ -1,505 +0,0 @@
SET_FLAG DEBUG FALSE
SET_FLAG MODE BATCH
SET_FLAG STANDALONE_MODE FALSE
SET_PREFERENCE devicefamily spartan6
SET_PREFERENCE device xc6slx9
SET_PREFERENCE speedgrade -2
SET_PREFERENCE package tqg144
SET_PREFERENCE verilogsim true
SET_PREFERENCE vhdlsim false
SET_PREFERENCE simulationfiles Behavioral
SET_PREFERENCE busformat BusFormatAngleBracketNotRipped
SET_PREFERENCE outputdirectory /home/tim/Projects/fpga/micro_test/ipcore_dir/
SET_PREFERENCE workingdirectory /home/tim/Projects/fpga/micro_test/ipcore_dir/tmp/
SET_PREFERENCE subworkingdirectory /home/tim/Projects/fpga/micro_test/ipcore_dir/tmp/_cg/
SET_PREFERENCE transientdirectory /home/tim/Projects/fpga/micro_test/ipcore_dir/tmp/_cg/_dbg/
SET_PREFERENCE designentry Verilog
SET_PREFERENCE flowvendor Other
SET_PREFERENCE addpads false
SET_PREFERENCE projectname coregen
SET_PREFERENCE formalverification false
SET_PREFERENCE asysymbol false
SET_PREFERENCE implementationfiletype Ngc
SET_PREFERENCE foundationsym false
SET_PREFERENCE createndf false
SET_PREFERENCE removerpms false
SET_PARAMETER Component_Name hdmi_clk
SET_PARAMETER Use_Freq_Synth true
SET_PARAMETER Use_Phase_Alignment false
SET_PARAMETER Use_Min_Power false
SET_PARAMETER Use_Dyn_Phase_Shift false
SET_PARAMETER Use_Dyn_Reconfig false
SET_PARAMETER Jitter_Sel No_Jitter
SET_PARAMETER Use_Spread_Spectrum false
SET_PARAMETER Use_Spread_Spectrum_1 false
SET_PARAMETER Prim_In_Freq 50
SET_PARAMETER In_Freq_Units Units_MHz
SET_PARAMETER In_Jitter_Units Units_UI
SET_PARAMETER Relative_Inclk REL_PRIMARY
SET_PARAMETER Secondary_In_Freq 100.000
SET_PARAMETER Jitter_Options UI
SET_PARAMETER Clkin1_UI_Jitter 0.010
SET_PARAMETER Clkin2_UI_Jitter 0.010
SET_PARAMETER Prim_In_Jitter 0.010
SET_PARAMETER Secondary_In_Jitter 0.010
SET_PARAMETER Clkin1_Jitter_Ps 200.0
SET_PARAMETER Clkin2_Jitter_Ps 100.0
SET_PARAMETER Clkout2_Used true
SET_PARAMETER Clkout3_Used false
SET_PARAMETER Clkout4_Used false
SET_PARAMETER Clkout5_Used false
SET_PARAMETER Clkout6_Used false
SET_PARAMETER Clkout7_Used false
SET_PARAMETER Num_Out_Clks 2
SET_PARAMETER Clk_Out1_Use_Fine_Ps_GUI false
SET_PARAMETER Clk_Out2_Use_Fine_Ps_GUI false
SET_PARAMETER Clk_Out3_Use_Fine_Ps_GUI false
SET_PARAMETER Clk_Out4_Use_Fine_Ps_GUI false
SET_PARAMETER Clk_Out5_Use_Fine_Ps_GUI false
SET_PARAMETER Clk_Out6_Use_Fine_Ps_GUI false
SET_PARAMETER Clk_Out7_Use_Fine_Ps_GUI false
SET_PARAMETER primary_port CLK_IN1
SET_PARAMETER CLK_OUT1_port CLK_OUT1
SET_PARAMETER CLK_OUT2_port CLK_OUT2
SET_PARAMETER CLK_OUT3_port CLK_OUT3
SET_PARAMETER CLK_OUT4_port CLK_OUT4
SET_PARAMETER CLK_OUT5_port CLK_OUT5
SET_PARAMETER CLK_OUT6_port CLK_OUT6
SET_PARAMETER CLK_OUT7_port CLK_OUT7
SET_PARAMETER DADDR_port DADDR
SET_PARAMETER DCLK_port DCLK
SET_PARAMETER DRDY_port DRDY
SET_PARAMETER DWE_port DWE
SET_PARAMETER DIN_port DIN
SET_PARAMETER DOUT_port DOUT
SET_PARAMETER DEN_port DEN
SET_PARAMETER PSCLK_port PSCLK
SET_PARAMETER PSEN_port PSEN
SET_PARAMETER PSINCDEC_port PSINCDEC
SET_PARAMETER PSDONE_port PSDONE
SET_PARAMETER Clkout1_Requested_Out_Freq 75
SET_PARAMETER Clkout1_Requested_Phase 0.000
SET_PARAMETER Clkout1_Requested_Duty_Cycle 50.000
SET_PARAMETER Clkout2_Requested_Out_Freq 175
SET_PARAMETER Clkout2_Requested_Phase 0.000
SET_PARAMETER Clkout2_Requested_Duty_Cycle 50.000
SET_PARAMETER Clkout3_Requested_Out_Freq 100.000
SET_PARAMETER Clkout3_Requested_Phase 0.000
SET_PARAMETER Clkout3_Requested_Duty_Cycle 50.000
SET_PARAMETER Clkout4_Requested_Out_Freq 100.000
SET_PARAMETER Clkout4_Requested_Phase 0.000
SET_PARAMETER Clkout4_Requested_Duty_Cycle 50.000
SET_PARAMETER Clkout5_Requested_Out_Freq 100.000
SET_PARAMETER Clkout5_Requested_Phase 0.000
SET_PARAMETER Clkout5_Requested_Duty_Cycle 50.000
SET_PARAMETER Clkout6_Requested_Out_Freq 100.000
SET_PARAMETER Clkout6_Requested_Phase 0.000
SET_PARAMETER Clkout6_Requested_Duty_Cycle 50.000
SET_PARAMETER Clkout7_Requested_Out_Freq 100.000
SET_PARAMETER Clkout7_Requested_Phase 0.000
SET_PARAMETER Clkout7_Requested_Duty_Cycle 50.000
SET_PARAMETER Use_Max_I_Jitter false
SET_PARAMETER Use_Min_O_Jitter false
SET_PARAMETER Prim_Source Single_ended_clock_capable_pin
SET_PARAMETER Use_Inclk_Switchover false
SET_PARAMETER secondary_port CLK_IN2
SET_PARAMETER Secondary_Source Single_ended_clock_capable_pin
SET_PARAMETER Clkout1_Drives BUFG
SET_PARAMETER Clkout2_Drives BUFG
SET_PARAMETER Clkout3_Drives BUFG
SET_PARAMETER Clkout4_Drives BUFG
SET_PARAMETER Clkout5_Drives BUFG
SET_PARAMETER Clkout6_Drives BUFG
SET_PARAMETER Clkout7_Drives BUFG
SET_PARAMETER Feedback_Source FDBK_AUTO
SET_PARAMETER Clkfb_In_Signaling SINGLE
SET_PARAMETER CLKFB_IN_port CLKFB_IN
SET_PARAMETER CLKFB_IN_P_port CLKFB_IN_P
SET_PARAMETER CLKFB_IN_N_port CLKFB_IN_N
SET_PARAMETER CLKFB_OUT_port CLKFB_OUT
SET_PARAMETER CLKFB_OUT_P_port CLKFB_OUT_P
SET_PARAMETER CLKFB_OUT_N_port CLKFB_OUT_N
SET_PARAMETER Platform lin64
SET_PARAMETER Summary_Strings empty
SET_PARAMETER Use_Locked false
SET_PARAMETER calc_done DONE
SET_PARAMETER Use_Reset false
SET_PARAMETER Use_Power_Down false
SET_PARAMETER Use_Status false
SET_PARAMETER Use_Freeze false
SET_PARAMETER Use_Clk_Valid false
SET_PARAMETER Use_Inclk_Stopped false
SET_PARAMETER Use_Clkfb_Stopped false
SET_PARAMETER RESET_port RESET
SET_PARAMETER LOCKED_port LOCKED
SET_PARAMETER Power_Down_port POWER_DOWN
SET_PARAMETER CLK_VALID_port CLK_VALID
SET_PARAMETER STATUS_port STATUS
SET_PARAMETER CLK_IN_SEL_port CLK_IN_SEL
SET_PARAMETER INPUT_CLK_STOPPED_port INPUT_CLK_STOPPED
SET_PARAMETER CLKFB_STOPPED_port CLKFB_STOPPED
SET_PARAMETER Override_Mmcm false
SET_PARAMETER Mmcm_Notes None
SET_PARAMETER Mmcm_Divclk_Divide 1
SET_PARAMETER Mmcm_Bandwidth OPTIMIZED
SET_PARAMETER Mmcm_Clkfbout_Mult_F 4.000
SET_PARAMETER Mmcm_Clkfbout_Phase 0.000
SET_PARAMETER Mmcm_Clkfbout_Use_Fine_Ps false
SET_PARAMETER Mmcm_Clkin1_Period 10.000
SET_PARAMETER Mmcm_Clkin2_Period 10.000
SET_PARAMETER Mmcm_Clkout4_Cascade false
SET_PARAMETER Mmcm_Clock_Hold false
SET_PARAMETER Mmcm_Compensation ZHOLD
SET_PARAMETER Mmcm_Ref_Jitter1 0.010
SET_PARAMETER Mmcm_Ref_Jitter2 0.010
SET_PARAMETER Mmcm_Startup_Wait false
SET_PARAMETER Mmcm_Clkout0_Divide_F 4.000
SET_PARAMETER Mmcm_Clkout0_Duty_Cycle 0.500
SET_PARAMETER Mmcm_Clkout0_Phase 0.000
SET_PARAMETER Mmcm_Clkout0_Use_Fine_Ps false
SET_PARAMETER Mmcm_Clkout1_Divide 1
SET_PARAMETER Mmcm_Clkout1_Duty_Cycle 0.500
SET_PARAMETER Mmcm_Clkout1_Phase 0.000
SET_PARAMETER Mmcm_Clkout1_Use_Fine_Ps false
SET_PARAMETER Mmcm_Clkout2_Divide 1
SET_PARAMETER Mmcm_Clkout2_Duty_Cycle 0.500
SET_PARAMETER Mmcm_Clkout2_Phase 0.000
SET_PARAMETER Mmcm_Clkout2_Use_Fine_Ps false
SET_PARAMETER Mmcm_Clkout3_Divide 1
SET_PARAMETER Mmcm_Clkout3_Duty_Cycle 0.500
SET_PARAMETER Mmcm_Clkout3_Phase 0.000
SET_PARAMETER Mmcm_Clkout3_Use_Fine_Ps false
SET_PARAMETER Mmcm_Clkout4_Divide 1
SET_PARAMETER Mmcm_Clkout4_Duty_Cycle 0.500
SET_PARAMETER Mmcm_Clkout4_Phase 0.000
SET_PARAMETER Mmcm_Clkout4_Use_Fine_Ps false
SET_PARAMETER Mmcm_Clkout5_Divide 1
SET_PARAMETER Mmcm_Clkout5_Duty_Cycle 0.500
SET_PARAMETER Mmcm_Clkout5_Phase 0.000
SET_PARAMETER Mmcm_Clkout5_Use_Fine_Ps false
SET_PARAMETER Mmcm_Clkout6_Divide 1
SET_PARAMETER Mmcm_Clkout6_Duty_Cycle 0.500
SET_PARAMETER Mmcm_Clkout6_Phase 0.000
SET_PARAMETER Mmcm_Clkout6_Use_Fine_Ps false
SET_PARAMETER Override_Dcm false
SET_PARAMETER Dcm_Notes None
SET_PARAMETER Dcm_Clkdv_Divide 2.0
SET_PARAMETER Dcm_Clkfx_Divide 2
SET_PARAMETER Dcm_Clkfx_Multiply 3
SET_PARAMETER Dcm_Clkin_Divide_By_2 false
SET_PARAMETER Dcm_Clkin_Period 20.000
SET_PARAMETER Dcm_Clkout_Phase_Shift NONE
SET_PARAMETER Dcm_Deskew_Adjust SYSTEM_SYNCHRONOUS
SET_PARAMETER Dcm_Phase_Shift 0
SET_PARAMETER Dcm_Clk_Feedback NONE
SET_PARAMETER Dcm_Startup_Wait false
SET_PARAMETER Dcm_Clk_Out1_Port CLKFX
SET_PARAMETER Dcm_Clk_Out2_Port CLK0
SET_PARAMETER Dcm_Clk_Out3_Port CLK0
SET_PARAMETER Dcm_Clk_Out4_Port CLK0
SET_PARAMETER Dcm_Clk_Out5_Port CLK0
SET_PARAMETER Dcm_Clk_Out6_Port CLK0
SET_PARAMETER Override_Dcm_Clkgen false
SET_PARAMETER Dcm_Clkgen_Notes None
SET_PARAMETER Dcm_Clkgen_Clkfx_Divide 1
SET_PARAMETER Dcm_Clkgen_Clkfx_Multiply 4
SET_PARAMETER Dcm_Clkgen_Clkfxdv_Divide 2
SET_PARAMETER Dcm_Clkgen_Clkfx_Md_Max 0.000
SET_PARAMETER Dcm_Clkgen_Startup_Wait false
SET_PARAMETER Dcm_Clkgen_Clkin_Period 10.000
SET_PARAMETER Dcm_Clkgen_Spread_Spectrum NONE
SET_PARAMETER Dcm_Clkgen_Clk_Out1_Port CLKFX
SET_PARAMETER Dcm_Clkgen_Clk_Out2_Port CLKFX
SET_PARAMETER Dcm_Clkgen_Clk_Out3_Port CLKFX
SET_PARAMETER Override_Pll false
SET_PARAMETER Pll_Notes None
SET_PARAMETER Pll_Bandwidth OPTIMIZED
SET_PARAMETER Pll_Clkfbout_Mult 21
SET_PARAMETER Pll_Clkfbout_Phase 0.000
SET_PARAMETER Pll_Clk_Feedback CLKFBOUT
SET_PARAMETER Pll_Divclk_Divide 2
SET_PARAMETER Pll_Clkin_Period 20.000
SET_PARAMETER Pll_Compensation INTERNAL
SET_PARAMETER Pll_Ref_Jitter 0.010
SET_PARAMETER Pll_Clkout0_Divide 7
SET_PARAMETER Pll_Clkout0_Duty_Cycle 0.500
SET_PARAMETER Pll_Clkout0_Phase 0.000
SET_PARAMETER Pll_Clkout1_Divide 3
SET_PARAMETER Pll_Clkout1_Duty_Cycle 0.500
SET_PARAMETER Pll_Clkout1_Phase 0.000
SET_PARAMETER Pll_Clkout2_Divide 1
SET_PARAMETER Pll_Clkout2_Duty_Cycle 0.500
SET_PARAMETER Pll_Clkout2_Phase 0.000
SET_PARAMETER Pll_Clkout3_Divide 1
SET_PARAMETER Pll_Clkout3_Duty_Cycle 0.500
SET_PARAMETER Pll_Clkout3_Phase 0.000
SET_PARAMETER Pll_Clkout4_Divide 1
SET_PARAMETER Pll_Clkout4_Duty_Cycle 0.500
SET_PARAMETER Pll_Clkout4_Phase 0.000
SET_PARAMETER Pll_Clkout5_Divide 1
SET_PARAMETER Pll_Clkout5_Duty_Cycle 0.500
SET_PARAMETER Pll_Clkout5_Phase 0.000
SET_PARAMETER dcm_pll_cascade NONE
SET_PARAMETER clock_mgr_type AUTO
SET_PARAMETER primtype_sel PLL_BASE
SET_PARAMETER primitive MMCM
SET_PARAMETER SS_Mode CENTER_HIGH
SET_PARAMETER SS_Mod_Freq 250
SET_SIM_PARAMETER c_clkout2_used 1
SET_SIM_PARAMETER c_clkout3_used 0
SET_SIM_PARAMETER c_clkout4_used 0
SET_SIM_PARAMETER c_clkout5_used 0
SET_SIM_PARAMETER c_clkout6_used 0
SET_SIM_PARAMETER c_clkout7_used 0
SET_SIM_PARAMETER c_use_clkout1_bar 0
SET_SIM_PARAMETER c_use_clkout2_bar 0
SET_SIM_PARAMETER c_use_clkout3_bar 0
SET_SIM_PARAMETER c_use_clkout4_bar 0
SET_SIM_PARAMETER c_component_name hdmi_clk
SET_SIM_PARAMETER c_platform lin64
SET_SIM_PARAMETER c_use_freq_synth 1
SET_SIM_PARAMETER c_use_phase_alignment 0
SET_SIM_PARAMETER c_prim_in_jitter 0.010
SET_SIM_PARAMETER c_secondary_in_jitter 0.010
SET_SIM_PARAMETER c_jitter_sel No_Jitter
SET_SIM_PARAMETER c_use_min_power 0
SET_SIM_PARAMETER c_use_min_o_jitter 0
SET_SIM_PARAMETER c_use_max_i_jitter 0
SET_SIM_PARAMETER c_use_dyn_phase_shift 0
SET_SIM_PARAMETER c_use_inclk_switchover 0
SET_SIM_PARAMETER c_use_dyn_reconfig 0
SET_SIM_PARAMETER c_use_spread_spectrum 0
SET_SIM_PARAMETER c_use_spread_spectrum_1 0
SET_SIM_PARAMETER c_primtype_sel PLL_BASE
SET_SIM_PARAMETER c_use_clk_valid 0
SET_SIM_PARAMETER c_prim_in_freq 50
SET_SIM_PARAMETER c_in_freq_units Units_MHz
SET_SIM_PARAMETER c_secondary_in_freq 100.000
SET_SIM_PARAMETER c_feedback_source FDBK_AUTO
SET_SIM_PARAMETER c_prim_source Single_ended_clock_capable_pin
SET_SIM_PARAMETER c_secondary_source Single_ended_clock_capable_pin
SET_SIM_PARAMETER c_clkfb_in_signaling SINGLE
SET_SIM_PARAMETER c_use_reset 0
SET_SIM_PARAMETER c_use_locked 0
SET_SIM_PARAMETER c_use_inclk_stopped 0
SET_SIM_PARAMETER c_use_clkfb_stopped 0
SET_SIM_PARAMETER c_use_power_down 0
SET_SIM_PARAMETER c_use_status 0
SET_SIM_PARAMETER c_use_freeze 0
SET_SIM_PARAMETER c_num_out_clks 2
SET_SIM_PARAMETER c_clkout1_drives BUFG
SET_SIM_PARAMETER c_clkout2_drives BUFG
SET_SIM_PARAMETER c_clkout3_drives BUFG
SET_SIM_PARAMETER c_clkout4_drives BUFG
SET_SIM_PARAMETER c_clkout5_drives BUFG
SET_SIM_PARAMETER c_clkout6_drives BUFG
SET_SIM_PARAMETER c_clkout7_drives BUFG
SET_SIM_PARAMETER c_inclk_sum_row0 "Input Clock Freq (MHz) Input Jitter (UI)"
SET_SIM_PARAMETER c_inclk_sum_row1 __primary______________50____________0.010
SET_SIM_PARAMETER c_inclk_sum_row2 no_secondary_input_clock
SET_SIM_PARAMETER c_outclk_sum_row0a "Output Output Phase Duty Pk-to-Pk Phase"
SET_SIM_PARAMETER c_outclk_sum_row0b "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
SET_SIM_PARAMETER c_outclk_sum_row1 CLK_OUT1____75.000______0.000______50.0______321.816____253.010
SET_SIM_PARAMETER c_outclk_sum_row2 CLK_OUT2___175.000______0.000______50.0______265.664____253.010
SET_SIM_PARAMETER c_outclk_sum_row3 no_CLK_OUT3_output
SET_SIM_PARAMETER c_outclk_sum_row4 no_CLK_OUT4_output
SET_SIM_PARAMETER c_outclk_sum_row5 no_CLK_OUT5_output
SET_SIM_PARAMETER c_outclk_sum_row6 no_CLK_OUT6_output
SET_SIM_PARAMETER c_outclk_sum_row7 no_CLK_OUT7_output
SET_SIM_PARAMETER c_clkout1_requested_out_freq 75
SET_SIM_PARAMETER c_clkout2_requested_out_freq 175
SET_SIM_PARAMETER c_clkout3_requested_out_freq 100.000
SET_SIM_PARAMETER c_clkout4_requested_out_freq 100.000
SET_SIM_PARAMETER c_clkout5_requested_out_freq 100.000
SET_SIM_PARAMETER c_clkout6_requested_out_freq 100.000
SET_SIM_PARAMETER c_clkout7_requested_out_freq 100.000
SET_SIM_PARAMETER c_clkout1_requested_phase 0.000
SET_SIM_PARAMETER c_clkout2_requested_phase 0.000
SET_SIM_PARAMETER c_clkout3_requested_phase 0.000
SET_SIM_PARAMETER c_clkout4_requested_phase 0.000
SET_SIM_PARAMETER c_clkout5_requested_phase 0.000
SET_SIM_PARAMETER c_clkout6_requested_phase 0.000
SET_SIM_PARAMETER c_clkout7_requested_phase 0.000
SET_SIM_PARAMETER c_clkout1_requested_duty_cycle 50.000
SET_SIM_PARAMETER c_clkout2_requested_duty_cycle 50.000
SET_SIM_PARAMETER c_clkout3_requested_duty_cycle 50.000
SET_SIM_PARAMETER c_clkout4_requested_duty_cycle 50.000
SET_SIM_PARAMETER c_clkout5_requested_duty_cycle 50.000
SET_SIM_PARAMETER c_clkout6_requested_duty_cycle 50.000
SET_SIM_PARAMETER c_clkout7_requested_duty_cycle 50.000
SET_SIM_PARAMETER c_clkout1_out_freq 75.000
SET_SIM_PARAMETER c_clkout2_out_freq 175.000
SET_SIM_PARAMETER c_clkout3_out_freq N/A
SET_SIM_PARAMETER c_clkout4_out_freq N/A
SET_SIM_PARAMETER c_clkout5_out_freq N/A
SET_SIM_PARAMETER c_clkout6_out_freq N/A
SET_SIM_PARAMETER c_clkout7_out_freq N/A
SET_SIM_PARAMETER c_clkout1_phase 0.000
SET_SIM_PARAMETER c_clkout2_phase 0.000
SET_SIM_PARAMETER c_clkout3_phase N/A
SET_SIM_PARAMETER c_clkout4_phase N/A
SET_SIM_PARAMETER c_clkout5_phase N/A
SET_SIM_PARAMETER c_clkout6_phase N/A
SET_SIM_PARAMETER c_clkout7_phase N/A
SET_SIM_PARAMETER c_clkout1_duty_cycle 50.0
SET_SIM_PARAMETER c_clkout2_duty_cycle 50.0
SET_SIM_PARAMETER c_clkout3_duty_cycle N/A
SET_SIM_PARAMETER c_clkout4_duty_cycle N/A
SET_SIM_PARAMETER c_clkout5_duty_cycle N/A
SET_SIM_PARAMETER c_clkout6_duty_cycle N/A
SET_SIM_PARAMETER c_clkout7_duty_cycle N/A
SET_SIM_PARAMETER c_mmcm_notes None
SET_SIM_PARAMETER c_mmcm_bandwidth OPTIMIZED
SET_SIM_PARAMETER c_mmcm_clkfbout_mult_f 4.000
SET_SIM_PARAMETER c_mmcm_clkin1_period 10.000
SET_SIM_PARAMETER c_mmcm_clkin2_period 10.000
SET_SIM_PARAMETER c_mmcm_clkout4_cascade FALSE
SET_SIM_PARAMETER c_mmcm_clock_hold FALSE
SET_SIM_PARAMETER c_mmcm_compensation ZHOLD
SET_SIM_PARAMETER c_mmcm_divclk_divide 1
SET_SIM_PARAMETER c_mmcm_ref_jitter1 0.010
SET_SIM_PARAMETER c_mmcm_ref_jitter2 0.010
SET_SIM_PARAMETER c_mmcm_startup_wait FALSE
SET_SIM_PARAMETER c_mmcm_clkout0_divide_f 4.000
SET_SIM_PARAMETER c_mmcm_clkout1_divide 1
SET_SIM_PARAMETER c_mmcm_clkout2_divide 1
SET_SIM_PARAMETER c_mmcm_clkout3_divide 1
SET_SIM_PARAMETER c_mmcm_clkout4_divide 1
SET_SIM_PARAMETER c_mmcm_clkout5_divide 1
SET_SIM_PARAMETER c_mmcm_clkout6_divide 1
SET_SIM_PARAMETER c_mmcm_clkout0_duty_cycle 0.500
SET_SIM_PARAMETER c_mmcm_clkout1_duty_cycle 0.500
SET_SIM_PARAMETER c_mmcm_clkout2_duty_cycle 0.500
SET_SIM_PARAMETER c_mmcm_clkout3_duty_cycle 0.500
SET_SIM_PARAMETER c_mmcm_clkout4_duty_cycle 0.500
SET_SIM_PARAMETER c_mmcm_clkout5_duty_cycle 0.500
SET_SIM_PARAMETER c_mmcm_clkout6_duty_cycle 0.500
SET_SIM_PARAMETER c_mmcm_clkfbout_phase 0.000
SET_SIM_PARAMETER c_mmcm_clkout0_phase 0.000
SET_SIM_PARAMETER c_mmcm_clkout1_phase 0.000
SET_SIM_PARAMETER c_mmcm_clkout2_phase 0.000
SET_SIM_PARAMETER c_mmcm_clkout3_phase 0.000
SET_SIM_PARAMETER c_mmcm_clkout4_phase 0.000
SET_SIM_PARAMETER c_mmcm_clkout5_phase 0.000
SET_SIM_PARAMETER c_mmcm_clkout6_phase 0.000
SET_SIM_PARAMETER c_mmcm_clkfbout_use_fine_ps FALSE
SET_SIM_PARAMETER c_mmcm_clkout0_use_fine_ps FALSE
SET_SIM_PARAMETER c_mmcm_clkout1_use_fine_ps FALSE
SET_SIM_PARAMETER c_mmcm_clkout2_use_fine_ps FALSE
SET_SIM_PARAMETER c_mmcm_clkout3_use_fine_ps FALSE
SET_SIM_PARAMETER c_mmcm_clkout4_use_fine_ps FALSE
SET_SIM_PARAMETER c_mmcm_clkout5_use_fine_ps FALSE
SET_SIM_PARAMETER c_mmcm_clkout6_use_fine_ps FALSE
SET_SIM_PARAMETER c_pll_notes None
SET_SIM_PARAMETER c_pll_bandwidth OPTIMIZED
SET_SIM_PARAMETER c_pll_clk_feedback CLKFBOUT
SET_SIM_PARAMETER c_pll_clkfbout_mult 21
SET_SIM_PARAMETER c_pll_clkin_period 20.000
SET_SIM_PARAMETER c_pll_compensation INTERNAL
SET_SIM_PARAMETER c_pll_divclk_divide 2
SET_SIM_PARAMETER c_pll_ref_jitter 0.010
SET_SIM_PARAMETER c_pll_clkout0_divide 7
SET_SIM_PARAMETER c_pll_clkout1_divide 3
SET_SIM_PARAMETER c_pll_clkout2_divide 1
SET_SIM_PARAMETER c_pll_clkout3_divide 1
SET_SIM_PARAMETER c_pll_clkout4_divide 1
SET_SIM_PARAMETER c_pll_clkout5_divide 1
SET_SIM_PARAMETER c_pll_clkout0_duty_cycle 0.500
SET_SIM_PARAMETER c_pll_clkout1_duty_cycle 0.500
SET_SIM_PARAMETER c_pll_clkout2_duty_cycle 0.500
SET_SIM_PARAMETER c_pll_clkout3_duty_cycle 0.500
SET_SIM_PARAMETER c_pll_clkout4_duty_cycle 0.500
SET_SIM_PARAMETER c_pll_clkout5_duty_cycle 0.500
SET_SIM_PARAMETER c_pll_clkfbout_phase 0.000
SET_SIM_PARAMETER c_pll_clkout0_phase 0.000
SET_SIM_PARAMETER c_pll_clkout1_phase 0.000
SET_SIM_PARAMETER c_pll_clkout2_phase 0.000
SET_SIM_PARAMETER c_pll_clkout3_phase 0.000
SET_SIM_PARAMETER c_pll_clkout4_phase 0.000
SET_SIM_PARAMETER c_pll_clkout5_phase 0.000
SET_SIM_PARAMETER c_dcm_notes None
SET_SIM_PARAMETER c_dcm_clkdv_divide 2.000
SET_SIM_PARAMETER c_dcm_clkfx_divide 2
SET_SIM_PARAMETER c_dcm_clkfx_multiply 3
SET_SIM_PARAMETER c_dcm_clkin_divide_by_2 FALSE
SET_SIM_PARAMETER c_dcm_clkin_period 20.0
SET_SIM_PARAMETER c_dcm_clkout_phase_shift NONE
SET_SIM_PARAMETER c_dcm_clk_feedback NONE
SET_SIM_PARAMETER c_dcm_clk_feedback_port NONE
SET_SIM_PARAMETER c_dcm_deskew_adjust SYSTEM_SYNCHRONOUS
SET_SIM_PARAMETER c_dcm_phase_shift 0
SET_SIM_PARAMETER c_dcm_startup_wait FALSE
SET_SIM_PARAMETER c_dcm_clk_out1_port CLKFX
SET_SIM_PARAMETER c_dcm_clk_out2_port CLK0
SET_SIM_PARAMETER c_dcm_clk_out3_port NONE
SET_SIM_PARAMETER c_dcm_clk_out4_port NONE
SET_SIM_PARAMETER c_dcm_clk_out5_port NONE
SET_SIM_PARAMETER c_dcm_clk_out6_port NONE
SET_SIM_PARAMETER c_dcm_clkgen_notes None
SET_SIM_PARAMETER c_dcm_clkgen_clkfxdv_divide 2
SET_SIM_PARAMETER c_dcm_clkgen_clkfx_divide 1
SET_SIM_PARAMETER c_dcm_clkgen_clkfx_multiply 4
SET_SIM_PARAMETER c_dcm_clkgen_dfs_bandwidth OPTIMIZED
SET_SIM_PARAMETER c_dcm_clkgen_prog_md_bandwidth OPTIMIZED
SET_SIM_PARAMETER c_dcm_clkgen_clkin_period 20.0
SET_SIM_PARAMETER c_dcm_clkgen_clkfx_md_max 0.000
SET_SIM_PARAMETER c_dcm_clkgen_spread_spectrum NONE
SET_SIM_PARAMETER c_dcm_clkgen_startup_wait FALSE
SET_SIM_PARAMETER c_dcm_clkgen_clk_out1_port CLKFX
SET_SIM_PARAMETER c_dcm_clkgen_clk_out2_port CLKFX
SET_SIM_PARAMETER c_dcm_clkgen_clk_out3_port NONE
SET_SIM_PARAMETER c_clock_mgr_type AUTO
SET_SIM_PARAMETER c_override_mmcm 0
SET_SIM_PARAMETER c_override_pll 0
SET_SIM_PARAMETER c_override_dcm 0
SET_SIM_PARAMETER c_override_dcm_clkgen 0
SET_SIM_PARAMETER c_dcm_pll_cascade NONE
SET_SIM_PARAMETER c_primary_port CLK_IN1
SET_SIM_PARAMETER c_secondary_port CLK_IN2
SET_SIM_PARAMETER c_clk_out1_port CLK_OUT1
SET_SIM_PARAMETER c_clk_out2_port CLK_OUT2
SET_SIM_PARAMETER c_clk_out3_port CLK_OUT3
SET_SIM_PARAMETER c_clk_out4_port CLK_OUT4
SET_SIM_PARAMETER c_clk_out5_port CLK_OUT5
SET_SIM_PARAMETER c_clk_out6_port CLK_OUT6
SET_SIM_PARAMETER c_clk_out7_port CLK_OUT7
SET_SIM_PARAMETER c_reset_port RESET
SET_SIM_PARAMETER c_locked_port LOCKED
SET_SIM_PARAMETER c_clkfb_in_port CLKFB_IN
SET_SIM_PARAMETER c_clkfb_in_p_port CLKFB_IN_P
SET_SIM_PARAMETER c_clkfb_in_n_port CLKFB_IN_N
SET_SIM_PARAMETER c_clkfb_out_port CLKFB_OUT
SET_SIM_PARAMETER c_clkfb_out_p_port CLKFB_OUT_P
SET_SIM_PARAMETER c_clkfb_out_n_port CLKFB_OUT_N
SET_SIM_PARAMETER c_power_down_port POWER_DOWN
SET_SIM_PARAMETER c_daddr_port DADDR
SET_SIM_PARAMETER c_dclk_port DCLK
SET_SIM_PARAMETER c_drdy_port DRDY
SET_SIM_PARAMETER c_dwe_port DWE
SET_SIM_PARAMETER c_din_port DIN
SET_SIM_PARAMETER c_dout_port DOUT
SET_SIM_PARAMETER c_den_port DEN
SET_SIM_PARAMETER c_psclk_port PSCLK
SET_SIM_PARAMETER c_psen_port PSEN
SET_SIM_PARAMETER c_psincdec_port PSINCDEC
SET_SIM_PARAMETER c_psdone_port PSDONE
SET_SIM_PARAMETER c_clk_valid_port CLK_VALID
SET_SIM_PARAMETER c_status_port STATUS
SET_SIM_PARAMETER c_clk_in_sel_port CLK_IN_SEL
SET_SIM_PARAMETER c_input_clk_stopped_port INPUT_CLK_STOPPED
SET_SIM_PARAMETER c_clkfb_stopped_port CLKFB_STOPPED
SET_SIM_PARAMETER c_clkin1_jitter_ps 200.0
SET_SIM_PARAMETER c_clkin2_jitter_ps 100.0
SET_SIM_PARAMETER c_primitive MMCM
SET_SIM_PARAMETER c_ss_mode CENTER_HIGH
SET_SIM_PARAMETER c_ss_mod_period 4000
SET_CORE_NAME Clocking Wizard
SET_CORE_VERSION 3.6
SET_CORE_VLNV xilinx.com:ip:clk_wiz:3.6
SET_CORE_CLASS com.xilinx.ip.clk_wiz_v3_6.clk_wiz_v3_6
SET_CORE_PATH /opt/Xilinx/14.7/ISE_DS/ISE/coregen/ip/xilinx/primary/com/xilinx/ip/clk_wiz_v3_6
SET_CORE_GUIPATH /opt/Xilinx/14.7/ISE_DS/ISE/coregen/ip/xilinx/primary/com/xilinx/ip/clk_wiz_v3_6/gui/clk_wiz_v3_6.tcl
SET_CORE_DATASHEET /opt/Xilinx/14.7/ISE_DS/ISE/coregen/ip/xilinx/primary/com/xilinx/ip/clk_wiz_v3_6/doc/pg065_clk_wiz.pdf
ADD_CORE_DOCUMENT </opt/Xilinx/14.7/ISE_DS/ISE/coregen/ip/xilinx/primary/com/xilinx/ip/clk_wiz_v3_6/doc/pg065_clk_wiz.pdf><pg065_clk_wiz.pdf>
ADD_CORE_DOCUMENT </opt/Xilinx/14.7/ISE_DS/ISE/coregen/ip/xilinx/primary/com/xilinx/ip/clk_wiz_v3_6/doc/clk_wiz_v3_6_readme.txt><clk_wiz_v3_6_readme.txt>
ADD_CORE_DOCUMENT </opt/Xilinx/14.7/ISE_DS/ISE/coregen/ip/xilinx/primary/com/xilinx/ip/clk_wiz_v3_6/doc/clk_wiz_v3_6_vinfo.html><clk_wiz_v3_6_vinfo.html>

505
ipcore_dir/tmp/customization_gui.0.232841994722.out
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@ -1,505 +0,0 @@
SET_FLAG DEBUG FALSE
SET_FLAG MODE BATCH
SET_FLAG STANDALONE_MODE FALSE
SET_PREFERENCE devicefamily spartan6
SET_PREFERENCE device xc6slx9
SET_PREFERENCE speedgrade -2
SET_PREFERENCE package tqg144
SET_PREFERENCE verilogsim true
SET_PREFERENCE vhdlsim false
SET_PREFERENCE simulationfiles Behavioral
SET_PREFERENCE busformat BusFormatAngleBracketNotRipped
SET_PREFERENCE outputdirectory /home/tim/Projects/fpga/micro_test/ipcore_dir/
SET_PREFERENCE workingdirectory /home/tim/Projects/fpga/micro_test/ipcore_dir/tmp/
SET_PREFERENCE subworkingdirectory /home/tim/Projects/fpga/micro_test/ipcore_dir/tmp/_cg/
SET_PREFERENCE transientdirectory /home/tim/Projects/fpga/micro_test/ipcore_dir/tmp/_cg/_dbg/
SET_PREFERENCE designentry Verilog
SET_PREFERENCE flowvendor Other
SET_PREFERENCE addpads false
SET_PREFERENCE projectname coregen
SET_PREFERENCE formalverification false
SET_PREFERENCE asysymbol false
SET_PREFERENCE implementationfiletype Ngc
SET_PREFERENCE foundationsym false
SET_PREFERENCE createndf false
SET_PREFERENCE removerpms false
SET_PARAMETER Component_Name clk_wiz
SET_PARAMETER Use_Freq_Synth true
SET_PARAMETER Use_Phase_Alignment false
SET_PARAMETER Use_Min_Power false
SET_PARAMETER Use_Dyn_Phase_Shift false
SET_PARAMETER Use_Dyn_Reconfig false
SET_PARAMETER Jitter_Sel No_Jitter
SET_PARAMETER Use_Spread_Spectrum false
SET_PARAMETER Use_Spread_Spectrum_1 false
SET_PARAMETER Prim_In_Freq 50.000
SET_PARAMETER In_Freq_Units Units_MHz
SET_PARAMETER In_Jitter_Units Units_UI
SET_PARAMETER Relative_Inclk REL_PRIMARY
SET_PARAMETER Secondary_In_Freq 100.000
SET_PARAMETER Jitter_Options UI
SET_PARAMETER Clkin1_UI_Jitter 0.010
SET_PARAMETER Clkin2_UI_Jitter 0.010
SET_PARAMETER Prim_In_Jitter 0.010
SET_PARAMETER Secondary_In_Jitter 0.010
SET_PARAMETER Clkin1_Jitter_Ps 200.0
SET_PARAMETER Clkin2_Jitter_Ps 100.0
SET_PARAMETER Clkout2_Used false
SET_PARAMETER Clkout3_Used false
SET_PARAMETER Clkout4_Used false
SET_PARAMETER Clkout5_Used false
SET_PARAMETER Clkout6_Used false
SET_PARAMETER Clkout7_Used false
SET_PARAMETER Num_Out_Clks 1
SET_PARAMETER Clk_Out1_Use_Fine_Ps_GUI false
SET_PARAMETER Clk_Out2_Use_Fine_Ps_GUI false
SET_PARAMETER Clk_Out3_Use_Fine_Ps_GUI false
SET_PARAMETER Clk_Out4_Use_Fine_Ps_GUI false
SET_PARAMETER Clk_Out5_Use_Fine_Ps_GUI false
SET_PARAMETER Clk_Out6_Use_Fine_Ps_GUI false
SET_PARAMETER Clk_Out7_Use_Fine_Ps_GUI false
SET_PARAMETER primary_port CLK_IN1
SET_PARAMETER CLK_OUT1_port CLK_OUT1
SET_PARAMETER CLK_OUT2_port CLK_OUT2
SET_PARAMETER CLK_OUT3_port CLK_OUT3
SET_PARAMETER CLK_OUT4_port CLK_OUT4
SET_PARAMETER CLK_OUT5_port CLK_OUT5
SET_PARAMETER CLK_OUT6_port CLK_OUT6
SET_PARAMETER CLK_OUT7_port CLK_OUT7
SET_PARAMETER DADDR_port DADDR
SET_PARAMETER DCLK_port DCLK
SET_PARAMETER DRDY_port DRDY
SET_PARAMETER DWE_port DWE
SET_PARAMETER DIN_port DIN
SET_PARAMETER DOUT_port DOUT
SET_PARAMETER DEN_port DEN
SET_PARAMETER PSCLK_port PSCLK
SET_PARAMETER PSEN_port PSEN
SET_PARAMETER PSINCDEC_port PSINCDEC
SET_PARAMETER PSDONE_port PSDONE
SET_PARAMETER Clkout1_Requested_Out_Freq 75.000
SET_PARAMETER Clkout1_Requested_Phase 0.000
SET_PARAMETER Clkout1_Requested_Duty_Cycle 50.000
SET_PARAMETER Clkout2_Requested_Out_Freq 100.000
SET_PARAMETER Clkout2_Requested_Phase 0.000
SET_PARAMETER Clkout2_Requested_Duty_Cycle 50.000
SET_PARAMETER Clkout3_Requested_Out_Freq 100.000
SET_PARAMETER Clkout3_Requested_Phase 0.000
SET_PARAMETER Clkout3_Requested_Duty_Cycle 50.000
SET_PARAMETER Clkout4_Requested_Out_Freq 100.000
SET_PARAMETER Clkout4_Requested_Phase 0.000
SET_PARAMETER Clkout4_Requested_Duty_Cycle 50.000
SET_PARAMETER Clkout5_Requested_Out_Freq 100.000
SET_PARAMETER Clkout5_Requested_Phase 0.000
SET_PARAMETER Clkout5_Requested_Duty_Cycle 50.000
SET_PARAMETER Clkout6_Requested_Out_Freq 100.000
SET_PARAMETER Clkout6_Requested_Phase 0.000
SET_PARAMETER Clkout6_Requested_Duty_Cycle 50.000
SET_PARAMETER Clkout7_Requested_Out_Freq 100.000
SET_PARAMETER Clkout7_Requested_Phase 0.000
SET_PARAMETER Clkout7_Requested_Duty_Cycle 50.000
SET_PARAMETER Use_Max_I_Jitter false
SET_PARAMETER Use_Min_O_Jitter false
SET_PARAMETER Prim_Source Single_ended_clock_capable_pin
SET_PARAMETER Use_Inclk_Switchover false
SET_PARAMETER secondary_port CLK_IN2
SET_PARAMETER Secondary_Source Single_ended_clock_capable_pin
SET_PARAMETER Clkout1_Drives BUFG
SET_PARAMETER Clkout2_Drives BUFG
SET_PARAMETER Clkout3_Drives BUFG
SET_PARAMETER Clkout4_Drives BUFG
SET_PARAMETER Clkout5_Drives BUFG
SET_PARAMETER Clkout6_Drives BUFG
SET_PARAMETER Clkout7_Drives BUFG
SET_PARAMETER Feedback_Source FDBK_AUTO
SET_PARAMETER Clkfb_In_Signaling SINGLE
SET_PARAMETER CLKFB_IN_port CLKFB_IN
SET_PARAMETER CLKFB_IN_P_port CLKFB_IN_P
SET_PARAMETER CLKFB_IN_N_port CLKFB_IN_N
SET_PARAMETER CLKFB_OUT_port CLKFB_OUT
SET_PARAMETER CLKFB_OUT_P_port CLKFB_OUT_P
SET_PARAMETER CLKFB_OUT_N_port CLKFB_OUT_N
SET_PARAMETER Platform lin64
SET_PARAMETER Summary_Strings empty
SET_PARAMETER Use_Locked false
SET_PARAMETER calc_done DONE
SET_PARAMETER Use_Reset false
SET_PARAMETER Use_Power_Down false
SET_PARAMETER Use_Status false
SET_PARAMETER Use_Freeze false
SET_PARAMETER Use_Clk_Valid false
SET_PARAMETER Use_Inclk_Stopped false
SET_PARAMETER Use_Clkfb_Stopped false
SET_PARAMETER RESET_port RESET
SET_PARAMETER LOCKED_port LOCKED
SET_PARAMETER Power_Down_port POWER_DOWN
SET_PARAMETER CLK_VALID_port CLK_VALID
SET_PARAMETER STATUS_port STATUS
SET_PARAMETER CLK_IN_SEL_port CLK_IN_SEL
SET_PARAMETER INPUT_CLK_STOPPED_port INPUT_CLK_STOPPED
SET_PARAMETER CLKFB_STOPPED_port CLKFB_STOPPED
SET_PARAMETER Override_Mmcm false
SET_PARAMETER Mmcm_Notes None
SET_PARAMETER Mmcm_Divclk_Divide 1
SET_PARAMETER Mmcm_Bandwidth OPTIMIZED
SET_PARAMETER Mmcm_Clkfbout_Mult_F 4.000
SET_PARAMETER Mmcm_Clkfbout_Phase 0.000
SET_PARAMETER Mmcm_Clkfbout_Use_Fine_Ps false
SET_PARAMETER Mmcm_Clkin1_Period 10.000
SET_PARAMETER Mmcm_Clkin2_Period 10.000
SET_PARAMETER Mmcm_Clkout4_Cascade false
SET_PARAMETER Mmcm_Clock_Hold false
SET_PARAMETER Mmcm_Compensation ZHOLD
SET_PARAMETER Mmcm_Ref_Jitter1 0.010
SET_PARAMETER Mmcm_Ref_Jitter2 0.010
SET_PARAMETER Mmcm_Startup_Wait false
SET_PARAMETER Mmcm_Clkout0_Divide_F 4.000
SET_PARAMETER Mmcm_Clkout0_Duty_Cycle 0.500
SET_PARAMETER Mmcm_Clkout0_Phase 0.000
SET_PARAMETER Mmcm_Clkout0_Use_Fine_Ps false
SET_PARAMETER Mmcm_Clkout1_Divide 1
SET_PARAMETER Mmcm_Clkout1_Duty_Cycle 0.500
SET_PARAMETER Mmcm_Clkout1_Phase 0.000
SET_PARAMETER Mmcm_Clkout1_Use_Fine_Ps false
SET_PARAMETER Mmcm_Clkout2_Divide 1
SET_PARAMETER Mmcm_Clkout2_Duty_Cycle 0.500
SET_PARAMETER Mmcm_Clkout2_Phase 0.000
SET_PARAMETER Mmcm_Clkout2_Use_Fine_Ps false
SET_PARAMETER Mmcm_Clkout3_Divide 1
SET_PARAMETER Mmcm_Clkout3_Duty_Cycle 0.500
SET_PARAMETER Mmcm_Clkout3_Phase 0.000
SET_PARAMETER Mmcm_Clkout3_Use_Fine_Ps false
SET_PARAMETER Mmcm_Clkout4_Divide 1
SET_PARAMETER Mmcm_Clkout4_Duty_Cycle 0.500
SET_PARAMETER Mmcm_Clkout4_Phase 0.000
SET_PARAMETER Mmcm_Clkout4_Use_Fine_Ps false
SET_PARAMETER Mmcm_Clkout5_Divide 1
SET_PARAMETER Mmcm_Clkout5_Duty_Cycle 0.500
SET_PARAMETER Mmcm_Clkout5_Phase 0.000
SET_PARAMETER Mmcm_Clkout5_Use_Fine_Ps false
SET_PARAMETER Mmcm_Clkout6_Divide 1
SET_PARAMETER Mmcm_Clkout6_Duty_Cycle 0.500
SET_PARAMETER Mmcm_Clkout6_Phase 0.000
SET_PARAMETER Mmcm_Clkout6_Use_Fine_Ps false
SET_PARAMETER Override_Dcm false
SET_PARAMETER Dcm_Notes None
SET_PARAMETER Dcm_Clkdv_Divide 2.0
SET_PARAMETER Dcm_Clkfx_Divide 2
SET_PARAMETER Dcm_Clkfx_Multiply 3
SET_PARAMETER Dcm_Clkin_Divide_By_2 false
SET_PARAMETER Dcm_Clkin_Period 20.000
SET_PARAMETER Dcm_Clkout_Phase_Shift NONE
SET_PARAMETER Dcm_Deskew_Adjust SYSTEM_SYNCHRONOUS
SET_PARAMETER Dcm_Phase_Shift 0
SET_PARAMETER Dcm_Clk_Feedback NONE
SET_PARAMETER Dcm_Startup_Wait false
SET_PARAMETER Dcm_Clk_Out1_Port CLKFX
SET_PARAMETER Dcm_Clk_Out2_Port CLK0
SET_PARAMETER Dcm_Clk_Out3_Port CLK0
SET_PARAMETER Dcm_Clk_Out4_Port CLK0
SET_PARAMETER Dcm_Clk_Out5_Port CLK0
SET_PARAMETER Dcm_Clk_Out6_Port CLK0
SET_PARAMETER Override_Dcm_Clkgen false
SET_PARAMETER Dcm_Clkgen_Notes None
SET_PARAMETER Dcm_Clkgen_Clkfx_Divide 1
SET_PARAMETER Dcm_Clkgen_Clkfx_Multiply 4
SET_PARAMETER Dcm_Clkgen_Clkfxdv_Divide 2
SET_PARAMETER Dcm_Clkgen_Clkfx_Md_Max 0.000
SET_PARAMETER Dcm_Clkgen_Startup_Wait false
SET_PARAMETER Dcm_Clkgen_Clkin_Period 10.000
SET_PARAMETER Dcm_Clkgen_Spread_Spectrum NONE
SET_PARAMETER Dcm_Clkgen_Clk_Out1_Port CLKFX
SET_PARAMETER Dcm_Clkgen_Clk_Out2_Port CLKFX
SET_PARAMETER Dcm_Clkgen_Clk_Out3_Port CLKFX
SET_PARAMETER Override_Pll false
SET_PARAMETER Pll_Notes None
SET_PARAMETER Pll_Bandwidth OPTIMIZED
SET_PARAMETER Pll_Clkfbout_Mult 4
SET_PARAMETER Pll_Clkfbout_Phase 0.000
SET_PARAMETER Pll_Clk_Feedback CLKFBOUT
SET_PARAMETER Pll_Divclk_Divide 1
SET_PARAMETER Pll_Clkin_Period 10.000
SET_PARAMETER Pll_Compensation INTERNAL
SET_PARAMETER Pll_Ref_Jitter 0.010
SET_PARAMETER Pll_Clkout0_Divide 1
SET_PARAMETER Pll_Clkout0_Duty_Cycle 0.500
SET_PARAMETER Pll_Clkout0_Phase 0.000
SET_PARAMETER Pll_Clkout1_Divide 1
SET_PARAMETER Pll_Clkout1_Duty_Cycle 0.500
SET_PARAMETER Pll_Clkout1_Phase 0.000
SET_PARAMETER Pll_Clkout2_Divide 1
SET_PARAMETER Pll_Clkout2_Duty_Cycle 0.500
SET_PARAMETER Pll_Clkout2_Phase 0.000
SET_PARAMETER Pll_Clkout3_Divide 1
SET_PARAMETER Pll_Clkout3_Duty_Cycle 0.500
SET_PARAMETER Pll_Clkout3_Phase 0.000
SET_PARAMETER Pll_Clkout4_Divide 1
SET_PARAMETER Pll_Clkout4_Duty_Cycle 0.500
SET_PARAMETER Pll_Clkout4_Phase 0.000
SET_PARAMETER Pll_Clkout5_Divide 1
SET_PARAMETER Pll_Clkout5_Duty_Cycle 0.500
SET_PARAMETER Pll_Clkout5_Phase 0.000
SET_PARAMETER dcm_pll_cascade NONE
SET_PARAMETER clock_mgr_type AUTO
SET_PARAMETER primtype_sel PLL_BASE
SET_PARAMETER primitive MMCM
SET_PARAMETER SS_Mode CENTER_HIGH
SET_PARAMETER SS_Mod_Freq 250
SET_SIM_PARAMETER c_clkout2_used 0
SET_SIM_PARAMETER c_clkout3_used 0
SET_SIM_PARAMETER c_clkout4_used 0
SET_SIM_PARAMETER c_clkout5_used 0
SET_SIM_PARAMETER c_clkout6_used 0
SET_SIM_PARAMETER c_clkout7_used 0
SET_SIM_PARAMETER c_use_clkout1_bar 0
SET_SIM_PARAMETER c_use_clkout2_bar 0
SET_SIM_PARAMETER c_use_clkout3_bar 0
SET_SIM_PARAMETER c_use_clkout4_bar 0
SET_SIM_PARAMETER c_component_name clk_wiz
SET_SIM_PARAMETER c_platform lin64
SET_SIM_PARAMETER c_use_freq_synth 1
SET_SIM_PARAMETER c_use_phase_alignment 0
SET_SIM_PARAMETER c_prim_in_jitter 0.010
SET_SIM_PARAMETER c_secondary_in_jitter 0.010
SET_SIM_PARAMETER c_jitter_sel No_Jitter
SET_SIM_PARAMETER c_use_min_power 0
SET_SIM_PARAMETER c_use_min_o_jitter 0
SET_SIM_PARAMETER c_use_max_i_jitter 0
SET_SIM_PARAMETER c_use_dyn_phase_shift 0
SET_SIM_PARAMETER c_use_inclk_switchover 0
SET_SIM_PARAMETER c_use_dyn_reconfig 0
SET_SIM_PARAMETER c_use_spread_spectrum 0
SET_SIM_PARAMETER c_use_spread_spectrum_1 0
SET_SIM_PARAMETER c_primtype_sel DCM_SP
SET_SIM_PARAMETER c_use_clk_valid 0
SET_SIM_PARAMETER c_prim_in_freq 50.000
SET_SIM_PARAMETER c_in_freq_units Units_MHz
SET_SIM_PARAMETER c_secondary_in_freq 100.000
SET_SIM_PARAMETER c_feedback_source FDBK_AUTO
SET_SIM_PARAMETER c_prim_source Single_ended_clock_capable_pin
SET_SIM_PARAMETER c_secondary_source Single_ended_clock_capable_pin
SET_SIM_PARAMETER c_clkfb_in_signaling SINGLE
SET_SIM_PARAMETER c_use_reset 0
SET_SIM_PARAMETER c_use_locked 0
SET_SIM_PARAMETER c_use_inclk_stopped 0
SET_SIM_PARAMETER c_use_clkfb_stopped 0
SET_SIM_PARAMETER c_use_power_down 0
SET_SIM_PARAMETER c_use_status 0
SET_SIM_PARAMETER c_use_freeze 0
SET_SIM_PARAMETER c_num_out_clks 1
SET_SIM_PARAMETER c_clkout1_drives BUFG
SET_SIM_PARAMETER c_clkout2_drives BUFG
SET_SIM_PARAMETER c_clkout3_drives BUFG
SET_SIM_PARAMETER c_clkout4_drives BUFG
SET_SIM_PARAMETER c_clkout5_drives BUFG
SET_SIM_PARAMETER c_clkout6_drives BUFG
SET_SIM_PARAMETER c_clkout7_drives BUFG
SET_SIM_PARAMETER c_inclk_sum_row0 "Input Clock Freq (MHz) Input Jitter (UI)"
SET_SIM_PARAMETER c_inclk_sum_row1 __primary__________50.000____________0.010
SET_SIM_PARAMETER c_inclk_sum_row2 no_secondary_input_clock
SET_SIM_PARAMETER c_outclk_sum_row0a "Output Output Phase Duty Pk-to-Pk Phase"
SET_SIM_PARAMETER c_outclk_sum_row0b "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
SET_SIM_PARAMETER c_outclk_sum_row1 CLK_OUT1____75.000______0.000______50.0______466.667____150.000
SET_SIM_PARAMETER c_outclk_sum_row2 no_CLK_OUT2_output
SET_SIM_PARAMETER c_outclk_sum_row3 no_CLK_OUT3_output
SET_SIM_PARAMETER c_outclk_sum_row4 no_CLK_OUT4_output
SET_SIM_PARAMETER c_outclk_sum_row5 no_CLK_OUT5_output
SET_SIM_PARAMETER c_outclk_sum_row6 no_CLK_OUT6_output
SET_SIM_PARAMETER c_outclk_sum_row7 no_CLK_OUT7_output
SET_SIM_PARAMETER c_clkout1_requested_out_freq 75.000
SET_SIM_PARAMETER c_clkout2_requested_out_freq 100.000
SET_SIM_PARAMETER c_clkout3_requested_out_freq 100.000
SET_SIM_PARAMETER c_clkout4_requested_out_freq 100.000
SET_SIM_PARAMETER c_clkout5_requested_out_freq 100.000
SET_SIM_PARAMETER c_clkout6_requested_out_freq 100.000
SET_SIM_PARAMETER c_clkout7_requested_out_freq 100.000
SET_SIM_PARAMETER c_clkout1_requested_phase 0.000
SET_SIM_PARAMETER c_clkout2_requested_phase 0.000
SET_SIM_PARAMETER c_clkout3_requested_phase 0.000
SET_SIM_PARAMETER c_clkout4_requested_phase 0.000
SET_SIM_PARAMETER c_clkout5_requested_phase 0.000
SET_SIM_PARAMETER c_clkout6_requested_phase 0.000
SET_SIM_PARAMETER c_clkout7_requested_phase 0.000
SET_SIM_PARAMETER c_clkout1_requested_duty_cycle 50.000
SET_SIM_PARAMETER c_clkout2_requested_duty_cycle 50.000
SET_SIM_PARAMETER c_clkout3_requested_duty_cycle 50.000
SET_SIM_PARAMETER c_clkout4_requested_duty_cycle 50.000
SET_SIM_PARAMETER c_clkout5_requested_duty_cycle 50.000
SET_SIM_PARAMETER c_clkout6_requested_duty_cycle 50.000
SET_SIM_PARAMETER c_clkout7_requested_duty_cycle 50.000
SET_SIM_PARAMETER c_clkout1_out_freq 75.000
SET_SIM_PARAMETER c_clkout2_out_freq N/A
SET_SIM_PARAMETER c_clkout3_out_freq N/A
SET_SIM_PARAMETER c_clkout4_out_freq N/A
SET_SIM_PARAMETER c_clkout5_out_freq N/A
SET_SIM_PARAMETER c_clkout6_out_freq N/A
SET_SIM_PARAMETER c_clkout7_out_freq N/A
SET_SIM_PARAMETER c_clkout1_phase 0.000
SET_SIM_PARAMETER c_clkout2_phase N/A
SET_SIM_PARAMETER c_clkout3_phase N/A
SET_SIM_PARAMETER c_clkout4_phase N/A
SET_SIM_PARAMETER c_clkout5_phase N/A
SET_SIM_PARAMETER c_clkout6_phase N/A
SET_SIM_PARAMETER c_clkout7_phase N/A
SET_SIM_PARAMETER c_clkout1_duty_cycle 50.0
SET_SIM_PARAMETER c_clkout2_duty_cycle N/A
SET_SIM_PARAMETER c_clkout3_duty_cycle N/A
SET_SIM_PARAMETER c_clkout4_duty_cycle N/A
SET_SIM_PARAMETER c_clkout5_duty_cycle N/A
SET_SIM_PARAMETER c_clkout6_duty_cycle N/A
SET_SIM_PARAMETER c_clkout7_duty_cycle N/A
SET_SIM_PARAMETER c_mmcm_notes None
SET_SIM_PARAMETER c_mmcm_bandwidth OPTIMIZED
SET_SIM_PARAMETER c_mmcm_clkfbout_mult_f 4.000
SET_SIM_PARAMETER c_mmcm_clkin1_period 10.000
SET_SIM_PARAMETER c_mmcm_clkin2_period 10.000
SET_SIM_PARAMETER c_mmcm_clkout4_cascade FALSE
SET_SIM_PARAMETER c_mmcm_clock_hold FALSE
SET_SIM_PARAMETER c_mmcm_compensation ZHOLD
SET_SIM_PARAMETER c_mmcm_divclk_divide 1
SET_SIM_PARAMETER c_mmcm_ref_jitter1 0.010
SET_SIM_PARAMETER c_mmcm_ref_jitter2 0.010
SET_SIM_PARAMETER c_mmcm_startup_wait FALSE
SET_SIM_PARAMETER c_mmcm_clkout0_divide_f 4.000
SET_SIM_PARAMETER c_mmcm_clkout1_divide 1
SET_SIM_PARAMETER c_mmcm_clkout2_divide 1
SET_SIM_PARAMETER c_mmcm_clkout3_divide 1
SET_SIM_PARAMETER c_mmcm_clkout4_divide 1
SET_SIM_PARAMETER c_mmcm_clkout5_divide 1
SET_SIM_PARAMETER c_mmcm_clkout6_divide 1
SET_SIM_PARAMETER c_mmcm_clkout0_duty_cycle 0.500
SET_SIM_PARAMETER c_mmcm_clkout1_duty_cycle 0.500
SET_SIM_PARAMETER c_mmcm_clkout2_duty_cycle 0.500
SET_SIM_PARAMETER c_mmcm_clkout3_duty_cycle 0.500
SET_SIM_PARAMETER c_mmcm_clkout4_duty_cycle 0.500
SET_SIM_PARAMETER c_mmcm_clkout5_duty_cycle 0.500
SET_SIM_PARAMETER c_mmcm_clkout6_duty_cycle 0.500
SET_SIM_PARAMETER c_mmcm_clkfbout_phase 0.000
SET_SIM_PARAMETER c_mmcm_clkout0_phase 0.000
SET_SIM_PARAMETER c_mmcm_clkout1_phase 0.000
SET_SIM_PARAMETER c_mmcm_clkout2_phase 0.000
SET_SIM_PARAMETER c_mmcm_clkout3_phase 0.000
SET_SIM_PARAMETER c_mmcm_clkout4_phase 0.000
SET_SIM_PARAMETER c_mmcm_clkout5_phase 0.000
SET_SIM_PARAMETER c_mmcm_clkout6_phase 0.000
SET_SIM_PARAMETER c_mmcm_clkfbout_use_fine_ps FALSE
SET_SIM_PARAMETER c_mmcm_clkout0_use_fine_ps FALSE
SET_SIM_PARAMETER c_mmcm_clkout1_use_fine_ps FALSE
SET_SIM_PARAMETER c_mmcm_clkout2_use_fine_ps FALSE
SET_SIM_PARAMETER c_mmcm_clkout3_use_fine_ps FALSE
SET_SIM_PARAMETER c_mmcm_clkout4_use_fine_ps FALSE
SET_SIM_PARAMETER c_mmcm_clkout5_use_fine_ps FALSE
SET_SIM_PARAMETER c_mmcm_clkout6_use_fine_ps FALSE
SET_SIM_PARAMETER c_pll_notes None
SET_SIM_PARAMETER c_pll_bandwidth OPTIMIZED
SET_SIM_PARAMETER c_pll_clk_feedback CLKFBOUT
SET_SIM_PARAMETER c_pll_clkfbout_mult 4
SET_SIM_PARAMETER c_pll_clkin_period 10.000
SET_SIM_PARAMETER c_pll_compensation INTERNAL
SET_SIM_PARAMETER c_pll_divclk_divide 1
SET_SIM_PARAMETER c_pll_ref_jitter 0.010
SET_SIM_PARAMETER c_pll_clkout0_divide 1
SET_SIM_PARAMETER c_pll_clkout1_divide 1
SET_SIM_PARAMETER c_pll_clkout2_divide 1
SET_SIM_PARAMETER c_pll_clkout3_divide 1
SET_SIM_PARAMETER c_pll_clkout4_divide 1
SET_SIM_PARAMETER c_pll_clkout5_divide 1
SET_SIM_PARAMETER c_pll_clkout0_duty_cycle 0.500
SET_SIM_PARAMETER c_pll_clkout1_duty_cycle 0.500
SET_SIM_PARAMETER c_pll_clkout2_duty_cycle 0.500
SET_SIM_PARAMETER c_pll_clkout3_duty_cycle 0.500
SET_SIM_PARAMETER c_pll_clkout4_duty_cycle 0.500
SET_SIM_PARAMETER c_pll_clkout5_duty_cycle 0.500
SET_SIM_PARAMETER c_pll_clkfbout_phase 0.000
SET_SIM_PARAMETER c_pll_clkout0_phase 0.000
SET_SIM_PARAMETER c_pll_clkout1_phase 0.000
SET_SIM_PARAMETER c_pll_clkout2_phase 0.000
SET_SIM_PARAMETER c_pll_clkout3_phase 0.000
SET_SIM_PARAMETER c_pll_clkout4_phase 0.000
SET_SIM_PARAMETER c_pll_clkout5_phase 0.000
SET_SIM_PARAMETER c_dcm_notes None
SET_SIM_PARAMETER c_dcm_clkdv_divide 2.000
SET_SIM_PARAMETER c_dcm_clkfx_divide 2
SET_SIM_PARAMETER c_dcm_clkfx_multiply 3
SET_SIM_PARAMETER c_dcm_clkin_divide_by_2 FALSE
SET_SIM_PARAMETER c_dcm_clkin_period 20.0
SET_SIM_PARAMETER c_dcm_clkout_phase_shift NONE
SET_SIM_PARAMETER c_dcm_clk_feedback NONE
SET_SIM_PARAMETER c_dcm_clk_feedback_port NONE
SET_SIM_PARAMETER c_dcm_deskew_adjust SYSTEM_SYNCHRONOUS
SET_SIM_PARAMETER c_dcm_phase_shift 0
SET_SIM_PARAMETER c_dcm_startup_wait FALSE
SET_SIM_PARAMETER c_dcm_clk_out1_port CLKFX
SET_SIM_PARAMETER c_dcm_clk_out2_port NONE
SET_SIM_PARAMETER c_dcm_clk_out3_port NONE
SET_SIM_PARAMETER c_dcm_clk_out4_port NONE
SET_SIM_PARAMETER c_dcm_clk_out5_port NONE
SET_SIM_PARAMETER c_dcm_clk_out6_port NONE
SET_SIM_PARAMETER c_dcm_clkgen_notes None
SET_SIM_PARAMETER c_dcm_clkgen_clkfxdv_divide 2
SET_SIM_PARAMETER c_dcm_clkgen_clkfx_divide 1
SET_SIM_PARAMETER c_dcm_clkgen_clkfx_multiply 4
SET_SIM_PARAMETER c_dcm_clkgen_dfs_bandwidth OPTIMIZED
SET_SIM_PARAMETER c_dcm_clkgen_prog_md_bandwidth OPTIMIZED
SET_SIM_PARAMETER c_dcm_clkgen_clkin_period 20.0
SET_SIM_PARAMETER c_dcm_clkgen_clkfx_md_max 0.000
SET_SIM_PARAMETER c_dcm_clkgen_spread_spectrum NONE
SET_SIM_PARAMETER c_dcm_clkgen_startup_wait FALSE
SET_SIM_PARAMETER c_dcm_clkgen_clk_out1_port CLKFX
SET_SIM_PARAMETER c_dcm_clkgen_clk_out2_port NONE
SET_SIM_PARAMETER c_dcm_clkgen_clk_out3_port NONE
SET_SIM_PARAMETER c_clock_mgr_type AUTO
SET_SIM_PARAMETER c_override_mmcm 0
SET_SIM_PARAMETER c_override_pll 0
SET_SIM_PARAMETER c_override_dcm 0
SET_SIM_PARAMETER c_override_dcm_clkgen 0
SET_SIM_PARAMETER c_dcm_pll_cascade NONE
SET_SIM_PARAMETER c_primary_port CLK_IN1
SET_SIM_PARAMETER c_secondary_port CLK_IN2
SET_SIM_PARAMETER c_clk_out1_port CLK_OUT1
SET_SIM_PARAMETER c_clk_out2_port CLK_OUT2
SET_SIM_PARAMETER c_clk_out3_port CLK_OUT3
SET_SIM_PARAMETER c_clk_out4_port CLK_OUT4
SET_SIM_PARAMETER c_clk_out5_port CLK_OUT5
SET_SIM_PARAMETER c_clk_out6_port CLK_OUT6
SET_SIM_PARAMETER c_clk_out7_port CLK_OUT7
SET_SIM_PARAMETER c_reset_port RESET
SET_SIM_PARAMETER c_locked_port LOCKED
SET_SIM_PARAMETER c_clkfb_in_port CLKFB_IN
SET_SIM_PARAMETER c_clkfb_in_p_port CLKFB_IN_P
SET_SIM_PARAMETER c_clkfb_in_n_port CLKFB_IN_N
SET_SIM_PARAMETER c_clkfb_out_port CLKFB_OUT
SET_SIM_PARAMETER c_clkfb_out_p_port CLKFB_OUT_P
SET_SIM_PARAMETER c_clkfb_out_n_port CLKFB_OUT_N
SET_SIM_PARAMETER c_power_down_port POWER_DOWN
SET_SIM_PARAMETER c_daddr_port DADDR
SET_SIM_PARAMETER c_dclk_port DCLK
SET_SIM_PARAMETER c_drdy_port DRDY
SET_SIM_PARAMETER c_dwe_port DWE
SET_SIM_PARAMETER c_din_port DIN
SET_SIM_PARAMETER c_dout_port DOUT
SET_SIM_PARAMETER c_den_port DEN
SET_SIM_PARAMETER c_psclk_port PSCLK
SET_SIM_PARAMETER c_psen_port PSEN
SET_SIM_PARAMETER c_psincdec_port PSINCDEC
SET_SIM_PARAMETER c_psdone_port PSDONE
SET_SIM_PARAMETER c_clk_valid_port CLK_VALID
SET_SIM_PARAMETER c_status_port STATUS
SET_SIM_PARAMETER c_clk_in_sel_port CLK_IN_SEL
SET_SIM_PARAMETER c_input_clk_stopped_port INPUT_CLK_STOPPED
SET_SIM_PARAMETER c_clkfb_stopped_port CLKFB_STOPPED
SET_SIM_PARAMETER c_clkin1_jitter_ps 200.0
SET_SIM_PARAMETER c_clkin2_jitter_ps 100.0
SET_SIM_PARAMETER c_primitive MMCM
SET_SIM_PARAMETER c_ss_mode CENTER_HIGH
SET_SIM_PARAMETER c_ss_mod_period 4000
SET_CORE_NAME Clocking Wizard
SET_CORE_VERSION 3.6
SET_CORE_VLNV xilinx.com:ip:clk_wiz:3.6
SET_CORE_CLASS com.xilinx.ip.clk_wiz_v3_6.clk_wiz_v3_6
SET_CORE_PATH /opt/Xilinx/14.7/ISE_DS/ISE/coregen/ip/xilinx/primary/com/xilinx/ip/clk_wiz_v3_6
SET_CORE_GUIPATH /opt/Xilinx/14.7/ISE_DS/ISE/coregen/ip/xilinx/primary/com/xilinx/ip/clk_wiz_v3_6/gui/clk_wiz_v3_6.tcl
SET_CORE_DATASHEET /opt/Xilinx/14.7/ISE_DS/ISE/coregen/ip/xilinx/primary/com/xilinx/ip/clk_wiz_v3_6/doc/pg065_clk_wiz.pdf
ADD_CORE_DOCUMENT </opt/Xilinx/14.7/ISE_DS/ISE/coregen/ip/xilinx/primary/com/xilinx/ip/clk_wiz_v3_6/doc/pg065_clk_wiz.pdf><pg065_clk_wiz.pdf>
ADD_CORE_DOCUMENT </opt/Xilinx/14.7/ISE_DS/ISE/coregen/ip/xilinx/primary/com/xilinx/ip/clk_wiz_v3_6/doc/clk_wiz_v3_6_readme.txt><clk_wiz_v3_6_readme.txt>
ADD_CORE_DOCUMENT </opt/Xilinx/14.7/ISE_DS/ISE/coregen/ip/xilinx/primary/com/xilinx/ip/clk_wiz_v3_6/doc/clk_wiz_v3_6_vinfo.html><clk_wiz_v3_6_vinfo.html>

505
ipcore_dir/tmp/customization_gui.0.241021374353.out
View File

@ -1,505 +0,0 @@
SET_FLAG DEBUG FALSE
SET_FLAG MODE BATCH
SET_FLAG STANDALONE_MODE FALSE
SET_PREFERENCE devicefamily spartan6
SET_PREFERENCE device xc6slx9
SET_PREFERENCE speedgrade -2
SET_PREFERENCE package tqg144
SET_PREFERENCE verilogsim true
SET_PREFERENCE vhdlsim false
SET_PREFERENCE simulationfiles Behavioral
SET_PREFERENCE busformat BusFormatAngleBracketNotRipped
SET_PREFERENCE outputdirectory /home/tim/Projects/fpga/micro_test/ipcore_dir/
SET_PREFERENCE workingdirectory /home/tim/Projects/fpga/micro_test/ipcore_dir/tmp/
SET_PREFERENCE subworkingdirectory /home/tim/Projects/fpga/micro_test/ipcore_dir/tmp/_cg/
SET_PREFERENCE transientdirectory /home/tim/Projects/fpga/micro_test/ipcore_dir/tmp/_cg/_dbg/
SET_PREFERENCE designentry Verilog
SET_PREFERENCE flowvendor Other
SET_PREFERENCE addpads false
SET_PREFERENCE projectname coregen
SET_PREFERENCE formalverification false
SET_PREFERENCE asysymbol false
SET_PREFERENCE implementationfiletype Ngc
SET_PREFERENCE foundationsym false
SET_PREFERENCE createndf false
SET_PREFERENCE removerpms false
SET_PARAMETER Component_Name hdmi_clk
SET_PARAMETER Use_Freq_Synth true
SET_PARAMETER Use_Phase_Alignment false
SET_PARAMETER Use_Min_Power false
SET_PARAMETER Use_Dyn_Phase_Shift false
SET_PARAMETER Use_Dyn_Reconfig false
SET_PARAMETER Jitter_Sel No_Jitter
SET_PARAMETER Use_Spread_Spectrum false
SET_PARAMETER Use_Spread_Spectrum_1 false
SET_PARAMETER Prim_In_Freq 50
SET_PARAMETER In_Freq_Units Units_MHz
SET_PARAMETER In_Jitter_Units Units_UI
SET_PARAMETER Relative_Inclk REL_PRIMARY
SET_PARAMETER Secondary_In_Freq 100.000
SET_PARAMETER Jitter_Options UI
SET_PARAMETER Clkin1_UI_Jitter 0.010
SET_PARAMETER Clkin2_UI_Jitter 0.010
SET_PARAMETER Prim_In_Jitter 0.010
SET_PARAMETER Secondary_In_Jitter 0.010
SET_PARAMETER Clkin1_Jitter_Ps 200.0
SET_PARAMETER Clkin2_Jitter_Ps 100.0
SET_PARAMETER Clkout2_Used false
SET_PARAMETER Clkout3_Used false
SET_PARAMETER Clkout4_Used false
SET_PARAMETER Clkout5_Used false
SET_PARAMETER Clkout6_Used false
SET_PARAMETER Clkout7_Used false
SET_PARAMETER Num_Out_Clks 1
SET_PARAMETER Clk_Out1_Use_Fine_Ps_GUI false
SET_PARAMETER Clk_Out2_Use_Fine_Ps_GUI false
SET_PARAMETER Clk_Out3_Use_Fine_Ps_GUI false
SET_PARAMETER Clk_Out4_Use_Fine_Ps_GUI false
SET_PARAMETER Clk_Out5_Use_Fine_Ps_GUI false
SET_PARAMETER Clk_Out6_Use_Fine_Ps_GUI false
SET_PARAMETER Clk_Out7_Use_Fine_Ps_GUI false
SET_PARAMETER primary_port CLK_IN1
SET_PARAMETER CLK_OUT1_port CLK_OUT1
SET_PARAMETER CLK_OUT2_port CLK_OUT2
SET_PARAMETER CLK_OUT3_port CLK_OUT3
SET_PARAMETER CLK_OUT4_port CLK_OUT4
SET_PARAMETER CLK_OUT5_port CLK_OUT5
SET_PARAMETER CLK_OUT6_port CLK_OUT6
SET_PARAMETER CLK_OUT7_port CLK_OUT7
SET_PARAMETER DADDR_port DADDR
SET_PARAMETER DCLK_port DCLK
SET_PARAMETER DRDY_port DRDY
SET_PARAMETER DWE_port DWE
SET_PARAMETER DIN_port DIN
SET_PARAMETER DOUT_port DOUT
SET_PARAMETER DEN_port DEN
SET_PARAMETER PSCLK_port PSCLK
SET_PARAMETER PSEN_port PSEN
SET_PARAMETER PSINCDEC_port PSINCDEC
SET_PARAMETER PSDONE_port PSDONE
SET_PARAMETER Clkout1_Requested_Out_Freq 75
SET_PARAMETER Clkout1_Requested_Phase 0.000
SET_PARAMETER Clkout1_Requested_Duty_Cycle 50.000
SET_PARAMETER Clkout2_Requested_Out_Freq 100.000
SET_PARAMETER Clkout2_Requested_Phase 0.000
SET_PARAMETER Clkout2_Requested_Duty_Cycle 50.000
SET_PARAMETER Clkout3_Requested_Out_Freq 100.000
SET_PARAMETER Clkout3_Requested_Phase 0.000
SET_PARAMETER Clkout3_Requested_Duty_Cycle 50.000
SET_PARAMETER Clkout4_Requested_Out_Freq 100.000
SET_PARAMETER Clkout4_Requested_Phase 0.000
SET_PARAMETER Clkout4_Requested_Duty_Cycle 50.000
SET_PARAMETER Clkout5_Requested_Out_Freq 100.000
SET_PARAMETER Clkout5_Requested_Phase 0.000
SET_PARAMETER Clkout5_Requested_Duty_Cycle 50.000
SET_PARAMETER Clkout6_Requested_Out_Freq 100.000
SET_PARAMETER Clkout6_Requested_Phase 0.000
SET_PARAMETER Clkout6_Requested_Duty_Cycle 50.000
SET_PARAMETER Clkout7_Requested_Out_Freq 100.000
SET_PARAMETER Clkout7_Requested_Phase 0.000
SET_PARAMETER Clkout7_Requested_Duty_Cycle 50.000
SET_PARAMETER Use_Max_I_Jitter false
SET_PARAMETER Use_Min_O_Jitter false
SET_PARAMETER Prim_Source Single_ended_clock_capable_pin
SET_PARAMETER Use_Inclk_Switchover false
SET_PARAMETER secondary_port CLK_IN2
SET_PARAMETER Secondary_Source Single_ended_clock_capable_pin
SET_PARAMETER Clkout1_Drives BUFG
SET_PARAMETER Clkout2_Drives BUFG
SET_PARAMETER Clkout3_Drives BUFG
SET_PARAMETER Clkout4_Drives BUFG
SET_PARAMETER Clkout5_Drives BUFG
SET_PARAMETER Clkout6_Drives BUFG
SET_PARAMETER Clkout7_Drives BUFG
SET_PARAMETER Feedback_Source FDBK_AUTO
SET_PARAMETER Clkfb_In_Signaling SINGLE
SET_PARAMETER CLKFB_IN_port CLKFB_IN
SET_PARAMETER CLKFB_IN_P_port CLKFB_IN_P
SET_PARAMETER CLKFB_IN_N_port CLKFB_IN_N
SET_PARAMETER CLKFB_OUT_port CLKFB_OUT
SET_PARAMETER CLKFB_OUT_P_port CLKFB_OUT_P
SET_PARAMETER CLKFB_OUT_N_port CLKFB_OUT_N
SET_PARAMETER Platform lin64
SET_PARAMETER Summary_Strings empty
SET_PARAMETER Use_Locked false
SET_PARAMETER calc_done DONE
SET_PARAMETER Use_Reset false
SET_PARAMETER Use_Power_Down false
SET_PARAMETER Use_Status false
SET_PARAMETER Use_Freeze false
SET_PARAMETER Use_Clk_Valid false
SET_PARAMETER Use_Inclk_Stopped false
SET_PARAMETER Use_Clkfb_Stopped false
SET_PARAMETER RESET_port RESET
SET_PARAMETER LOCKED_port LOCKED
SET_PARAMETER Power_Down_port POWER_DOWN
SET_PARAMETER CLK_VALID_port CLK_VALID
SET_PARAMETER STATUS_port STATUS
SET_PARAMETER CLK_IN_SEL_port CLK_IN_SEL
SET_PARAMETER INPUT_CLK_STOPPED_port INPUT_CLK_STOPPED
SET_PARAMETER CLKFB_STOPPED_port CLKFB_STOPPED
SET_PARAMETER Override_Mmcm false
SET_PARAMETER Mmcm_Notes None
SET_PARAMETER Mmcm_Divclk_Divide 1
SET_PARAMETER Mmcm_Bandwidth OPTIMIZED
SET_PARAMETER Mmcm_Clkfbout_Mult_F 4.000
SET_PARAMETER Mmcm_Clkfbout_Phase 0.000
SET_PARAMETER Mmcm_Clkfbout_Use_Fine_Ps false
SET_PARAMETER Mmcm_Clkin1_Period 10.000
SET_PARAMETER Mmcm_Clkin2_Period 10.000
SET_PARAMETER Mmcm_Clkout4_Cascade false
SET_PARAMETER Mmcm_Clock_Hold false
SET_PARAMETER Mmcm_Compensation ZHOLD
SET_PARAMETER Mmcm_Ref_Jitter1 0.010
SET_PARAMETER Mmcm_Ref_Jitter2 0.010
SET_PARAMETER Mmcm_Startup_Wait false
SET_PARAMETER Mmcm_Clkout0_Divide_F 4.000
SET_PARAMETER Mmcm_Clkout0_Duty_Cycle 0.500
SET_PARAMETER Mmcm_Clkout0_Phase 0.000
SET_PARAMETER Mmcm_Clkout0_Use_Fine_Ps false
SET_PARAMETER Mmcm_Clkout1_Divide 1
SET_PARAMETER Mmcm_Clkout1_Duty_Cycle 0.500
SET_PARAMETER Mmcm_Clkout1_Phase 0.000
SET_PARAMETER Mmcm_Clkout1_Use_Fine_Ps false
SET_PARAMETER Mmcm_Clkout2_Divide 1
SET_PARAMETER Mmcm_Clkout2_Duty_Cycle 0.500
SET_PARAMETER Mmcm_Clkout2_Phase 0.000
SET_PARAMETER Mmcm_Clkout2_Use_Fine_Ps false
SET_PARAMETER Mmcm_Clkout3_Divide 1
SET_PARAMETER Mmcm_Clkout3_Duty_Cycle 0.500
SET_PARAMETER Mmcm_Clkout3_Phase 0.000
SET_PARAMETER Mmcm_Clkout3_Use_Fine_Ps false
SET_PARAMETER Mmcm_Clkout4_Divide 1
SET_PARAMETER Mmcm_Clkout4_Duty_Cycle 0.500
SET_PARAMETER Mmcm_Clkout4_Phase 0.000
SET_PARAMETER Mmcm_Clkout4_Use_Fine_Ps false
SET_PARAMETER Mmcm_Clkout5_Divide 1
SET_PARAMETER Mmcm_Clkout5_Duty_Cycle 0.500
SET_PARAMETER Mmcm_Clkout5_Phase 0.000
SET_PARAMETER Mmcm_Clkout5_Use_Fine_Ps false
SET_PARAMETER Mmcm_Clkout6_Divide 1
SET_PARAMETER Mmcm_Clkout6_Duty_Cycle 0.500
SET_PARAMETER Mmcm_Clkout6_Phase 0.000
SET_PARAMETER Mmcm_Clkout6_Use_Fine_Ps false
SET_PARAMETER Override_Dcm false
SET_PARAMETER Dcm_Notes None
SET_PARAMETER Dcm_Clkdv_Divide 2.0
SET_PARAMETER Dcm_Clkfx_Divide 2
SET_PARAMETER Dcm_Clkfx_Multiply 3
SET_PARAMETER Dcm_Clkin_Divide_By_2 false
SET_PARAMETER Dcm_Clkin_Period 20.000
SET_PARAMETER Dcm_Clkout_Phase_Shift NONE
SET_PARAMETER Dcm_Deskew_Adjust SYSTEM_SYNCHRONOUS
SET_PARAMETER Dcm_Phase_Shift 0
SET_PARAMETER Dcm_Clk_Feedback NONE
SET_PARAMETER Dcm_Startup_Wait false
SET_PARAMETER Dcm_Clk_Out1_Port CLKFX
SET_PARAMETER Dcm_Clk_Out2_Port CLK0
SET_PARAMETER Dcm_Clk_Out3_Port CLK0
SET_PARAMETER Dcm_Clk_Out4_Port CLK0
SET_PARAMETER Dcm_Clk_Out5_Port CLK0
SET_PARAMETER Dcm_Clk_Out6_Port CLK0
SET_PARAMETER Override_Dcm_Clkgen false
SET_PARAMETER Dcm_Clkgen_Notes None
SET_PARAMETER Dcm_Clkgen_Clkfx_Divide 1
SET_PARAMETER Dcm_Clkgen_Clkfx_Multiply 4
SET_PARAMETER Dcm_Clkgen_Clkfxdv_Divide 2
SET_PARAMETER Dcm_Clkgen_Clkfx_Md_Max 0.000
SET_PARAMETER Dcm_Clkgen_Startup_Wait false
SET_PARAMETER Dcm_Clkgen_Clkin_Period 10.000
SET_PARAMETER Dcm_Clkgen_Spread_Spectrum NONE
SET_PARAMETER Dcm_Clkgen_Clk_Out1_Port CLKFX
SET_PARAMETER Dcm_Clkgen_Clk_Out2_Port CLKFX
SET_PARAMETER Dcm_Clkgen_Clk_Out3_Port CLKFX
SET_PARAMETER Override_Pll false
SET_PARAMETER Pll_Notes None
SET_PARAMETER Pll_Bandwidth OPTIMIZED
SET_PARAMETER Pll_Clkfbout_Mult 4
SET_PARAMETER Pll_Clkfbout_Phase 0.000
SET_PARAMETER Pll_Clk_Feedback CLKFBOUT
SET_PARAMETER Pll_Divclk_Divide 1
SET_PARAMETER Pll_Clkin_Period 10.000
SET_PARAMETER Pll_Compensation INTERNAL
SET_PARAMETER Pll_Ref_Jitter 0.010
SET_PARAMETER Pll_Clkout0_Divide 1
SET_PARAMETER Pll_Clkout0_Duty_Cycle 0.500
SET_PARAMETER Pll_Clkout0_Phase 0.000
SET_PARAMETER Pll_Clkout1_Divide 1
SET_PARAMETER Pll_Clkout1_Duty_Cycle 0.500
SET_PARAMETER Pll_Clkout1_Phase 0.000
SET_PARAMETER Pll_Clkout2_Divide 1
SET_PARAMETER Pll_Clkout2_Duty_Cycle 0.500
SET_PARAMETER Pll_Clkout2_Phase 0.000
SET_PARAMETER Pll_Clkout3_Divide 1
SET_PARAMETER Pll_Clkout3_Duty_Cycle 0.500
SET_PARAMETER Pll_Clkout3_Phase 0.000
SET_PARAMETER Pll_Clkout4_Divide 1
SET_PARAMETER Pll_Clkout4_Duty_Cycle 0.500
SET_PARAMETER Pll_Clkout4_Phase 0.000
SET_PARAMETER Pll_Clkout5_Divide 1
SET_PARAMETER Pll_Clkout5_Duty_Cycle 0.500
SET_PARAMETER Pll_Clkout5_Phase 0.000
SET_PARAMETER dcm_pll_cascade NONE
SET_PARAMETER clock_mgr_type AUTO
SET_PARAMETER primtype_sel PLL_BASE
SET_PARAMETER primitive MMCM
SET_PARAMETER SS_Mode CENTER_HIGH
SET_PARAMETER SS_Mod_Freq 250
SET_SIM_PARAMETER c_clkout2_used 0
SET_SIM_PARAMETER c_clkout3_used 0
SET_SIM_PARAMETER c_clkout4_used 0
SET_SIM_PARAMETER c_clkout5_used 0
SET_SIM_PARAMETER c_clkout6_used 0
SET_SIM_PARAMETER c_clkout7_used 0
SET_SIM_PARAMETER c_use_clkout1_bar 0
SET_SIM_PARAMETER c_use_clkout2_bar 0
SET_SIM_PARAMETER c_use_clkout3_bar 0
SET_SIM_PARAMETER c_use_clkout4_bar 0
SET_SIM_PARAMETER c_component_name hdmi_clk
SET_SIM_PARAMETER c_platform lin64
SET_SIM_PARAMETER c_use_freq_synth 1
SET_SIM_PARAMETER c_use_phase_alignment 0
SET_SIM_PARAMETER c_prim_in_jitter 0.010
SET_SIM_PARAMETER c_secondary_in_jitter 0.010
SET_SIM_PARAMETER c_jitter_sel No_Jitter
SET_SIM_PARAMETER c_use_min_power 0
SET_SIM_PARAMETER c_use_min_o_jitter 0
SET_SIM_PARAMETER c_use_max_i_jitter 0
SET_SIM_PARAMETER c_use_dyn_phase_shift 0
SET_SIM_PARAMETER c_use_inclk_switchover 0
SET_SIM_PARAMETER c_use_dyn_reconfig 0
SET_SIM_PARAMETER c_use_spread_spectrum 0
SET_SIM_PARAMETER c_use_spread_spectrum_1 0
SET_SIM_PARAMETER c_primtype_sel DCM_SP
SET_SIM_PARAMETER c_use_clk_valid 0
SET_SIM_PARAMETER c_prim_in_freq 50
SET_SIM_PARAMETER c_in_freq_units Units_MHz
SET_SIM_PARAMETER c_secondary_in_freq 100.000
SET_SIM_PARAMETER c_feedback_source FDBK_AUTO
SET_SIM_PARAMETER c_prim_source Single_ended_clock_capable_pin
SET_SIM_PARAMETER c_secondary_source Single_ended_clock_capable_pin
SET_SIM_PARAMETER c_clkfb_in_signaling SINGLE
SET_SIM_PARAMETER c_use_reset 0
SET_SIM_PARAMETER c_use_locked 0
SET_SIM_PARAMETER c_use_inclk_stopped 0
SET_SIM_PARAMETER c_use_clkfb_stopped 0
SET_SIM_PARAMETER c_use_power_down 0
SET_SIM_PARAMETER c_use_status 0
SET_SIM_PARAMETER c_use_freeze 0
SET_SIM_PARAMETER c_num_out_clks 1
SET_SIM_PARAMETER c_clkout1_drives BUFG
SET_SIM_PARAMETER c_clkout2_drives BUFG
SET_SIM_PARAMETER c_clkout3_drives BUFG
SET_SIM_PARAMETER c_clkout4_drives BUFG
SET_SIM_PARAMETER c_clkout5_drives BUFG
SET_SIM_PARAMETER c_clkout6_drives BUFG
SET_SIM_PARAMETER c_clkout7_drives BUFG
SET_SIM_PARAMETER c_inclk_sum_row0 "Input Clock Freq (MHz) Input Jitter (UI)"
SET_SIM_PARAMETER c_inclk_sum_row1 __primary______________50____________0.010
SET_SIM_PARAMETER c_inclk_sum_row2 no_secondary_input_clock
SET_SIM_PARAMETER c_outclk_sum_row0a "Output Output Phase Duty Pk-to-Pk Phase"
SET_SIM_PARAMETER c_outclk_sum_row0b "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
SET_SIM_PARAMETER c_outclk_sum_row1 CLK_OUT1____75.000______0.000______50.0______466.667____150.000
SET_SIM_PARAMETER c_outclk_sum_row2 no_CLK_OUT2_output
SET_SIM_PARAMETER c_outclk_sum_row3 no_CLK_OUT3_output
SET_SIM_PARAMETER c_outclk_sum_row4 no_CLK_OUT4_output
SET_SIM_PARAMETER c_outclk_sum_row5 no_CLK_OUT5_output
SET_SIM_PARAMETER c_outclk_sum_row6 no_CLK_OUT6_output
SET_SIM_PARAMETER c_outclk_sum_row7 no_CLK_OUT7_output
SET_SIM_PARAMETER c_clkout1_requested_out_freq 75
SET_SIM_PARAMETER c_clkout2_requested_out_freq 100.000
SET_SIM_PARAMETER c_clkout3_requested_out_freq 100.000
SET_SIM_PARAMETER c_clkout4_requested_out_freq 100.000
SET_SIM_PARAMETER c_clkout5_requested_out_freq 100.000
SET_SIM_PARAMETER c_clkout6_requested_out_freq 100.000
SET_SIM_PARAMETER c_clkout7_requested_out_freq 100.000
SET_SIM_PARAMETER c_clkout1_requested_phase 0.000
SET_SIM_PARAMETER c_clkout2_requested_phase 0.000
SET_SIM_PARAMETER c_clkout3_requested_phase 0.000
SET_SIM_PARAMETER c_clkout4_requested_phase 0.000
SET_SIM_PARAMETER c_clkout5_requested_phase 0.000
SET_SIM_PARAMETER c_clkout6_requested_phase 0.000
SET_SIM_PARAMETER c_clkout7_requested_phase 0.000
SET_SIM_PARAMETER c_clkout1_requested_duty_cycle 50.000
SET_SIM_PARAMETER c_clkout2_requested_duty_cycle 50.000
SET_SIM_PARAMETER c_clkout3_requested_duty_cycle 50.000
SET_SIM_PARAMETER c_clkout4_requested_duty_cycle 50.000
SET_SIM_PARAMETER c_clkout5_requested_duty_cycle 50.000
SET_SIM_PARAMETER c_clkout6_requested_duty_cycle 50.000
SET_SIM_PARAMETER c_clkout7_requested_duty_cycle 50.000
SET_SIM_PARAMETER c_clkout1_out_freq 75.000
SET_SIM_PARAMETER c_clkout2_out_freq N/A
SET_SIM_PARAMETER c_clkout3_out_freq N/A
SET_SIM_PARAMETER c_clkout4_out_freq N/A
SET_SIM_PARAMETER c_clkout5_out_freq N/A
SET_SIM_PARAMETER c_clkout6_out_freq N/A
SET_SIM_PARAMETER c_clkout7_out_freq N/A
SET_SIM_PARAMETER c_clkout1_phase 0.000
SET_SIM_PARAMETER c_clkout2_phase N/A
SET_SIM_PARAMETER c_clkout3_phase N/A
SET_SIM_PARAMETER c_clkout4_phase N/A
SET_SIM_PARAMETER c_clkout5_phase N/A
SET_SIM_PARAMETER c_clkout6_phase N/A
SET_SIM_PARAMETER c_clkout7_phase N/A
SET_SIM_PARAMETER c_clkout1_duty_cycle 50.0
SET_SIM_PARAMETER c_clkout2_duty_cycle N/A
SET_SIM_PARAMETER c_clkout3_duty_cycle N/A
SET_SIM_PARAMETER c_clkout4_duty_cycle N/A
SET_SIM_PARAMETER c_clkout5_duty_cycle N/A
SET_SIM_PARAMETER c_clkout6_duty_cycle N/A
SET_SIM_PARAMETER c_clkout7_duty_cycle N/A
SET_SIM_PARAMETER c_mmcm_notes None
SET_SIM_PARAMETER c_mmcm_bandwidth OPTIMIZED
SET_SIM_PARAMETER c_mmcm_clkfbout_mult_f 4.000
SET_SIM_PARAMETER c_mmcm_clkin1_period 10.000
SET_SIM_PARAMETER c_mmcm_clkin2_period 10.000
SET_SIM_PARAMETER c_mmcm_clkout4_cascade FALSE
SET_SIM_PARAMETER c_mmcm_clock_hold FALSE
SET_SIM_PARAMETER c_mmcm_compensation ZHOLD
SET_SIM_PARAMETER c_mmcm_divclk_divide 1
SET_SIM_PARAMETER c_mmcm_ref_jitter1 0.010
SET_SIM_PARAMETER c_mmcm_ref_jitter2 0.010
SET_SIM_PARAMETER c_mmcm_startup_wait FALSE
SET_SIM_PARAMETER c_mmcm_clkout0_divide_f 4.000
SET_SIM_PARAMETER c_mmcm_clkout1_divide 1
SET_SIM_PARAMETER c_mmcm_clkout2_divide 1
SET_SIM_PARAMETER c_mmcm_clkout3_divide 1
SET_SIM_PARAMETER c_mmcm_clkout4_divide 1
SET_SIM_PARAMETER c_mmcm_clkout5_divide 1
SET_SIM_PARAMETER c_mmcm_clkout6_divide 1
SET_SIM_PARAMETER c_mmcm_clkout0_duty_cycle 0.500
SET_SIM_PARAMETER c_mmcm_clkout1_duty_cycle 0.500
SET_SIM_PARAMETER c_mmcm_clkout2_duty_cycle 0.500
SET_SIM_PARAMETER c_mmcm_clkout3_duty_cycle 0.500
SET_SIM_PARAMETER c_mmcm_clkout4_duty_cycle 0.500
SET_SIM_PARAMETER c_mmcm_clkout5_duty_cycle 0.500
SET_SIM_PARAMETER c_mmcm_clkout6_duty_cycle 0.500
SET_SIM_PARAMETER c_mmcm_clkfbout_phase 0.000
SET_SIM_PARAMETER c_mmcm_clkout0_phase 0.000
SET_SIM_PARAMETER c_mmcm_clkout1_phase 0.000
SET_SIM_PARAMETER c_mmcm_clkout2_phase 0.000
SET_SIM_PARAMETER c_mmcm_clkout3_phase 0.000
SET_SIM_PARAMETER c_mmcm_clkout4_phase 0.000
SET_SIM_PARAMETER c_mmcm_clkout5_phase 0.000
SET_SIM_PARAMETER c_mmcm_clkout6_phase 0.000
SET_SIM_PARAMETER c_mmcm_clkfbout_use_fine_ps FALSE
SET_SIM_PARAMETER c_mmcm_clkout0_use_fine_ps FALSE
SET_SIM_PARAMETER c_mmcm_clkout1_use_fine_ps FALSE
SET_SIM_PARAMETER c_mmcm_clkout2_use_fine_ps FALSE
SET_SIM_PARAMETER c_mmcm_clkout3_use_fine_ps FALSE
SET_SIM_PARAMETER c_mmcm_clkout4_use_fine_ps FALSE
SET_SIM_PARAMETER c_mmcm_clkout5_use_fine_ps FALSE
SET_SIM_PARAMETER c_mmcm_clkout6_use_fine_ps FALSE
SET_SIM_PARAMETER c_pll_notes None
SET_SIM_PARAMETER c_pll_bandwidth OPTIMIZED
SET_SIM_PARAMETER c_pll_clk_feedback CLKFBOUT
SET_SIM_PARAMETER c_pll_clkfbout_mult 4
SET_SIM_PARAMETER c_pll_clkin_period 10.000
SET_SIM_PARAMETER c_pll_compensation INTERNAL
SET_SIM_PARAMETER c_pll_divclk_divide 1
SET_SIM_PARAMETER c_pll_ref_jitter 0.010
SET_SIM_PARAMETER c_pll_clkout0_divide 1
SET_SIM_PARAMETER c_pll_clkout1_divide 1
SET_SIM_PARAMETER c_pll_clkout2_divide 1
SET_SIM_PARAMETER c_pll_clkout3_divide 1
SET_SIM_PARAMETER c_pll_clkout4_divide 1
SET_SIM_PARAMETER c_pll_clkout5_divide 1
SET_SIM_PARAMETER c_pll_clkout0_duty_cycle 0.500
SET_SIM_PARAMETER c_pll_clkout1_duty_cycle 0.500
SET_SIM_PARAMETER c_pll_clkout2_duty_cycle 0.500
SET_SIM_PARAMETER c_pll_clkout3_duty_cycle 0.500
SET_SIM_PARAMETER c_pll_clkout4_duty_cycle 0.500
SET_SIM_PARAMETER c_pll_clkout5_duty_cycle 0.500
SET_SIM_PARAMETER c_pll_clkfbout_phase 0.000
SET_SIM_PARAMETER c_pll_clkout0_phase 0.000
SET_SIM_PARAMETER c_pll_clkout1_phase 0.000
SET_SIM_PARAMETER c_pll_clkout2_phase 0.000
SET_SIM_PARAMETER c_pll_clkout3_phase 0.000
SET_SIM_PARAMETER c_pll_clkout4_phase 0.000
SET_SIM_PARAMETER c_pll_clkout5_phase 0.000
SET_SIM_PARAMETER c_dcm_notes None
SET_SIM_PARAMETER c_dcm_clkdv_divide 2.000
SET_SIM_PARAMETER c_dcm_clkfx_divide 2
SET_SIM_PARAMETER c_dcm_clkfx_multiply 3
SET_SIM_PARAMETER c_dcm_clkin_divide_by_2 FALSE
SET_SIM_PARAMETER c_dcm_clkin_period 20.0
SET_SIM_PARAMETER c_dcm_clkout_phase_shift NONE
SET_SIM_PARAMETER c_dcm_clk_feedback NONE
SET_SIM_PARAMETER c_dcm_clk_feedback_port NONE
SET_SIM_PARAMETER c_dcm_deskew_adjust SYSTEM_SYNCHRONOUS
SET_SIM_PARAMETER c_dcm_phase_shift 0
SET_SIM_PARAMETER c_dcm_startup_wait FALSE
SET_SIM_PARAMETER c_dcm_clk_out1_port CLKFX
SET_SIM_PARAMETER c_dcm_clk_out2_port NONE
SET_SIM_PARAMETER c_dcm_clk_out3_port NONE
SET_SIM_PARAMETER c_dcm_clk_out4_port NONE
SET_SIM_PARAMETER c_dcm_clk_out5_port NONE
SET_SIM_PARAMETER c_dcm_clk_out6_port NONE
SET_SIM_PARAMETER c_dcm_clkgen_notes None
SET_SIM_PARAMETER c_dcm_clkgen_clkfxdv_divide 2
SET_SIM_PARAMETER c_dcm_clkgen_clkfx_divide 1
SET_SIM_PARAMETER c_dcm_clkgen_clkfx_multiply 4
SET_SIM_PARAMETER c_dcm_clkgen_dfs_bandwidth OPTIMIZED
SET_SIM_PARAMETER c_dcm_clkgen_prog_md_bandwidth OPTIMIZED
SET_SIM_PARAMETER c_dcm_clkgen_clkin_period 20.0
SET_SIM_PARAMETER c_dcm_clkgen_clkfx_md_max 0.000
SET_SIM_PARAMETER c_dcm_clkgen_spread_spectrum NONE
SET_SIM_PARAMETER c_dcm_clkgen_startup_wait FALSE
SET_SIM_PARAMETER c_dcm_clkgen_clk_out1_port CLKFX
SET_SIM_PARAMETER c_dcm_clkgen_clk_out2_port NONE
SET_SIM_PARAMETER c_dcm_clkgen_clk_out3_port NONE
SET_SIM_PARAMETER c_clock_mgr_type AUTO
SET_SIM_PARAMETER c_override_mmcm 0
SET_SIM_PARAMETER c_override_pll 0
SET_SIM_PARAMETER c_override_dcm 0
SET_SIM_PARAMETER c_override_dcm_clkgen 0
SET_SIM_PARAMETER c_dcm_pll_cascade NONE
SET_SIM_PARAMETER c_primary_port CLK_IN1
SET_SIM_PARAMETER c_secondary_port CLK_IN2
SET_SIM_PARAMETER c_clk_out1_port CLK_OUT1
SET_SIM_PARAMETER c_clk_out2_port CLK_OUT2
SET_SIM_PARAMETER c_clk_out3_port CLK_OUT3
SET_SIM_PARAMETER c_clk_out4_port CLK_OUT4
SET_SIM_PARAMETER c_clk_out5_port CLK_OUT5
SET_SIM_PARAMETER c_clk_out6_port CLK_OUT6
SET_SIM_PARAMETER c_clk_out7_port CLK_OUT7
SET_SIM_PARAMETER c_reset_port RESET
SET_SIM_PARAMETER c_locked_port LOCKED
SET_SIM_PARAMETER c_clkfb_in_port CLKFB_IN
SET_SIM_PARAMETER c_clkfb_in_p_port CLKFB_IN_P
SET_SIM_PARAMETER c_clkfb_in_n_port CLKFB_IN_N
SET_SIM_PARAMETER c_clkfb_out_port CLKFB_OUT
SET_SIM_PARAMETER c_clkfb_out_p_port CLKFB_OUT_P
SET_SIM_PARAMETER c_clkfb_out_n_port CLKFB_OUT_N
SET_SIM_PARAMETER c_power_down_port POWER_DOWN
SET_SIM_PARAMETER c_daddr_port DADDR
SET_SIM_PARAMETER c_dclk_port DCLK
SET_SIM_PARAMETER c_drdy_port DRDY
SET_SIM_PARAMETER c_dwe_port DWE
SET_SIM_PARAMETER c_din_port DIN
SET_SIM_PARAMETER c_dout_port DOUT
SET_SIM_PARAMETER c_den_port DEN
SET_SIM_PARAMETER c_psclk_port PSCLK
SET_SIM_PARAMETER c_psen_port PSEN
SET_SIM_PARAMETER c_psincdec_port PSINCDEC
SET_SIM_PARAMETER c_psdone_port PSDONE
SET_SIM_PARAMETER c_clk_valid_port CLK_VALID
SET_SIM_PARAMETER c_status_port STATUS
SET_SIM_PARAMETER c_clk_in_sel_port CLK_IN_SEL
SET_SIM_PARAMETER c_input_clk_stopped_port INPUT_CLK_STOPPED
SET_SIM_PARAMETER c_clkfb_stopped_port CLKFB_STOPPED
SET_SIM_PARAMETER c_clkin1_jitter_ps 200.0
SET_SIM_PARAMETER c_clkin2_jitter_ps 100.0
SET_SIM_PARAMETER c_primitive MMCM
SET_SIM_PARAMETER c_ss_mode CENTER_HIGH
SET_SIM_PARAMETER c_ss_mod_period 4000
SET_CORE_NAME Clocking Wizard
SET_CORE_VERSION 3.6
SET_CORE_VLNV xilinx.com:ip:clk_wiz:3.6
SET_CORE_CLASS com.xilinx.ip.clk_wiz_v3_6.clk_wiz_v3_6
SET_CORE_PATH /opt/Xilinx/14.7/ISE_DS/ISE/coregen/ip/xilinx/primary/com/xilinx/ip/clk_wiz_v3_6
SET_CORE_GUIPATH /opt/Xilinx/14.7/ISE_DS/ISE/coregen/ip/xilinx/primary/com/xilinx/ip/clk_wiz_v3_6/gui/clk_wiz_v3_6.tcl
SET_CORE_DATASHEET /opt/Xilinx/14.7/ISE_DS/ISE/coregen/ip/xilinx/primary/com/xilinx/ip/clk_wiz_v3_6/doc/pg065_clk_wiz.pdf
ADD_CORE_DOCUMENT </opt/Xilinx/14.7/ISE_DS/ISE/coregen/ip/xilinx/primary/com/xilinx/ip/clk_wiz_v3_6/doc/pg065_clk_wiz.pdf><pg065_clk_wiz.pdf>
ADD_CORE_DOCUMENT </opt/Xilinx/14.7/ISE_DS/ISE/coregen/ip/xilinx/primary/com/xilinx/ip/clk_wiz_v3_6/doc/clk_wiz_v3_6_readme.txt><clk_wiz_v3_6_readme.txt>
ADD_CORE_DOCUMENT </opt/Xilinx/14.7/ISE_DS/ISE/coregen/ip/xilinx/primary/com/xilinx/ip/clk_wiz_v3_6/doc/clk_wiz_v3_6_vinfo.html><clk_wiz_v3_6_vinfo.html>

505
ipcore_dir/tmp/customization_gui.0.329899148238.out
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@ -1,505 +0,0 @@
SET_FLAG DEBUG FALSE
SET_FLAG MODE BATCH
SET_FLAG STANDALONE_MODE FALSE
SET_PREFERENCE devicefamily spartan6
SET_PREFERENCE device xc6slx9
SET_PREFERENCE speedgrade -2
SET_PREFERENCE package tqg144
SET_PREFERENCE verilogsim true
SET_PREFERENCE vhdlsim false
SET_PREFERENCE simulationfiles Behavioral
SET_PREFERENCE busformat BusFormatAngleBracketNotRipped
SET_PREFERENCE outputdirectory /home/tim/Projects/fpga/micro_test/ipcore_dir/
SET_PREFERENCE workingdirectory /home/tim/Projects/fpga/micro_test/ipcore_dir/tmp/
SET_PREFERENCE subworkingdirectory /home/tim/Projects/fpga/micro_test/ipcore_dir/tmp/_cg/
SET_PREFERENCE transientdirectory /home/tim/Projects/fpga/micro_test/ipcore_dir/tmp/_cg/_dbg/
SET_PREFERENCE designentry Verilog
SET_PREFERENCE flowvendor Other
SET_PREFERENCE addpads false
SET_PREFERENCE projectname coregen
SET_PREFERENCE formalverification false
SET_PREFERENCE asysymbol false
SET_PREFERENCE implementationfiletype Ngc
SET_PREFERENCE foundationsym false
SET_PREFERENCE createndf false
SET_PREFERENCE removerpms false
SET_PARAMETER Component_Name hdmi_clk
SET_PARAMETER Use_Freq_Synth true
SET_PARAMETER Use_Phase_Alignment false
SET_PARAMETER Use_Min_Power false
SET_PARAMETER Use_Dyn_Phase_Shift false
SET_PARAMETER Use_Dyn_Reconfig false
SET_PARAMETER Jitter_Sel No_Jitter
SET_PARAMETER Use_Spread_Spectrum false
SET_PARAMETER Use_Spread_Spectrum_1 false
SET_PARAMETER Prim_In_Freq 50
SET_PARAMETER In_Freq_Units Units_MHz
SET_PARAMETER In_Jitter_Units Units_UI
SET_PARAMETER Relative_Inclk REL_PRIMARY
SET_PARAMETER Secondary_In_Freq 100.000
SET_PARAMETER Jitter_Options UI
SET_PARAMETER Clkin1_UI_Jitter 0.010
SET_PARAMETER Clkin2_UI_Jitter 0.010
SET_PARAMETER Prim_In_Jitter 0.010
SET_PARAMETER Secondary_In_Jitter 0.010
SET_PARAMETER Clkin1_Jitter_Ps 200.0
SET_PARAMETER Clkin2_Jitter_Ps 100.0
SET_PARAMETER Clkout2_Used true
SET_PARAMETER Clkout3_Used false
SET_PARAMETER Clkout4_Used false
SET_PARAMETER Clkout5_Used false
SET_PARAMETER Clkout6_Used false
SET_PARAMETER Clkout7_Used false
SET_PARAMETER Num_Out_Clks 2
SET_PARAMETER Clk_Out1_Use_Fine_Ps_GUI false
SET_PARAMETER Clk_Out2_Use_Fine_Ps_GUI false
SET_PARAMETER Clk_Out3_Use_Fine_Ps_GUI false
SET_PARAMETER Clk_Out4_Use_Fine_Ps_GUI false
SET_PARAMETER Clk_Out5_Use_Fine_Ps_GUI false
SET_PARAMETER Clk_Out6_Use_Fine_Ps_GUI false
SET_PARAMETER Clk_Out7_Use_Fine_Ps_GUI false
SET_PARAMETER primary_port CLK_IN1
SET_PARAMETER CLK_OUT1_port CLK_OUT1
SET_PARAMETER CLK_OUT2_port CLK_OUT2
SET_PARAMETER CLK_OUT3_port CLK_OUT3
SET_PARAMETER CLK_OUT4_port CLK_OUT4
SET_PARAMETER CLK_OUT5_port CLK_OUT5
SET_PARAMETER CLK_OUT6_port CLK_OUT6
SET_PARAMETER CLK_OUT7_port CLK_OUT7
SET_PARAMETER DADDR_port DADDR
SET_PARAMETER DCLK_port DCLK
SET_PARAMETER DRDY_port DRDY
SET_PARAMETER DWE_port DWE
SET_PARAMETER DIN_port DIN
SET_PARAMETER DOUT_port DOUT
SET_PARAMETER DEN_port DEN
SET_PARAMETER PSCLK_port PSCLK
SET_PARAMETER PSEN_port PSEN
SET_PARAMETER PSINCDEC_port PSINCDEC
SET_PARAMETER PSDONE_port PSDONE
SET_PARAMETER Clkout1_Requested_Out_Freq 75
SET_PARAMETER Clkout1_Requested_Phase 0.000
SET_PARAMETER Clkout1_Requested_Duty_Cycle 50.000
SET_PARAMETER Clkout2_Requested_Out_Freq 200
SET_PARAMETER Clkout2_Requested_Phase 0.000
SET_PARAMETER Clkout2_Requested_Duty_Cycle 50.000
SET_PARAMETER Clkout3_Requested_Out_Freq 100.000
SET_PARAMETER Clkout3_Requested_Phase 0.000
SET_PARAMETER Clkout3_Requested_Duty_Cycle 50.000
SET_PARAMETER Clkout4_Requested_Out_Freq 100.000
SET_PARAMETER Clkout4_Requested_Phase 0.000
SET_PARAMETER Clkout4_Requested_Duty_Cycle 50.000
SET_PARAMETER Clkout5_Requested_Out_Freq 100.000
SET_PARAMETER Clkout5_Requested_Phase 0.000
SET_PARAMETER Clkout5_Requested_Duty_Cycle 50.000
SET_PARAMETER Clkout6_Requested_Out_Freq 100.000
SET_PARAMETER Clkout6_Requested_Phase 0.000
SET_PARAMETER Clkout6_Requested_Duty_Cycle 50.000
SET_PARAMETER Clkout7_Requested_Out_Freq 100.000
SET_PARAMETER Clkout7_Requested_Phase 0.000
SET_PARAMETER Clkout7_Requested_Duty_Cycle 50.000
SET_PARAMETER Use_Max_I_Jitter false
SET_PARAMETER Use_Min_O_Jitter false
SET_PARAMETER Prim_Source Single_ended_clock_capable_pin
SET_PARAMETER Use_Inclk_Switchover false
SET_PARAMETER secondary_port CLK_IN2
SET_PARAMETER Secondary_Source Single_ended_clock_capable_pin
SET_PARAMETER Clkout1_Drives BUFG
SET_PARAMETER Clkout2_Drives BUFG
SET_PARAMETER Clkout3_Drives BUFG
SET_PARAMETER Clkout4_Drives BUFG
SET_PARAMETER Clkout5_Drives BUFG
SET_PARAMETER Clkout6_Drives BUFG
SET_PARAMETER Clkout7_Drives BUFG
SET_PARAMETER Feedback_Source FDBK_AUTO
SET_PARAMETER Clkfb_In_Signaling SINGLE
SET_PARAMETER CLKFB_IN_port CLKFB_IN
SET_PARAMETER CLKFB_IN_P_port CLKFB_IN_P
SET_PARAMETER CLKFB_IN_N_port CLKFB_IN_N
SET_PARAMETER CLKFB_OUT_port CLKFB_OUT
SET_PARAMETER CLKFB_OUT_P_port CLKFB_OUT_P
SET_PARAMETER CLKFB_OUT_N_port CLKFB_OUT_N
SET_PARAMETER Platform lin64
SET_PARAMETER Summary_Strings empty
SET_PARAMETER Use_Locked false
SET_PARAMETER calc_done DONE
SET_PARAMETER Use_Reset false
SET_PARAMETER Use_Power_Down false
SET_PARAMETER Use_Status false
SET_PARAMETER Use_Freeze false
SET_PARAMETER Use_Clk_Valid false
SET_PARAMETER Use_Inclk_Stopped false
SET_PARAMETER Use_Clkfb_Stopped false
SET_PARAMETER RESET_port RESET
SET_PARAMETER LOCKED_port LOCKED
SET_PARAMETER Power_Down_port POWER_DOWN
SET_PARAMETER CLK_VALID_port CLK_VALID
SET_PARAMETER STATUS_port STATUS
SET_PARAMETER CLK_IN_SEL_port CLK_IN_SEL
SET_PARAMETER INPUT_CLK_STOPPED_port INPUT_CLK_STOPPED
SET_PARAMETER CLKFB_STOPPED_port CLKFB_STOPPED
SET_PARAMETER Override_Mmcm false
SET_PARAMETER Mmcm_Notes None
SET_PARAMETER Mmcm_Divclk_Divide 1
SET_PARAMETER Mmcm_Bandwidth OPTIMIZED
SET_PARAMETER Mmcm_Clkfbout_Mult_F 4.000
SET_PARAMETER Mmcm_Clkfbout_Phase 0.000
SET_PARAMETER Mmcm_Clkfbout_Use_Fine_Ps false
SET_PARAMETER Mmcm_Clkin1_Period 10.000
SET_PARAMETER Mmcm_Clkin2_Period 10.000
SET_PARAMETER Mmcm_Clkout4_Cascade false
SET_PARAMETER Mmcm_Clock_Hold false
SET_PARAMETER Mmcm_Compensation ZHOLD
SET_PARAMETER Mmcm_Ref_Jitter1 0.010
SET_PARAMETER Mmcm_Ref_Jitter2 0.010
SET_PARAMETER Mmcm_Startup_Wait false
SET_PARAMETER Mmcm_Clkout0_Divide_F 4.000
SET_PARAMETER Mmcm_Clkout0_Duty_Cycle 0.500
SET_PARAMETER Mmcm_Clkout0_Phase 0.000
SET_PARAMETER Mmcm_Clkout0_Use_Fine_Ps false
SET_PARAMETER Mmcm_Clkout1_Divide 1
SET_PARAMETER Mmcm_Clkout1_Duty_Cycle 0.500
SET_PARAMETER Mmcm_Clkout1_Phase 0.000
SET_PARAMETER Mmcm_Clkout1_Use_Fine_Ps false
SET_PARAMETER Mmcm_Clkout2_Divide 1
SET_PARAMETER Mmcm_Clkout2_Duty_Cycle 0.500
SET_PARAMETER Mmcm_Clkout2_Phase 0.000
SET_PARAMETER Mmcm_Clkout2_Use_Fine_Ps false
SET_PARAMETER Mmcm_Clkout3_Divide 1
SET_PARAMETER Mmcm_Clkout3_Duty_Cycle 0.500
SET_PARAMETER Mmcm_Clkout3_Phase 0.000
SET_PARAMETER Mmcm_Clkout3_Use_Fine_Ps false
SET_PARAMETER Mmcm_Clkout4_Divide 1
SET_PARAMETER Mmcm_Clkout4_Duty_Cycle 0.500
SET_PARAMETER Mmcm_Clkout4_Phase 0.000
SET_PARAMETER Mmcm_Clkout4_Use_Fine_Ps false
SET_PARAMETER Mmcm_Clkout5_Divide 1
SET_PARAMETER Mmcm_Clkout5_Duty_Cycle 0.500
SET_PARAMETER Mmcm_Clkout5_Phase 0.000
SET_PARAMETER Mmcm_Clkout5_Use_Fine_Ps false
SET_PARAMETER Mmcm_Clkout6_Divide 1
SET_PARAMETER Mmcm_Clkout6_Duty_Cycle 0.500
SET_PARAMETER Mmcm_Clkout6_Phase 0.000
SET_PARAMETER Mmcm_Clkout6_Use_Fine_Ps false
SET_PARAMETER Override_Dcm false
SET_PARAMETER Dcm_Notes None
SET_PARAMETER Dcm_Clkdv_Divide 2.0
SET_PARAMETER Dcm_Clkfx_Divide 2
SET_PARAMETER Dcm_Clkfx_Multiply 3
SET_PARAMETER Dcm_Clkin_Divide_By_2 false
SET_PARAMETER Dcm_Clkin_Period 20.000
SET_PARAMETER Dcm_Clkout_Phase_Shift NONE
SET_PARAMETER Dcm_Deskew_Adjust SYSTEM_SYNCHRONOUS
SET_PARAMETER Dcm_Phase_Shift 0
SET_PARAMETER Dcm_Clk_Feedback NONE
SET_PARAMETER Dcm_Startup_Wait false
SET_PARAMETER Dcm_Clk_Out1_Port CLKFX
SET_PARAMETER Dcm_Clk_Out2_Port CLK0
SET_PARAMETER Dcm_Clk_Out3_Port CLK0
SET_PARAMETER Dcm_Clk_Out4_Port CLK0
SET_PARAMETER Dcm_Clk_Out5_Port CLK0
SET_PARAMETER Dcm_Clk_Out6_Port CLK0
SET_PARAMETER Override_Dcm_Clkgen false
SET_PARAMETER Dcm_Clkgen_Notes None
SET_PARAMETER Dcm_Clkgen_Clkfx_Divide 1
SET_PARAMETER Dcm_Clkgen_Clkfx_Multiply 4
SET_PARAMETER Dcm_Clkgen_Clkfxdv_Divide 2
SET_PARAMETER Dcm_Clkgen_Clkfx_Md_Max 0.000
SET_PARAMETER Dcm_Clkgen_Startup_Wait false
SET_PARAMETER Dcm_Clkgen_Clkin_Period 10.000
SET_PARAMETER Dcm_Clkgen_Spread_Spectrum NONE
SET_PARAMETER Dcm_Clkgen_Clk_Out1_Port CLKFX
SET_PARAMETER Dcm_Clkgen_Clk_Out2_Port CLKFX
SET_PARAMETER Dcm_Clkgen_Clk_Out3_Port CLKFX
SET_PARAMETER Override_Pll false
SET_PARAMETER Pll_Notes None
SET_PARAMETER Pll_Bandwidth OPTIMIZED
SET_PARAMETER Pll_Clkfbout_Mult 12
SET_PARAMETER Pll_Clkfbout_Phase 0.000
SET_PARAMETER Pll_Clk_Feedback CLKFBOUT
SET_PARAMETER Pll_Divclk_Divide 1
SET_PARAMETER Pll_Clkin_Period 20.000
SET_PARAMETER Pll_Compensation INTERNAL
SET_PARAMETER Pll_Ref_Jitter 0.010
SET_PARAMETER Pll_Clkout0_Divide 8
SET_PARAMETER Pll_Clkout0_Duty_Cycle 0.500
SET_PARAMETER Pll_Clkout0_Phase 0.000
SET_PARAMETER Pll_Clkout1_Divide 3
SET_PARAMETER Pll_Clkout1_Duty_Cycle 0.500
SET_PARAMETER Pll_Clkout1_Phase 0.000
SET_PARAMETER Pll_Clkout2_Divide 1
SET_PARAMETER Pll_Clkout2_Duty_Cycle 0.500
SET_PARAMETER Pll_Clkout2_Phase 0.000
SET_PARAMETER Pll_Clkout3_Divide 1
SET_PARAMETER Pll_Clkout3_Duty_Cycle 0.500
SET_PARAMETER Pll_Clkout3_Phase 0.000
SET_PARAMETER Pll_Clkout4_Divide 1
SET_PARAMETER Pll_Clkout4_Duty_Cycle 0.500
SET_PARAMETER Pll_Clkout4_Phase 0.000
SET_PARAMETER Pll_Clkout5_Divide 1
SET_PARAMETER Pll_Clkout5_Duty_Cycle 0.500
SET_PARAMETER Pll_Clkout5_Phase 0.000
SET_PARAMETER dcm_pll_cascade NONE
SET_PARAMETER clock_mgr_type AUTO
SET_PARAMETER primtype_sel PLL_BASE
SET_PARAMETER primitive MMCM
SET_PARAMETER SS_Mode CENTER_HIGH
SET_PARAMETER SS_Mod_Freq 250
SET_SIM_PARAMETER c_clkout2_used 1
SET_SIM_PARAMETER c_clkout3_used 0
SET_SIM_PARAMETER c_clkout4_used 0
SET_SIM_PARAMETER c_clkout5_used 0
SET_SIM_PARAMETER c_clkout6_used 0
SET_SIM_PARAMETER c_clkout7_used 0
SET_SIM_PARAMETER c_use_clkout1_bar 0
SET_SIM_PARAMETER c_use_clkout2_bar 0
SET_SIM_PARAMETER c_use_clkout3_bar 0
SET_SIM_PARAMETER c_use_clkout4_bar 0
SET_SIM_PARAMETER c_component_name hdmi_clk
SET_SIM_PARAMETER c_platform lin64
SET_SIM_PARAMETER c_use_freq_synth 1
SET_SIM_PARAMETER c_use_phase_alignment 0
SET_SIM_PARAMETER c_prim_in_jitter 0.010
SET_SIM_PARAMETER c_secondary_in_jitter 0.010
SET_SIM_PARAMETER c_jitter_sel No_Jitter
SET_SIM_PARAMETER c_use_min_power 0
SET_SIM_PARAMETER c_use_min_o_jitter 0
SET_SIM_PARAMETER c_use_max_i_jitter 0
SET_SIM_PARAMETER c_use_dyn_phase_shift 0
SET_SIM_PARAMETER c_use_inclk_switchover 0
SET_SIM_PARAMETER c_use_dyn_reconfig 0
SET_SIM_PARAMETER c_use_spread_spectrum 0
SET_SIM_PARAMETER c_use_spread_spectrum_1 0
SET_SIM_PARAMETER c_primtype_sel PLL_BASE
SET_SIM_PARAMETER c_use_clk_valid 0
SET_SIM_PARAMETER c_prim_in_freq 50
SET_SIM_PARAMETER c_in_freq_units Units_MHz
SET_SIM_PARAMETER c_secondary_in_freq 100.000
SET_SIM_PARAMETER c_feedback_source FDBK_AUTO
SET_SIM_PARAMETER c_prim_source Single_ended_clock_capable_pin
SET_SIM_PARAMETER c_secondary_source Single_ended_clock_capable_pin
SET_SIM_PARAMETER c_clkfb_in_signaling SINGLE
SET_SIM_PARAMETER c_use_reset 0
SET_SIM_PARAMETER c_use_locked 0
SET_SIM_PARAMETER c_use_inclk_stopped 0
SET_SIM_PARAMETER c_use_clkfb_stopped 0
SET_SIM_PARAMETER c_use_power_down 0
SET_SIM_PARAMETER c_use_status 0
SET_SIM_PARAMETER c_use_freeze 0
SET_SIM_PARAMETER c_num_out_clks 2
SET_SIM_PARAMETER c_clkout1_drives BUFG
SET_SIM_PARAMETER c_clkout2_drives BUFG
SET_SIM_PARAMETER c_clkout3_drives BUFG
SET_SIM_PARAMETER c_clkout4_drives BUFG
SET_SIM_PARAMETER c_clkout5_drives BUFG
SET_SIM_PARAMETER c_clkout6_drives BUFG
SET_SIM_PARAMETER c_clkout7_drives BUFG
SET_SIM_PARAMETER c_inclk_sum_row0 "Input Clock Freq (MHz) Input Jitter (UI)"
SET_SIM_PARAMETER c_inclk_sum_row1 __primary______________50____________0.010
SET_SIM_PARAMETER c_inclk_sum_row2 no_secondary_input_clock
SET_SIM_PARAMETER c_outclk_sum_row0a "Output Output Phase Duty Pk-to-Pk Phase"
SET_SIM_PARAMETER c_outclk_sum_row0b "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
SET_SIM_PARAMETER c_outclk_sum_row1 CLK_OUT1____75.000______0.000______50.0______247.866____213.839
SET_SIM_PARAMETER c_outclk_sum_row2 CLK_OUT2___200.000______0.000______50.0______202.306____213.839
SET_SIM_PARAMETER c_outclk_sum_row3 no_CLK_OUT3_output
SET_SIM_PARAMETER c_outclk_sum_row4 no_CLK_OUT4_output
SET_SIM_PARAMETER c_outclk_sum_row5 no_CLK_OUT5_output
SET_SIM_PARAMETER c_outclk_sum_row6 no_CLK_OUT6_output
SET_SIM_PARAMETER c_outclk_sum_row7 no_CLK_OUT7_output
SET_SIM_PARAMETER c_clkout1_requested_out_freq 75
SET_SIM_PARAMETER c_clkout2_requested_out_freq 200
SET_SIM_PARAMETER c_clkout3_requested_out_freq 100.000
SET_SIM_PARAMETER c_clkout4_requested_out_freq 100.000
SET_SIM_PARAMETER c_clkout5_requested_out_freq 100.000
SET_SIM_PARAMETER c_clkout6_requested_out_freq 100.000
SET_SIM_PARAMETER c_clkout7_requested_out_freq 100.000
SET_SIM_PARAMETER c_clkout1_requested_phase 0.000
SET_SIM_PARAMETER c_clkout2_requested_phase 0.000
SET_SIM_PARAMETER c_clkout3_requested_phase 0.000
SET_SIM_PARAMETER c_clkout4_requested_phase 0.000
SET_SIM_PARAMETER c_clkout5_requested_phase 0.000
SET_SIM_PARAMETER c_clkout6_requested_phase 0.000
SET_SIM_PARAMETER c_clkout7_requested_phase 0.000
SET_SIM_PARAMETER c_clkout1_requested_duty_cycle 50.000
SET_SIM_PARAMETER c_clkout2_requested_duty_cycle 50.000
SET_SIM_PARAMETER c_clkout3_requested_duty_cycle 50.000
SET_SIM_PARAMETER c_clkout4_requested_duty_cycle 50.000
SET_SIM_PARAMETER c_clkout5_requested_duty_cycle 50.000
SET_SIM_PARAMETER c_clkout6_requested_duty_cycle 50.000
SET_SIM_PARAMETER c_clkout7_requested_duty_cycle 50.000
SET_SIM_PARAMETER c_clkout1_out_freq 75.000
SET_SIM_PARAMETER c_clkout2_out_freq 200.000
SET_SIM_PARAMETER c_clkout3_out_freq N/A
SET_SIM_PARAMETER c_clkout4_out_freq N/A
SET_SIM_PARAMETER c_clkout5_out_freq N/A
SET_SIM_PARAMETER c_clkout6_out_freq N/A
SET_SIM_PARAMETER c_clkout7_out_freq N/A
SET_SIM_PARAMETER c_clkout1_phase 0.000
SET_SIM_PARAMETER c_clkout2_phase 0.000
SET_SIM_PARAMETER c_clkout3_phase N/A
SET_SIM_PARAMETER c_clkout4_phase N/A
SET_SIM_PARAMETER c_clkout5_phase N/A
SET_SIM_PARAMETER c_clkout6_phase N/A
SET_SIM_PARAMETER c_clkout7_phase N/A
SET_SIM_PARAMETER c_clkout1_duty_cycle 50.0
SET_SIM_PARAMETER c_clkout2_duty_cycle 50.0
SET_SIM_PARAMETER c_clkout3_duty_cycle N/A
SET_SIM_PARAMETER c_clkout4_duty_cycle N/A
SET_SIM_PARAMETER c_clkout5_duty_cycle N/A
SET_SIM_PARAMETER c_clkout6_duty_cycle N/A
SET_SIM_PARAMETER c_clkout7_duty_cycle N/A
SET_SIM_PARAMETER c_mmcm_notes None
SET_SIM_PARAMETER c_mmcm_bandwidth OPTIMIZED
SET_SIM_PARAMETER c_mmcm_clkfbout_mult_f 4.000
SET_SIM_PARAMETER c_mmcm_clkin1_period 10.000
SET_SIM_PARAMETER c_mmcm_clkin2_period 10.000
SET_SIM_PARAMETER c_mmcm_clkout4_cascade FALSE
SET_SIM_PARAMETER c_mmcm_clock_hold FALSE
SET_SIM_PARAMETER c_mmcm_compensation ZHOLD
SET_SIM_PARAMETER c_mmcm_divclk_divide 1
SET_SIM_PARAMETER c_mmcm_ref_jitter1 0.010
SET_SIM_PARAMETER c_mmcm_ref_jitter2 0.010
SET_SIM_PARAMETER c_mmcm_startup_wait FALSE
SET_SIM_PARAMETER c_mmcm_clkout0_divide_f 4.000
SET_SIM_PARAMETER c_mmcm_clkout1_divide 1
SET_SIM_PARAMETER c_mmcm_clkout2_divide 1
SET_SIM_PARAMETER c_mmcm_clkout3_divide 1
SET_SIM_PARAMETER c_mmcm_clkout4_divide 1
SET_SIM_PARAMETER c_mmcm_clkout5_divide 1
SET_SIM_PARAMETER c_mmcm_clkout6_divide 1
SET_SIM_PARAMETER c_mmcm_clkout0_duty_cycle 0.500
SET_SIM_PARAMETER c_mmcm_clkout1_duty_cycle 0.500
SET_SIM_PARAMETER c_mmcm_clkout2_duty_cycle 0.500
SET_SIM_PARAMETER c_mmcm_clkout3_duty_cycle 0.500
SET_SIM_PARAMETER c_mmcm_clkout4_duty_cycle 0.500
SET_SIM_PARAMETER c_mmcm_clkout5_duty_cycle 0.500
SET_SIM_PARAMETER c_mmcm_clkout6_duty_cycle 0.500
SET_SIM_PARAMETER c_mmcm_clkfbout_phase 0.000
SET_SIM_PARAMETER c_mmcm_clkout0_phase 0.000
SET_SIM_PARAMETER c_mmcm_clkout1_phase 0.000
SET_SIM_PARAMETER c_mmcm_clkout2_phase 0.000
SET_SIM_PARAMETER c_mmcm_clkout3_phase 0.000
SET_SIM_PARAMETER c_mmcm_clkout4_phase 0.000
SET_SIM_PARAMETER c_mmcm_clkout5_phase 0.000
SET_SIM_PARAMETER c_mmcm_clkout6_phase 0.000
SET_SIM_PARAMETER c_mmcm_clkfbout_use_fine_ps FALSE
SET_SIM_PARAMETER c_mmcm_clkout0_use_fine_ps FALSE
SET_SIM_PARAMETER c_mmcm_clkout1_use_fine_ps FALSE
SET_SIM_PARAMETER c_mmcm_clkout2_use_fine_ps FALSE
SET_SIM_PARAMETER c_mmcm_clkout3_use_fine_ps FALSE
SET_SIM_PARAMETER c_mmcm_clkout4_use_fine_ps FALSE
SET_SIM_PARAMETER c_mmcm_clkout5_use_fine_ps FALSE
SET_SIM_PARAMETER c_mmcm_clkout6_use_fine_ps FALSE
SET_SIM_PARAMETER c_pll_notes None
SET_SIM_PARAMETER c_pll_bandwidth OPTIMIZED
SET_SIM_PARAMETER c_pll_clk_feedback CLKFBOUT
SET_SIM_PARAMETER c_pll_clkfbout_mult 12
SET_SIM_PARAMETER c_pll_clkin_period 20.000
SET_SIM_PARAMETER c_pll_compensation INTERNAL
SET_SIM_PARAMETER c_pll_divclk_divide 1
SET_SIM_PARAMETER c_pll_ref_jitter 0.010
SET_SIM_PARAMETER c_pll_clkout0_divide 8
SET_SIM_PARAMETER c_pll_clkout1_divide 3
SET_SIM_PARAMETER c_pll_clkout2_divide 1
SET_SIM_PARAMETER c_pll_clkout3_divide 1
SET_SIM_PARAMETER c_pll_clkout4_divide 1
SET_SIM_PARAMETER c_pll_clkout5_divide 1
SET_SIM_PARAMETER c_pll_clkout0_duty_cycle 0.500
SET_SIM_PARAMETER c_pll_clkout1_duty_cycle 0.500
SET_SIM_PARAMETER c_pll_clkout2_duty_cycle 0.500
SET_SIM_PARAMETER c_pll_clkout3_duty_cycle 0.500
SET_SIM_PARAMETER c_pll_clkout4_duty_cycle 0.500
SET_SIM_PARAMETER c_pll_clkout5_duty_cycle 0.500
SET_SIM_PARAMETER c_pll_clkfbout_phase 0.000
SET_SIM_PARAMETER c_pll_clkout0_phase 0.000
SET_SIM_PARAMETER c_pll_clkout1_phase 0.000
SET_SIM_PARAMETER c_pll_clkout2_phase 0.000
SET_SIM_PARAMETER c_pll_clkout3_phase 0.000
SET_SIM_PARAMETER c_pll_clkout4_phase 0.000
SET_SIM_PARAMETER c_pll_clkout5_phase 0.000
SET_SIM_PARAMETER c_dcm_notes None
SET_SIM_PARAMETER c_dcm_clkdv_divide 2.000
SET_SIM_PARAMETER c_dcm_clkfx_divide 2
SET_SIM_PARAMETER c_dcm_clkfx_multiply 3
SET_SIM_PARAMETER c_dcm_clkin_divide_by_2 FALSE
SET_SIM_PARAMETER c_dcm_clkin_period 20.0
SET_SIM_PARAMETER c_dcm_clkout_phase_shift NONE
SET_SIM_PARAMETER c_dcm_clk_feedback NONE
SET_SIM_PARAMETER c_dcm_clk_feedback_port NONE
SET_SIM_PARAMETER c_dcm_deskew_adjust SYSTEM_SYNCHRONOUS
SET_SIM_PARAMETER c_dcm_phase_shift 0
SET_SIM_PARAMETER c_dcm_startup_wait FALSE
SET_SIM_PARAMETER c_dcm_clk_out1_port CLKFX
SET_SIM_PARAMETER c_dcm_clk_out2_port CLK0
SET_SIM_PARAMETER c_dcm_clk_out3_port NONE
SET_SIM_PARAMETER c_dcm_clk_out4_port NONE
SET_SIM_PARAMETER c_dcm_clk_out5_port NONE
SET_SIM_PARAMETER c_dcm_clk_out6_port NONE
SET_SIM_PARAMETER c_dcm_clkgen_notes None
SET_SIM_PARAMETER c_dcm_clkgen_clkfxdv_divide 2
SET_SIM_PARAMETER c_dcm_clkgen_clkfx_divide 1
SET_SIM_PARAMETER c_dcm_clkgen_clkfx_multiply 4
SET_SIM_PARAMETER c_dcm_clkgen_dfs_bandwidth OPTIMIZED
SET_SIM_PARAMETER c_dcm_clkgen_prog_md_bandwidth OPTIMIZED
SET_SIM_PARAMETER c_dcm_clkgen_clkin_period 20.0
SET_SIM_PARAMETER c_dcm_clkgen_clkfx_md_max 0.000
SET_SIM_PARAMETER c_dcm_clkgen_spread_spectrum NONE
SET_SIM_PARAMETER c_dcm_clkgen_startup_wait FALSE
SET_SIM_PARAMETER c_dcm_clkgen_clk_out1_port CLKFX
SET_SIM_PARAMETER c_dcm_clkgen_clk_out2_port CLKFX
SET_SIM_PARAMETER c_dcm_clkgen_clk_out3_port NONE
SET_SIM_PARAMETER c_clock_mgr_type AUTO
SET_SIM_PARAMETER c_override_mmcm 0
SET_SIM_PARAMETER c_override_pll 0
SET_SIM_PARAMETER c_override_dcm 0
SET_SIM_PARAMETER c_override_dcm_clkgen 0
SET_SIM_PARAMETER c_dcm_pll_cascade NONE
SET_SIM_PARAMETER c_primary_port CLK_IN1
SET_SIM_PARAMETER c_secondary_port CLK_IN2
SET_SIM_PARAMETER c_clk_out1_port CLK_OUT1
SET_SIM_PARAMETER c_clk_out2_port CLK_OUT2
SET_SIM_PARAMETER c_clk_out3_port CLK_OUT3
SET_SIM_PARAMETER c_clk_out4_port CLK_OUT4
SET_SIM_PARAMETER c_clk_out5_port CLK_OUT5
SET_SIM_PARAMETER c_clk_out6_port CLK_OUT6
SET_SIM_PARAMETER c_clk_out7_port CLK_OUT7
SET_SIM_PARAMETER c_reset_port RESET
SET_SIM_PARAMETER c_locked_port LOCKED
SET_SIM_PARAMETER c_clkfb_in_port CLKFB_IN
SET_SIM_PARAMETER c_clkfb_in_p_port CLKFB_IN_P
SET_SIM_PARAMETER c_clkfb_in_n_port CLKFB_IN_N
SET_SIM_PARAMETER c_clkfb_out_port CLKFB_OUT
SET_SIM_PARAMETER c_clkfb_out_p_port CLKFB_OUT_P
SET_SIM_PARAMETER c_clkfb_out_n_port CLKFB_OUT_N
SET_SIM_PARAMETER c_power_down_port POWER_DOWN
SET_SIM_PARAMETER c_daddr_port DADDR
SET_SIM_PARAMETER c_dclk_port DCLK
SET_SIM_PARAMETER c_drdy_port DRDY
SET_SIM_PARAMETER c_dwe_port DWE
SET_SIM_PARAMETER c_din_port DIN
SET_SIM_PARAMETER c_dout_port DOUT
SET_SIM_PARAMETER c_den_port DEN
SET_SIM_PARAMETER c_psclk_port PSCLK
SET_SIM_PARAMETER c_psen_port PSEN
SET_SIM_PARAMETER c_psincdec_port PSINCDEC
SET_SIM_PARAMETER c_psdone_port PSDONE
SET_SIM_PARAMETER c_clk_valid_port CLK_VALID
SET_SIM_PARAMETER c_status_port STATUS
SET_SIM_PARAMETER c_clk_in_sel_port CLK_IN_SEL
SET_SIM_PARAMETER c_input_clk_stopped_port INPUT_CLK_STOPPED
SET_SIM_PARAMETER c_clkfb_stopped_port CLKFB_STOPPED
SET_SIM_PARAMETER c_clkin1_jitter_ps 200.0
SET_SIM_PARAMETER c_clkin2_jitter_ps 100.0
SET_SIM_PARAMETER c_primitive MMCM
SET_SIM_PARAMETER c_ss_mode CENTER_HIGH
SET_SIM_PARAMETER c_ss_mod_period 4000
SET_CORE_NAME Clocking Wizard
SET_CORE_VERSION 3.6
SET_CORE_VLNV xilinx.com:ip:clk_wiz:3.6
SET_CORE_CLASS com.xilinx.ip.clk_wiz_v3_6.clk_wiz_v3_6
SET_CORE_PATH /opt/Xilinx/14.7/ISE_DS/ISE/coregen/ip/xilinx/primary/com/xilinx/ip/clk_wiz_v3_6
SET_CORE_GUIPATH /opt/Xilinx/14.7/ISE_DS/ISE/coregen/ip/xilinx/primary/com/xilinx/ip/clk_wiz_v3_6/gui/clk_wiz_v3_6.tcl
SET_CORE_DATASHEET /opt/Xilinx/14.7/ISE_DS/ISE/coregen/ip/xilinx/primary/com/xilinx/ip/clk_wiz_v3_6/doc/pg065_clk_wiz.pdf
ADD_CORE_DOCUMENT </opt/Xilinx/14.7/ISE_DS/ISE/coregen/ip/xilinx/primary/com/xilinx/ip/clk_wiz_v3_6/doc/pg065_clk_wiz.pdf><pg065_clk_wiz.pdf>
ADD_CORE_DOCUMENT </opt/Xilinx/14.7/ISE_DS/ISE/coregen/ip/xilinx/primary/com/xilinx/ip/clk_wiz_v3_6/doc/clk_wiz_v3_6_readme.txt><clk_wiz_v3_6_readme.txt>
ADD_CORE_DOCUMENT </opt/Xilinx/14.7/ISE_DS/ISE/coregen/ip/xilinx/primary/com/xilinx/ip/clk_wiz_v3_6/doc/clk_wiz_v3_6_vinfo.html><clk_wiz_v3_6_vinfo.html>

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