82 lines
4.9 KiB
Verilog
82 lines
4.9 KiB
Verilog
/*******************************************************************************
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* This file is owned and controlled by Xilinx and must be used solely *
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* for design, simulation, implementation and creation of design files *
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* limited to Xilinx devices or technologies. Use with non-Xilinx *
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* devices or technologies is expressly prohibited and immediately *
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* terminates your license. *
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* *
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* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
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* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
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* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
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* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
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* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
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* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
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* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
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* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
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* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
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* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
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* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
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* PARTICULAR PURPOSE. *
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* *
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* Xilinx products are not intended for use in life support appliances, *
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* devices, or systems. Use in such applications are expressly *
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* prohibited. *
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* *
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* (c) Copyright 1995-2020 Xilinx, Inc. *
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* All rights reserved. *
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*******************************************************************************/
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/*******************************************************************************
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* Generated from core with identifier: xilinx.com:ip:microblaze_mcs:1.4 *
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* *
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* MicroBlaze Micro Controller System (MCS) is a light-weight general *
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* purpose micro controller system, based on the MicroBlaze processor. *
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* It is primarily intended for simple control applications, where a *
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* hardware solution would be less flexible and more difficult to *
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* implement. Software development with the Xilinx Software Development *
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* Kit (SDK) is supported, including a software driver for the *
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* peripherals. Debugging is available either via SDK or directly with *
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* the Xilinx Microprocessor Debugger. *
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* *
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* The MCS consists of the processor itself, local memory with sizes *
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* ranging from 4KB to 64KB, up to 4 Fixed Interval Timers, up to 4 *
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* Programmable Interval Timers, up to 4 32-bit General Purpose Output *
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* ports, up to 4 32-bit General Purpose Input ports, and an Interrupt *
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* Controller with up to 16 external interrupt inputs. *
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* *
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*******************************************************************************/
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// Interfaces:
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// IO_BUS
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// MicroBlaze MCS IO Bus Interface
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// TRACE
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// MicroBlaze MCS Trace Interface
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// The following must be inserted into your Verilog file for this
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// core to be instantiated. Change the instance name and port connections
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// (in parentheses) to your own signal names.
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//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
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microblaze_mcs your_instance_name (
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.Clk(Clk), // input Clk
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.Reset(Reset), // input Reset
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.GPO1(GPO1), // output [15 : 0] GPO1
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.GPO2(GPO2), // output [15 : 0] GPO2
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.GPO3(GPO3), // output [0 : 0] GPO3
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.GPO4(GPO4), // output [5 : 0] GPO4
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.GPI1(GPI1), // input [7 : 0] GPI1
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.GPI1_Interrupt(GPI1_Interrupt), // output GPI1_Interrupt
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.GPI2(GPI2), // input [0 : 0] GPI2
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.GPI2_Interrupt(GPI2_Interrupt), // output GPI2_Interrupt
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.GPI3(GPI3), // input [1 : 0] GPI3
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.GPI3_Interrupt(GPI3_Interrupt), // output GPI3_Interrupt
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.INTC_IRQ(INTC_IRQ) // output INTC_IRQ
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);
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// INST_TAG_END ------ End INSTANTIATION Template ---------
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// You must compile the wrapper file microblaze_mcs.v when simulating
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// the core, microblaze_mcs. When compiling the wrapper file, be sure to
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// reference the XilinxCoreLib Verilog simulation library. For detailed
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// instructions, please refer to the "CORE Generator Help".
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