117 lines
2.6 KiB
Verilog
117 lines
2.6 KiB
Verilog
`timescale 1ns / 1ps
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/*
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This file was generated automatically by Alchitry Labs version 1.2.0.
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Do not edit this file directly. Instead edit the original Lucid source.
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This is a temporary file and any changes made to it will be destroyed.
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*/
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/*
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Parameters:
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SIZE = DATA_IN_SIZE
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DEPTH = 16
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*/
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module async_fifo (
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input wclk,
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input wrst,
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input [29:0] din,
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input wput,
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output reg full,
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input rclk,
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input rrst,
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output reg [29:0] dout,
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input rget,
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output reg empty
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);
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localparam SIZE = 5'h1e;
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localparam DEPTH = 5'h10;
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localparam ADDR_SIZE = 3'h4;
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reg [3:0] M_waddr_d, M_waddr_q = 1'h0;
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reg [7:0] M_wsync_d, M_wsync_q = 1'h0;
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reg [3:0] M_raddr_d, M_raddr_q = 1'h0;
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reg [7:0] M_rsync_d, M_rsync_q = 1'h0;
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wire [30-1:0] M_ram_read_data;
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reg [1-1:0] M_ram_wclk;
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reg [4-1:0] M_ram_waddr;
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reg [30-1:0] M_ram_write_data;
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reg [1-1:0] M_ram_write_en;
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reg [1-1:0] M_ram_rclk;
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reg [4-1:0] M_ram_raddr;
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simple_dual_ram #(.SIZE(5'h1e), .DEPTH(5'h10)) ram (
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.wclk(M_ram_wclk),
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.waddr(M_ram_waddr),
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.write_data(M_ram_write_data),
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.write_en(M_ram_write_en),
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.rclk(M_ram_rclk),
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.raddr(M_ram_raddr),
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.read_data(M_ram_read_data)
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);
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reg [3:0] waddr_gray;
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reg [3:0] wnext_gray;
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reg [3:0] raddr_gray;
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reg wrdy;
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reg rrdy;
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always @* begin
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M_rsync_d = M_rsync_q;
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M_wsync_d = M_wsync_q;
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M_waddr_d = M_waddr_q;
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M_raddr_d = M_raddr_q;
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M_ram_wclk = wclk;
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M_ram_rclk = rclk;
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M_ram_write_en = 1'h0;
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waddr_gray = (M_waddr_q >> 1'h1) ^ M_waddr_q;
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wnext_gray = ((M_waddr_q + 1'h1) >> 1'h1) ^ (M_waddr_q + 1'h1);
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raddr_gray = (M_raddr_q >> 1'h1) ^ M_raddr_q;
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M_rsync_d = {M_rsync_q[0+3-:4], waddr_gray};
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M_wsync_d = {M_wsync_q[0+3-:4], raddr_gray};
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wrdy = wnext_gray != M_wsync_q[4+3-:4];
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rrdy = raddr_gray != M_rsync_q[4+3-:4];
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full = !wrdy;
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empty = !rrdy;
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M_ram_waddr = M_waddr_q;
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M_ram_raddr = M_raddr_q;
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M_ram_write_data = din;
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if (wput && wrdy) begin
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M_waddr_d = M_waddr_q + 1'h1;
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M_ram_write_en = 1'h1;
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end
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if (rget && rrdy) begin
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M_raddr_d = M_raddr_q + 1'h1;
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M_ram_raddr = M_raddr_q + 1'h1;
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end
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dout = M_ram_read_data;
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end
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always @(posedge rclk) begin
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if (rrst == 1'b1) begin
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M_raddr_q <= 1'h0;
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M_rsync_q <= 1'h0;
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end else begin
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M_raddr_q <= M_raddr_d;
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M_rsync_q <= M_rsync_d;
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end
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end
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always @(posedge wclk) begin
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if (wrst == 1'b1) begin
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M_waddr_q <= 1'h0;
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M_wsync_q <= 1'h0;
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end else begin
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M_waddr_q <= M_waddr_d;
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M_wsync_q <= M_wsync_d;
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end
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end
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endmodule |