68 lines
1.4 KiB
Verilog
68 lines
1.4 KiB
Verilog
`timescale 1ns / 1ps
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/*
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This file was generated automatically by Alchitry Labs version 1.2.0.
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Do not edit this file directly. Instead edit the original Lucid source.
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This is a temporary file and any changes made to it will be destroyed.
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*/
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/*
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Parameters:
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DATA_IN_SIZE = 30
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*/
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module fifo_2x_reducer (
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input rst,
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input clk,
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input clkx2,
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input [29:0] data_in,
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output reg [14:0] data_out
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);
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localparam DATA_IN_SIZE = 5'h1e;
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wire [1-1:0] M_fifo_full;
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wire [30-1:0] M_fifo_dout;
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wire [1-1:0] M_fifo_empty;
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reg [30-1:0] M_fifo_din;
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reg [1-1:0] M_fifo_wput;
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reg [1-1:0] M_fifo_rget;
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async_fifo fifo (
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.wclk(clk),
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.rclk(clkx2),
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.wrst(rst),
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.rrst(rst),
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.din(M_fifo_din),
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.wput(M_fifo_wput),
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.rget(M_fifo_rget),
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.full(M_fifo_full),
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.dout(M_fifo_dout),
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.empty(M_fifo_empty)
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);
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reg M_flag_d, M_flag_q = 1'h0;
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reg [29:0] M_word_d, M_word_q = 1'h0;
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always @* begin
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M_flag_d = M_flag_q;
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M_word_d = M_word_q;
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M_fifo_din = data_in;
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M_fifo_wput = 1'h1;
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M_fifo_rget = 1'h0;
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if (!M_flag_q && !M_fifo_empty) begin
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M_fifo_rget = 1'h1;
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M_flag_d = 1'h1;
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M_word_d = M_fifo_dout;
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end
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if (M_flag_q) begin
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M_flag_d = 1'h0;
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end
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data_out = !M_flag_q ? M_word_q[15+14-:15] : M_word_q[0+14-:15];
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end
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always @(posedge clkx2) begin
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M_flag_q <= M_flag_d;
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M_word_q <= M_word_d;
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end
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endmodule |