79 lines
4.0 KiB
XML
79 lines
4.0 KiB
XML
<?xml version="1.0" encoding="UTF-8"?>
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<!-- IMPORTANT: This is an internal file that has been generated
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by the Xilinx ISE software. Any direct editing or
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changes made to this file may result in unpredictable
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behavior or data corruption. It is strongly advised that
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users do not edit the contents of this file. -->
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<messages>
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<msg type="info" file="sim" num="172" delta="old" >Generating IP...
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</msg>
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<msg type="warning" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">Verilog simulation file type 'Behavioral' is not valid for this core. Overriding with simulation file type 'Structural'.</arg>
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</msg>
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<msg type="warning" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">A core named 'microblaze_mcs' already exists in the project. Output products for this core may be overwritten.</arg>
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</msg>
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<msg type="warning" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">Verilog simulation file type 'Behavioral' is not valid for this core. Overriding with simulation file type 'Structural'.</arg>
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</msg>
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<msg type="warning" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">A core named 'microblaze_mcs' already exists in the project. Output products for this core may be overwritten.</arg>
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</msg>
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<msg type="info" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">Pre-processing HDL files for 'microblaze_mcs'...</arg>
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</msg>
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<msg type="info" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">Running microblaze_mcs_gen_script.tcl</arg>
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</msg>
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<msg type="info" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">Please source the "microblaze_mcs_setup.tcl" script in the Tcl Console to complete MicroBlaze MCS core generation</arg>
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</msg>
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<msg type="warning" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">Verilog simulation file type 'Behavioral' is not valid for this core. Overriding with simulation file type 'Structural'.</arg>
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</msg>
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<msg type="warning" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">Verilog simulation file type 'Behavioral' is not valid for this core. Overriding with simulation file type 'Structural'.</arg>
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</msg>
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<msg type="info" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">Running microblaze_mcs_sim_script.tcl</arg>
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</msg>
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<msg type="info" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">C_MICROBLAZE_INSTANCE = microblaze_mcs</arg>
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</msg>
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<msg type="info" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">Netlist filename = ./_cg/microblaze_mcs.v</arg>
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</msg>
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<msg type="info" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">Setting INIT_FILE = "microblaze_mcs.lmb_bram_7.mem" for BRAM 7</arg>
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</msg>
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<msg type="info" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">Setting INIT_FILE = "microblaze_mcs.lmb_bram_6.mem" for BRAM 6</arg>
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</msg>
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<msg type="info" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">Setting INIT_FILE = "microblaze_mcs.lmb_bram_5.mem" for BRAM 5</arg>
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</msg>
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<msg type="info" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">Setting INIT_FILE = "microblaze_mcs.lmb_bram_4.mem" for BRAM 4</arg>
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</msg>
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<msg type="info" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">Setting INIT_FILE = "microblaze_mcs.lmb_bram_3.mem" for BRAM 3</arg>
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</msg>
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<msg type="info" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">Setting INIT_FILE = "microblaze_mcs.lmb_bram_2.mem" for BRAM 2</arg>
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</msg>
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<msg type="info" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">Setting INIT_FILE = "microblaze_mcs.lmb_bram_1.mem" for BRAM 1</arg>
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</msg>
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<msg type="info" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">Setting INIT_FILE = "microblaze_mcs.lmb_bram_0.mem" for BRAM 0</arg>
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</msg>
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<msg type="info" file="sim" num="949" delta="old" >Finished generation of ASY schematic symbol.
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</msg>
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<msg type="info" file="sim" num="948" delta="old" >Finished FLIST file generation.
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</msg>
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</messages>
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