123 lines
4.1 KiB
Verilog
123 lines
4.1 KiB
Verilog
`timescale 1ns / 1ps
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/*
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This file was generated automatically by Alchitry Labs version 1.2.0.
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Do not edit this file directly. Instead edit the original Lucid source.
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This is a temporary file and any changes made to it will be destroyed.
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*/
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module tmds_encoder (
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input clk,
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input rst,
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input [7:0] data_in,
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input c0,
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input c1,
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input de,
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output reg [9:0] data_out
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);
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reg [9:0] M_dout_d, M_dout_q = 1'h0;
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reg [4:0] M_count_d, M_count_q = 1'h0;
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reg [3:0] M_num_ones_d, M_num_ones_q = 1'h0;
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reg [7:0] M_din_d, M_din_q = 1'h0;
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reg [3:0] M_num_ones9_d, M_num_ones9_q = 1'h0;
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reg [1:0] M_c0_pipe_d, M_c0_pipe_q = 1'h0;
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reg [1:0] M_c1_pipe_d, M_c1_pipe_q = 1'h0;
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reg [1:0] M_de_pipe_d, M_de_pipe_q = 1'h0;
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reg [8:0] M_data9_pipe_d, M_data9_pipe_q = 1'h0;
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reg xor_flag;
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reg [8:0] data9;
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integer i;
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reg cond_flip;
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reg flip;
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always @* begin
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M_c0_pipe_d = M_c0_pipe_q;
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M_dout_d = M_dout_q;
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M_num_ones9_d = M_num_ones9_q;
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M_din_d = M_din_q;
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M_data9_pipe_d = M_data9_pipe_q;
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M_count_d = M_count_q;
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M_c1_pipe_d = M_c1_pipe_q;
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M_de_pipe_d = M_de_pipe_q;
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M_num_ones_d = M_num_ones_q;
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data_out = M_dout_q;
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M_c0_pipe_d = {M_c0_pipe_q[0+0-:1], c0};
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M_c1_pipe_d = {M_c1_pipe_q[0+0-:1], c1};
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M_de_pipe_d = {M_de_pipe_q[0+0-:1], de};
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M_num_ones_d = data_in[0+0-:1] + data_in[1+0-:1] + data_in[2+0-:1] + data_in[3+0-:1] + data_in[4+0-:1] + data_in[5+0-:1] + data_in[6+0-:1] + data_in[7+0-:1];
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M_din_d = data_in;
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xor_flag = (M_num_ones_q > 3'h4) || (M_num_ones_q == 3'h4 && M_din_q[0+0-:1] == 1'h0);
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data9[0+0-:1] = M_din_q[0+0-:1];
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for (i = 1'h1; i < 4'h8; i = i + 1) begin
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data9[(i)*1+0-:1] = xor_flag ? data9[(i - 1'h1)*1+0-:1] ~^ M_din_q[(i)*1+0-:1] : data9[(i - 1'h1)*1+0-:1] ^ M_din_q[(i)*1+0-:1];
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end
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data9[8+0-:1] = ~xor_flag;
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M_num_ones9_d = data9[0+0-:1] + data9[1+0-:1] + data9[2+0-:1] + data9[3+0-:1] + data9[4+0-:1] + data9[5+0-:1] + data9[6+0-:1] + data9[7+0-:1];
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M_data9_pipe_d = data9;
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cond_flip = M_count_q == 1'h0 || M_num_ones9_q == 3'h4;
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flip = ((~M_count_q[4+0-:1]) && (M_num_ones9_q > 3'h4)) || (M_count_q[4+0-:1] && (3'h4 > M_num_ones9_q));
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if (M_de_pipe_q[1+0-:1]) begin
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if (cond_flip) begin
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M_dout_d[9+0-:1] = ~M_data9_pipe_q[8+0-:1];
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M_dout_d[8+0-:1] = M_data9_pipe_q[8+0-:1];
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M_dout_d[0+7-:8] = M_data9_pipe_q[8+0-:1] ? M_data9_pipe_q[0+7-:8] : ~M_data9_pipe_q[0+7-:8];
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M_count_d = (~M_data9_pipe_q[8+0-:1]) ? (M_count_q + (4'h8 - M_num_ones9_q) - M_num_ones9_q) : (M_count_q + M_num_ones9_q - (4'h8 - M_num_ones9_q));
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end else begin
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if (flip) begin
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M_dout_d[9+0-:1] = 1'h1;
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M_dout_d[8+0-:1] = M_data9_pipe_q[8+0-:1];
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M_dout_d[0+7-:8] = ~M_data9_pipe_q[0+7-:8];
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M_count_d = M_count_q + {M_data9_pipe_q[8+0-:1], 1'h0} + (4'h8 - M_num_ones9_q) - M_num_ones9_q;
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end else begin
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M_dout_d[9+0-:1] = 1'h0;
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M_dout_d[0+8-:9] = M_data9_pipe_q[0+8-:9];
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M_count_d = M_count_q - {~M_data9_pipe_q[8+0-:1], 1'h0} + M_num_ones9_q - (4'h8 - M_num_ones9_q);
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end
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end
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end else begin
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case ({M_c1_pipe_q[1+0-:1], M_c0_pipe_q[1+0-:1]})
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2'h0: begin
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M_dout_d = 10'h354;
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end
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2'h1: begin
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M_dout_d = 10'h0ab;
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end
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2'h2: begin
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M_dout_d = 10'h154;
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end
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default: begin
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M_dout_d = 10'h2ab;
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end
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endcase
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M_count_d = 1'h0;
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end
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end
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always @(posedge clk) begin
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M_num_ones_q <= M_num_ones_d;
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M_din_q <= M_din_d;
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M_num_ones9_q <= M_num_ones9_d;
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M_c0_pipe_q <= M_c0_pipe_d;
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M_c1_pipe_q <= M_c1_pipe_d;
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M_de_pipe_q <= M_de_pipe_d;
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M_data9_pipe_q <= M_data9_pipe_d;
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if (rst == 1'b1) begin
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M_dout_q <= 1'h0;
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M_count_q <= 1'h0;
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end else begin
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M_dout_q <= M_dout_d;
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M_count_q <= M_count_d;
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end
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end
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endmodule |