144 lines
5.5 KiB
Verilog
Executable File
144 lines
5.5 KiB
Verilog
Executable File
// file: hdmi_clk.v
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//
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// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
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//
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// This file contains confidential and proprietary information
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// of Xilinx, Inc. and is protected under U.S. and
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// international copyright and other intellectual property
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// laws.
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//
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// DISCLAIMER
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// This disclaimer is not a license and does not grant any
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// rights to the materials distributed herewith. Except as
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// otherwise provided in a valid license issued to you by
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// Xilinx, and to the maximum extent permitted by applicable
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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// (2) Xilinx shall not be liable (whether in contract or tort,
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// including negligence, or under any other theory of
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// liability) for any loss or damage of any kind or nature
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// related to, arising under or in connection with these
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// materials, including for any direct, or any indirect,
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// special, incidental, or consequential loss or damage
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// (including loss of data, profits, goodwill, or any type of
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// loss or damage suffered as a result of any action brought
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// by a third party) even if such damage or loss was
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// reasonably foreseeable or Xilinx had been advised of the
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// possibility of the same.
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//
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// CRITICAL APPLICATIONS
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// Xilinx products are not designed or intended to be fail-
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// safe, or for use in any application requiring fail-safe
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// performance, such as life-support or safety devices or
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// systems, Class III medical devices, nuclear facilities,
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// applications related to the deployment of airbags, or any
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// other applications that could lead to death, personal
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// injury, or severe property or environmental damage
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// (individually and collectively, "Critical
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// Applications"). Customer assumes the sole risk and
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// liability of any use of Xilinx products in Critical
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// Applications, subject only to applicable laws and
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// regulations governing limitations on product liability.
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//
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// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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// PART OF THIS FILE AT ALL TIMES.
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//
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//----------------------------------------------------------------------------
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// User entered comments
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//----------------------------------------------------------------------------
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// None
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//
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//----------------------------------------------------------------------------
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// "Output Output Phase Duty Pk-to-Pk Phase"
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// "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
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//----------------------------------------------------------------------------
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// CLK_OUT1____75.000______0.000______50.0______248.869____240.171
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// CLK_OUT2___150.000______0.000______50.0______216.897____240.171
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//
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//----------------------------------------------------------------------------
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// "Input Clock Freq (MHz) Input Jitter (UI)"
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//----------------------------------------------------------------------------
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// __primary______________50____________0.010
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`timescale 1ps/1ps
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(* CORE_GENERATION_INFO = "hdmi_clk,clk_wiz_v3_6,{component_name=hdmi_clk,use_phase_alignment=false,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=PLL_BASE,num_out_clk=2,clkin1_period=20.000,clkin2_period=20.000,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}" *)
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module hdmi_clk
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(// Clock in ports
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input CLK_IN1,
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// Clock out ports
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output CLK_OUT1,
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output CLK_OUT2
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);
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// Input buffering
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//------------------------------------
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IBUFG clkin1_buf
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(.O (clkin1),
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.I (CLK_IN1));
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// Clocking primitive
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//------------------------------------
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// Instantiation of the PLL primitive
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// * Unused inputs are tied off
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// * Unused outputs are labeled unused
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wire [15:0] do_unused;
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wire drdy_unused;
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wire locked_unused;
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wire clkfbout;
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wire clkout2_unused;
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wire clkout3_unused;
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wire clkout4_unused;
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wire clkout5_unused;
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PLL_BASE
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#(.BANDWIDTH ("OPTIMIZED"),
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.CLK_FEEDBACK ("CLKFBOUT"),
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.COMPENSATION ("INTERNAL"),
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.DIVCLK_DIVIDE (1),
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.CLKFBOUT_MULT (9),
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.CLKFBOUT_PHASE (0.000),
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.CLKOUT0_DIVIDE (6),
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.CLKOUT0_PHASE (0.000),
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.CLKOUT0_DUTY_CYCLE (0.500),
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.CLKOUT1_DIVIDE (3),
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.CLKOUT1_PHASE (0.000),
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.CLKOUT1_DUTY_CYCLE (0.500),
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.CLKIN_PERIOD (20.000),
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.REF_JITTER (0.010))
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pll_base_inst
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// Output clocks
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(.CLKFBOUT (clkfbout),
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.CLKOUT0 (clkout0),
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.CLKOUT1 (clkout1),
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.CLKOUT2 (clkout2_unused),
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.CLKOUT3 (clkout3_unused),
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.CLKOUT4 (clkout4_unused),
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.CLKOUT5 (clkout5_unused),
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.LOCKED (locked_unused),
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.RST (1'b0),
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// Input clock control
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.CLKFBIN (clkfbout),
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.CLKIN (clkin1));
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// Output buffering
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//-----------------------------------
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BUFG clkout1_buf
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(.O (CLK_OUT1),
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.I (clkout0));
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BUFG clkout2_buf
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(.O (CLK_OUT2),
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.I (clkout1));
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endmodule
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