56 lines
1.2 KiB
Verilog
56 lines
1.2 KiB
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 22:16:37 09/18/2020
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// Design Name:
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// Module Name: color_map
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// Project Name:
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// Target Devices:
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// Tool versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module color_map(
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input clk,
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input[3:0] colorcode,
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output reg[23:0] color
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);
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wire [23:0] colors [15:0];
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always @(posedge clk) begin
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color <= colors[colorcode];
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end
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// VGA Colors
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// Normal colors
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assign colors[0] = 24'h000000;
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assign colors[1] = 24'hAA0000;
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assign colors[2] = 24'h00AA00;
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assign colors[3] = 24'hAA5500;
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assign colors[4] = 24'h0000AA;
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assign colors[5] = 24'hAA00AA;
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assign colors[6] = 24'h00AAAA;
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assign colors[7] = 24'hAAAAAA;
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// Bright colors
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assign colors[8] = 24'h555555;
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assign colors[9] = 24'hFF5555;
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assign colors[10] = 24'h55FF55;
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assign colors[11] = 24'hFFFF55;
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assign colors[12] = 24'h5555FF;
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assign colors[13] = 24'hFF55FF;
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assign colors[14] = 24'h55FFFF;
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assign colors[15] = 24'hFFFFFF;
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endmodule
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