198 lines
4.5 KiB
Verilog
198 lines
4.5 KiB
Verilog
`timescale 1ns / 1ps
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/*
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This file was generated automatically by Alchitry Labs version 1.2.0.
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Do not edit this file directly. Instead edit the original Lucid source.
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This is a temporary file and any changes made to it will be destroyed.
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*/
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module dvi_encoder (
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input pclk,
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input pclkx2,
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input pclkx10,
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input strobe,
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input rst,
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input [7:0] red,
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input [7:0] green,
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input [7:0] blue,
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input hsync,
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input vsync,
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input de,
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output reg [3:0] tmds,
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output reg [3:0] tmdsb
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);
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reg M_toggle_d, M_toggle_q = 1'h0;
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wire [1-1:0] M_clkser_iob_out;
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reg [5-1:0] M_clkser_data;
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serdes_n_to_1 clkser (
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.ioclk(pclkx10),
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.strobe(strobe),
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.gclk(pclkx2),
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.rst(rst),
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.data(M_clkser_data),
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.iob_out(M_clkser_iob_out)
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);
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wire [1-1:0] M_clkbuf_O;
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wire [1-1:0] M_clkbuf_OB;
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OBUFDS clkbuf (
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.I(M_clkser_iob_out),
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.O(M_clkbuf_O),
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.OB(M_clkbuf_OB)
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);
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wire [10-1:0] M_enc_blue_data_out;
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reg [8-1:0] M_enc_blue_data_in;
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reg [1-1:0] M_enc_blue_c0;
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reg [1-1:0] M_enc_blue_c1;
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reg [1-1:0] M_enc_blue_de;
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tmds_encoder enc_blue (
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.clk(pclk),
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.rst(rst),
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.data_in(M_enc_blue_data_in),
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.c0(M_enc_blue_c0),
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.c1(M_enc_blue_c1),
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.de(M_enc_blue_de),
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.data_out(M_enc_blue_data_out)
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);
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wire [10-1:0] M_enc_green_data_out;
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reg [8-1:0] M_enc_green_data_in;
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reg [1-1:0] M_enc_green_c0;
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reg [1-1:0] M_enc_green_c1;
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reg [1-1:0] M_enc_green_de;
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tmds_encoder enc_green (
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.clk(pclk),
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.rst(rst),
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.data_in(M_enc_green_data_in),
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.c0(M_enc_green_c0),
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.c1(M_enc_green_c1),
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.de(M_enc_green_de),
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.data_out(M_enc_green_data_out)
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);
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wire [10-1:0] M_enc_red_data_out;
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reg [8-1:0] M_enc_red_data_in;
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reg [1-1:0] M_enc_red_c0;
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reg [1-1:0] M_enc_red_c1;
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reg [1-1:0] M_enc_red_de;
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tmds_encoder enc_red (
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.clk(pclk),
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.rst(rst),
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.data_in(M_enc_red_data_in),
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.c0(M_enc_red_c0),
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.c1(M_enc_red_c1),
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.de(M_enc_red_de),
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.data_out(M_enc_red_data_out)
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);
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wire [15-1:0] M_fifo_data_out;
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reg [30-1:0] M_fifo_data_in;
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fifo_2x_reducer fifo (
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.rst(rst),
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.clk(pclk),
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.clkx2(pclkx2),
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.data_in(M_fifo_data_in),
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.data_out(M_fifo_data_out)
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);
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wire [1-1:0] M_redser_iob_out;
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reg [5-1:0] M_redser_data;
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serdes_n_to_1 redser (
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.ioclk(pclkx10),
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.strobe(strobe),
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.gclk(pclkx2),
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.rst(rst),
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.data(M_redser_data),
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.iob_out(M_redser_iob_out)
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);
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wire [1-1:0] M_greenser_iob_out;
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reg [5-1:0] M_greenser_data;
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serdes_n_to_1 greenser (
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.ioclk(pclkx10),
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.strobe(strobe),
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.gclk(pclkx2),
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.rst(rst),
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.data(M_greenser_data),
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.iob_out(M_greenser_iob_out)
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);
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wire [1-1:0] M_blueser_iob_out;
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reg [5-1:0] M_blueser_data;
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serdes_n_to_1 blueser (
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.ioclk(pclkx10),
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.strobe(strobe),
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.gclk(pclkx2),
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.rst(rst),
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.data(M_blueser_data),
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.iob_out(M_blueser_iob_out)
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);
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wire [1-1:0] M_redbuf_O;
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wire [1-1:0] M_redbuf_OB;
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OBUFDS redbuf (
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.I(M_redser_iob_out),
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.O(M_redbuf_O),
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.OB(M_redbuf_OB)
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);
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wire [1-1:0] M_greenbuf_O;
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wire [1-1:0] M_greenbuf_OB;
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OBUFDS greenbuf (
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.I(M_greenser_iob_out),
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.O(M_greenbuf_O),
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.OB(M_greenbuf_OB)
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);
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wire [1-1:0] M_bluebuf_O;
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wire [1-1:0] M_bluebuf_OB;
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OBUFDS bluebuf (
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.I(M_blueser_iob_out),
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.O(M_bluebuf_O),
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.OB(M_bluebuf_OB)
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);
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always @* begin
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M_toggle_d = M_toggle_q;
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M_toggle_d = ~M_toggle_q;
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M_clkser_data = {3'h5{~M_toggle_q}};
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tmds[3+0-:1] = M_clkbuf_O;
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tmdsb[3+0-:1] = M_clkbuf_OB;
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M_enc_red_data_in = red;
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M_enc_green_data_in = green;
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M_enc_blue_data_in = blue;
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M_enc_red_c0 = hsync;
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M_enc_red_c1 = vsync;
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M_enc_red_de = de;
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M_enc_green_c0 = hsync;
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M_enc_green_c1 = vsync;
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M_enc_green_de = de;
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M_enc_blue_c0 = hsync;
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M_enc_blue_c1 = vsync;
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M_enc_blue_de = de;
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M_fifo_data_in = {M_enc_red_data_out[5+4-:5], M_enc_green_data_out[5+4-:5], M_enc_blue_data_out[5+4-:5], M_enc_red_data_out[0+4-:5], M_enc_green_data_out[0+4-:5], M_enc_blue_data_out[0+4-:5]};
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M_redser_data = M_fifo_data_out[10+4-:5];
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M_greenser_data = M_fifo_data_out[5+4-:5];
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M_blueser_data = M_fifo_data_out[0+4-:5];
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tmds[0+0-:1] = M_bluebuf_O;
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tmdsb[0+0-:1] = M_bluebuf_OB;
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tmds[1+0-:1] = M_greenbuf_O;
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tmdsb[1+0-:1] = M_greenbuf_OB;
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tmds[2+0-:1] = M_redbuf_O;
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tmdsb[2+0-:1] = M_redbuf_OB;
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end
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always @(posedge pclkx2) begin
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if (rst == 1'b1) begin
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M_toggle_q <= 1'h0;
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end else begin
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M_toggle_q <= M_toggle_d;
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end
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end
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endmodule |