16 lines
750 B
XML
16 lines
750 B
XML
<?xml version="1.0" encoding="UTF-8"?>
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<!-- IMPORTANT: This is an internal file that has been generated -->
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<!-- by the Xilinx ISE software. Any direct editing or -->
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<!-- changes made to this file may result in unpredictable -->
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<!-- behavior or data corruption. It is strongly advised that -->
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<!-- users do not edit the contents of this file. -->
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<!-- -->
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<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
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<messages>
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<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file "/home/tim/Projects/z80/hdmi/ipcore_dir/hdmi_clk.v" into library work</arg>
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</msg>
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</messages>
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