362 lines
18 KiB
C
Executable File
362 lines
18 KiB
C
Executable File
////////////////////////////////////////////////////////////////////////////////
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// Copyright (c) 2004-2012 Xilinx, Inc. All rights reserved.
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//
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// Xilinx, Inc.
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// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
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// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
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// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
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// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
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// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
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// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
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// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
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// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
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// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
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// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
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// AND FITNESS FOR A PARTICULAR PURPOSE.
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//
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//
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// Summary:
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// Header file for mb_interface
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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#ifndef _MICROBLAZE_INTERFACE_H_
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#define _MICROBLAZE_INTERFACE_H_
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#include "xbasic_types.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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extern void microblaze_enable_interrupts(void); /* Enable Interrupts */
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extern void microblaze_disable_interrupts(void); /* Disable Interrupts */
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extern void microblaze_enable_icache(void); /* Enable Instruction Cache */
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extern void microblaze_disable_icache(void); /* Disable Instruction Cache */
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extern void microblaze_enable_dcache(void); /* Enable Instruction Cache */
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extern void microblaze_disable_dcache(void); /* Disable Instruction Cache */
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extern void microblaze_enable_exceptions(void); /* Enable hardware exceptions */
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extern void microblaze_disable_exceptions(void); /* Disable hardware exceptions */
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extern void microblaze_register_handler(XInterruptHandler Handler, void *DataPtr); /* Register top level interrupt handler */
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extern void microblaze_register_exception_handler(Xuint8 ExceptionId, XExceptionHandler Handler, void *DataPtr); /* Register exception handler */
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extern void microblaze_invalidate_icache(void); /* Invalidate the entire icache */
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extern void microblaze_invalidate_dcache(void); /* Invalidate the entire dcache */
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extern void microblaze_flush_dcache(void); /* Flush the whole dcache */
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extern void microblaze_invalidate_icache_range(unsigned int cacheaddr, unsigned int len); /* Invalidate a part of the icache */
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extern void microblaze_invalidate_dcache_range(unsigned int cacheaddr, unsigned int len); /* Invalidate a part of the dcache */
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extern void microblaze_flush_dcache_range(unsigned int cacheaddr, unsigned int len); /* Flush a part of the dcache */
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extern void microblaze_scrub(void); /* Scrub LMB and internal BRAM */
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/* Deprecated */
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extern void microblaze_update_icache (int , int , int ) __attribute__((deprecated));
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extern void microblaze_init_icache_range (int , int ) __attribute__((deprecated));
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extern void microblaze_update_dcache (int , int , int ) __attribute__((deprecated));
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extern void microblaze_init_dcache_range (int , int ) __attribute__((deprecated));
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/* necessary for pre-processor */
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#define stringify(s) tostring(s)
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#define tostring(s) #s
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/* FSL Access Macros */
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/* Blocking Data Read and Write to FSL no. id */
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#define getfsl(val, id) asm volatile ("get\t%0,rfsl" stringify(id) : "=d" (val))
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#define putfsl(val, id) asm volatile ("put\t%0,rfsl" stringify(id) :: "d" (val))
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/* Non-blocking Data Read and Write to FSL no. id */
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#define ngetfsl(val, id) asm volatile ("nget\t%0,rfsl" stringify(id) : "=d" (val))
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#define nputfsl(val, id) asm volatile ("nput\t%0,rfsl" stringify(id) :: "d" (val))
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/* Blocking Control Read and Write to FSL no. id */
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#define cgetfsl(val, id) asm volatile ("cget\t%0,rfsl" stringify(id) : "=d" (val))
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#define cputfsl(val, id) asm volatile ("cput\t%0,rfsl" stringify(id) :: "d" (val))
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/* Non-blocking Control Read and Write to FSL no. id */
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#define ncgetfsl(val, id) asm volatile ("ncget\t%0,rfsl" stringify(id) : "=d" (val))
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#define ncputfsl(val, id) asm volatile ("ncput\t%0,rfsl" stringify(id) :: "d" (val))
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/* Polling versions of FSL access macros. This makes the FSL access interruptible */
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#define getfsl_interruptible(val, id) asm volatile ("\n1:\n\tnget\t%0,rfsl" stringify(id) "\n\t" \
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"addic\tr18,r0,0\n\t" \
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"bnei\tr18,1b\n" \
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: "=d" (val) :: "r18")
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#define putfsl_interruptible(val, id) asm volatile ("\n1:\n\tnput\t%0,rfsl" stringify(id) "\n\t" \
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"addic\tr18,r0,0\n\t" \
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"bnei\tr18,1b\n" \
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:: "d" (val) : "r18")
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#define cgetfsl_interruptible(val, id) asm volatile ("\n1:\n\tncget\t%0,rfsl" stringify(id) "\n\t" \
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"addic\tr18,r0,0\n\t" \
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"bnei\tr18,1b\n" \
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: "=d" (val) :: "r18")
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#define cputfsl_interruptible(val, id) asm volatile ("\n1:\n\tncput\t%0,rfsl" stringify(id) "\n\t" \
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"addic\tr18,r0,0\n\t" \
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"bnei\tr18,1b\n" \
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:: "d" (val) : "r18")
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/* FSL valid and error check macros. */
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#define fsl_isinvalid(result) asm volatile ("addic\t%0,r0,0" : "=d" (result))
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#define fsl_iserror(error) asm volatile ("mfs\t%0,rmsr\n\t" \
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"andi\t%0,%0,0x10" : "=d" (error))
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/* Pseudo assembler instructions */
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#define clz(v) ({ unsigned int _rval; \
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__asm__ __volatile__ ( \
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"clz\t%0,%1\n" : "=d"(_rval): "d" (v) \
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); \
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_rval; \
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})
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#define mbar(mask) ({ __asm__ __volatile__ ("mbar\t" stringify(mask) ); })
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#define mb_sleep() ({ __asm__ __volatile__ ("sleep\t"); })
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#define mb_swapb(v) ({ unsigned int _rval; \
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__asm__ __volatile__ ( \
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"swapb\t%0,%1\n" : "=d"(_rval) : "d" (v) \
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); \
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_rval; \
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})
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#define mb_swaph(v) ({ unsigned int _rval; \
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__asm__ __volatile__ ( \
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"swaph\t%0,%1\n" : "=d"(_rval) : "d" (v) \
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); \
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_rval; \
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})
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#define mfgpr(rn) ({ unsigned int _rval; \
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__asm__ __volatile__ ( \
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"or\t%0,r0," stringify(rn) "\n" : "=d"(_rval) \
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); \
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_rval; \
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})
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#define mfmsr() ({ unsigned int _rval; \
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__asm__ __volatile__ ( \
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"mfs\t%0,rmsr\n" : "=d"(_rval) \
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); \
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_rval; \
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})
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#define mfear() ({ unsigned int _rval; \
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__asm__ __volatile__ ( \
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"mfs\t%0,rear\n" : "=d"(_rval) \
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); \
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_rval; \
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})
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#define mfesr() ({ unsigned int _rval; \
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__asm__ __volatile__ ( \
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"mfs\t%0,resr\n" : "=d"(_rval) \
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); \
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_rval; \
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})
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#define mffsr() ({ unsigned int _rval; \
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__asm__ __volatile__ ( \
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"mfs\t%0,rfsr\n" : "=d"(_rval) \
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); \
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_rval; \
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})
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#define mfpvr(rn) ({ unsigned int _rval; \
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__asm__ __volatile__ ( \
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"mfs\t%0,rpvr" stringify(rn) "\n" : "=d"(_rval) \
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); \
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_rval; \
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})
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#define mfbtr() ({ unsigned int _rval; \
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__asm__ __volatile__ ( \
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"mfs\t%0,rbtr\n" : "=d"(_rval) \
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); \
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_rval; \
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})
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#define mfedr() ({ unsigned int _rval; \
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__asm__ __volatile__ ( \
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"mfs\t%0,redr\n" : "=d"(_rval) \
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); \
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_rval; \
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})
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#define mfpid() ({ unsigned int _rval; \
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__asm__ __volatile__ ( \
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"mfs\t%0,rpid\n" : "=d"(_rval)\
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); \
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_rval; \
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})
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#define mfzpr() ({ unsigned int _rval; \
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__asm__ __volatile__ ( \
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"mfs\t%0,rzpr\n" : "=d"(_rval) \
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); \
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_rval; \
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})
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#define mftlbx() ({ unsigned int _rval; \
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__asm__ __volatile__ ( \
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"mfs\t%0,rtlbx\n" : "=d"(_rval) \
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); \
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_rval; \
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})
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#define mftlblo() ({ unsigned int _rval; \
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__asm__ __volatile__ ( \
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"mfs\t%0,rtlblo\n" : "=d"(_rval) \
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); \
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_rval; \
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})
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#define mftlbhi() ({ unsigned int _rval; \
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__asm__ __volatile__ ( \
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"mfs\t%0,rtlbhi\n" : "=d"(_rval) \
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); \
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_rval; \
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})
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#define mfslr() ({ unsigned int _rval; \
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__asm__ __volatile__ ( \
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"mfs\t%0,rslr\n" : "=d"(_rval) \
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); \
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_rval; \
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})
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#define mfshr() ({ unsigned int _rval; \
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__asm__ __volatile__ ( \
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"mfs\t%0,rshr\n" : "=d"(_rval) \
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); \
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_rval; \
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})
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#define mtgpr(rn, v) ({ __asm__ __volatile__ ( \
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"or\t" stringify(rn) ",r0,%0\n" :: "d" (v) \
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); \
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})
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#define mtmsr(v) ({ __asm__ __volatile__ ( \
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"mts\trmsr,%0\n\tnop\n" :: "d" (v) \
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); \
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})
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#define mtfsr(v) ({ __asm__ __volatile__ ( \
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"mts\trfsr,%0\n\tnop\n" :: "d" (v) \
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); \
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})
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#define mtpid(v) ({ __asm__ __volatile__ ( \
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"mts\trpid,%0\n\tnop\n" :: "d" (v) \
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); \
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})
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#define mtzpr(v) ({ __asm__ __volatile__ ( \
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"mts\trzpr,%0\n\tnop\n" :: "d" (v) \
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); \
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})
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#define mttlbx(v) ({ __asm__ __volatile__ ( \
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"mts\trtlbx,%0\n\tnop\n" :: "d" (v) \
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); \
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})
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#define mttlblo(v) ({ __asm__ __volatile__ ( \
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"mts\trtlblo,%0\n\tnop\n" :: "d" (v) \
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); \
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})
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#define mttlbhi(v) ({ __asm__ __volatile__ ( \
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"mts\trtlbhi,%0\n\tnop\n" :: "d" (v) \
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); \
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})
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#define mttlbsx(v) ({ __asm__ __volatile__ ( \
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"mts\trtlbsx,%0\n\tnop\n" :: "d" (v) \
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); \
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})
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#define mtslr(v) ({ __asm__ __volatile__ ( \
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"mts\trslr,%0\n\tnop\n" :: "d" (v) \
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); \
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})
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#define mtshr(v) ({ __asm__ __volatile__ ( \
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"mts\trshr,%0\n\tnop\n" :: "d" (v) \
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); \
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})
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#define lwx(address) ({ unsigned int _rval; \
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__asm__ __volatile__ ( \
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"lwx\t%0,%1,r0\n" : "=d"(_rval) : "d" (address) \
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); \
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_rval; \
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})
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#define lwr(address) ({ unsigned int _rval; \
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__asm__ __volatile__ ( \
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"lwr\t%0,%1,r0\n" : "=d"(_rval) : "d" (address) \
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); \
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_rval; \
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})
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#define lhur(address) ({ unsigned int _rval; \
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__asm__ __volatile__ ( \
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"lhur\t%0,%1,r0\n" : "=d"(_rval) : "d" (address) \
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); \
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_rval; \
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})
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#define lbur(address) ({ unsigned int _rval; \
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__asm__ __volatile__ ( \
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"lbur\t%0,%1,r0\n" : "=d"(_rval) : "d" (address) \
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); \
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_rval; \
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})
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#define swx(address, data) ({ __asm__ __volatile__ ( \
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"swx\t%0,%1,r0\n" :: "d" (data), "d" (address) \
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); \
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})
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#define swr(address, data) ({ __asm__ __volatile__ ( \
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"swr\t%0,%1,r0\n" :: "d" (data), "d" (address) \
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); \
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})
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#define shr(address, data) ({ __asm__ __volatile__ ( \
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"shr\t%0,%1,r0\n" :: "d" (data), "d" (address) \
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); \
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})
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#define sbr(address, data) ({ __asm__ __volatile__ ( \
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"sbr\t%0,%1,r0\n" :: "d" (data), "d" (address) \
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); \
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})
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#define microblaze_getfpex_operand_a() ({ \
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extern unsigned int mb_fpex_op_a; \
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mb_fpex_op_a; \
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})
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#define microblaze_getfpex_operand_b() ({ \
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extern unsigned int mb_fpex_op_b; \
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mb_fpex_op_b; \
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})
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/* Deprecated MicroBlaze FSL macros */
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#define microblaze_bread_datafsl(val, id) getfsl(val,id)
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#define microblaze_bwrite_datafsl(val, id) putfsl(val,id)
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#define microblaze_nbread_datafsl(val, id) ngetfsl(val,id)
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#define microblaze_nbwrite_datafsl(val, id) nputfsl(val,id)
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#define microblaze_bread_cntlfsl(val, id) cgetfsl(val,id)
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#define microblaze_bwrite_cntlfsl(val, id) cputfsl(val,id)
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#define microblaze_nbread_cntlfsl(val, id) ncgetfsl(val,id)
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#define microblaze_nbwrite_cntlfsl(val, id) ncputfsl(val,id)
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#ifdef __cplusplus
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}
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#endif
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#endif // _MICROBLAZE_INTERFACE_H_
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