416 lines
19 KiB
C
416 lines
19 KiB
C
/******************************************************************************
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*
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* (c) Copyright 2011-2013 Xilinx, Inc. All rights reserved.
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*
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* This file contains confidential and proprietary information of Xilinx, Inc.
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* and is protected under U.S. and international copyright and other
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* intellectual property laws.
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*
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* DISCLAIMER
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* This disclaimer is not a license and does not grant any rights to the
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* materials distributed herewith. Except as otherwise provided in a valid
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* license issued to you by Xilinx, and to the maximum extent permitted by
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* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
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* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
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* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
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* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
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* and (2) Xilinx shall not be liable (whether in contract or tort, including
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* negligence, or under any other theory of liability) for any loss or damage
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* of any kind or nature related to, arising under or in connection with these
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* materials, including for any direct, or any indirect, special, incidental,
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* or consequential loss or damage (including loss of data, profits, goodwill,
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* or any type of loss or damage suffered as a result of any action brought by
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* a third party) even if such damage or loss was reasonably foreseeable or
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* Xilinx had been advised of the possibility of the same.
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*
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* CRITICAL APPLICATIONS
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* Xilinx products are not designed or intended to be fail-safe, or for use in
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* any application requiring fail-safe performance, such as life-support or
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* safety devices or systems, Class III medical devices, nuclear facilities,
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* applications related to the deployment of airbags, or any other applications
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* that could lead to death, personal injury, or severe property or
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* environmental damage (individually and collectively, "Critical
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* Applications"). Customer assumes the sole risk and liability of any use of
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* Xilinx products in Critical Applications, subject only to applicable laws
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* and regulations governing limitations on product liability.
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*
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* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
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* AT ALL TIMES.
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*
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******************************************************************************/
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/*****************************************************************************/
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/**
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*
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* @file xbram_hw.h
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*
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* This header file contains identifiers and driver functions (or
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* macros) that can be used to access the device. The user should refer to the
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* hardware device specification for more details of the device operation.
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*
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* <pre>
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* MODIFICATION HISTORY:
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*
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* Ver Who Date Changes
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* ----- ---- -------- -----------------------------------------------
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* 1.00a sa 24/11/10 First release
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* </pre>
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*
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******************************************************************************/
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#ifndef XBRAM_HW_H /* prevent circular inclusions */
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#define XBRAM_HW_H /* by using protection macros */
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#ifdef __cplusplus
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extern "C" {
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#endif
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/***************************** Include Files *********************************/
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#include "xil_types.h"
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#include "xil_assert.h"
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#include "xil_io.h"
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/************************** Constant Definitions *****************************/
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/** @name Registers
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*
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* Register offsets for this device.
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* @{
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*/
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#define XBRAM_ECC_STATUS_OFFSET 0x0 /**< ECC status Register */
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#define XBRAM_ECC_EN_IRQ_OFFSET 0x4 /**< ECC interrupt enable Register */
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#define XBRAM_ECC_ON_OFF_OFFSET 0x8 /**< ECC on/off register */
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#define XBRAM_CE_CNT_OFFSET 0xC /**< Correctable error counter Register */
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#define XBRAM_CE_FFD_0_OFFSET 0x100 /**< Correctable error first failing
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* data Register, 31-0 */
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#define XBRAM_CE_FFD_1_OFFSET 0x104 /**< Correctable error first failing
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* data Register, 63-32 */
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#define XBRAM_CE_FFD_2_OFFSET 0x108 /**< Correctable error first failing
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* data Register, 95-64 */
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#define XBRAM_CE_FFD_3_OFFSET 0x10C /**< Correctable error first failing
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* data Register, 127-96 */
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#define XBRAM_CE_FFD_4_OFFSET 0x110 /**< Correctable error first failing
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* data Register, 159-128 */
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#define XBRAM_CE_FFD_5_OFFSET 0x114 /**< Correctable error first failing
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* data Register, 191-160 */
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#define XBRAM_CE_FFD_6_OFFSET 0x118 /**< Correctable error first failing
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* data Register, 223-192 */
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#define XBRAM_CE_FFD_7_OFFSET 0x11C /**< Correctable error first failing
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* data Register, 255-224 */
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#define XBRAM_CE_FFD_8_OFFSET 0x120 /**< Correctable error first failing
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* data Register, 287-256 */
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#define XBRAM_CE_FFD_9_OFFSET 0x124 /**< Correctable error first failing
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* data Register, 319-288 */
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#define XBRAM_CE_FFD_10_OFFSET 0x128 /**< Correctable error first failing
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* data Register, 351-320 */
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#define XBRAM_CE_FFD_11_OFFSET 0x12C /**< Correctable error first failing
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* data Register, 383-352 */
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#define XBRAM_CE_FFD_12_OFFSET 0x130 /**< Correctable error first failing
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* data Register, 415-384 */
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#define XBRAM_CE_FFD_13_OFFSET 0x134 /**< Correctable error first failing
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* data Register, 447-416 */
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#define XBRAM_CE_FFD_14_OFFSET 0x138 /**< Correctable error first failing
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* data Register, 479-448 */
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#define XBRAM_CE_FFD_15_OFFSET 0x13C /**< Correctable error first failing
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* data Register, 511-480 */
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#define XBRAM_CE_FFD_16_OFFSET 0x140 /**< Correctable error first failing
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* data Register, 543-512 */
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#define XBRAM_CE_FFD_17_OFFSET 0x144 /**< Correctable error first failing
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* data Register, 575-544 */
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#define XBRAM_CE_FFD_18_OFFSET 0x148 /**< Correctable error first failing
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* data Register, 607-576 */
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#define XBRAM_CE_FFD_19_OFFSET 0x14C /**< Correctable error first failing
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* data Register, 639-608 */
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#define XBRAM_CE_FFD_20_OFFSET 0x150 /**< Correctable error first failing
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* data Register, 671-640 */
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#define XBRAM_CE_FFD_21_OFFSET 0x154 /**< Correctable error first failing
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* data Register, 703-672 */
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#define XBRAM_CE_FFD_22_OFFSET 0x158 /**< Correctable error first failing
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* data Register, 735-704 */
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#define XBRAM_CE_FFD_23_OFFSET 0x15C /**< Correctable error first failing
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* data Register, 767-736 */
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#define XBRAM_CE_FFD_24_OFFSET 0x160 /**< Correctable error first failing
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* data Register, 799-768 */
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#define XBRAM_CE_FFD_25_OFFSET 0x164 /**< Correctable error first failing
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* data Register, 831-800 */
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#define XBRAM_CE_FFD_26_OFFSET 0x168 /**< Correctable error first failing
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* data Register, 863-832 */
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#define XBRAM_CE_FFD_27_OFFSET 0x16C /**< Correctable error first failing
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* data Register, 895-864 */
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#define XBRAM_CE_FFD_28_OFFSET 0x170 /**< Correctable error first failing
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* data Register, 927-896 */
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#define XBRAM_CE_FFD_29_OFFSET 0x174 /**< Correctable error first failing
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* data Register, 959-928 */
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#define XBRAM_CE_FFD_30_OFFSET 0x178 /**< Correctable error first failing
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* data Register, 991-960 */
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#define XBRAM_CE_FFD_31_OFFSET 0x17C /**< Correctable error first failing
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* data Register, 1023-992 */
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#define XBRAM_CE_FFE_0_OFFSET 0x180 /**< Correctable error first failing
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* ECC Register, 31-0 */
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#define XBRAM_CE_FFE_1_OFFSET 0x184 /**< Correctable error first failing
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* ECC Register, 63-32 */
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#define XBRAM_CE_FFE_2_OFFSET 0x188 /**< Correctable error first failing
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* ECC Register, 95-64 */
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#define XBRAM_CE_FFE_3_OFFSET 0x18C /**< Correctable error first failing
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* ECC Register, 127-96 */
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#define XBRAM_CE_FFE_4_OFFSET 0x190 /**< Correctable error first failing
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* ECC Register, 159-128 */
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#define XBRAM_CE_FFE_5_OFFSET 0x194 /**< Correctable error first failing
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* ECC Register, 191-160 */
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#define XBRAM_CE_FFE_6_OFFSET 0x198 /**< Correctable error first failing
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* ECC Register, 223-192 */
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#define XBRAM_CE_FFE_7_OFFSET 0x19C /**< Correctable error first failing
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* ECC Register, 255-224 */
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#define XBRAM_CE_FFA_0_OFFSET 0x1C0 /**< Correctable error first failing
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* address Register 31-0 */
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#define XBRAM_CE_FFA_1_OFFSET 0x1C4 /**< Correctable error first failing
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* address Register 63-32 */
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#define XBRAM_UE_FFD_0_OFFSET 0x200 /**< Uncorrectable error first failing
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* data Register, 31-0 */
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#define XBRAM_UE_FFD_1_OFFSET 0x204 /**< Uncorrectable error first failing
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* data Register, 63-32 */
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#define XBRAM_UE_FFD_2_OFFSET 0x208 /**< Uncorrectable error first failing
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* data Register, 95-64 */
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#define XBRAM_UE_FFD_3_OFFSET 0x20C /**< Uncorrectable error first failing
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* data Register, 127-96 */
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#define XBRAM_UE_FFD_4_OFFSET 0x210 /**< Uncorrectable error first failing
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* data Register, 159-128 */
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#define XBRAM_UE_FFD_5_OFFSET 0x214 /**< Uncorrectable error first failing
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* data Register, 191-160 */
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#define XBRAM_UE_FFD_6_OFFSET 0x218 /**< Uncorrectable error first failing
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* data Register, 223-192 */
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#define XBRAM_UE_FFD_7_OFFSET 0x21C /**< Uncorrectable error first failing
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* data Register, 255-224 */
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#define XBRAM_UE_FFD_8_OFFSET 0x220 /**< Uncorrectable error first failing
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* data Register, 287-256 */
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#define XBRAM_UE_FFD_9_OFFSET 0x224 /**< Uncorrectable error first failing
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* data Register, 319-288 */
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#define XBRAM_UE_FFD_10_OFFSET 0x228 /**< Uncorrectable error first failing
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* data Register, 351-320 */
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#define XBRAM_UE_FFD_11_OFFSET 0x22C /**< Uncorrectable error first failing
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* data Register, 383-352 */
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#define XBRAM_UE_FFD_12_OFFSET 0x230 /**< Uncorrectable error first failing
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* data Register, 415-384 */
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#define XBRAM_UE_FFD_13_OFFSET 0x234 /**< Uncorrectable error first failing
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* data Register, 447-416 */
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#define XBRAM_UE_FFD_14_OFFSET 0x238 /**< Uncorrectable error first failing
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* data Register, 479-448 */
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#define XBRAM_UE_FFD_15_OFFSET 0x23C /**< Uncorrectable error first failing
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* data Register, 511-480 */
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#define XBRAM_UE_FFD_16_OFFSET 0x240 /**< Uncorrectable error first failing
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* data Register, 543-512 */
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#define XBRAM_UE_FFD_17_OFFSET 0x244 /**< Uncorrectable error first failing
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* data Register, 575-544 */
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#define XBRAM_UE_FFD_18_OFFSET 0x248 /**< Uncorrectable error first failing
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* data Register, 607-576 */
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#define XBRAM_UE_FFD_19_OFFSET 0x24C /**< Uncorrectable error first failing
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* data Register, 639-608 */
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#define XBRAM_UE_FFD_20_OFFSET 0x250 /**< Uncorrectable error first failing
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* data Register, 671-640 */
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#define XBRAM_UE_FFD_21_OFFSET 0x254 /**< Uncorrectable error first failing
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* data Register, 703-672 */
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#define XBRAM_UE_FFD_22_OFFSET 0x258 /**< Uncorrectable error first failing
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* data Register, 735-704 */
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#define XBRAM_UE_FFD_23_OFFSET 0x25C /**< Uncorrectable error first failing
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* data Register, 767-736 */
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#define XBRAM_UE_FFD_24_OFFSET 0x260 /**< Uncorrectable error first failing
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* data Register, 799-768 */
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#define XBRAM_UE_FFD_25_OFFSET 0x264 /**< Uncorrectable error first failing
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* data Register, 831-800 */
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#define XBRAM_UE_FFD_26_OFFSET 0x268 /**< Uncorrectable error first failing
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* data Register, 863-832 */
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#define XBRAM_UE_FFD_27_OFFSET 0x26C /**< Uncorrectable error first failing
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* data Register, 895-864 */
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#define XBRAM_UE_FFD_28_OFFSET 0x270 /**< Uncorrectable error first failing
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* data Register, 927-896 */
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#define XBRAM_UE_FFD_29_OFFSET 0x274 /**< Uncorrectable error first failing
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* data Register, 959-928 */
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#define XBRAM_UE_FFD_30_OFFSET 0x278 /**< Uncorrectable error first failing
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* data Register, 991-960 */
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#define XBRAM_UE_FFD_31_OFFSET 0x27C /**< Uncorrectable error first failing
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* data Register, 1023-992 */
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#define XBRAM_UE_FFE_0_OFFSET 0x280 /**< Uncorrectable error first failing
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* ECC Register, 31-0 */
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#define XBRAM_UE_FFE_1_OFFSET 0x284 /**< Uncorrectable error first failing
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* ECC Register, 63-32 */
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#define XBRAM_UE_FFE_2_OFFSET 0x288 /**< Uncorrectable error first failing
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* ECC Register, 95-64 */
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#define XBRAM_UE_FFE_3_OFFSET 0x28C /**< Uncorrectable error first failing
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* ECC Register, 127-96 */
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#define XBRAM_UE_FFE_4_OFFSET 0x290 /**< Uncorrectable error first failing
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* ECC Register, 159-128 */
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#define XBRAM_UE_FFE_5_OFFSET 0x294 /**< Uncorrectable error first failing
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* ECC Register, 191-160 */
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#define XBRAM_UE_FFE_6_OFFSET 0x298 /**< Uncorrectable error first failing
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* ECC Register, 223-192 */
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#define XBRAM_UE_FFE_7_OFFSET 0x29C /**< Uncorrectable error first failing
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* ECC Register, 255-224 */
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#define XBRAM_UE_FFA_0_OFFSET 0x2C0 /**< Uncorrectable error first failing
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* address Register 31-0 */
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#define XBRAM_UE_FFA_1_OFFSET 0x2C4 /**< Uncorrectable error first failing
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* address Register 63-32 */
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#define XBRAM_FI_D_0_OFFSET 0x300 /**< Fault injection Data Register,
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* 31-0 */
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#define XBRAM_FI_D_1_OFFSET 0x304 /**< Fault injection Data Register,
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* 63-32 */
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#define XBRAM_FI_D_2_OFFSET 0x308 /**< Fault injection Data Register,
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* 95-64 */
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#define XBRAM_FI_D_3_OFFSET 0x30C /**< Fault injection Data Register,
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* 127-96 */
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#define XBRAM_FI_D_4_OFFSET 0x310 /**< Fault injection Data Register,
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* 159-128 */
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#define XBRAM_FI_D_5_OFFSET 0x314 /**< Fault injection Data Register,
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* 191-160 */
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#define XBRAM_FI_D_6_OFFSET 0x318 /**< Fault injection Data Register,
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* 223-192 */
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#define XBRAM_FI_D_7_OFFSET 0x31C /**< Fault injection Data Register,
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* 255-224 */
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#define XBRAM_FI_D_8_OFFSET 0x320 /**< Fault injection Data Register,
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* 287-256 */
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#define XBRAM_FI_D_9_OFFSET 0x324 /**< Fault injection Data Register,
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* 319-288 */
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#define XBRAM_FI_D_10_OFFSET 0x328 /**< Fault injection Data Register,
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* 351-320 */
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#define XBRAM_FI_D_11_OFFSET 0x32C /**< Fault injection Data Register,
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* 383-352 */
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#define XBRAM_FI_D_12_OFFSET 0x330 /**< Fault injection Data Register,
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* 415-384 */
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#define XBRAM_FI_D_13_OFFSET 0x334 /**< Fault injection Data Register,
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* 447-416 */
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#define XBRAM_FI_D_14_OFFSET 0x338 /**< Fault injection Data Register,
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* 479-448 */
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#define XBRAM_FI_D_15_OFFSET 0x33C /**< Fault injection Data Register,
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* 511-480 */
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#define XBRAM_FI_D_16_OFFSET 0x340 /**< Fault injection Data Register,
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* 543-512 */
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#define XBRAM_FI_D_17_OFFSET 0x344 /**< Fault injection Data Register,
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* 575-544 */
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#define XBRAM_FI_D_18_OFFSET 0x348 /**< Fault injection Data Register,
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* 607-576 */
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#define XBRAM_FI_D_19_OFFSET 0x34C /**< Fault injection Data Register,
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* 639-608 */
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#define XBRAM_FI_D_20_OFFSET 0x350 /**< Fault injection Data Register,
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* 671-640 */
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#define XBRAM_FI_D_21_OFFSET 0x354 /**< Fault injection Data Register,
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* 703-672 */
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#define XBRAM_FI_D_22_OFFSET 0x358 /**< Fault injection Data Register,
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* 735-704 */
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#define XBRAM_FI_D_23_OFFSET 0x35C /**< Fault injection Data Register,
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* 767-736 */
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#define XBRAM_FI_D_24_OFFSET 0x360 /**< Fault injection Data Register,
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* 799-768 */
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#define XBRAM_FI_D_25_OFFSET 0x364 /**< Fault injection Data Register,
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* 831-800 */
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#define XBRAM_FI_D_26_OFFSET 0x368 /**< Fault injection Data Register,
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* 863-832 */
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#define XBRAM_FI_D_27_OFFSET 0x36C /**< Fault injection Data Register,
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* 895-864 */
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#define XBRAM_FI_D_28_OFFSET 0x370 /**< Fault injection Data Register,
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* 927-896 */
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#define XBRAM_FI_D_29_OFFSET 0x374 /**< Fault injection Data Register,
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* 959-928 */
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#define XBRAM_FI_D_30_OFFSET 0x378 /**< Fault injection Data Register,
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* 991-960 */
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#define XBRAM_FI_D_31_OFFSET 0x37C /**< Fault injection Data Register,
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* 1023-992 */
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#define XBRAM_FI_ECC_0_OFFSET 0x380 /**< Fault injection ECC Register,
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* 31-0 */
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#define XBRAM_FI_ECC_1_OFFSET 0x384 /**< Fault injection ECC Register,
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* 63-32 */
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#define XBRAM_FI_ECC_2_OFFSET 0x388 /**< Fault injection ECC Register,
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* 95-64 */
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#define XBRAM_FI_ECC_3_OFFSET 0x38C /**< Fault injection ECC Register,
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* 127-96 */
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#define XBRAM_FI_ECC_4_OFFSET 0x390 /**< Fault injection ECC Register,
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* 159-128 */
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#define XBRAM_FI_ECC_5_OFFSET 0x394 /**< Fault injection ECC Register,
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* 191-160 */
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#define XBRAM_FI_ECC_6_OFFSET 0x398 /**< Fault injection ECC Register,
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* 223-192 */
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#define XBRAM_FI_ECC_7_OFFSET 0x39C /**< Fault injection ECC Register,
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* 255-224 */
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/* @} */
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/** @name Interrupt Status and Enable Register bitmaps and masks
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*
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* Bit definitions for the ECC status register and ECC interrupt enable register.
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* @{
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*/
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#define XBRAM_IR_CE_MASK 0x2 /**< Mask for the correctable error */
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#define XBRAM_IR_UE_MASK 0x1 /**< Mask for the uncorrectable error */
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#define XBRAM_IR_ALL_MASK 0x3 /**< Mask of all bits */
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/*@}*/
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/**************************** Type Definitions *******************************/
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/***************** Macros (Inline Functions) Definitions *********************/
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#define XBram_In32 Xil_In32
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#define XBram_Out32 Xil_Out32
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#define XBram_In16 Xil_In16
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#define XBram_Out16 Xil_Out16
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#define XBram_In8 Xil_In8
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#define XBram_Out8 Xil_Out8
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/****************************************************************************/
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/**
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*
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* Write a value to a BRAM register. A 32 bit write is performed.
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*
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* @param BaseAddress is the base address of the BRAM device register.
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* @param RegOffset is the register offset from the base to write to.
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* @param Data is the data written to the register.
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*
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* @return None.
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*
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* @note C-style signature:
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* void XBram_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)
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*
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****************************************************************************/
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#define XBram_WriteReg(BaseAddress, RegOffset, Data) \
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XBram_Out32((BaseAddress) + (RegOffset), (u32)(Data))
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/****************************************************************************/
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/**
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*
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* Read a value from a BRAM register. A 32 bit read is performed.
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*
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* @param BaseAddress is the base address of the BRAM device registers.
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* @param RegOffset is the register offset from the base to read from.
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*
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* @return Data read from the register.
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*
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* @note C-style signature:
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* u32 XBram_ReadReg(u32 BaseAddress, u32 RegOffset)
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*
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****************************************************************************/
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#define XBram_ReadReg(BaseAddress, RegOffset) \
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XBram_In32((BaseAddress) + (RegOffset))
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/************************** Function Prototypes ******************************/
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/************************** Variable Definitions *****************************/
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#ifdef __cplusplus
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}
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#endif
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#endif /* end of protection macro */
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