447 lines
16 KiB
C
447 lines
16 KiB
C
/* $Id$ */
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/******************************************************************************
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*
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* (c) Copyright 2011,2012 Xilinx, Inc. All rights reserved.
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*
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* This file contains confidential and proprietary information of Xilinx, Inc.
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* and is protected under U.S. and international copyright and other
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* intellectual property laws.
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*
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* DISCLAIMER
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* This disclaimer is not a license and does not grant any rights to the
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* materials distributed herewith. Except as otherwise provided in a valid
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* license issued to you by Xilinx, and to the maximum extent permitted by
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* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
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* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
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* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
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* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
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* and (2) Xilinx shall not be liable (whether in contract or tort, including
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* negligence, or under any other theory of liability) for any loss or damage
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* of any kind or nature related to, arising under or in connection with these
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* materials, including for any direct, or any indirect, special, incidental,
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* or consequential loss or damage (including loss of data, profits, goodwill,
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* or any type of loss or damage suffered as a result of any action brought by
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* a third party) even if such damage or loss was reasonably foreseeable or
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* Xilinx had been advised of the possibility of the same.
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*
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* CRITICAL APPLICATIONS
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* Xilinx products are not designed or intended to be fail-safe, or for use in
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* any application requiring fail-safe performance, such as life-support or
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* safety devices or systems, Class III medical devices, nuclear facilities,
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* applications related to the deployment of airbags, or any other applications
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* that could lead to death, personal injury, or severe property or
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* environmental damage (individually and collectively, "Critical
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* Applications"). Customer assumes the sole risk and liability of any use of
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* Xilinx products in Critical Applications, subject only to applicable laws
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* and regulations governing limitations on product liability.
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*
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* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
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* AT ALL TIMES.
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*
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******************************************************************************/
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/*****************************************************************************/
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/**
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*
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* @file xiomodule_l.h
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*
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* This header file contains identifiers and low-level driver functions (or
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* macros) that can be used to access the device. The user should refer to the
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* hardware device specification for more details of the device operation.
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*
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*
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* Note that users of the driver interface given in this file can register
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* an interrupt handler dynamically (at run-time) using the
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* XIntc_RegisterHandler() function.
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* User of the driver interface given in xiomodule.h should still use
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* XIntc_Connect(), as always.
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* Also see the discussion of the interrupt vector tables in xiomodule.h.
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*
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* There are currently two interrupt handlers specified in this interface.
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*
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* - XIOModule_LowLevelInterruptHandler() is a handler without any arguments
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* that is used in cases where there is a single interrupt controller device
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* in the system and the handler cannot be passed an argument. This function
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* is provided mostly for backward compatibility.
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*
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* - XIOModule_DeviceInterruptHandler() is a handler that takes a device ID
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* as an argument, indicating which interrupt controller device in the system
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* is causing the interrupt - thereby supporting multiple interrupt
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* controllers.
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*
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* <pre>
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* MODIFICATION HISTORY:
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*
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* Ver Who Date Changes
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* ----- ---- -------- -----------------------------------------------------
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* 1.00a sa 07/15/11 First release
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* 1.01a sa 04/10/12 Updated with fast interrupt
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* 1.02a sa 07/25/12 Updated with GPI interrupt support
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* </pre>
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*
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******************************************************************************/
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#ifndef XIOMODULE_L_H /* prevent circular inclusions */
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#define XIOMODULE_L_H /* by using protection macros */
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#ifdef __cplusplus
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extern "C" {
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#endif
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/***************************** Include Files *********************************/
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#include "xbasic_types.h"
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#include "xparameters.h"
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#include "xiomodule_io.h"
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#include "xio.h"
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/************************** Constant Definitions *****************************/
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/**
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* Defines the number of timer counters within a single hardware device. This
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* number is not currently parameterized in the hardware but may be in the
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* future.
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*/
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#define XTC_DEVICE_TIMER_COUNT 4
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/**
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* Each timer counter consumes 16 bytes of address space.
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*/
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#define XTC_TIMER_COUNTER_OFFSET 16
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#define XTC_TIMER_COUNTER_SHIFT 4
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/**
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* Define the offsets from the base address for all the registers of the
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* IO module, some registers may be optional in the hardware device.
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*/
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#define XUL_RX_OFFSET 0x00000000 /**< UART Receive Register - R */
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#define XUL_TX_OFFSET 0x00000004 /**< UART Transmit Register - W */
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#define XUL_STATUS_REG_OFFSET 0x00000008 /**< UART Status Register - R */
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#define XUL_BAUDRATE_OFFSET 0x0000004C /**< UART Baud Rate Register - W */
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#define XIN_IMR_OFFSET 0x0000000C /**< Intr Mode Register - W */
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#define XGO_OUT_OFFSET 0x00000010 /**< General Purpose Output - W */
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#define XGI_IN_OFFSET 0x00000020 /**< General Purpose Input - R */
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#define XIN_ISR_OFFSET 0x00000030 /**< Intr Status Register - R */
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#define XIN_IPR_OFFSET 0x00000034 /**< Intr Pending Register - R */
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#define XIN_IER_OFFSET 0x00000038 /**< Intr Enable Register - W */
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#define XIN_IAR_OFFSET 0x0000003C /**< Intr Acknowledge Register - W */
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#define XTC_TLR_OFFSET 0x00000040 /**< Timer Load register - W */
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#define XTC_TCR_OFFSET 0x00000044 /**< Timer counter register - R */
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#define XTC_TCSR_OFFSET 0x00000048 /**< Timer Control register - W */
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#define XIN_IVAR_OFFSET 0x00000080 /**< Intr Vector Address Register,
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Interrupt 0 offset, present
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only for Fast Interrupt - W */
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/**
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* UART status register bit position masks
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*/
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#define XUL_SR_PARITY_ERROR 0x80
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#define XUL_SR_FRAMING_ERROR 0x40
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#define XUL_SR_OVERRUN_ERROR 0x20
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#define XUL_SR_INTR_ENABLED 0x10 /**< UART Interrupt enabled */
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#define XUL_SR_TX_FIFO_FULL 0x08 /**< UART Transmit FIFO full */
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#define XUL_SR_RX_FIFO_VALID_DATA 0x01 /**< UART Data Register valid */
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/**
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* UART stop bits are fixed at 1. Baud, parity, and data bits are fixed on a
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* per instance basis.
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*/
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#define XUL_STOP_BITS 1
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/**
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* UART Parity definitions.
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*/
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#define XUL_PARITY_NONE 0
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#define XUL_PARITY_ODD 1
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#define XUL_PARITY_EVEN 2
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/**
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* Defines the number of GPI and GPO within a single hardware device. This
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* number is not currently parameterized in the hardware but may be in the
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* future.
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* @{
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*/
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#define XGPI_DEVICE_COUNT 4
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#define XGPO_DEVICE_COUNT 4
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/**
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* The following constants describe the offset of each GPI and GPO channel's
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* data from the base address.
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*/
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#define XGPI_CHAN_OFFSET 0x00004
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#define XGPI_DATA_OFFSET 0x00020
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#define XGPO_CHAN_OFFSET 0x00004
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#define XGPO_DATA_OFFSET 0x00010
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/**
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* Interrupt register bit position masks.
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*/
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#define XIN_IOMODULE_GPI_4_INTERRUPT_INTR 14
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#define XIN_IOMODULE_GPI_3_INTERRUPT_INTR 13
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#define XIN_IOMODULE_GPI_2_INTERRUPT_INTR 12
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#define XIN_IOMODULE_GPI_1_INTERRUPT_INTR 11
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#define XIN_IOMODULE_FIT_4_INTERRUPT_INTR 10
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#define XIN_IOMODULE_FIT_3_INTERRUPT_INTR 9
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#define XIN_IOMODULE_FIT_2_INTERRUPT_INTR 8
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#define XIN_IOMODULE_FIT_1_INTERRUPT_INTR 7
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#define XIN_IOMODULE_PIT_4_INTERRUPT_INTR 6
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#define XIN_IOMODULE_PIT_3_INTERRUPT_INTR 5
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#define XIN_IOMODULE_PIT_2_INTERRUPT_INTR 4
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#define XIN_IOMODULE_PIT_1_INTERRUPT_INTR 3
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#define XIN_IOMODULE_UART_RX_INTERRUPT_INTR 2
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#define XIN_IOMODULE_UART_TX_INTERRUPT_INTR 1
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#define XIN_IOMODULE_UART_ERROR_INTERRUPT_INTR 0
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#define XIN_IOMODULE_EXTERNAL_INTERRUPT_INTR 16
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/* @} */
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/**
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* @name Control Status Register Bit Definitions
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* Control Status Register bit masks
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* Used to configure the timer counter device.
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* @{
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*/
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#define XTC_CSR_ENABLE_TMR_MASK 0x00000001 /**< Enables the timer */
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#define XTC_CSR_AUTO_RELOAD_MASK 0x00000002 /**< In compare mode,
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configures the timer
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reload from the Load
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Register. The default
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mode causes the timer
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counter to hold when it
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rolls under. */
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/* @} */
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/**************************** Type Definitions *******************************/
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/* The following data type defines each entry in an interrupt vector table.
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* The callback reference is the base address of the interrupting device
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* for the driver interface given in this file and an instance pointer for the
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* driver interface given in xintc.h file.
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*/
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typedef struct {
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XInterruptHandler Handler;
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void *CallBackRef;
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} XIOModule_VectorTableEntry;
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typedef void (*XFastInterruptHandler) (void);
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/***************** Macros (Inline Functions) Definitions *********************/
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/****************************************************************************/
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/**
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*
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* Enable specific interrupt(s) in the interrupt controller.
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*
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* @param BaseAddress is the base address of the device
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* @param EnableMask is the 32-bit value to write to the enable register.
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* Each bit of the mask corresponds to an interrupt input signal
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* that is connected to the interrupt controller (INT0 = LSB).
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* Only the bits which are set in the mask will enable interrupts.
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*
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* @return None.
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*
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* @note C-style signature:
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* void XIOModule_EnableIntr(u32 BaseAddress, u32 EnableMask);
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*
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*****************************************************************************/
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#define XIOModule_EnableIntr(BaseAddress, EnableMask) \
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XIomodule_Out32((BaseAddress) + XIN_IER_OFFSET, (EnableMask))
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/****************************************************************************/
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/**
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*
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* Disable specific interrupt(s) in the interrupt controller.
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*
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* @param BaseAddress is the base address of the device
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* @param DisableMask is the 32-bit value to write to enable register.
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* Each bit of the mask corresponds to an interrupt input signal
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* that is connected to the interrupt controller (INT0 = LSB).
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* Only bits which are set in the mask will disable interrupts.
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*
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* @return None.
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*
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* @note C-style signature:
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* void XIOModule_DisableIntr(u32 BaseAddress, u32 DisableMask);
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*
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*****************************************************************************/
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#define XIOModule_DisableIntr(BaseAddress, DisableMask) \
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XIomodule_Out32((BaseAddress) + XIN_IER_OFFSET, ~(DisableMask))
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/****************************************************************************/
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/**
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*
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* Acknowledge specific interrupt(s) in the interrupt controller.
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*
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* @param BaseAddress is the base address of the device
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* @param AckMask is the 32-bit value to write to the acknowledge
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* register. Each bit of the mask corresponds to an interrupt
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* input signal that is connected to the interrupt controller
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* (INT0 = LSB). Only the bits which are set in the mask will
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* acknowledge interrupts.
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*
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* @return None.
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*
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* @note C-style signature:
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* void XIOModule_AckIntr(u32 BaseAddress, u32 AckMask);
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*
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*****************************************************************************/
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#define XIOModule_AckIntr(BaseAddress, AckMask) \
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XIomodule_Out32((BaseAddress) + XIN_IAR_OFFSET, (AckMask))
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/****************************************************************************/
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/**
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*
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* Get the interrupt status from the interrupt controller which indicates
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* which interrupts are active and enabled.
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*
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* @param BaseAddress is the base address of the device
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*
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* @return The 32-bit contents of the interrupt status register. Each bit
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* corresponds to an interrupt input signal that is connected to
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* the interrupt controller (INT0 = LSB). Bits which are set
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* indicate an active interrupt which is also enabled.
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*
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* @note C-style signature:
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* u32 XIOModule_GetIntrStatus(u32 BaseAddress);
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*
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*****************************************************************************/
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#define XIOModule_GetIntrStatus(BaseAddress) \
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(XIomodule_In32((BaseAddress) + XIN_IPR_OFFSET))
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/****************************************************************************/
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/**
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*
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* Get the contents of the UART status register. Use the XUL_SR_* constants
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* defined above to interpret the bit-mask returned.
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*
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* @param BaseAddress is the base address of the device
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*
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* @return A 32-bit value representing the contents of the status
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* register.
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*
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* @note C-style Signature:
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* u32 XIOModule_GetStatusReg(u32 BaseAddress);
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*
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*****************************************************************************/
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#define XIOModule_GetStatusReg(BaseAddress) \
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XIomodule_In32((BaseAddress) + XUL_STATUS_REG_OFFSET)
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/****************************************************************************/
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/**
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*
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* Check to see if the UART receiver has data.
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*
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* @param BaseAddress is the base address of the device
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*
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* @return TRUE if the receiver is empty, FALSE if there is data present.
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*
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* @note C-style Signature:
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* int XIOModule_IsReceiveEmpty(u32 BaseAddress);
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*
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*****************************************************************************/
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#define XIOModule_IsReceiveEmpty(BaseAddress) \
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((XIOModule_GetStatusReg((BaseAddress)) & XUL_SR_RX_FIFO_VALID_DATA) != \
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XUL_SR_RX_FIFO_VALID_DATA)
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/****************************************************************************/
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/**
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*
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* Check to see if the transmitter is full.
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*
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* @param BaseAddress is the base address of the device
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*
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* @return TRUE if the transmitter is full, FALSE otherwise.
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*
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* @note C-style Signature:
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* int XIOModule_IsTransmitFull(u32 BaseAddress);
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*
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*****************************************************************************/
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#define XIOModule_IsTransmitFull(BaseAddress) \
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((XIOModule_GetStatusReg((BaseAddress)) & XUL_SR_TX_FIFO_FULL) == \
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XUL_SR_TX_FIFO_FULL)
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/****************************************************************************/
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/**
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*
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* Write a value to a GPO register. A 32 bit write is performed. If the
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* GPO component is implemented in a smaller width, only the least
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* significant data is written.
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*
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* @param BaseAddress is the base address of the GPO device.
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* @param RegOffset is the register offset from the base to write to.
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* @param Data is the data written to the register.
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*
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* @return None.
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*
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* @note C-style signature:
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* void XIOModule_WriteReg(u32 BaseAddress,
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* unsigned RegOffset, u32 Data)
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*
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****************************************************************************/
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#define XIOModule_WriteReg(BaseAddress, RegOffset, Data) \
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XIomodule_Out32((BaseAddress) + (RegOffset), (u32)(Data))
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/****************************************************************************/
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/**
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*
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* Read a value from a GPI register. A 32 bit read is performed. If the
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* GPI component is implemented in a smaller width, only the least
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* significant data is read from the register. The most significant data
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* will be read as 0.
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*
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* @param BaseAddress is the base address of the GPI device.
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* @param RegOffset is the register offset from the base to read from.
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*
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* @return Data read from the register.
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*
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* @note C-style signature:
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* u32 XIOModule_ReadReg(u32 BaseAddress, unsigned RegOffset)
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*
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******************************************************************************/
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#define XIOModule_ReadReg(BaseAddress, RegOffset) \
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XIomodule_In32((BaseAddress) + (RegOffset))
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/************************** Function Prototypes ******************************/
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/*
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* UART standard in and standard out handlers, to be connected to generic
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* I/O handling code.
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*/
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void XIOModule_SendByte(u32 BaseAddress, u8 Data);
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u8 XIOModule_RecvByte(u32 BaseAddress);
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/*
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* Interrupt controller handlers, to be connected to processor exception
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* handling code.
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*/
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void XIOModule_LowLevelInterruptHandler(void);
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void XIOModule_DeviceInterruptHandler(void *DeviceId);
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/* Various configuration functions */
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void XIOModule_SetIntrSvcOption(u32 BaseAddress, int Option);
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void XIOModule_RegisterHandler(u32 BaseAddress,
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int InterruptId,
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XInterruptHandler Handler,
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void *CallBackRef);
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/************************** Variable Definitions *****************************/
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#ifdef __cplusplus
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}
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#endif
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#endif /* end of protection macro */
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