39 lines
1.1 KiB
INI
39 lines
1.1 KiB
INI
#
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# Numato Mimas A7 Mini - Artix 7 FPGA Board
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#
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# https://numato.com/product/mimas-a7-mini-fpga-development-board
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#
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interface ftdi
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ftdi_device_desc "Mimas A7 Mini FPGA Module"
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ftdi_vid_pid 0x2a19 0x100e
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# channel 0 is for custom purpose by users (like uart, fifo etc)
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# channel 1 is reserved for JTAG (by-default) or SPI (possible via changing solder jumpers)
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ftdi_channel 1
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ftdi_tdo_sample_edge falling
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# FTDI Pin Layout
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#
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# +--------+-------+-------+-------+-------+-------+-------+-------+
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# | DBUS7 | DBUS6 | DBUS5 | DBUS4 | DBUS3 | DBUS2 | DBUS1 | DBUS0 |
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# +--------+-------+-------+-------+-------+-------+-------+-------+
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# | PROG_B | OE_N | NC | NC | TMS | TDO | TDI | TCK |
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# +--------+-------+-------+-------+-------+-------+-------+-------+
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#
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# OE_N is JTAG buffer output enable signal (active-low)
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# PROG_B is not used, so left as input to FTDI.
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#
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ftdi_layout_init 0x0008 0x004b
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reset_config none
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adapter_khz 30000
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source [find cpld/xilinx-xc7.cfg]
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source [find cpld/jtagspi.cfg]
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proc fpga_program {} {
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global _CHIPNAME
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xc7_program $_CHIPNAME.tap
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}
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