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28
software/LED_Controller_bsp/microblaze_mcs/libsrc/bram_v3_03_a/src/Makefile Normal file
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COMPILER=
ARCHIVER=
CP=cp
COMPILER_FLAGS=
EXTRA_COMPILER_FLAGS=
LIB=libxil.a
RELEASEDIR=../../../lib
INCLUDEDIR=../../../include
INCLUDES=-I./. -I${INCLUDEDIR}
INCLUDEFILES=*.h
LIBSOURCES=*.c
OUTS = *.o
libs:
echo "Compiling bram"
$(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES)
$(ARCHIVER) -r ${RELEASEDIR}/${LIB} $(OUTS)
make clean
include:
${CP} ${INCLUDEFILES} ${INCLUDEDIR}
clean:
rm -rf ${OUTS}

153
software/LED_Controller_bsp/microblaze_mcs/libsrc/bram_v3_03_a/src/xbram.c Normal file
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/******************************************************************************
*
* (c) Copyright 2010-2013 Xilinx, Inc. All rights reserved.
*
* This file contains confidential and proprietary information of Xilinx, Inc.
* and is protected under U.S. and international copyright and other
* intellectual property laws.
*
* DISCLAIMER
* This disclaimer is not a license and does not grant any rights to the
* materials distributed herewith. Except as otherwise provided in a valid
* license issued to you by Xilinx, and to the maximum extent permitted by
* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
* and (2) Xilinx shall not be liable (whether in contract or tort, including
* negligence, or under any other theory of liability) for any loss or damage
* of any kind or nature related to, arising under or in connection with these
* materials, including for any direct, or any indirect, special, incidental,
* or consequential loss or damage (including loss of data, profits, goodwill,
* or any type of loss or damage suffered as a result of any action brought by
* a third party) even if such damage or loss was reasonably foreseeable or
* Xilinx had been advised of the possibility of the same.
*
* CRITICAL APPLICATIONS
* Xilinx products are not designed or intended to be fail-safe, or for use in
* any application requiring fail-safe performance, such as life-support or
* safety devices or systems, Class III medical devices, nuclear facilities,
* applications related to the deployment of airbags, or any other applications
* that could lead to death, personal injury, or severe property or
* environmental damage (individually and collectively, "Critical
* Applications"). Customer assumes the sole risk and liability of any use of
* Xilinx products in Critical Applications, subject only to applicable laws
* and regulations governing limitations on product liability.
*
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
* AT ALL TIMES.
*
******************************************************************************/
/**
* @file xbram.c
*
* The implementation of the XBram driver's basic functionality.
* See xbram.h for more information about the driver.
*
* @note
*
* None
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.00a sa 05/11/10 First release
* 3.01a sa 13/01/12 Added CorrectableFailingDataRegs and
* UncorrectableFailingDataRegs in
* XBram_CfgInitialize API.
*</pre>
*
*****************************************************************************/
/***************************** Include Files ********************************/
#include "xbram.h"
#include "xstatus.h"
/************************** Constant Definitions ****************************/
/**************************** Type Definitions ******************************/
/***************** Macros (Inline Functions) Definitions ********************/
/************************** Variable Definitions ****************************/
/************************** Function Prototypes *****************************/
/****************************************************************************/
/**
* Initialize the XBram instance provided by the caller based on the given
* configuration data.
*
* Nothing is done except to initialize the InstancePtr.
*
* @param InstancePtr is a pointer to an XBram instance.
* The memory the pointer references must be pre-allocated by
* the caller. Further calls to manipulate the driver through
* the XBram API must be made with this pointer.
* @param Config is a reference to a structure containing information
* about a specific BRAM device. This function
* initializes an InstancePtr object for a specific device
* specified by the contents of Config. This function can
* initialize multiple instance objects with the use of multiple
* calls giving different Config information on each call.
* @param EffectiveAddr is the device base address in the virtual memory
* address space. The caller is responsible for keeping the
* address mapping from EffectiveAddr to the device physical base
* address unchanged once this function is invoked. Unexpected
* errors may occur if the address mapping changes after this
* function is called. If address translation is not used, use
* Config->BaseAddress for this parameters, passing the physical
* address instead.
*
* @return
* - XST_SUCCESS Initialization was successful.
*
* @note None.
*
*****************************************************************************/
int XBram_CfgInitialize(XBram *InstancePtr,
XBram_Config *Config,
u32 EffectiveAddr)
{
/*
* Assert arguments
*/
Xil_AssertNonvoid(InstancePtr != NULL);
/*
* Set some default values.
*/
InstancePtr->Config.CtrlBaseAddress = EffectiveAddr;
InstancePtr->Config.MemBaseAddress = Config->MemBaseAddress;
InstancePtr->Config.MemHighAddress = Config->MemHighAddress;
InstancePtr->Config.DataWidth = Config->DataWidth;
InstancePtr->Config.EccPresent = Config->EccPresent;
InstancePtr->Config.FaultInjectionPresent =
Config->FaultInjectionPresent;
InstancePtr->Config.CorrectableFailingRegisters =
Config->CorrectableFailingRegisters;
InstancePtr->Config.CorrectableFailingDataRegs =
Config->CorrectableFailingDataRegs;
InstancePtr->Config.UncorrectableFailingRegisters =
Config->UncorrectableFailingRegisters;
InstancePtr->Config.UncorrectableFailingDataRegs =
Config->UncorrectableFailingDataRegs;
InstancePtr->Config.EccStatusInterruptPresent =
Config->EccStatusInterruptPresent;
InstancePtr->Config.CorrectableCounterBits =
Config->CorrectableCounterBits;
InstancePtr->Config.WriteAccess = Config->WriteAccess;
/*
* Indicate the instance is now ready to use, initialized without error
*/
InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
return (XST_SUCCESS);
}

218
software/LED_Controller_bsp/microblaze_mcs/libsrc/bram_v3_03_a/src/xbram.h Executable file
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/******************************************************************************
*
* (c) Copyright 2006-2013 Xilinx, Inc. All rights reserved.
*
* This file contains confidential and proprietary information of Xilinx, Inc.
* and is protected under U.S. and international copyright and other
* intellectual property laws.
*
* DISCLAIMER
* This disclaimer is not a license and does not grant any rights to the
* materials distributed herewith. Except as otherwise provided in a valid
* license issued to you by Xilinx, and to the maximum extent permitted by
* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
* and (2) Xilinx shall not be liable (whether in contract or tort, including
* negligence, or under any other theory of liability) for any loss or damage
* of any kind or nature related to, arising under or in connection with these
* materials, including for any direct, or any indirect, special, incidental,
* or consequential loss or damage (including loss of data, profits, goodwill,
* or any type of loss or damage suffered as a result of any action brought by
* a third party) even if such damage or loss was reasonably foreseeable or
* Xilinx had been advised of the possibility of the same.
*
* CRITICAL APPLICATIONS
* Xilinx products are not designed or intended to be fail-safe, or for use in
* any application requiring fail-safe performance, such as life-support or
* safety devices or systems, Class III medical devices, nuclear facilities,
* applications related to the deployment of airbags, or any other applications
* that could lead to death, personal injury, or severe property or
* environmental damage (individually and collectively, "Critical
* Applications"). Customer assumes the sole risk and liability of any use of
* Xilinx products in Critical Applications, subject only to applicable laws
* and regulations governing limitations on product liability.
*
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
* AT ALL TIMES.
*
******************************************************************************/
/*****************************************************************************/
/**
* @file xbram.h
*
* If ECC is not enabled, this driver exists only to allow the tools to
* create a memory test application and to populate xparameters.h with memory
* range constants. In this case there is no source code.
*
* If ECC is enabled, this file contains the software API definition of the
* Xilinx BRAM Interface Controller (XBram) device driver.
*
* The Xilinx BRAM controller is a soft IP core designed for Xilinx
* FPGAs and contains the following general features:
* - LMB v2.0 bus interfaces with byte enable support
* - Used in conjunction with bram_block peripheral to provide fast BRAM
* memory solution for MicroBlaze ILMB and DLMB ports
* - Supports byte, half-word, and word transfers
* - Supports optional BRAM error correction and detection.
*
* The driver provides interrupt management functions. Implementation of
* interrupt handlers is left to the user. Refer to the provided interrupt
* example in the examples directory for details.
*
* This driver is intended to be RTOS and processor independent. Any needs for
* dynamic memory management, threads or thread mutual exclusion, virtual
* memory, or cache control must be satisfied by the layer above this driver.
*
* <b>Initialization & Configuration</b>
*
* The XBram_Config structure is used by the driver to configure
* itself. This configuration structure is typically created by the tool-chain
* based on HW build properties.
*
* To support multiple runtime loading and initialization strategies employed
* by various operating systems, the driver instance can be initialized as
* follows:
*
* - XBram_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr) -
* Uses a configuration structure provided by the caller. If running in a
* system with address translation, the provided virtual memory base address
* replaces the physical address present in the configuration structure.
*
* @note
*
* This API utilizes 32 bit I/O to the BRAM registers. With less
* than 32 bits, the unused bits from registers are read as zero and written as
* don't cares.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 3.00a sa 05/11/10 Added ECC support
* 3.01a sa 01/13/12 Changed Selftest API from
* XBram_SelfTest(XBram *InstancePtr) to
* XBram_SelfTest(XBram *InstancePtr, u8 IntMask) and
* fixed a problem with interrupt generation for CR 639274
* Modified Selftest example to return XST_SUCCESS when
* ECC is not enabled and return XST_FAILURE when ECC is
* enabled and Control Base Address is zero (CR 636581)
* Modified Selftest to use correct CorrectableCounterBits
* for CR 635655
* Updated to check CorrectableFailingDataRegs in the case
* of LMB BRAM.
* Added CorrectableFailingDataRegs and
* UncorrectableFailingDataRegs to the config structure to
* distinguish between AXI BRAM and LMB BRAM.
* These registers are not present in the current version of
* the AXI BRAM Controller.
* 3.02a sa 04/16/12 Added test of byte and halfword read-modify-write
* 3.02a sa 04/16/12 Modified driver tcl to sort the address parameters
* to support both xps and vivado designs.
* 3.02a adk 24/4/13 Modified the tcl file to avoid warnings
* when ecc is disabled cr:705002.
* 3.03a bss 05/22/13 Added Xil_DCacheFlushRange in xbram_selftest.c to
* flush the Cache after writing to BRAM in InjectErrors
* API(CR #719011)
* </pre>
*****************************************************************************/
#ifndef XBRAM_H /* prevent circular inclusions */
#define XBRAM_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files ********************************/
#include "xil_types.h"
#include "xil_assert.h"
#include "xstatus.h"
#include "xbram_hw.h"
/************************** Constant Definitions ****************************/
/**************************** Type Definitions ******************************/
/**
* This typedef contains configuration information for the device.
*/
typedef struct {
u16 DeviceId; /**< Unique ID of device */
u32 DataWidth; /**< BRAM data width */
int EccPresent; /**< Is ECC supported in H/W */
int FaultInjectionPresent; /**< Is Fault Injection
* supported in H/W */
int CorrectableFailingRegisters; /**< Is Correctable Failing Registers
* supported in H/W */
int CorrectableFailingDataRegs; /**< Is Correctable Failing Data
* Registers supported in H/W */
int UncorrectableFailingRegisters; /**< Is Un-correctable Failing
* Registers supported in H/W */
int UncorrectableFailingDataRegs; /**< Is Un-correctable Failing Data
* Registers supported in H/W */
int EccStatusInterruptPresent; /**< Are ECC status and interrupts
* supported in H/W */
int CorrectableCounterBits; /**< Number of bits in the
* Correctable Error Counter */
int EccOnOffRegister; /**< Is ECC on/off register supported
* in h/w */
int EccOnOffResetValue; /**< Reset value of the ECC on/off
* register in h/w */
int WriteAccess; /**< Is write access enabled in
* h/w */
u32 MemBaseAddress; /**< Device memory base address */
u32 MemHighAddress; /**< Device memory high address */
u32 CtrlBaseAddress; /**< Device register base address.*/
u32 CtrlHighAddress; /**< Device register base address.*/
} XBram_Config;
/**
* The XBram driver instance data. The user is required to
* allocate a variable of this type for every BRAM device in the
* system. A pointer to a variable of this type is then passed to the driver
* API functions.
*/
typedef struct {
XBram_Config Config; /* BRAM config structure */
u32 IsReady; /* Device is initialized and ready */
} XBram;
/***************** Macros (Inline Functions) Definitions ********************/
/************************** Function Prototypes *****************************/
/*
* Functions in xbram_sinit.c
*/
XBram_Config *XBram_LookupConfig(u16 DeviceId);
/*
* Functions implemented in xbram.c
*/
int XBram_CfgInitialize(XBram *InstancePtr, XBram_Config *Config,
u32 EffectiveAddr);
/*
* Functions implemented in xbram_selftest.c
*/
int XBram_SelfTest(XBram *InstancePtr, u8 IntMask);
/*
* Functions implemented in xbram_intr.c
*/
void XBram_InterruptEnable(XBram *InstancePtr, u32 Mask);
void XBram_InterruptDisable(XBram *InstancePtr, u32 Mask);
void XBram_InterruptClear(XBram *InstancePtr, u32 Mask);
u32 XBram_InterruptGetEnabled(XBram *InstancePtr);
u32 XBram_InterruptGetStatus(XBram *InstancePtr);
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */

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software/LED_Controller_bsp/microblaze_mcs/libsrc/bram_v3_03_a/src/xbram_g.c Normal file
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/*******************************************************************
*
* CAUTION: This file is automatically generated by libgen.
* Version: Xilinx EDK 14.7 EDK_P.20131013
* DO NOT EDIT.
*
* Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
*
* Description: Driver configuration
*
*******************************************************************/
#include "xparameters.h"
#include "xbram.h"
/*
* The configuration table for devices
*/
XBram_Config XBram_ConfigTable[] =
{
{
XPAR_DLMB_CNTLR_DEVICE_ID,
XPAR_DLMB_CNTLR_DATA_WIDTH,
XPAR_DLMB_CNTLR_ECC,
XPAR_DLMB_CNTLR_FAULT_INJECT,
XPAR_DLMB_CNTLR_CE_FAILING_REGISTERS,
XPAR_DLMB_CNTLR_CE_FAILING_REGISTERS,
XPAR_DLMB_CNTLR_UE_FAILING_REGISTERS,
XPAR_DLMB_CNTLR_UE_FAILING_REGISTERS,
XPAR_DLMB_CNTLR_ECC_STATUS_REGISTERS,
XPAR_DLMB_CNTLR_CE_COUNTER_WIDTH,
XPAR_DLMB_CNTLR_ECC_ONOFF_REGISTER,
XPAR_DLMB_CNTLR_ECC_ONOFF_RESET_VALUE,
XPAR_DLMB_CNTLR_WRITE_ACCESS,
XPAR_DLMB_CNTLR_BASEADDR,
XPAR_DLMB_CNTLR_HIGHADDR,
XPAR_DLMB_CNTLR_S_AXI_CTRL_BASEADDR,
XPAR_DLMB_CNTLR_S_AXI_CTRL_HIGHADDR
},
{
XPAR_ILMB_CNTLR_DEVICE_ID,
XPAR_ILMB_CNTLR_DATA_WIDTH,
XPAR_ILMB_CNTLR_ECC,
XPAR_ILMB_CNTLR_FAULT_INJECT,
XPAR_ILMB_CNTLR_CE_FAILING_REGISTERS,
XPAR_ILMB_CNTLR_CE_FAILING_REGISTERS,
XPAR_ILMB_CNTLR_UE_FAILING_REGISTERS,
XPAR_ILMB_CNTLR_UE_FAILING_REGISTERS,
XPAR_ILMB_CNTLR_ECC_STATUS_REGISTERS,
XPAR_ILMB_CNTLR_CE_COUNTER_WIDTH,
XPAR_ILMB_CNTLR_ECC_ONOFF_REGISTER,
XPAR_ILMB_CNTLR_ECC_ONOFF_RESET_VALUE,
XPAR_ILMB_CNTLR_WRITE_ACCESS,
XPAR_ILMB_CNTLR_BASEADDR,
XPAR_ILMB_CNTLR_HIGHADDR,
XPAR_ILMB_CNTLR_S_AXI_CTRL_BASEADDR,
XPAR_ILMB_CNTLR_S_AXI_CTRL_HIGHADDR
}
};

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software/LED_Controller_bsp/microblaze_mcs/libsrc/bram_v3_03_a/src/xbram_hw.h Normal file
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/******************************************************************************
*
* (c) Copyright 2011-2013 Xilinx, Inc. All rights reserved.
*
* This file contains confidential and proprietary information of Xilinx, Inc.
* and is protected under U.S. and international copyright and other
* intellectual property laws.
*
* DISCLAIMER
* This disclaimer is not a license and does not grant any rights to the
* materials distributed herewith. Except as otherwise provided in a valid
* license issued to you by Xilinx, and to the maximum extent permitted by
* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
* and (2) Xilinx shall not be liable (whether in contract or tort, including
* negligence, or under any other theory of liability) for any loss or damage
* of any kind or nature related to, arising under or in connection with these
* materials, including for any direct, or any indirect, special, incidental,
* or consequential loss or damage (including loss of data, profits, goodwill,
* or any type of loss or damage suffered as a result of any action brought by
* a third party) even if such damage or loss was reasonably foreseeable or
* Xilinx had been advised of the possibility of the same.
*
* CRITICAL APPLICATIONS
* Xilinx products are not designed or intended to be fail-safe, or for use in
* any application requiring fail-safe performance, such as life-support or
* safety devices or systems, Class III medical devices, nuclear facilities,
* applications related to the deployment of airbags, or any other applications
* that could lead to death, personal injury, or severe property or
* environmental damage (individually and collectively, "Critical
* Applications"). Customer assumes the sole risk and liability of any use of
* Xilinx products in Critical Applications, subject only to applicable laws
* and regulations governing limitations on product liability.
*
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
* AT ALL TIMES.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xbram_hw.h
*
* This header file contains identifiers and driver functions (or
* macros) that can be used to access the device. The user should refer to the
* hardware device specification for more details of the device operation.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.00a sa 24/11/10 First release
* </pre>
*
******************************************************************************/
#ifndef XBRAM_HW_H /* prevent circular inclusions */
#define XBRAM_HW_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xil_types.h"
#include "xil_assert.h"
#include "xil_io.h"
/************************** Constant Definitions *****************************/
/** @name Registers
*
* Register offsets for this device.
* @{
*/
#define XBRAM_ECC_STATUS_OFFSET 0x0 /**< ECC status Register */
#define XBRAM_ECC_EN_IRQ_OFFSET 0x4 /**< ECC interrupt enable Register */
#define XBRAM_ECC_ON_OFF_OFFSET 0x8 /**< ECC on/off register */
#define XBRAM_CE_CNT_OFFSET 0xC /**< Correctable error counter Register */
#define XBRAM_CE_FFD_0_OFFSET 0x100 /**< Correctable error first failing
* data Register, 31-0 */
#define XBRAM_CE_FFD_1_OFFSET 0x104 /**< Correctable error first failing
* data Register, 63-32 */
#define XBRAM_CE_FFD_2_OFFSET 0x108 /**< Correctable error first failing
* data Register, 95-64 */
#define XBRAM_CE_FFD_3_OFFSET 0x10C /**< Correctable error first failing
* data Register, 127-96 */
#define XBRAM_CE_FFD_4_OFFSET 0x110 /**< Correctable error first failing
* data Register, 159-128 */
#define XBRAM_CE_FFD_5_OFFSET 0x114 /**< Correctable error first failing
* data Register, 191-160 */
#define XBRAM_CE_FFD_6_OFFSET 0x118 /**< Correctable error first failing
* data Register, 223-192 */
#define XBRAM_CE_FFD_7_OFFSET 0x11C /**< Correctable error first failing
* data Register, 255-224 */
#define XBRAM_CE_FFD_8_OFFSET 0x120 /**< Correctable error first failing
* data Register, 287-256 */
#define XBRAM_CE_FFD_9_OFFSET 0x124 /**< Correctable error first failing
* data Register, 319-288 */
#define XBRAM_CE_FFD_10_OFFSET 0x128 /**< Correctable error first failing
* data Register, 351-320 */
#define XBRAM_CE_FFD_11_OFFSET 0x12C /**< Correctable error first failing
* data Register, 383-352 */
#define XBRAM_CE_FFD_12_OFFSET 0x130 /**< Correctable error first failing
* data Register, 415-384 */
#define XBRAM_CE_FFD_13_OFFSET 0x134 /**< Correctable error first failing
* data Register, 447-416 */
#define XBRAM_CE_FFD_14_OFFSET 0x138 /**< Correctable error first failing
* data Register, 479-448 */
#define XBRAM_CE_FFD_15_OFFSET 0x13C /**< Correctable error first failing
* data Register, 511-480 */
#define XBRAM_CE_FFD_16_OFFSET 0x140 /**< Correctable error first failing
* data Register, 543-512 */
#define XBRAM_CE_FFD_17_OFFSET 0x144 /**< Correctable error first failing
* data Register, 575-544 */
#define XBRAM_CE_FFD_18_OFFSET 0x148 /**< Correctable error first failing
* data Register, 607-576 */
#define XBRAM_CE_FFD_19_OFFSET 0x14C /**< Correctable error first failing
* data Register, 639-608 */
#define XBRAM_CE_FFD_20_OFFSET 0x150 /**< Correctable error first failing
* data Register, 671-640 */
#define XBRAM_CE_FFD_21_OFFSET 0x154 /**< Correctable error first failing
* data Register, 703-672 */
#define XBRAM_CE_FFD_22_OFFSET 0x158 /**< Correctable error first failing
* data Register, 735-704 */
#define XBRAM_CE_FFD_23_OFFSET 0x15C /**< Correctable error first failing
* data Register, 767-736 */
#define XBRAM_CE_FFD_24_OFFSET 0x160 /**< Correctable error first failing
* data Register, 799-768 */
#define XBRAM_CE_FFD_25_OFFSET 0x164 /**< Correctable error first failing
* data Register, 831-800 */
#define XBRAM_CE_FFD_26_OFFSET 0x168 /**< Correctable error first failing
* data Register, 863-832 */
#define XBRAM_CE_FFD_27_OFFSET 0x16C /**< Correctable error first failing
* data Register, 895-864 */
#define XBRAM_CE_FFD_28_OFFSET 0x170 /**< Correctable error first failing
* data Register, 927-896 */
#define XBRAM_CE_FFD_29_OFFSET 0x174 /**< Correctable error first failing
* data Register, 959-928 */
#define XBRAM_CE_FFD_30_OFFSET 0x178 /**< Correctable error first failing
* data Register, 991-960 */
#define XBRAM_CE_FFD_31_OFFSET 0x17C /**< Correctable error first failing
* data Register, 1023-992 */
#define XBRAM_CE_FFE_0_OFFSET 0x180 /**< Correctable error first failing
* ECC Register, 31-0 */
#define XBRAM_CE_FFE_1_OFFSET 0x184 /**< Correctable error first failing
* ECC Register, 63-32 */
#define XBRAM_CE_FFE_2_OFFSET 0x188 /**< Correctable error first failing
* ECC Register, 95-64 */
#define XBRAM_CE_FFE_3_OFFSET 0x18C /**< Correctable error first failing
* ECC Register, 127-96 */
#define XBRAM_CE_FFE_4_OFFSET 0x190 /**< Correctable error first failing
* ECC Register, 159-128 */
#define XBRAM_CE_FFE_5_OFFSET 0x194 /**< Correctable error first failing
* ECC Register, 191-160 */
#define XBRAM_CE_FFE_6_OFFSET 0x198 /**< Correctable error first failing
* ECC Register, 223-192 */
#define XBRAM_CE_FFE_7_OFFSET 0x19C /**< Correctable error first failing
* ECC Register, 255-224 */
#define XBRAM_CE_FFA_0_OFFSET 0x1C0 /**< Correctable error first failing
* address Register 31-0 */
#define XBRAM_CE_FFA_1_OFFSET 0x1C4 /**< Correctable error first failing
* address Register 63-32 */
#define XBRAM_UE_FFD_0_OFFSET 0x200 /**< Uncorrectable error first failing
* data Register, 31-0 */
#define XBRAM_UE_FFD_1_OFFSET 0x204 /**< Uncorrectable error first failing
* data Register, 63-32 */
#define XBRAM_UE_FFD_2_OFFSET 0x208 /**< Uncorrectable error first failing
* data Register, 95-64 */
#define XBRAM_UE_FFD_3_OFFSET 0x20C /**< Uncorrectable error first failing
* data Register, 127-96 */
#define XBRAM_UE_FFD_4_OFFSET 0x210 /**< Uncorrectable error first failing
* data Register, 159-128 */
#define XBRAM_UE_FFD_5_OFFSET 0x214 /**< Uncorrectable error first failing
* data Register, 191-160 */
#define XBRAM_UE_FFD_6_OFFSET 0x218 /**< Uncorrectable error first failing
* data Register, 223-192 */
#define XBRAM_UE_FFD_7_OFFSET 0x21C /**< Uncorrectable error first failing
* data Register, 255-224 */
#define XBRAM_UE_FFD_8_OFFSET 0x220 /**< Uncorrectable error first failing
* data Register, 287-256 */
#define XBRAM_UE_FFD_9_OFFSET 0x224 /**< Uncorrectable error first failing
* data Register, 319-288 */
#define XBRAM_UE_FFD_10_OFFSET 0x228 /**< Uncorrectable error first failing
* data Register, 351-320 */
#define XBRAM_UE_FFD_11_OFFSET 0x22C /**< Uncorrectable error first failing
* data Register, 383-352 */
#define XBRAM_UE_FFD_12_OFFSET 0x230 /**< Uncorrectable error first failing
* data Register, 415-384 */
#define XBRAM_UE_FFD_13_OFFSET 0x234 /**< Uncorrectable error first failing
* data Register, 447-416 */
#define XBRAM_UE_FFD_14_OFFSET 0x238 /**< Uncorrectable error first failing
* data Register, 479-448 */
#define XBRAM_UE_FFD_15_OFFSET 0x23C /**< Uncorrectable error first failing
* data Register, 511-480 */
#define XBRAM_UE_FFD_16_OFFSET 0x240 /**< Uncorrectable error first failing
* data Register, 543-512 */
#define XBRAM_UE_FFD_17_OFFSET 0x244 /**< Uncorrectable error first failing
* data Register, 575-544 */
#define XBRAM_UE_FFD_18_OFFSET 0x248 /**< Uncorrectable error first failing
* data Register, 607-576 */
#define XBRAM_UE_FFD_19_OFFSET 0x24C /**< Uncorrectable error first failing
* data Register, 639-608 */
#define XBRAM_UE_FFD_20_OFFSET 0x250 /**< Uncorrectable error first failing
* data Register, 671-640 */
#define XBRAM_UE_FFD_21_OFFSET 0x254 /**< Uncorrectable error first failing
* data Register, 703-672 */
#define XBRAM_UE_FFD_22_OFFSET 0x258 /**< Uncorrectable error first failing
* data Register, 735-704 */
#define XBRAM_UE_FFD_23_OFFSET 0x25C /**< Uncorrectable error first failing
* data Register, 767-736 */
#define XBRAM_UE_FFD_24_OFFSET 0x260 /**< Uncorrectable error first failing
* data Register, 799-768 */
#define XBRAM_UE_FFD_25_OFFSET 0x264 /**< Uncorrectable error first failing
* data Register, 831-800 */
#define XBRAM_UE_FFD_26_OFFSET 0x268 /**< Uncorrectable error first failing
* data Register, 863-832 */
#define XBRAM_UE_FFD_27_OFFSET 0x26C /**< Uncorrectable error first failing
* data Register, 895-864 */
#define XBRAM_UE_FFD_28_OFFSET 0x270 /**< Uncorrectable error first failing
* data Register, 927-896 */
#define XBRAM_UE_FFD_29_OFFSET 0x274 /**< Uncorrectable error first failing
* data Register, 959-928 */
#define XBRAM_UE_FFD_30_OFFSET 0x278 /**< Uncorrectable error first failing
* data Register, 991-960 */
#define XBRAM_UE_FFD_31_OFFSET 0x27C /**< Uncorrectable error first failing
* data Register, 1023-992 */
#define XBRAM_UE_FFE_0_OFFSET 0x280 /**< Uncorrectable error first failing
* ECC Register, 31-0 */
#define XBRAM_UE_FFE_1_OFFSET 0x284 /**< Uncorrectable error first failing
* ECC Register, 63-32 */
#define XBRAM_UE_FFE_2_OFFSET 0x288 /**< Uncorrectable error first failing
* ECC Register, 95-64 */
#define XBRAM_UE_FFE_3_OFFSET 0x28C /**< Uncorrectable error first failing
* ECC Register, 127-96 */
#define XBRAM_UE_FFE_4_OFFSET 0x290 /**< Uncorrectable error first failing
* ECC Register, 159-128 */
#define XBRAM_UE_FFE_5_OFFSET 0x294 /**< Uncorrectable error first failing
* ECC Register, 191-160 */
#define XBRAM_UE_FFE_6_OFFSET 0x298 /**< Uncorrectable error first failing
* ECC Register, 223-192 */
#define XBRAM_UE_FFE_7_OFFSET 0x29C /**< Uncorrectable error first failing
* ECC Register, 255-224 */
#define XBRAM_UE_FFA_0_OFFSET 0x2C0 /**< Uncorrectable error first failing
* address Register 31-0 */
#define XBRAM_UE_FFA_1_OFFSET 0x2C4 /**< Uncorrectable error first failing
* address Register 63-32 */
#define XBRAM_FI_D_0_OFFSET 0x300 /**< Fault injection Data Register,
* 31-0 */
#define XBRAM_FI_D_1_OFFSET 0x304 /**< Fault injection Data Register,
* 63-32 */
#define XBRAM_FI_D_2_OFFSET 0x308 /**< Fault injection Data Register,
* 95-64 */
#define XBRAM_FI_D_3_OFFSET 0x30C /**< Fault injection Data Register,
* 127-96 */
#define XBRAM_FI_D_4_OFFSET 0x310 /**< Fault injection Data Register,
* 159-128 */
#define XBRAM_FI_D_5_OFFSET 0x314 /**< Fault injection Data Register,
* 191-160 */
#define XBRAM_FI_D_6_OFFSET 0x318 /**< Fault injection Data Register,
* 223-192 */
#define XBRAM_FI_D_7_OFFSET 0x31C /**< Fault injection Data Register,
* 255-224 */
#define XBRAM_FI_D_8_OFFSET 0x320 /**< Fault injection Data Register,
* 287-256 */
#define XBRAM_FI_D_9_OFFSET 0x324 /**< Fault injection Data Register,
* 319-288 */
#define XBRAM_FI_D_10_OFFSET 0x328 /**< Fault injection Data Register,
* 351-320 */
#define XBRAM_FI_D_11_OFFSET 0x32C /**< Fault injection Data Register,
* 383-352 */
#define XBRAM_FI_D_12_OFFSET 0x330 /**< Fault injection Data Register,
* 415-384 */
#define XBRAM_FI_D_13_OFFSET 0x334 /**< Fault injection Data Register,
* 447-416 */
#define XBRAM_FI_D_14_OFFSET 0x338 /**< Fault injection Data Register,
* 479-448 */
#define XBRAM_FI_D_15_OFFSET 0x33C /**< Fault injection Data Register,
* 511-480 */
#define XBRAM_FI_D_16_OFFSET 0x340 /**< Fault injection Data Register,
* 543-512 */
#define XBRAM_FI_D_17_OFFSET 0x344 /**< Fault injection Data Register,
* 575-544 */
#define XBRAM_FI_D_18_OFFSET 0x348 /**< Fault injection Data Register,
* 607-576 */
#define XBRAM_FI_D_19_OFFSET 0x34C /**< Fault injection Data Register,
* 639-608 */
#define XBRAM_FI_D_20_OFFSET 0x350 /**< Fault injection Data Register,
* 671-640 */
#define XBRAM_FI_D_21_OFFSET 0x354 /**< Fault injection Data Register,
* 703-672 */
#define XBRAM_FI_D_22_OFFSET 0x358 /**< Fault injection Data Register,
* 735-704 */
#define XBRAM_FI_D_23_OFFSET 0x35C /**< Fault injection Data Register,
* 767-736 */
#define XBRAM_FI_D_24_OFFSET 0x360 /**< Fault injection Data Register,
* 799-768 */
#define XBRAM_FI_D_25_OFFSET 0x364 /**< Fault injection Data Register,
* 831-800 */
#define XBRAM_FI_D_26_OFFSET 0x368 /**< Fault injection Data Register,
* 863-832 */
#define XBRAM_FI_D_27_OFFSET 0x36C /**< Fault injection Data Register,
* 895-864 */
#define XBRAM_FI_D_28_OFFSET 0x370 /**< Fault injection Data Register,
* 927-896 */
#define XBRAM_FI_D_29_OFFSET 0x374 /**< Fault injection Data Register,
* 959-928 */
#define XBRAM_FI_D_30_OFFSET 0x378 /**< Fault injection Data Register,
* 991-960 */
#define XBRAM_FI_D_31_OFFSET 0x37C /**< Fault injection Data Register,
* 1023-992 */
#define XBRAM_FI_ECC_0_OFFSET 0x380 /**< Fault injection ECC Register,
* 31-0 */
#define XBRAM_FI_ECC_1_OFFSET 0x384 /**< Fault injection ECC Register,
* 63-32 */
#define XBRAM_FI_ECC_2_OFFSET 0x388 /**< Fault injection ECC Register,
* 95-64 */
#define XBRAM_FI_ECC_3_OFFSET 0x38C /**< Fault injection ECC Register,
* 127-96 */
#define XBRAM_FI_ECC_4_OFFSET 0x390 /**< Fault injection ECC Register,
* 159-128 */
#define XBRAM_FI_ECC_5_OFFSET 0x394 /**< Fault injection ECC Register,
* 191-160 */
#define XBRAM_FI_ECC_6_OFFSET 0x398 /**< Fault injection ECC Register,
* 223-192 */
#define XBRAM_FI_ECC_7_OFFSET 0x39C /**< Fault injection ECC Register,
* 255-224 */
/* @} */
/** @name Interrupt Status and Enable Register bitmaps and masks
*
* Bit definitions for the ECC status register and ECC interrupt enable register.
* @{
*/
#define XBRAM_IR_CE_MASK 0x2 /**< Mask for the correctable error */
#define XBRAM_IR_UE_MASK 0x1 /**< Mask for the uncorrectable error */
#define XBRAM_IR_ALL_MASK 0x3 /**< Mask of all bits */
/*@}*/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
#define XBram_In32 Xil_In32
#define XBram_Out32 Xil_Out32
#define XBram_In16 Xil_In16
#define XBram_Out16 Xil_Out16
#define XBram_In8 Xil_In8
#define XBram_Out8 Xil_Out8
/****************************************************************************/
/**
*
* Write a value to a BRAM register. A 32 bit write is performed.
*
* @param BaseAddress is the base address of the BRAM device register.
* @param RegOffset is the register offset from the base to write to.
* @param Data is the data written to the register.
*
* @return None.
*
* @note C-style signature:
* void XBram_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)
*
****************************************************************************/
#define XBram_WriteReg(BaseAddress, RegOffset, Data) \
XBram_Out32((BaseAddress) + (RegOffset), (u32)(Data))
/****************************************************************************/
/**
*
* Read a value from a BRAM register. A 32 bit read is performed.
*
* @param BaseAddress is the base address of the BRAM device registers.
* @param RegOffset is the register offset from the base to read from.
*
* @return Data read from the register.
*
* @note C-style signature:
* u32 XBram_ReadReg(u32 BaseAddress, u32 RegOffset)
*
****************************************************************************/
#define XBram_ReadReg(BaseAddress, RegOffset) \
XBram_In32((BaseAddress) + (RegOffset))
/************************** Function Prototypes ******************************/
/************************** Variable Definitions *****************************/
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */

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/******************************************************************************
*
* (c) Copyright 2010-2013 Xilinx, Inc. All rights reserved.
*
* This file contains confidential and proprietary information of Xilinx, Inc.
* and is protected under U.S. and international copyright and other
* intellectual property laws.
*
* DISCLAIMER
* This disclaimer is not a license and does not grant any rights to the
* materials distributed herewith. Except as otherwise provided in a valid
* license issued to you by Xilinx, and to the maximum extent permitted by
* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
* and (2) Xilinx shall not be liable (whether in contract or tort, including
* negligence, or under any other theory of liability) for any loss or damage
* of any kind or nature related to, arising under or in connection with these
* materials, including for any direct, or any indirect, special, incidental,
* or consequential loss or damage (including loss of data, profits, goodwill,
* or any type of loss or damage suffered as a result of any action brought by
* a third party) even if such damage or loss was reasonably foreseeable or
* Xilinx had been advised of the possibility of the same.
*
* CRITICAL APPLICATIONS
* Xilinx products are not designed or intended to be fail-safe, or for use in
* any application requiring fail-safe performance, such as life-support or
* safety devices or systems, Class III medical devices, nuclear facilities,
* applications related to the deployment of airbags, or any other applications
* that could lead to death, personal injury, or severe property or
* environmental damage (individually and collectively, "Critical
* Applications"). Customer assumes the sole risk and liability of any use of
* Xilinx products in Critical Applications, subject only to applicable laws
* and regulations governing limitations on product liability.
*
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
* AT ALL TIMES.
*
******************************************************************************/
/*****************************************************************************/
/**
* @file xbram_intr.c
*
* Implements BRAM interrupt processing functions for the
* XBram driver. See xbram.h for more information
* about the driver.
*
* The functions in this file require the hardware device to be built with
* interrupt capabilities. The functions will assert if called using hardware
* that does not have interrupt capabilities.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.00a sa 05/11/10 Initial release
* </pre>
*
*****************************************************************************/
/***************************** Include Files ********************************/
#include "xbram.h"
/************************** Constant Definitions ****************************/
/**************************** Type Definitions ******************************/
/***************** Macros (Inline Functions) Definitions ********************/
/************************** Variable Definitions ****************************/
/************************** Function Prototypes *****************************/
/****************************************************************************/
/**
* Enable interrupts. This function will assert if the hardware device has not
* been built with interrupt capabilities.
*
* @param InstancePtr is the BRAM instance to operate on.
* @param Mask is the mask to enable. Bit positions of 1 are enabled.
* This mask is formed by OR'ing bits from XBRAM_IR*
* bits which are contained in xbram_hw.h.
*
* @return None.
*
* @note None.
*
*****************************************************************************/
void XBram_InterruptEnable(XBram *InstancePtr, u32 Mask)
{
u32 Register;
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Xil_AssertVoid(InstancePtr->Config.CtrlBaseAddress != 0);
/*
* Read the interrupt enable register and only enable the specified
* interrupts without disabling or enabling any others.
*/
Register = XBram_ReadReg(InstancePtr->Config.CtrlBaseAddress,
XBRAM_ECC_EN_IRQ_OFFSET);
XBram_WriteReg(InstancePtr->Config.CtrlBaseAddress,
XBRAM_ECC_EN_IRQ_OFFSET,
Register | Mask);
}
/****************************************************************************/
/**
* Disable interrupts. This function allows each specific interrupt to be
* disabled. This function will assert if the hardware device has not been
* built with interrupt capabilities.
*
* @param InstancePtr is the BRAM instance to operate on.
* @param Mask is the mask to disable. Bits set to 1 are disabled. This
* mask is formed by OR'ing bits from XBRAM_IR* bits
* which are contained in xbram_hw.h.
*
* @return None.
*
* @note None.
*
*****************************************************************************/
void XBram_InterruptDisable(XBram *InstancePtr, u32 Mask)
{
u32 Register;
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Xil_AssertVoid(InstancePtr->Config.CtrlBaseAddress != 0);
/*
* Read the interrupt enable register and only disable the specified
* interrupts without enabling or disabling any others.
*/
Register = XBram_ReadReg(InstancePtr->Config.CtrlBaseAddress,
XBRAM_ECC_EN_IRQ_OFFSET);
XBram_WriteReg(InstancePtr->Config.CtrlBaseAddress,
XBRAM_ECC_EN_IRQ_OFFSET,
Register & (~Mask));
}
/****************************************************************************/
/**
* Clear pending interrupts with the provided mask. This function should be
* called after the software has serviced the interrupts that are pending.
* This function will assert if the hardware device has not been built with
* interrupt capabilities.
*
* @param InstancePtr is the BRAM instance to operate on.
* @param Mask is the mask to clear pending interrupts for. Bit positions
* of 1 are cleared. This mask is formed by OR'ing bits from
* XBRAM_IR* bits which are contained in
* xbram_hw.h.
*
* @return None.
*
* @note None.
*
*****************************************************************************/
void XBram_InterruptClear(XBram *InstancePtr, u32 Mask)
{
u32 Register;
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Xil_AssertVoid(InstancePtr->Config.CtrlBaseAddress != 0);
/*
* Read the interrupt status register and only clear the interrupts
* that are specified without affecting any others. Since the register
* is a toggle on write, make sure any bits to be written are already
* set.
*/
Register = XBram_ReadReg(InstancePtr->Config.CtrlBaseAddress,
XBRAM_ECC_STATUS_OFFSET);
XBram_WriteReg(InstancePtr->Config.CtrlBaseAddress,
XBRAM_ECC_STATUS_OFFSET,
Register & Mask);
}
/****************************************************************************/
/**
* Returns the interrupt enable mask. This function will assert if the
* hardware device has not been built with interrupt capabilities.
*
* @param InstancePtr is the BRAM instance to operate on.
*
* @return A mask of bits made from XBRAM_IR* bits which
* are contained in xbram_hw.h.
*
* @return None.
*
* @note None.
*
*****************************************************************************/
u32 XBram_InterruptGetEnabled(XBram * InstancePtr)
{
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Xil_AssertNonvoid(InstancePtr->Config.CtrlBaseAddress != 0);
return XBram_ReadReg(InstancePtr->Config.CtrlBaseAddress,
XBRAM_ECC_EN_IRQ_OFFSET);
}
/****************************************************************************/
/**
* Returns the status of interrupt signals. Any bit in the mask set to 1
* indicates that the channel associated with the bit has asserted an interrupt
* condition. This function will assert if the hardware device has not been
* built with interrupt capabilities.
*
* @param InstancePtr is the BRAM instance to operate on.
*
* @return A pointer to a mask of bits made from XBRAM_IR*
* bits which are contained in xbram_hw.h.
*
* @note
*
* The interrupt status indicates the status of the device irregardless if
* the interrupts from the devices have been enabled or not through
* XBram_InterruptEnable().
*
*****************************************************************************/
u32 XBram_InterruptGetStatus(XBram * InstancePtr)
{
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Xil_AssertNonvoid(InstancePtr->Config.CtrlBaseAddress != 0);
return XBram_ReadReg(InstancePtr->Config.CtrlBaseAddress,
XBRAM_ECC_EN_IRQ_OFFSET);
}

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/******************************************************************************
*
* (c) Copyright 2011-2013 Xilinx, Inc. All rights reserved.
*
* This file contains confidential and proprietary information of Xilinx, Inc.
* and is protected under U.S. and international copyright and other
* intellectual property laws.
*
* DISCLAIMER
* This disclaimer is not a license and does not grant any rights to the
* materials distributed herewith. Except as otherwise provided in a valid
* license issued to you by Xilinx, and to the maximum extent permitted by
* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
* and (2) Xilinx shall not be liable (whether in contract or tort, including
* negligence, or under any other theory of liability) for any loss or damage
* of any kind or nature related to, arising under or in connection with these
* materials, including for any direct, or any indirect, special, incidental,
* or consequential loss or damage (including loss of data, profits, goodwill,
* or any type of loss or damage suffered as a result of any action brought by
* a third party) even if such damage or loss was reasonably foreseeable or
* Xilinx had been advised of the possibility of the same.
*
* CRITICAL APPLICATIONS
* Xilinx products are not designed or intended to be fail-safe, or for use in
* any application requiring fail-safe performance, such as life-support or
* safety devices or systems, Class III medical devices, nuclear facilities,
* applications related to the deployment of airbags, or any other applications
* that could lead to death, personal injury, or severe property or
* environmental damage (individually and collectively, "Critical
* Applications"). Customer assumes the sole risk and liability of any use of
* Xilinx products in Critical Applications, subject only to applicable laws
* and regulations governing limitations on product liability.
*
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
* AT ALL TIMES.
*
******************************************************************************/
/*****************************************************************************/
/**
* @file xbram_selftest.c
*
* The implementation of the XBram driver's self test function. This SelfTest
* is only applicable if ECC is enabled.
* If ECC is not enabled then this function will return XST_SUCCESS.
* See xbram.h for more information about the driver.
*
* @note
*
* None
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.00a sa 11/24/10 First release
* 3.01a sa 01/13/12 Changed Selftest API from
* XBram_SelfTest(XBram *InstancePtr) to
* XBram_SelfTest(XBram *InstancePtr, u8 IntMask) and
* fixed a problem with interrupt generation for CR 639274
* Modified Selftest example to return XST_SUCCESS when
* ECC is not enabled and return XST_FAILURE when ECC is
* enabled and Control Base Address is zero (CR 636581)
* Modified Selftest to use correct CorrectableCounterBits
* for CR 635655
* Updated to check CorrectableFailingDataRegs in the case
* of LMB BRAM.
* 3.02a sa 04/16/12 Added test of byte and halfword read-modify-write
* 3.03a bss 05/22/13 Added Xil_DCacheFlushRange in InjectErrors API to
* flush the Cache after writing to BRAM (CR #719011)
* </pre>
*****************************************************************************/
/***************************** Include Files ********************************/
#include "xbram.h"
#include "xil_cache.h"
/************************** Constant Definitions ****************************/
#define TOTAL_BITS 39
/**************************** Type Definitions ******************************/
/***************** Macros (Inline Functions) Definitions ********************/
#define RD(reg) XBram_ReadReg(InstancePtr->Config.CtrlBaseAddress, \
XBRAM_ ## reg)
#define WR(reg, data) XBram_WriteReg(InstancePtr->Config.CtrlBaseAddress, \
XBRAM_ ## reg, data)
#define CHECK(reg, data, result) if (result!=XST_SUCCESS || RD(reg)!=data) \
result = XST_FAILURE;
/************************** Variable Definitions ****************************/
static u32 PrngResult;
/************************** Function Prototypes *****************************/
static inline u32 PrngData(u32 *PrngResult);
static inline u32 CalculateEcc(u32 Data);
static void InjectErrors(XBram * InstancePtr, u32 Addr,
int Index1, int Index2, int Width,
u32 *ActualData, u32 *ActualEcc);
/*****************************************************************************/
/**
* Generate a pseudo random number.
*
* @param The PrngResult is the previous random number in the pseudo
* random sequence, also knwon as the seed. It is modified to
* the calculated pseudo random number by the function.
*
* @return The generated pseudo random number
*
* @note None.
*
******************************************************************************/
static inline u32 PrngData(u32 *PrngResult)
{
*PrngResult = *PrngResult * 0x77D15E25 + 0x3617C161;
return *PrngResult;
}
/*****************************************************************************/
/**
* Calculate ECC from Data.
*
* @param The Data Value
*
* @return The calculated ECC
*
* @note None.
*
******************************************************************************/
static inline u32 CalculateEcc(u32 Data)
{
unsigned char c[7], d[32];
u32 Result = 0;
int Index;
for (Index = 0; Index < 32; Index++) {
d[31 - Index] = Data & 1;
Data = Data >> 1;
}
c[0] = d[0] ^ d[1] ^ d[3] ^ d[4] ^ d[6] ^ d[8] ^ d[10] ^ d[11] ^
d[13] ^ d[15] ^ d[17] ^ d[19] ^ d[21] ^ d[23] ^ d[25] ^ d[26] ^
d[28] ^ d[30];
c[1] = d[0] ^ d[2] ^ d[3] ^ d[5] ^ d[6] ^ d[9] ^ d[10] ^ d[12] ^
d[13] ^ d[16] ^ d[17] ^ d[20] ^ d[21] ^ d[24] ^ d[25] ^ d[27] ^
d[28] ^ d[31];
c[2] = d[1] ^ d[2] ^ d[3] ^ d[7] ^ d[8] ^ d[9] ^ d[10] ^ d[14] ^
d[15] ^ d[16] ^ d[17] ^ d[22] ^ d[23] ^ d[24] ^ d[25] ^ d[29] ^
d[30] ^ d[31];
c[3] = d[4] ^ d[5] ^ d[6] ^ d[7] ^ d[8] ^ d[9] ^ d[10] ^ d[18] ^
d[19] ^ d[20] ^ d[21] ^ d[22] ^ d[23] ^ d[24] ^ d[25];
c[4] = d[11] ^ d[12] ^ d[13] ^ d[14] ^ d[15] ^ d[16] ^ d[17] ^ d[18] ^
d[19] ^ d[20] ^ d[21] ^ d[22] ^ d[23] ^ d[24] ^ d[25];
c[5] = d[26] ^ d[27] ^ d[28] ^ d[29] ^ d[30] ^ d[31];
c[6] = d[0] ^ d[1] ^ d[2] ^ d[3] ^ d[4] ^ d[5] ^ d[6] ^ d[7] ^
d[8] ^ d[9] ^ d[10] ^ d[11] ^ d[12] ^ d[13] ^ d[14] ^ d[15] ^
d[16] ^ d[17] ^ d[18] ^ d[19] ^ d[20] ^ d[21] ^ d[22] ^ d[23] ^
d[24] ^ d[25] ^ d[26] ^ d[27] ^ d[28] ^ d[29] ^ d[30] ^ d[31] ^
c[5] ^ c[4] ^ c[3] ^ c[2] ^ c[1] ^ c[0];
for (Index = 0; Index < 7; Index++) {
Result = Result << 1;
Result |= c[Index] & 1;
}
return Result;
}
/*****************************************************************************/
/**
* Get the expected actual data read in case of uncorrectable errors.
*
* @param The injected data value including errors (if any)
* @param The syndrome (calculated ecc ^ actual ecc read)
*
* @return The actual data value read
*
* @note None.
*
******************************************************************************/
static inline u32 UncorrectableData(u32 Data, u8 Syndrome)
{
switch (Syndrome) {
case 0x03: return Data ^ 0x00000034;
case 0x05: return Data ^ 0x001a2000;
case 0x09: return Data ^ 0x0d000000;
case 0x0d: return Data ^ 0x00001a00;
case 0x11: return Data ^ 0x60000000;
case 0x13: return Data ^ 0x00000003;
case 0x15: return Data ^ 0x00018000;
case 0x19: return Data ^ 0x00c00000;
case 0x1d: return Data ^ 0x00000180;
case 0x21: return Data ^ 0x80000000;
case 0x23: return Data ^ 0x00000008;
case 0x25: return Data ^ 0x00040000;
case 0x29: return Data ^ 0x02000000;
case 0x2d: return Data ^ 0x00000400;
case 0x31: return Data ^ 0x10000000;
case 0x35: return Data ^ 0x00004000;
case 0x39: return Data ^ 0x00200000;
case 0x3d: return Data ^ 0x00000040;
}
return Data;
}
/*****************************************************************************/
/**
* Inject errors using the hardware fault injection functionality, and write
* random data and read it back using the indicated location.
*
* @param InstancePtr is a pointer to the XBram instance to
* be worked on.
* @param The Addr is the indicated memory location to use
* @param The Index1 is the bit location of the first injected error
* @param The Index2 is the bit location of the second injected error
* @param The Width is the data byte width
* @param The ActualData is filled in with expected data for checking
* @param The ActualEcc is filled in with expected ECC for checking
*
* @return None
*
* @note None.
*
******************************************************************************/
static void InjectErrors(XBram * InstancePtr, u32 Addr,
int Index1, int Index2, int Width,
u32 *ActualData, u32 *ActualEcc)
{
u32 InjectedData = 0;
u32 InjectedEcc = 0;
u32 RandomData = PrngData(&PrngResult);
if (Index1 < 32) {
InjectedData = 1 << Index1;
} else {
InjectedEcc = 1 << (Index1 - 32);
}
if (Index2 < 32) {
InjectedData |= (1 << Index2);
} else {
InjectedEcc |= 1 << (Index2 - 32);
}
WR(FI_D_0_OFFSET, InjectedData);
WR(FI_ECC_0_OFFSET, InjectedEcc);
XBram_Out32(Addr, RandomData);
Xil_DCacheFlushRange(Addr, 4);
switch (Width) {
case 1: /* Byte - Write to do Read-Modify-Write */
XBram_Out8(Addr, PrngData(&PrngResult) & 0xFF);
break;
case 2: /* Halfword - Write to do Read-Modify-Write */
XBram_Out16(Addr, PrngData(&PrngResult) & 0xFFFF);
break;
case 4: /* Word - Read */
(void) XBram_In32(Addr);
break;
}
*ActualData = InjectedData ^ RandomData;
*ActualEcc = InjectedEcc ^ CalculateEcc(RandomData);
}
/*****************************************************************************/
/**
* Run a self-test on the driver/device. Unless fault injection is implemented
* in hardware, this function only does a minimal test in which available
* registers (if any) are written and read.
*
* With fault injection, all possible single-bit and double-bit errors are
* injected, and checked to the extent possible, given the implemented hardware.
*
* @param InstancePtr is a pointer to the XBram instance.
* @param IntMask is the interrupt mask to use. When testing
* with interrupts, this should be set to allow interrupt
* generation, otherwise it should be 0.
*
* @return
* - XST_SUCCESS if fault injection/detection is working properly OR
* if ECC is Not Enabled in the HW.
* - XST_FAILURE if the injected fault is not correctly detected or
* the Control Base Address is Zero when ECC is enabled.
* .
*
* If the BRAM device is not present in the
* hardware a bus error could be generated. Other indicators of a
* bus error, such as registers in bridges or buses, may be
* necessary to determine if this function caused a bus error.
*
* @note None.
*
******************************************************************************/
int XBram_SelfTest(XBram *InstancePtr, u8 IntMask)
{
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
if (InstancePtr->Config.EccPresent == 0) {
return (XST_SUCCESS);
}
if (InstancePtr->Config.CtrlBaseAddress == 0) {
return (XST_SUCCESS);
}
/*
* Only 32-bit data width is supported as of yet. 64-bit and 128-bit
* widths will be supported in future.
*/
if (InstancePtr->Config.DataWidth != 32)
return (XST_SUCCESS);
/*
* Read from the implemented readable registers in the hardware device.
*/
if (InstancePtr->Config.CorrectableFailingRegisters) {
(void) RD(CE_FFA_0_OFFSET);
}
if (InstancePtr->Config.CorrectableFailingDataRegs) {
(void) RD(CE_FFD_0_OFFSET);
(void) RD(CE_FFE_0_OFFSET);
}
if (InstancePtr->Config.UncorrectableFailingRegisters) {
(void) RD(UE_FFA_0_OFFSET);
}
if (InstancePtr->Config.UncorrectableFailingDataRegs) {
(void) RD(UE_FFD_0_OFFSET);
(void) RD(UE_FFE_0_OFFSET);
}
/*
* Write and read the implemented read/write registers in the hardware
* device.
*/
if (InstancePtr->Config.EccStatusInterruptPresent) {
WR(ECC_EN_IRQ_OFFSET, 0);
if (RD(ECC_EN_IRQ_OFFSET) != 0) {
return (XST_FAILURE);
}
}
if (InstancePtr->Config.CorrectableCounterBits > 0) {
u32 Value;
/* Calculate counter max value */
if (InstancePtr->Config.CorrectableCounterBits == 32) {
Value = 0xFFFFFFFF;
} else {
Value = (1 <<
InstancePtr->Config.CorrectableCounterBits) - 1;
}
WR(CE_CNT_OFFSET, Value);
if (RD(CE_CNT_OFFSET) != Value) {
return (XST_FAILURE);
}
WR(CE_CNT_OFFSET, 0);
if (RD(CE_CNT_OFFSET) != 0) {
return (XST_FAILURE);
}
}
/*
* If fault injection is implemented, inject all possible single-bit
* and double-bit errors, and check all observable effects.
*/
if (InstancePtr->Config.FaultInjectionPresent &&
InstancePtr->Config.WriteAccess != 0) {
const u32 Addr[2] = {InstancePtr->Config.MemBaseAddress &
0xfffffffc,
InstancePtr->Config.MemHighAddress &
0xfffffffc};
u32 SavedWords[2];
u32 ActualData;
u32 ActualEcc;
u32 CounterValue = 0;
u32 CounterMax;
int WordIndex = 0;
int Result = XST_SUCCESS;
int Index1;
int Index2;
int Width;
PrngResult = 42; /* Random seed */
/* Save two words in BRAM used for test */
SavedWords[0] = XBram_In32(Addr[0]);
SavedWords[1] = XBram_In32(Addr[1]);
for (Width = 1; Width <= 4; Width <<= 1) {
/* Calculate counter max value */
if (InstancePtr->Config.CorrectableCounterBits == 32) {
CounterMax = 0xFFFFFFFF;
} else {
CounterMax =(1 <<
InstancePtr->Config.CorrectableCounterBits) - 1;
}
/* Inject and check all single bit errors */
for (Index1 = 0; Index1 < TOTAL_BITS; Index1++) {
/* Save counter value */
if (InstancePtr->Config.CorrectableCounterBits > 0) {
CounterValue = RD(CE_CNT_OFFSET);
}
/* Inject single bit error */
InjectErrors(InstancePtr, Addr[WordIndex], Index1,
Index1, Width, &ActualData, &ActualEcc);
/* Check that CE is set */
if (InstancePtr->Config.EccStatusInterruptPresent) {
CHECK(ECC_STATUS_OFFSET,
XBRAM_IR_CE_MASK, Result);
}
/* Check that address, data, ECC are correct */
if (InstancePtr->Config.CorrectableFailingRegisters) {
CHECK(CE_FFA_0_OFFSET, Addr[WordIndex], Result);
}
/* Checks are only for LMB BRAM */
if (InstancePtr->Config.CorrectableFailingDataRegs) {
CHECK(CE_FFD_0_OFFSET, ActualData, Result);
CHECK(CE_FFE_0_OFFSET, ActualEcc, Result);
}
/* Check that counter has incremented */
if (InstancePtr->Config.CorrectableCounterBits > 0 &&
CounterValue < CounterMax) {
CHECK(CE_CNT_OFFSET,
CounterValue + 1, Result);
}
/* Restore correct data in the used word */
XBram_Out32(Addr[WordIndex], SavedWords[WordIndex]);
/* Allow interrupts to occur */
/* Clear status register */
if (InstancePtr->Config.EccStatusInterruptPresent) {
WR(ECC_EN_IRQ_OFFSET, IntMask);
WR(ECC_STATUS_OFFSET, XBRAM_IR_ALL_MASK);
WR(ECC_EN_IRQ_OFFSET, 0);
}
/* Switch to the other word */
WordIndex = WordIndex ^ 1;
if (Result != XST_SUCCESS) break;
}
if (Result != XST_SUCCESS) {
return XST_FAILURE;
}
for (Index1 = 0; Index1 < TOTAL_BITS; Index1++) {
for (Index2 = 0; Index2 < TOTAL_BITS; Index2++) {
if (Index1 != Index2) {
/* Inject double bit error */
InjectErrors(InstancePtr,
Addr[WordIndex],
Index1, Index2, Width,
&ActualData,
&ActualEcc);
/* Check that UE is set */
if (InstancePtr->Config.
EccStatusInterruptPresent) {
CHECK(ECC_STATUS_OFFSET,
XBRAM_IR_UE_MASK,
Result);
}
/* Check that address, data, ECC are correct */
if (InstancePtr->Config.
UncorrectableFailingRegisters) {
CHECK(UE_FFA_0_OFFSET, Addr[WordIndex],
Result);
CHECK(UE_FFD_0_OFFSET,
ActualData, Result);
CHECK(UE_FFE_0_OFFSET, ActualEcc,
Result);
}
/* Restore correct data in the used word */
XBram_Out32(Addr[WordIndex],
SavedWords[WordIndex]);
/* Allow interrupts to occur */
/* Clear status register */
if (InstancePtr->Config.
EccStatusInterruptPresent) {
WR(ECC_EN_IRQ_OFFSET, IntMask);
WR(ECC_STATUS_OFFSET,
XBRAM_IR_ALL_MASK);
WR(ECC_EN_IRQ_OFFSET, 0);
}
/* Switch to the other word */
WordIndex = WordIndex ^ 1;
}
if (Result != XST_SUCCESS) break;
}
if (Result != XST_SUCCESS) break;
}
/* Check saturation of correctable error counter */
if (InstancePtr->Config.CorrectableCounterBits > 0 &&
Result == XST_SUCCESS) {
WR(CE_CNT_OFFSET, CounterMax);
InjectErrors(InstancePtr, Addr[WordIndex], 0, 0,
4, &ActualData, &ActualEcc);
CHECK(CE_CNT_OFFSET, CounterMax, Result);
}
/* Restore the two words used for test */
XBram_Out32(Addr[0], SavedWords[0]);
XBram_Out32(Addr[1], SavedWords[1]);
/* Clear the Status Register. */
if (InstancePtr->Config.EccStatusInterruptPresent) {
WR(ECC_STATUS_OFFSET, XBRAM_IR_ALL_MASK);
}
/* Set Correctable Counter to zero */
if (InstancePtr->Config.CorrectableCounterBits > 0) {
WR(CE_CNT_OFFSET, 0);
}
if (Result != XST_SUCCESS) break;
} /* Width loop */
return (Result);
}
return (XST_SUCCESS);
}

110
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/******************************************************************************
*
* (c) Copyright 2010-2013 Xilinx, Inc. All rights reserved.
*
* This file contains confidential and proprietary information of Xilinx, Inc.
* and is protected under U.S. and international copyright and other
* intellectual property laws.
*
* DISCLAIMER
* This disclaimer is not a license and does not grant any rights to the
* materials distributed herewith. Except as otherwise provided in a valid
* license issued to you by Xilinx, and to the maximum extent permitted by
* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
* and (2) Xilinx shall not be liable (whether in contract or tort, including
* negligence, or under any other theory of liability) for any loss or damage
* of any kind or nature related to, arising under or in connection with these
* materials, including for any direct, or any indirect, special, incidental,
* or consequential loss or damage (including loss of data, profits, goodwill,
* or any type of loss or damage suffered as a result of any action brought by
* a third party) even if such damage or loss was reasonably foreseeable or
* Xilinx had been advised of the possibility of the same.
*
* CRITICAL APPLICATIONS
* Xilinx products are not designed or intended to be fail-safe, or for use in
* any application requiring fail-safe performance, such as life-support or
* safety devices or systems, Class III medical devices, nuclear facilities,
* applications related to the deployment of airbags, or any other applications
* that could lead to death, personal injury, or severe property or
* environmental damage (individually and collectively, "Critical
* Applications"). Customer assumes the sole risk and liability of any use of
* Xilinx products in Critical Applications, subject only to applicable laws
* and regulations governing limitations on product liability.
*
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
* AT ALL TIMES.
*
******************************************************************************/
/*****************************************************************************/
/**
* @file xbram_sinit.c
*
* The implementation of the XBram driver's static initialzation
* functionality.
*
* @note
*
* None
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 2.01a jvb 10/13/05 First release
* 2.11a mta 03/21/07 Updated to new coding style
* </pre>
*
*****************************************************************************/
/***************************** Include Files ********************************/
#include "xstatus.h"
#include "xparameters.h"
#include "xbram.h"
/************************** Constant Definitions ****************************/
/**************************** Type Definitions ******************************/
/***************** Macros (Inline Functions) Definitions ********************/
/************************** Variable Definitions ****************************/
extern XBram_Config XBram_ConfigTable[];
/************************** Function Prototypes *****************************/
/*****************************************************************************/
/**
* Lookup the device configuration based on the unique device ID. The table
* ConfigTable contains the configuration info for each device in the system.
*
* @param DeviceId is the device identifier to lookup.
*
* @return
* - A pointer of data type XBram_Config which
* points to the device configuration if DeviceID is found.
* - NULL if DeviceID is not found.
*
* @note None.
*
******************************************************************************/
XBram_Config *XBram_LookupConfig(u16 DeviceId)
{
XBram_Config *CfgPtr = NULL;
int Index;
for (Index = 0; Index < XPAR_XBRAM_NUM_INSTANCES; Index++) {
if (XBram_ConfigTable[Index].DeviceId == DeviceId) {
CfgPtr = &XBram_ConfigTable[Index];
break;
}
}
return CfgPtr;
}

28
software/LED_Controller_bsp/microblaze_mcs/libsrc/common_v1_00_a/src/Makefile Normal file
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COMPILER=
ARCHIVER=
CP=cp
COMPILER_FLAGS=
EXTRA_COMPILER_FLAGS=
LIB=libxil.a
RELEASEDIR=../../../lib
INCLUDEDIR=../../../include
INCLUDES=-I${INCLUDEDIR}
OUTS = *.o
LIBSOURCES=*.c
INCLUDEFILES=xbasic_types.h xenv.h xenv_none.h xenv_standalone.h xenv_vxworks.h xstatus.h xutil.h xversion.h xdebug.h
libs:
echo "Compiling common"
$(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES)
$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS}
make clean
include:
${CP} $(INCLUDEFILES) $(INCLUDEDIR)
clean:
rm -rf $(OUTS)

137
software/LED_Controller_bsp/microblaze_mcs/libsrc/common_v1_00_a/src/xbasic_types.c Executable file
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/* $Id $ */
/******************************************************************************
*
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
* AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
* SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE,
* OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
* APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
* THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE.
*
* (c) Copyright 2002-2012 Xilinx Inc.
* All rights reserved.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xbasic_types.c
*
* This file contains basic functions for Xilinx software IP.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00a rpm 11/07/03 Added XNullHandler function as a stub interrupt handler
* 1.00a xd 11/03/04 Improved support for doxygen.
* 1.00a bss 13/01/12 Removed a compiler warning in XNullHandler;
* </pre>
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "xbasic_types.h"
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Variable Definitions *****************************/
/**
* This variable allows testing to be done easier with asserts. An assert
* sets this variable such that a driver can evaluate this variable
* to determine if an assert occurred.
*/
unsigned int XAssertStatus;
/**
* This variable allows the assert functionality to be changed for testing
* such that it does not wait infinitely. Use the debugger to disable the
* waiting during testing of asserts.
*/
int XWaitInAssert = TRUE;
/* The callback function to be invoked when an assert is taken */
static XAssertCallback XAssertCallbackRoutine = (XAssertCallback) NULL;
/************************** Function Prototypes ******************************/
/*****************************************************************************/
/**
*
* Implements assert. Currently, it calls a user-defined callback function
* if one has been set. Then, it potentially enters an infinite loop depending
* on the value of the XWaitInAssert variable.
*
* @param File is the name of the filename of the source
* @param Line is the linenumber within File
*
* @return None.
*
* @note None.
*
******************************************************************************/
void XAssert(char *File, int Line)
{
/* if the callback has been set then invoke it */
if (XAssertCallbackRoutine != NULL) {
(*XAssertCallbackRoutine) (File, Line);
}
/* if specified, wait indefinitely such that the assert will show up
* in testing
*/
while (XWaitInAssert) {
}
}
/*****************************************************************************/
/**
*
* Sets up a callback function to be invoked when an assert occurs. If there
* was already a callback installed, then it is replaced.
*
* @param Routine is the callback to be invoked when an assert is taken
*
* @return None.
*
* @note This function has no effect if NDEBUG is set
*
******************************************************************************/
void XAssertSetCallback(XAssertCallback Routine)
{
XAssertCallbackRoutine = Routine;
}
/*****************************************************************************/
/**
*
* Null handler function. This follows the XInterruptHandler signature for
* interrupt handlers. It can be used to assign a null handler (a stub) to an
* interrupt controller vector table.
*
* @param NullParameter is an arbitrary void pointer and not used.
*
* @return None.
*
* @note None.
*
******************************************************************************/
void XNullHandler(void *NullParameter)
{
(void) NullParameter;
}

300
software/LED_Controller_bsp/microblaze_mcs/libsrc/common_v1_00_a/src/xbasic_types.h Executable file
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@@ -0,0 +1,300 @@
/* $Id: xbasic_types.h,v 1.19.10.4 2011/06/28 11:00:54 sadanan Exp $ */
/******************************************************************************
*
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
* AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
* SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE,
* OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
* APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
* THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE.
*
* (c) Copyright 2002-2007 Xilinx Inc.
* All rights reserved.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xbasic_types.h
*
* This file contains basic types for Xilinx software IP. These types do not
* follow the standard naming convention with respect to using the component
* name in front of each name because they are considered to be primitives.
*
* @note
*
* This file contains items which are architecture dependent.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00a rmm 12/14/01 First release
* rmm 05/09/03 Added "xassert always" macros to rid ourselves of diab
* compiler warnings
* 1.00a rpm 11/07/03 Added XNullHandler function as a stub interrupt handler
* 1.00a rpm 07/21/04 Added XExceptionHandler typedef for processor exceptions
* 1.00a xd 11/03/04 Improved support for doxygen.
* 1.00a wre 01/25/07 Added Linux style data types u32, u16, u8, TRUE, FALSE
* 1.00a rpm 04/02/07 Added ifndef KERNEL around u32, u16, u8 data types
* </pre>
*
******************************************************************************/
#ifndef XBASIC_TYPES_H /* prevent circular inclusions */
#define XBASIC_TYPES_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
/************************** Constant Definitions *****************************/
#ifndef TRUE
# define TRUE 1
#endif
#ifndef FALSE
# define FALSE 0
#endif
#ifndef NULL
#define NULL 0
#endif
/** Xilinx NULL, TRUE and FALSE legacy support. Deprecated. */
#define XNULL NULL
#define XTRUE TRUE
#define XFALSE FALSE
#define XCOMPONENT_IS_READY 0x11111111 /**< component has been initialized */
#define XCOMPONENT_IS_STARTED 0x22222222 /**< component has been started */
/* the following constants and declarations are for unit test purposes and are
* designed to be used in test applications.
*/
#define XTEST_PASSED 0
#define XTEST_FAILED 1
#define XASSERT_NONE 0
#define XASSERT_OCCURRED 1
extern unsigned int XAssertStatus;
extern void XAssert(char *, int);
/**************************** Type Definitions *******************************/
/** @name Legacy types
* Deprecated legacy types.
* @{
*/
typedef unsigned char Xuint8; /**< unsigned 8-bit */
typedef char Xint8; /**< signed 8-bit */
typedef unsigned short Xuint16; /**< unsigned 16-bit */
typedef short Xint16; /**< signed 16-bit */
typedef unsigned long Xuint32; /**< unsigned 32-bit */
typedef long Xint32; /**< signed 32-bit */
typedef float Xfloat32; /**< 32-bit floating point */
typedef double Xfloat64; /**< 64-bit double precision FP */
typedef unsigned long Xboolean; /**< boolean (XTRUE or XFALSE) */
#if !defined __XUINT64__
typedef struct
{
Xuint32 Upper;
Xuint32 Lower;
} Xuint64;
#endif
/** @name New types
* New simple types.
* @{
*/
#ifndef __KERNEL__
#ifndef XIL_TYPES_H
typedef Xuint32 u32;
typedef Xuint16 u16;
typedef Xuint8 u8;
#endif
#else
#include <linux/types.h>
#endif
/*@}*/
/**
* This data type defines an interrupt handler for a device.
* The argument points to the instance of the component
*/
typedef void (*XInterruptHandler) (void *InstancePtr);
/**
* This data type defines an exception handler for a processor.
* The argument points to the instance of the component
*/
typedef void (*XExceptionHandler) (void *InstancePtr);
/**
* This data type defines a callback to be invoked when an
* assert occurs. The callback is invoked only when asserts are enabled
*/
typedef void (*XAssertCallback) (char *FilenamePtr, int LineNumber);
/***************** Macros (Inline Functions) Definitions *********************/
/*****************************************************************************/
/**
* Return the most significant half of the 64 bit data type.
*
* @param x is the 64 bit word.
*
* @return The upper 32 bits of the 64 bit word.
*
* @note None.
*
******************************************************************************/
#define XUINT64_MSW(x) ((x).Upper)
/*****************************************************************************/
/**
* Return the least significant half of the 64 bit data type.
*
* @param x is the 64 bit word.
*
* @return The lower 32 bits of the 64 bit word.
*
* @note None.
*
******************************************************************************/
#define XUINT64_LSW(x) ((x).Lower)
#ifndef NDEBUG
/*****************************************************************************/
/**
* This assert macro is to be used for functions that do not return anything
* (void). This in conjunction with the XWaitInAssert boolean can be used to
* accomodate tests so that asserts which fail allow execution to continue.
*
* @param expression is the expression to evaluate. If it evaluates to
* false, the assert occurs.
*
* @return Returns void unless the XWaitInAssert variable is true, in which
* case no return is made and an infinite loop is entered.
*
* @note None.
*
******************************************************************************/
#define XASSERT_VOID(expression) \
{ \
if (expression) \
{ \
XAssertStatus = XASSERT_NONE; \
} \
else \
{ \
XAssert(__FILE__, __LINE__); \
XAssertStatus = XASSERT_OCCURRED; \
return; \
} \
}
/*****************************************************************************/
/**
* This assert macro is to be used for functions that do return a value. This in
* conjunction with the XWaitInAssert boolean can be used to accomodate tests so
* that asserts which fail allow execution to continue.
*
* @param expression is the expression to evaluate. If it evaluates to false,
* the assert occurs.
*
* @return Returns 0 unless the XWaitInAssert variable is true, in which case
* no return is made and an infinite loop is entered.
*
* @note None.
*
******************************************************************************/
#define XASSERT_NONVOID(expression) \
{ \
if (expression) \
{ \
XAssertStatus = XASSERT_NONE; \
} \
else \
{ \
XAssert(__FILE__, __LINE__); \
XAssertStatus = XASSERT_OCCURRED; \
return 0; \
} \
}
/*****************************************************************************/
/**
* Always assert. This assert macro is to be used for functions that do not
* return anything (void). Use for instances where an assert should always
* occur.
*
* @return Returns void unless the XWaitInAssert variable is true, in which case
* no return is made and an infinite loop is entered.
*
* @note None.
*
******************************************************************************/
#define XASSERT_VOID_ALWAYS() \
{ \
XAssert(__FILE__, __LINE__); \
XAssertStatus = XASSERT_OCCURRED; \
return; \
}
/*****************************************************************************/
/**
* Always assert. This assert macro is to be used for functions that do return
* a value. Use for instances where an assert should always occur.
*
* @return Returns void unless the XWaitInAssert variable is true, in which case
* no return is made and an infinite loop is entered.
*
* @note None.
*
******************************************************************************/
#define XASSERT_NONVOID_ALWAYS() \
{ \
XAssert(__FILE__, __LINE__); \
XAssertStatus = XASSERT_OCCURRED; \
return 0; \
}
#else
#define XASSERT_VOID(expression)
#define XASSERT_VOID_ALWAYS()
#define XASSERT_NONVOID(expression)
#define XASSERT_NONVOID_ALWAYS()
#endif
/************************** Function Prototypes ******************************/
void XAssertSetCallback(XAssertCallback Routine);
void XNullHandler(void *NullParameter);
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */

61
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#ifndef XDEBUG
#define XDEBUG
#undef DEBUG
#if defined(DEBUG) && !defined(NDEBUG)
#ifndef XDEBUG_WARNING
#define XDEBUG_WARNING
#warning DEBUG is enabled
#endif
int printf(const char *format, ...);
#define XDBG_DEBUG_ERROR 0x00000001 /* error condition messages */
#define XDBG_DEBUG_GENERAL 0x00000002 /* general debug messages */
#define XDBG_DEBUG_ALL 0xFFFFFFFF /* all debugging data */
#define XDBG_DEBUG_FIFO_REG 0x00000100 /* display register reads/writes */
#define XDBG_DEBUG_FIFO_RX 0x00000101 /* receive debug messages */
#define XDBG_DEBUG_FIFO_TX 0x00000102 /* transmit debug messages */
#define XDBG_DEBUG_FIFO_ALL 0x0000010F /* all fifo debug messages */
#define XDBG_DEBUG_TEMAC_REG 0x00000400 /* display register reads/writes */
#define XDBG_DEBUG_TEMAC_RX 0x00000401 /* receive debug messages */
#define XDBG_DEBUG_TEMAC_TX 0x00000402 /* transmit debug messages */
#define XDBG_DEBUG_TEMAC_ALL 0x0000040F /* all temac debug messages */
#define XDBG_DEBUG_TEMAC_ADPT_RX 0x00000800 /* receive debug messages */
#define XDBG_DEBUG_TEMAC_ADPT_TX 0x00000801 /* transmit debug messages */
#define XDBG_DEBUG_TEMAC_ADPT_IOCTL 0x00000802 /* ioctl debug messages */
#define XDBG_DEBUG_TEMAC_ADPT_MISC 0x00000803 /* debug msg for other routines */
#define XDBG_DEBUG_TEMAC_ADPT_ALL 0x0000080F /* all temac adapter debug messages */
#define xdbg_current_types (XDBG_DEBUG_ERROR)
#define xdbg_stmnt(x) x
/* In VxWorks, if _WRS_GNU_VAR_MACROS is defined, special syntax is needed for
* macros that accept variable number of arguments
*/
#if defined(XENV_VXWORKS) && defined(_WRS_GNU_VAR_MACROS)
#define xdbg_printf(type, args...) (((type) & xdbg_current_types) ? printf (## args) : 0)
#else /* ANSI Syntax */
#define xdbg_printf(type, ...) (((type) & xdbg_current_types) ? printf (__VA_ARGS__) : 0)
#endif
#else /* defined(DEBUG) && !defined(NDEBUG) */
#define xdbg_stmnt(x)
/* See VxWorks comments above */
#if defined(XENV_VXWORKS) && defined(_WRS_GNU_VAR_MACROS)
#define xdbg_printf(type, args...)
#else /* ANSI Syntax */
#define xdbg_printf(...)
#endif
#endif /* defined(DEBUG) && !defined(NDEBUG) */
#endif /* XDEBUG */

177
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/******************************************************************************
*
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
* AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
* SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE,
* OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
* APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
* THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE.
*
* (c) Copyright 2002 Xilinx Inc.
* All rights reserved.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xenv.h
*
* Defines common services that are typically found in a host operating.
* environment. This include file simply includes an OS specific file based
* on the compile-time constant BUILD_ENV_*, where * is the name of the target
* environment.
*
* All services are defined as macros.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.00b ch 10/24/02 Added XENV_LINUX
* 1.00a rmm 04/17/02 First release
* </pre>
*
******************************************************************************/
#ifndef XENV_H /* prevent circular inclusions */
#define XENV_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/*
* Select which target environment we are operating under
*/
/* VxWorks target environment */
#if defined XENV_VXWORKS
#include "xenv_vxworks.h"
/* Linux target environment */
#elif defined XENV_LINUX
#include "xenv_linux.h"
/* Unit test environment */
#elif defined XENV_UNITTEST
#include "ut_xenv.h"
/* Integration test environment */
#elif defined XENV_INTTEST
#include "int_xenv.h"
/* Standalone environment selected */
#else
#include "xenv_standalone.h"
#endif
/*
* The following comments specify the types and macro wrappers that are
* expected to be defined by the target specific header files
*/
/**************************** Type Definitions *******************************/
/*****************************************************************************/
/**
*
* XENV_TIME_STAMP
*
* A structure that contains a time stamp used by other time stamp macros
* defined below. This structure is processor dependent.
*/
/***************** Macros (Inline Functions) Definitions *********************/
/*****************************************************************************/
/**
*
* XENV_MEM_COPY(void *DestPtr, void *SrcPtr, unsigned Bytes)
*
* Copies a non-overlapping block of memory.
*
* @param DestPtr is the destination address to copy data to.
* @param SrcPtr is the source address to copy data from.
* @param Bytes is the number of bytes to copy.
*
* @return None
*/
/*****************************************************************************/
/**
*
* XENV_MEM_FILL(void *DestPtr, char Data, unsigned Bytes)
*
* Fills an area of memory with constant data.
*
* @param DestPtr is the destination address to set.
* @param Data contains the value to set.
* @param Bytes is the number of bytes to set.
*
* @return None
*/
/*****************************************************************************/
/**
*
* XENV_TIME_STAMP_GET(XTIME_STAMP *StampPtr)
*
* Samples the processor's or external timer's time base counter.
*
* @param StampPtr is the storage for the retrieved time stamp.
*
* @return None
*/
/*****************************************************************************/
/**
*
* XENV_TIME_STAMP_DELTA_US(XTIME_STAMP *Stamp1Ptr, XTIME_STAMP* Stamp2Ptr)
*
* Computes the delta between the two time stamps.
*
* @param Stamp1Ptr - First sampled time stamp.
* @param Stamp1Ptr - Sedond sampled time stamp.
*
* @return An unsigned int value with units of microseconds.
*/
/*****************************************************************************/
/**
*
* XENV_TIME_STAMP_DELTA_MS(XTIME_STAMP *Stamp1Ptr, XTIME_STAMP* Stamp2Ptr)
*
* Computes the delta between the two time stamps.
*
* @param Stamp1Ptr - First sampled time stamp.
* @param Stamp1Ptr - Sedond sampled time stamp.
*
* @return An unsigned int value with units of milliseconds.
*/
/*****************************************************************************//**
*
* XENV_USLEEP(unsigned delay)
*
* Delay the specified number of microseconds.
*
* @param delay is the number of microseconds to delay.
*
* @return None
*/
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */

241
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/******************************************************************************
*
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
* AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
* SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE,
* OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
* APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
* THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE.
*
* (c) Copyright 2002-2007 Xilinx Inc.
* All rights reserved.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xenv_linux.h
*
* Defines common services specified by xenv.h.
*
* @note
* This file is not intended to be included directly by driver code.
* Instead, the generic xenv.h file is intended to be included by driver
* code.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.00a wgr 02/28/07 Added cache handling macros.
* 1.00a wgr 02/27/07 Simplified code. Deprecated old-style macro names.
* 1.00a xd 11/03/04 Improved support for doxygen.
* 1.00a ch 10/24/02 First release
* 1.10a wgr 03/22/07 Converted to new coding style.
* </pre>
*
*
******************************************************************************/
#ifndef XENV_LINUX_H
#define XENV_LINUX_H
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include <asm/cache.h>
#include <asm/cacheflush.h>
#include <linux/string.h>
#include <linux/delay.h>
/******************************************************************************
*
* MEMCPY / MEMSET related macros.
*
* Those macros are defined to catch legacy code in Xilinx drivers. The
* XENV_MEM_COPY and XENV_MEM_FILL macros were used in early Xilinx driver
* code. They are being replaced by memcpy() and memset() function calls. These
* macros are defined to catch any remaining occurences of those macros.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* Copies a non-overlapping block of memory.
*
* @param DestPtr
* Destination address to copy data to.
*
* @param SrcPtr
* Source address to copy data from.
*
* @param Bytes
* Number of bytes to copy.
*
* @return None.
*
*****************************************************************************/
#define XENV_MEM_COPY(DestPtr, SrcPtr, Bytes) \
memcpy(DestPtr, SrcPtr, Bytes)
/* do_not_use_XENV_MEM_COPY_use_memcpy_instead */
/*****************************************************************************/
/**
*
* Fills an area of memory with constant data.
*
* @param DestPtr
* Destination address to copy data to.
*
* @param Data
* Value to set.
*
* @param Bytes
* Number of bytes to copy.
*
* @return None.
*
*****************************************************************************/
#define XENV_MEM_FILL(DestPtr, Data, Bytes) \
memset(DestPtr, Data, Bytes)
/* do_not_use_XENV_MEM_FILL_use_memset_instead */
/******************************************************************************
*
* TIME related macros
*
******************************************************************************/
/**
* A structure that contains a time stamp used by other time stamp macros
* defined below. This structure is processor dependent.
*/
typedef int XENV_TIME_STAMP;
/*****************************************************************************/
/**
*
* Time is derived from the 64 bit PPC timebase register
*
* @param StampPtr is the storage for the retrieved time stamp.
*
* @return None.
*
* @note
*
* Signature: void XENV_TIME_STAMP_GET(XTIME_STAMP *StampPtr)
* <br><br>
* This macro must be implemented by the user.
*
*****************************************************************************/
#define XENV_TIME_STAMP_GET(StampPtr)
/*****************************************************************************/
/**
*
* This macro is not yet implemented and always returns 0.
*
* @param Stamp1Ptr is the first sampled time stamp.
* @param Stamp2Ptr is the second sampled time stamp.
*
* @return 0
*
* @note
*
* This macro must be implemented by the user.
*
*****************************************************************************/
#define XENV_TIME_STAMP_DELTA_US(Stamp1Ptr, Stamp2Ptr) (0)
/*****************************************************************************/
/**
*
* This macro is not yet implemented and always returns 0.
*
* @param Stamp1Ptr is the first sampled time stamp.
* @param Stamp2Ptr is the second sampled time stamp.
*
* @return 0
*
* @note
*
* This macro must be implemented by the user
*
*****************************************************************************/
#define XENV_TIME_STAMP_DELTA_MS(Stamp1Ptr, Stamp2Ptr) (0)
/*****************************************************************************/
/**
*
* Delay the specified number of microseconds.
*
* @param delay
* Number of microseconds to delay.
*
* @return None.
*
* @note XENV_USLEEP is deprecated. Use udelay() instead.
*
*****************************************************************************/
#define XENV_USLEEP(delay) udelay(delay)
/* do_not_use_XENV_MEM_COPY_use_memcpy_instead */
/******************************************************************************
*
* CACHE handling macros / mappings
*
* The implementation of the cache handling functions can be found in
* arch/microblaze.
*
* These #defines are simple mappings to the Linux API.
*
* The underlying Linux implementation will take care of taking the right
* actions depending on the configuration of the MicroBlaze processor in the
* system.
*
******************************************************************************/
#define XCACHE_ENABLE_DCACHE() __enable_dcache()
#define XCACHE_DISABLE_DCACHE() __disable_dcache()
#define XCACHE_ENABLE_ICACHE() __enable_icache()
#define XCACHE_DISABLE_ICACHE() __disable_icache()
#define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len) invalidate_dcache_range((u32)(Addr), ((u32)(Addr)+(Len)))
#define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) flush_dcache_range((u32)(Addr), ((u32)(Addr)+(Len)))
#define XCACHE_INVALIDATE_ICACHE_RANGE(Addr, Len) "XCACHE_INVALIDATE_ICACHE_RANGE unsupported"
#define XCACHE_FLUSH_ICACHE_RANGE(Addr, Len) flush_icache_range(Addr, Len)
#define XCACHE_ENABLE_CACHE() \
{ XCACHE_ENABLE_DCACHE(); XCACHE_ENABLE_ICACHE(); }
#define XCACHE_DISABLE_CACHE() \
{ XCACHE_DISABLE_DCACHE(); XCACHE_DISABLE_ICACHE(); }
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */

41
software/LED_Controller_bsp/microblaze_mcs/libsrc/common_v1_00_a/src/xenv_none.h Executable file
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@@ -0,0 +1,41 @@
/******************************************************************************
*
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
* AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
* SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE,
* OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
* APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
* THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE.
*
* (c) Copyright 2002 Xilinx Inc.
* All rights reserved.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xenv_none.h
*
* This is a legacy file kept for backwards compatibility.
*
* Please modify your code to #include "xenv_standalone.h" instead.
*
*
******************************************************************************/
#warning ********************************************************************
#warning *
#warning * Use of xenv_none.h deprecated.
#warning * Please include the new xenv_standalone.h file instead.
#warning *
#warning ********************************************************************
#include "xenv_standalone.h"

356
software/LED_Controller_bsp/microblaze_mcs/libsrc/common_v1_00_a/src/xenv_standalone.h Normal file
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/******************************************************************************
*
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
* AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
* SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE,
* OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
* APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
* THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE.
*
* (c) Copyright 2002-2008 Xilinx Inc.
* All rights reserved.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xenv_standalone.h
*
* Defines common services specified by xenv.h.
*
* @note
* This file is not intended to be included directly by driver code.
* Instead, the generic xenv.h file is intended to be included by driver
* code.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.00a wgr 02/28/07 Added cache handling macros.
* 1.00a wgr 02/27/07 Simplified code. Deprecated old-style macro names.
* 1.00a rmm 01/24/06 Implemented XENV_USLEEP. Assume implementation is being
* used under Xilinx standalone BSP.
* 1.00a xd 11/03/04 Improved support for doxygen.
* 1.00a rmm 03/21/02 First release
* 1.00a wgr 03/22/07 Converted to new coding style.
* 1.00a rpm 06/29/07 Added udelay macro for standalone
* 1.00a xd 07/19/07 Included xparameters.h as XPAR_ constants are referred
* to in MICROBLAZE section
* 1.00a ecm 09/19/08 updated for v7.20 of Microblaze, new functionality
*
* </pre>
*
*
******************************************************************************/
#ifndef XENV_STANDALONE_H
#define XENV_STANDALONE_H
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
/******************************************************************************
*
* Get the processor dependent includes
*
******************************************************************************/
#include <string.h>
#if defined __MICROBLAZE__
# include "mb_interface.h"
# include "xparameters.h" /* XPAR constants used below in MB section */
#elif defined __PPC__
# include "sleep.h"
# include "xcache_l.h" /* also include xcache_l.h for caching macros */
#endif
/******************************************************************************
*
* MEMCPY / MEMSET related macros.
*
* The following are straight forward implementations of memset and memcpy.
*
* NOTE: memcpy may not work if source and target memory area are overlapping.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* Copies a non-overlapping block of memory.
*
* @param DestPtr
* Destination address to copy data to.
*
* @param SrcPtr
* Source address to copy data from.
*
* @param Bytes
* Number of bytes to copy.
*
* @return None.
*
* @note
* The use of XENV_MEM_COPY is deprecated. Use memcpy() instead.
*
* @note
* This implemention MAY BREAK work if source and target memory
* area are overlapping.
*
*****************************************************************************/
#define XENV_MEM_COPY(DestPtr, SrcPtr, Bytes) \
memcpy((void *) DestPtr, (const void *) SrcPtr, (size_t) Bytes)
/*****************************************************************************/
/**
*
* Fills an area of memory with constant data.
*
* @param DestPtr
* Destination address to copy data to.
*
* @param Data
* Value to set.
*
* @param Bytes
* Number of bytes to copy.
*
* @return None.
*
* @note
* The use of XENV_MEM_FILL is deprecated. Use memset() instead.
*
*****************************************************************************/
#define XENV_MEM_FILL(DestPtr, Data, Bytes) \
memset((void *) DestPtr, (int) Data, (size_t) Bytes)
/******************************************************************************
*
* TIME related macros
*
******************************************************************************/
/**
* A structure that contains a time stamp used by other time stamp macros
* defined below. This structure is processor dependent.
*/
typedef int XENV_TIME_STAMP;
/*****************************************************************************/
/**
*
* Time is derived from the 64 bit PPC timebase register
*
* @param StampPtr is the storage for the retrieved time stamp.
*
* @return None.
*
* @note
*
* Signature: void XENV_TIME_STAMP_GET(XTIME_STAMP *StampPtr)
* <br><br>
* This macro must be implemented by the user.
*
*****************************************************************************/
#define XENV_TIME_STAMP_GET(StampPtr)
/*****************************************************************************/
/**
*
* This macro is not yet implemented and always returns 0.
*
* @param Stamp1Ptr is the first sampled time stamp.
* @param Stamp2Ptr is the second sampled time stamp.
*
* @return 0
*
* @note
*
* This macro must be implemented by the user.
*
*****************************************************************************/
#define XENV_TIME_STAMP_DELTA_US(Stamp1Ptr, Stamp2Ptr) (0)
/*****************************************************************************/
/**
*
* This macro is not yet implemented and always returns 0.
*
* @param Stamp1Ptr is the first sampled time stamp.
* @param Stamp2Ptr is the second sampled time stamp.
*
* @return 0
*
* @note
*
* This macro must be implemented by the user.
*
*****************************************************************************/
#define XENV_TIME_STAMP_DELTA_MS(Stamp1Ptr, Stamp2Ptr) (0)
/*****************************************************************************/
/**
* XENV_USLEEP(unsigned delay)
*
* Delay the specified number of microseconds. Not implemented without OS
* support.
*
* @param delay
* Number of microseconds to delay.
*
* @return None.
*
*****************************************************************************/
#ifdef __PPC__
#define XENV_USLEEP(delay) usleep(delay)
#define udelay(delay) usleep(delay)
#else
#define XENV_USLEEP(delay)
#define udelay(delay)
#endif
/******************************************************************************
*
* CACHE handling macros / mappings
*
******************************************************************************/
/******************************************************************************
*
* Processor independent macros
*
******************************************************************************/
#define XCACHE_ENABLE_CACHE() \
{ XCACHE_ENABLE_DCACHE(); XCACHE_ENABLE_ICACHE(); }
#define XCACHE_DISABLE_CACHE() \
{ XCACHE_DISABLE_DCACHE(); XCACHE_DISABLE_ICACHE(); }
/******************************************************************************
*
* MicroBlaze case
*
* NOTE: Currently the following macros will only work on systems that contain
* only ONE MicroBlaze processor. Also, the macros will only be enabled if the
* system is built using a xparameters.h file.
*
******************************************************************************/
#if defined __MICROBLAZE__
/* Check if MicroBlaze data cache was built into the core.
*/
#if (XPAR_MICROBLAZE_USE_DCACHE == 1)
# define XCACHE_ENABLE_DCACHE() microblaze_enable_dcache()
# define XCACHE_DISABLE_DCACHE() microblaze_disable_dcache()
# define XCACHE_INVALIDATE_DCACHE() microblaze_invalidate_dcache()
# define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len) \
microblaze_invalidate_dcache_range((int)(Addr), (int)(Len))
#if (XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK == 1)
# define XCACHE_FLUSH_DCACHE() microblaze_flush_dcache()
# define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \
microblaze_flush_dcache_range((int)(Addr), (int)(Len))
#else
# define XCACHE_FLUSH_DCACHE() microblaze_invalidate_dcache()
# define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \
microblaze_invalidate_dcache_range((int)(Addr), (int)(Len))
#endif /*XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK*/
#else
# define XCACHE_ENABLE_DCACHE()
# define XCACHE_DISABLE_DCACHE()
# define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len)
# define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len)
#endif /*XPAR_MICROBLAZE_USE_DCACHE*/
/* Check if MicroBlaze instruction cache was built into the core.
*/
#if (XPAR_MICROBLAZE_USE_ICACHE == 1)
# define XCACHE_ENABLE_ICACHE() microblaze_enable_icache()
# define XCACHE_DISABLE_ICACHE() microblaze_disable_icache()
# define XCACHE_INVALIDATE_ICACHE() microblaze_invalidate_icache()
# define XCACHE_INVALIDATE_ICACHE_RANGE(Addr, Len) \
microblaze_invalidate_icache_range((int)(Addr), (int)(Len))
#else
# define XCACHE_ENABLE_ICACHE()
# define XCACHE_DISABLE_ICACHE()
#endif /*XPAR_MICROBLAZE_USE_ICACHE*/
/******************************************************************************
*
* PowerPC case
*
* Note that the XCACHE_ENABLE_xxx functions are hardcoded to enable a
* specific memory region (0x80000001). Each bit (0-30) in the regions
* bitmask stands for 128MB of memory. Bit 31 stands for the upper 2GB
* range.
*
* regions --> cached address range
* ------------|--------------------------------------------------
* 0x80000000 | [0, 0x7FFFFFF]
* 0x00000001 | [0xF8000000, 0xFFFFFFFF]
* 0x80000001 | [0, 0x7FFFFFF],[0xF8000000, 0xFFFFFFFF]
*
******************************************************************************/
#elif defined __PPC__
#define XCACHE_ENABLE_DCACHE() XCache_EnableDCache(0x80000001)
#define XCACHE_DISABLE_DCACHE() XCache_DisableDCache()
#define XCACHE_ENABLE_ICACHE() XCache_EnableICache(0x80000001)
#define XCACHE_DISABLE_ICACHE() XCache_DisableICache()
#define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len) \
XCache_InvalidateDCacheRange((unsigned int)(Addr), (unsigned)(Len))
#define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \
XCache_FlushDCacheRange((unsigned int)(Addr), (unsigned)(Len))
#define XCACHE_INVALIDATE_ICACHE() XCache_InvalidateICache()
/******************************************************************************
*
* Unknown processor / architecture
*
******************************************************************************/
#else
/* #error "Unknown processor / architecture. Must be MicroBlaze or PowerPC." */
#endif
#ifdef __cplusplus
}
#endif
#endif /* #ifndef XENV_STANDALONE_H */

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/******************************************************************************
*
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
* AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
* SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE,
* OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
* APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
* THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE.
*
* (c) Copyright 2002-2007 Xilinx Inc.
* All rights reserved.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xenv_vxworks.h
*
* Defines common services specified by xenv.h.
*
* @note
* This file is not intended to be included directly by driver code.
* Instead, the generic xenv.h file is intended to be included by driver
* code.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.00a wgr 02/28/07 Added cache handling macros.
* 1.00a wgr 02/27/07 Simplified code. Deprecated old-style macro names.
* 1.00a xd 11/03/04 Improved support for doxygen.
* rmm 09/13/03 CR 177068: Fix compiler warning in XENV_MEM_FILL
* rmm 10/24/02 Added XENV_USLEEP macro
* 1.00a rmm 07/16/01 First release
* 1.10a wgr 03/22/07 Converted to new coding style.
* </pre>
*
*
******************************************************************************/
#ifndef XENV_VXWORKS_H
#define XENV_VXWORKS_H
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xbasic_types.h"
#include "vxWorks.h"
#include "vxLib.h"
#include "sysLibExtra.h"
#include "cacheLib.h"
#include <string.h>
/*****************************************************************************/
/**
*
* Copies a non-overlapping block of memory.
*
* @param DestPtr
* Destination address to copy data to.
*
* @param SrcPtr
* Source address to copy data from.
*
* @param Bytes
* Number of bytes to copy.
*
* @return None.
*
* @note XENV_MEM_COPY is deprecated. Use memcpy() instead.
*
*****************************************************************************/
#define XENV_MEM_COPY(DestPtr, SrcPtr, Bytes) \
memcpy((void *) DestPtr, (const void *) SrcPtr, (size_t) Bytes)
/*****************************************************************************/
/**
*
* Fills an area of memory with constant data.
*
* @param DestPtr
* Destination address to copy data to.
*
* @param Data
* Value to set.
*
* @param Bytes
* Number of bytes to copy.
*
* @return None.
*
* @note XENV_MEM_FILL is deprecated. Use memset() instead.
*
*****************************************************************************/
#define XENV_MEM_FILL(DestPtr, Data, Bytes) \
memset((void *) DestPtr, (int) Data, (size_t) Bytes)
#if (CPU_FAMILY==PPC)
/**
* A structure that contains a time stamp used by other time stamp macros
* defined below. This structure is processor dependent.
*/
typedef struct
{
u32 TimeBaseUpper;
u32 TimeBaseLower;
} XENV_TIME_STAMP;
/*****************************************************************************/
/**
*
* Time is derived from the 64 bit PPC timebase register
*
* @param StampPtr is the storage for the retrieved time stamp.
*
* @return None.
*
* @note
*
* Signature: void XENV_TIME_STAMP_GET(XTIME_STAMP *StampPtr)
*
*****************************************************************************/
#define XENV_TIME_STAMP_GET(StampPtr) \
{ \
vxTimeBaseGet((UINT32*)&(StampPtr)->TimeBaseUpper, \
(UINT32*)&(StampPtr)->TimeBaseLower); \
}
/*****************************************************************************/
/**
*
* This macro is not yet implemented and always returns 0.
*
* @param Stamp1Ptr is the first sampled time stamp.
* @param Stamp2Ptr is the second sampled time stamp.
*
* @return 0
*
* @note None.
*
*****************************************************************************/
#define XENV_TIME_STAMP_DELTA_US(Stamp1Ptr, Stamp2Ptr) (0)
/*****************************************************************************/
/**
*
* This macro is not yet implemented and always returns 0.
*
* @param Stamp1Ptr is the first sampled time stamp.
* @param Stamp2Ptr is the second sampled time stamp.
*
* @return 0
*
* @note
*
* None.
*
*****************************************************************************/
#define XENV_TIME_STAMP_DELTA_MS(Stamp1Ptr, Stamp2Ptr) (0)
/* For non-PPC systems the above macros are not defined. Generate a error to
* make the developer aware of the problem.
*/
#else
#error "XENV_TIME_STAMP_GET used in a non-PPC system. Aborting."
#endif
/*****************************************************************************/
/**
*
* Delay the specified number of microseconds.
*
* @param delay
* Number of microseconds to delay.
*
* @return None.
*
*****************************************************************************/
#define XENV_USLEEP(delay) sysUsDelay(delay)
#define udelay(delay) sysUsDelay(delay)
/******************************************************************************
*
* CACHE handling macros / mappings
*
******************************************************************************/
/******************************************************************************
*
* PowerPC case
*
******************************************************************************/
#if (CPU_FAMILY==PPC)
#define XCACHE_ENABLE_CACHE() \
{ XCACHE_ENABLE_DCACHE(); XCACHE_ENABLE_ICACHE(); }
#define XCACHE_DISABLE_CACHE() \
{ XCACHE_DISABLE_DCACHE(); XCACHE_DISABLE_ICACHE(); }
#define XCACHE_ENABLE_DCACHE() cacheEnable(DATA_CACHE)
#define XCACHE_DISABLE_DCACHE() cacheDisable(DATA_CACHE)
#define XCACHE_ENABLE_ICACHE() cacheEnable(INSTRUCTION_CACHE)
#define XCACHE_DISABLE_ICACHE() cacheDisable(INSTRUCTION_CACHE)
#define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len) \
cacheInvalidate(DATA_CACHE, (void *)(Addr), (Len))
#define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \
cacheFlush(DATA_CACHE, (void *)(Addr), (Len))
#define XCACHE_INVALIDATE_ICACHE_RANGE(Addr, Len) \
cacheInvalidate(INSTRUCTION_CACHE, (void *)(Addr), (Len))
#define XCACHE_FLUSH_ICACHE_RANGE(Addr, Len) \
cacheFlush(INSTRUCTION_CACHE, (void *)(Addr), (Len))
/******************************************************************************
*
* Unknown processor / architecture
*
******************************************************************************/
#else
#error "Unknown processor / architecture. Must be PPC for VxWorks."
#endif
#ifdef __cplusplus
}
#endif
#endif /* #ifdef XENV_VXWORKS_H */

738
software/LED_Controller_bsp/microblaze_mcs/libsrc/common_v1_00_a/src/xparameters.h Executable file
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/* $Id: xparameters.h,v 1.83.2.11 2011/05/18 03:23:57 svemula Exp $ */
/******************************************************************************
*
* (c) Copyright 2002-2011 Xilinx, Inc. All rights reserved.
*
* This file contains confidential and proprietary information of Xilinx, Inc.
* and is protected under U.S. and international copyright and other
* intellectual property laws.
*
* DISCLAIMER
* This disclaimer is not a license and does not grant any rights to the
* materials distributed herewith. Except as otherwise provided in a valid
* license issued to you by Xilinx, and to the maximum extent permitted by
* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
* and (2) Xilinx shall not be liable (whether in contract or tort, including
* negligence, or under any other theory of liability) for any loss or damage
* of any kind or nature related to, arising under or in connection with these
* materials, including for any direct, or any indirect, special, incidental,
* or consequential loss or damage (including loss of data, profits, goodwill,
* or any type of loss or damage suffered as a result of any action brought by
* a third party) even if such damage or loss was reasonably foreseeable or
* Xilinx had been advised of the possibility of the same.
*
* CRITICAL APPLICATIONS
* Xilinx products are not designed or intended to be fail-safe, or for use in
* any application requiring fail-safe performance, such as life-support or
* safety devices or systems, Class III medical devices, nuclear facilities,
* applications related to the deployment of airbags, or any other applications
* that could lead to death, personal injury, or severe property or
* environmental damage (individually and collectively, "Critical
* Applications"). Customer assumes the sole risk and liability of any use of
* Xilinx products in Critical Applications, subject only to applicable laws
* and regulations governing limitations on product liability.
*
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
* AT ALL TIMES.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xparameters.h
*
* This file contains system parameters for the Xilinx device driver environment.
* It is a representation of the system in that it contains the number of each
* device in the system as well as the parameters and memory map for each
* device. The user can view this file to obtain a summary of the devices in
* their system and the device parameters.
*
* This file may be automatically generated by a design tool such as System
* Generator.
*
******************************************************************************/
/***************************** Include Files *********************************/
#ifndef XPARAMETERS_H /* prevent circular inclusions */
#define XPARAMETERS_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/* unifying driver changes
added XPAR_INTC_0_ACK_BEFORE, XPAR_INTC_1_ACK_BEFORE
changed XPAR_INTC_MAX_ID to XPAR_INTC_MAX_NUM_INTR_INPUTS
deleted XPAR_INTC_0_MAX_ID, XPAR_INTC_1_MAX_ID
*/
/************************** Constant Definitions *****************************/
/*
* The following constants are for each device.
*
* An instance must exist for each physical device that exists in the system.
* The device IDs in the following constants are unique between all devices to
* allow device IDs to be searched in the future.
*/
/*****************************************************************************
*
* System Level defines. These constants are for devices that do not require
* a device driver. Examples of these types of devices include volatile RAM
* devices.
*/
#define XPAR_ZBT_NUM_INSTANCES 1
#define XPAR_ZBT_0_BASE 0x00000000
#define XPAR_ZBT_0_SIZE 0x00100000
#define XPAR_SRAM_NUM_INSTANCES 1
#define XPAR_SRAM_0_BASE 0x00100000
#define XPAR_SRAM_0_SIZE 0x00200000
#define XPAR_DDR_NUM_INSTANCES 1
#define XPAR_DDR_0_BASE 0xF0000000
#define XPAR_DDR_0_SIZE 0x01000000
#define XPAR_CORE_CLOCK_FREQ_HZ 12500000
#define XPAR_CPU_PPC405_CORE_CLOCK_FREQ_HZ XPAR_CORE_CLOCK_FREQ_HZ
/*****************************************************************************
*
* Interrupt Controller (Intc) defines.
* DeviceID starts at 0
*/
#define XPAR_XINTC_NUM_INSTANCES 2 /* Number of instances */
#define XPAR_INTC_MAX_NUM_INTR_INPUTS 31 /* max # inputs of all */
#define XPAR_INTC_SINGLE_BASEADDR 0x70800000 /* low level driver base */
#define XPAR_INTC_SINGLE_DEVICE_ID 0 /* single instance ID */
#define XPAR_INTC_SINGLE_ACK_BEFORE 0xFFFF00FF /* low level driver */
#define XPAR_INTC_0_DEVICE_ID 1 /* Device ID for instance */
#define XPAR_INTC_0_ACK_BEFORE 0xFFFF00FF /* Ack timing, before/after */
#define XPAR_INTC_0_BASEADDR 0x70800000 /* Register base address */
#define XPAR_INTC_0_UARTLITE_0_VEC_ID 4 /* Interrupt source for vector */
#define XPAR_INTC_0_WDTTB_0_VEC_ID 5 /* Interrupt source for vector */
#define XPAR_INTC_0_WD_0_VEC_ID 6 /* Interrupt source for vector */
#define XPAR_INTC_0_TMRCTR_0_VEC_ID 7 /* Interrupt source for vector */
#define XPAR_INTC_0_SPI_0_VEC_ID 11 /* Interrupt source for vector */
#define XPAR_INTC_0_IIC_0_VEC_ID 12 /* Interrupt source for vector */
#define XPAR_INTC_0_UARTNS550_0_VEC_ID 13 /* Interrupt source for vector */
#define XPAR_INTC_0_UARTNS550_1_VEC_ID 14 /* Interrupt source for vector */
#define XPAR_INTC_0_EMAC_0_VEC_ID 15 /* Interrupt source for vector */
#define XPAR_INTC_0_AXIDMA_0_S2MM_INTROUT_VEC_ID 16 /* Intr ID for AXIDMA rx */
#define XPAR_INTC_0_AXIDMA_0_MM2S_INTROUT_VEC_ID 17 /* Intr ID for AXIDMA tx */
#define XPAR_INTC_0_AXICDMA_0_VEC_ID 18 /* Intr ID for AXICDMA */
#define XPAR_INTC_0_AXIVDMA_0_S2MM_INTROUT_VEC_ID 19 /* AXIVDMA write intr */
#define XPAR_INTC_0_AXIVDMA_0_MM2S_INTROUT_VEC_ID 20 /* AXIVDMA read intr */
#define XPAR_INTC_1_DEVICE_ID 2 /* Device ID for instance */
#define XPAR_INTC_1_ACK_BEFORE 0xFFFF00FF /* Ack timing, before/after */
#define XPAR_INTC_1_BASEADDR 0x70800020 /* Register base address */
#define XPAR_INTC_1_OPB_TO_PLB_ERR_VEC_ID 0 /* Interrupt source for vector */
#define XPAR_INTC_1_PLB_TO_OPB_ERR_VEC_ID 1 /* Interrupt source for vector */
/*****************************************************************************
*
* AXI DMA defines
*/
#define XPAR_XAXIDMA_NUM_INSTANCES 1
#define XPAR_AXI_DMA_0_DEVICE_ID 0
#define XPAR_AXI_DMA_0_BASEADDR 0x40000000
#define XPAR_AXI_DMA_0_HIGHADDR 0x4000007F
#define XPAR_AXI_DMA_0_SG_INCLUDE_STSCNTRL_STRM 1
#define XPAR_AXI_DMA_0_INCLUDE_MM2S_DRE 1
#define XPAR_AXI_DMA_0_INCLUDE_S2MM_DRE 1
#define XPAR_AXI_DMA_0_INCLUDE_MM2S 1
#define XPAR_AXI_DMA_0_INCLUDE_S2MM 1
#define XPAR_AXI_DMA_0_M_AXIS_MM2S_DATA_WIDTH 32
#define XPAR_AXI_DMA_0_S_AXIS_S2MM_DATA_WIDTH 32
/*****************************************************************************
*
* AXI Central DMA defines
*/
#define XPAR_XAXICDMA_NUM_INSTANCES 1
#define XPAR_AXI_CDMA_0_DEVICE_ID 0
#define XPAR_AXI_CDMA_0_BASEADDR 0x40001000
#define XPAR_AXI_CDMA_0_HIGHADDR 0x4000107F
#define XPAR_AXI_CDMA_0_INCLUDE_DRE 1
#define XPAR_AXI_CDMA_0_USE_DATAMOVER_LITE 0
#define XPAR_AXI_CDMA_0_M_AXI_DATA_WIDTH 32
/*****************************************************************************
*
* AXI Video DMA defines
*/
#define XPAR_XAXIVDMA_NUM_INSTANCES 1
#define XPAR_AXI_VDMA_0_DEVICE_ID 0
#define XPAR_AXI_VDMA_0_BASEADDR 0x40002000
#define XPAR_AXI_VDMA_0_NUM_FSTORES 16
#define XPAR_AXI_VDMA_0_INCLUDE_MM2S 1
#define XPAR_AXI_VDMA_0_INCLUDE_MM2S_DRE 1
#define XPAR_AXI_VDMA_0_M_AXIS_MM2S_DATA_WIDTH 32
#define XPAR_AXI_VDMA_0_INCLUDE_S2MM 1
#define XPAR_AXI_VDMA_0_INCLUDE_S2MM_DRE 1
#define XPAR_AXI_VDMA_0_S_AXIS_S2MM_DATA_WIDTH 32
/*****************************************************************************
*
* Ethernet 10/100 MAC defines.
* DeviceID starts at 10
*/
#define XPAR_XEMAC_NUM_INSTANCES 1 /* Number of instances */
#define XPAR_EMAC_0_DEVICE_ID 10 /* Device ID for instance */
#define XPAR_EMAC_0_BASEADDR 0x60000000/* Device base address */
#define XPAR_EMAC_0_DMA_PRESENT FALSE /* Does device have DMA? */
#define XPAR_EMAC_0_ERR_COUNT_EXIST TRUE /* Does device have counters? */
#define XPAR_EMAC_0_MII_EXIST TRUE /* Does device support MII? */
/*****************************************************************************
*
* NS16550 UART defines.
* DeviceID starts at 20
*/
#define XPAR_XUARTNS550_NUM_INSTANCES 1 /* Number of instances */
#define XPAR_UARTNS550_0_DEVICE_ID 20 /* Device ID for instance */
#define XPAR_UARTNS550_0_BASEADDR 0xA0010000 /* IPIF base address */
#define XPAR_UARTNS550_0_CLOCK_HZ (66000000L)/* 66 MHz clock */
#define XPAR_UARTNS550_1_DEVICE_ID 21 /* Device ID for instance */
#define XPAR_UARTNS550_1_BASEADDR 0xA0000000 /* IPIF base address */
#define XPAR_UARTNS550_1_CLOCK_HZ (66000000L)/* 66 MHz clock */
/*****************************************************************************
*
* UartLite defines.
* DeviceID starts at 30
*/
#define XPAR_XUARTLITE_NUM_INSTANCES 1 /* Number of instances */
#define XPAR_UARTLITE_0_DEVICE_ID 30 /* Device ID for instance */
#define XPAR_UARTLITE_0_BASEADDR 0xA0020000 /* Device base address */
#define XPAR_UARTLITE_0_BAUDRATE 19200 /* Baud rate */
#define XPAR_UARTLITE_0_USE_PARITY FALSE /* Parity generator enabled */
#define XPAR_UARTLITE_0_ODD_PARITY FALSE /* Type of parity generated */
#define XPAR_UARTLITE_0_DATA_BITS 8 /* Data bits */
/*****************************************************************************
*
* ATM controller defines.
* DeviceID starts at 40
*/
#define XPAR_XATMC_NUM_INSTANCES 1 /* Number of instances */
#define XPAR_ATMC_0_DEVICE_ID 40 /* Device ID for instance */
#define XPAR_ATMC_0_BASEADDR 0x70000000 /* Device base address */
#define XPAR_ATMC_0_DMA_PRESENT FALSE /* Does device have DMA? */
/*****************************************************************************
*
* Serial Peripheral Interface (SPI) defines.
* DeviceID starts at 50
*/
#define XPAR_XSPI_NUM_INSTANCES 2 /* Number of instances */
#define XPAR_SPI_0_DEVICE_ID 50 /* Device ID for instance */
#define XPAR_SPI_0_BASEADDR 0x50000000 /* Device base address */
#define XPAR_SPI_0_FIFO_EXIST TRUE /* Does device have FIFOs? */
#define XPAR_SPI_0_SLAVE_ONLY FALSE /* Is the device slave only? */
#define XPAR_SPI_0_NUM_SS_BITS 32 /* Number of slave select bits */
#define XPAR_SPI_1_DEVICE_ID 51 /* Device ID for instance */
#define XPAR_SPI_1_BASEADDR 0x50000100 /* IPIF base address */
#define XPAR_SPI_1_FIFO_EXIST TRUE /* Does device have FIFOs? */
#define XPAR_SPI_1_SLAVE_ONLY FALSE /* Is the device slave only? */
#define XPAR_SPI_1_NUM_SS_BITS 32 /* Number of slave select bits */
/*****************************************************************************
*
* OPB Arbiter defines.
* DeviceID starts at 60
*/
#define XPAR_XOPBARB_NUM_INSTANCES 1 /* Number of instances */
#define XPAR_OPBARB_0_DEVICE_ID 60 /* Device ID for instance */
#define XPAR_OPBARB_0_BASEADDR 0x80000000 /* Register base address */
#define XPAR_OPBARB_0_NUM_MASTERS 8 /* Number of masters on bus */
/*****************************************************************************
*
* Watchdog timer/timebase (WdtTb) defines.
* DeviceID starts at 70
*/
#define XPAR_XWDTTB_NUM_INSTANCES 1 /* Number of instances */
#define XPAR_WDTTB_0_DEVICE_ID 70 /* Device ID for instance */
#define XPAR_WDTTB_0_BASEADDR 0x70800040 /* Register base address */
/*****************************************************************************
*
* Timer Counter (TmrCtr) defines.
* DeviceID starts at 80
*/
#define XPAR_XTMRCTR_NUM_INSTANCES 2 /* Number of instances */
#define XPAR_TMRCTR_0_DEVICE_ID 80 /* Device ID for instance */
#define XPAR_TMRCTR_0_BASEADDR 0x70800100 /* Register base address */
/*****************************************************************************
*
* IIC defines.
* DeviceID starts at 90
*/
#define XPAR_XIIC_NUM_INSTANCES 2 /* Number of instances */
#define XPAR_IIC_0_DEVICE_ID 90 /* Device ID for instance */
#define XPAR_IIC_0_BASEADDR 0xA8000000 /* Device base address */
#define XPAR_IIC_0_TEN_BIT_ADR TRUE /* Supports 10 bit addresses */
#define XPAR_IIC_1_DEVICE_ID 91 /* Device ID for instance */
#define XPAR_IIC_1_BASEADDR 0xA8000000 /* Device base address */
#define XPAR_IIC_1_TEN_BIT_ADR TRUE /* Supports 10 bit addresses */
/*****************************************************************************
*
* Flash defines.
* DeviceID starts at 100
*/
#define XPAR_XFLASH_NUM_INSTANCES 1 /* Number of instances */
#define XPAR_FLASH_INTEL_SUPPORT /* Include intel flash support */
#define XPAR_FLASH_0_DEVICE_ID 100 /* Device ID for first instance
*/
#define XPAR_FLASH_0_BASEADDR 0xFF000000 /* Base address of parts */
#define XPAR_FLASH_0_NUM_PARTS 2 /* Number of parts in array */
#define XPAR_FLASH_0_PART_WIDTH 2 /* Width of each part in bytes */
#define XPAR_FLASH_0_PART_MODE 2 /* Mode of each part in bytes */
/*****************************************************************************
*
* GPIO defines.
* DeviceID starts at 110
*/
#define XPAR_XGPIO_NUM_INSTANCES 1
#define XPAR_GPIO_0_DEVICE_ID 110 /* Device ID for instance */
#define XPAR_GPIO_0_BASEADDR 0x90000000 /* Register base address */
#define XPAR_GPIO_0_INTERRUPT_PRESENT 0 /* Interrupts supported? */
#define XPAR_GPIO_0_IS_DUAL 0 /* Dual channels supported? */
/*****************************************************************************
*
* EMC defines.
* DeviceID starts at 120
*/
#define XPAR_XEMC_NUM_INSTANCES 1
#define XPAR_EMC_0_DEVICE_ID 120 /* Device ID for instance */
#define XPAR_EMC_0_BASEADDR 0xE0000000 /* Register base address */
#define XPAR_EMC_0_NUM_BANKS_MEM 3 /* Number of banks */
/*****************************************************************************
*
* PLB Arbiter defines.
* DeviceID starts at 130
*/
#define XPAR_XPLBARB_NUM_INSTANCES 1
#define XPAR_PLBARB_0_DEVICE_ID 130 /* Device ID for instance */
#define XPAR_PLBARB_0_BASEADDR 0x300 /* Register base address */
#define XPAR_PLBARB_0_NUM_MASTERS 1 /* Number of masters on bus */
/*****************************************************************************
*
* PLB To OPB Bridge defines.
* DeviceID starts at 140
*/
#define XPAR_XPLB2OPB_NUM_INSTANCES 1
#define XPAR_PLB2OPB_0_DEVICE_ID 140 /* Device ID for instance */
#define XPAR_PLB2OPB_0_DCR_BASEADDR 0x0 /* DCR Register base address
*/
#define XPAR_PLB2OPB_0_NUM_MASTERS 1 /* Number of masters on bus
*/
/*****************************************************************************
*
* OPB To PLB Bridge defines.
* DeviceID starts at 150
*/
#define XPAR_XOPB2PLB_NUM_INSTANCES 1
#define XPAR_XOPB2PLB_ANY_OPB_REG_INTF /* Accessible from OPB, not DCR */
#define XPAR_OPB2PLB_0_DEVICE_ID 150 /* Device ID for instance */
#define XPAR_OPB2PLB_0_OPB_BASEADDR 0x0 /* Register base address */
#define XPAR_OPB2PLB_0_DCR_BASEADDR 0x0 /* DCR Register base address */
/*****************************************************************************
*
* System ACE defines.
* DeviceID starts at 160
*/
#define XPAR_XSYSACE_NUM_INSTANCES 1
#define XPAR_SYSACE_0_DEVICE_ID 160 /* Device ID for instance */
#define XPAR_SYSACE_0_BASEADDR 0xCF000000 /* Register base address */
/*****************************************************************************
*
* HDLC defines.
* DeviceID starts at 170
*/
#define XPAR_XHDLC_NUM_INSTANCES 1
#define XPAR_HDLC_0_DEVICE_ID 170 /* Device ID for instance */
#define XPAR_HDLC_0_BASEADDR 0x60010000 /* Register base address */
#define XPAR_HDLC_0_TX_MEM_DEPTH 2048 /* Tx FIFO depth (bytes) */
#define XPAR_HDLC_0_RX_MEM_DEPTH 2048 /* Rx FIFO depth (bytes) */
#define XPAR_HDLC_0_DMA_PRESENT 3 /* DMA SG in hardware */
/*****************************************************************************
*
* PS2 Reference driver defines.
* DeviceID starts at 180
*/
#define XPAR_XPS2_NUM_INSTANCES 2
#define XPAR_PS2_0_DEVICE_ID 180 /* Device ID for instance */
#define XPAR_PS2_0_BASEADDR 0x40010000 /* Register base address */
#define XPAR_PS2_1_DEVICE_ID 181 /* Device ID for instance */
#define XPAR_PS2_1_BASEADDR 0x40020000 /* Register base address */
/*****************************************************************************
*
* Rapid IO defines.
* DeviceID starts at 190
*/
#define XPAR_XRAPIDIO_NUM_INSTANCES 1
#define XPAR_RAPIDIO_0_DEVICE_ID 190 /* Device ID for instance */
#define XPAR_RAPIDIO_0_BASEADDR 0x60000000 /* Register base address */
/*****************************************************************************
*
* PCI defines.
* DeviceID starts at 200
*/
#define XPAR_XPCI_NUM_INSTANCES 1
#define XPAR_OPB_PCI_1_DEVICE_ID 200
#define XPAR_OPB_PCI_1_BASEADDR 0x86000000
#define XPAR_OPB_PCI_1_HIGHADDR 0x860001FF
#define XPAR_OPB_PCI_1_PCIBAR_0 0x10000000
#define XPAR_OPB_PCI_1_PCIBAR_LEN_0 27
#define XPAR_OPB_PCI_1_PCIBAR2IPIF_0 0xF0000000
#define XPAR_OPB_PCI_1_PCIBAR_ENDIAN_TRANSLATE_EN_0 0
#define XPAR_OPB_PCI_1_PCI_PREFETCH_0 1
#define XPAR_OPB_PCI_1_PCI_SPACETYPE_0 1
#define XPAR_OPB_PCI_1_PCIBAR_1 0x3F000000
#define XPAR_OPB_PCI_1_PCIBAR_LEN_1 15
#define XPAR_OPB_PCI_1_PCIBAR2IPIF_1 0xC0FF8000
#define XPAR_OPB_PCI_1_PCIBAR_ENDIAN_TRANSLATE_EN_1 0
#define XPAR_OPB_PCI_1_PCI_PREFETCH_1 1
#define XPAR_OPB_PCI_1_PCI_SPACETYPE_1 1
#define XPAR_OPB_PCI_1_PCIBAR_2 0x5F000000
#define XPAR_OPB_PCI_1_PCIBAR_LEN_2 16
#define XPAR_OPB_PCI_1_PCIBAR2IPIF_2 0x00000000
#define XPAR_OPB_PCI_1_PCIBAR_ENDIAN_TRANSLATE_EN_2 0
#define XPAR_OPB_PCI_1_PCI_PREFETCH_2 1
#define XPAR_OPB_PCI_1_PCI_SPACETYPE_2 1
#define XPAR_OPB_PCI_1_IPIFBAR_0 0x80000000
#define XPAR_OPB_PCI_1_IPIF_HIGHADDR_0 0x81FFFFFF
#define XPAR_OPB_PCI_1_IPIFBAR2PCI_0 0xF0000000
#define XPAR_OPB_PCI_1_IPIFBAR_ENDIAN_TRANSLATE_EN_0 0
#define XPAR_OPB_PCI_1_IPIF_PREFETCH_0 1
#define XPAR_OPB_PCI_1_IPIF_SPACETYPE_0 1
#define XPAR_OPB_PCI_1_IPIFBAR_1 0x82000000
#define XPAR_OPB_PCI_1_IPIF_HIGHADDR_1 0x820007FF
#define XPAR_OPB_PCI_1_IPIFBAR2PCI_1 0xCE000000
#define XPAR_OPB_PCI_1_IPIFBAR_ENDIAN_TRANSLATE_EN_1 0
#define XPAR_OPB_PCI_1_IPIF_PREFETCH_1 1
#define XPAR_OPB_PCI_1_IPIF_SPACETYPE_1 1
#define XPAR_OPB_PCI_1_IPIFBAR_2 0x82320000
#define XPAR_OPB_PCI_1_IPIF_HIGHADDR_2 0x8232FFFF
#define XPAR_OPB_PCI_1_IPIFBAR2PCI_2 0x00010000
#define XPAR_OPB_PCI_1_IPIFBAR_ENDIAN_TRANSLATE_EN_2 0
#define XPAR_OPB_PCI_1_IPIF_PREFETCH_2 1
#define XPAR_OPB_PCI_1_IPIF_SPACETYPE_2 1
#define XPAR_OPB_PCI_1_IPIFBAR_3 0x82330000
#define XPAR_OPB_PCI_1_IPIF_HIGHADDR_3 0x8233FFFF
#define XPAR_OPB_PCI_1_IPIFBAR2PCI_3 0x00010000
#define XPAR_OPB_PCI_1_IPIFBAR_ENDIAN_TRANSLATE_EN_3 0
#define XPAR_OPB_PCI_1_IPIF_PREFETCH_3 1
#define XPAR_OPB_PCI_1_IPIF_SPACETYPE_3 0
#define XPAR_OPB_PCI_1_IPIFBAR_4 0x82340000
#define XPAR_OPB_PCI_1_IPIF_HIGHADDR_4 0x8234FFFF
#define XPAR_OPB_PCI_1_IPIFBAR2PCI_4 0x00010000
#define XPAR_OPB_PCI_1_IPIFBAR_ENDIAN_TRANSLATE_EN_4 0
#define XPAR_OPB_PCI_1_IPIF_PREFETCH_4 0
#define XPAR_OPB_PCI_1_IPIF_SPACETYPE_4 0
#define XPAR_OPB_PCI_1_IPIFBAR_5 0x82350000
#define XPAR_OPB_PCI_1_IPIF_HIGHADDR_5 0x8235FFFF
#define XPAR_OPB_PCI_1_IPIFBAR2PCI_5 0x00010000
#define XPAR_OPB_PCI_1_IPIFBAR_ENDIAN_TRANSLATE_EN_5 0
#define XPAR_OPB_PCI_1_IPIF_PREFETCH_5 1
#define XPAR_OPB_PCI_1_IPIF_SPACETYPE_5 1
#define XPAR_OPB_PCI_1_DMA_BASEADDR 0x87000000
#define XPAR_OPB_PCI_1_DMA_HIGHADDR 0x8700007F
#define XPAR_OPB_PCI_1_DMA_CHAN_TYPE 0
#define XPAR_OPB_PCI_1_DMA_LENGTH_WIDTH 11
/*****************************************************************************
*
* GEmac defines.
* DeviceID starts at 210
*/
#define XPAR_XGEMAC_NUM_INSTANCES 1
#define XPAR_GEMAC_0_DEVICE_ID 210
#define XPAR_GEMAC_0_BASEADDR 0x61000000
#define XPAR_GEMAC_0_DMA_TYPE 9
#define XPAR_GEMAC_0_MIIM_EXIST 0
#define XPAR_GEMAC_0_INCLUDE_STATS 0
/*****************************************************************************
*
* Touchscreen defines .
* DeviceID starts at 220
*/
#define XPAR_XTOUCHSCREEN_NUM_INSTANCES 1
#define XPAR_TOUCHSCREEN_0_DEVICE_ID 220
#define XPAR_TOUCHSCREEN_0_BASEADDR 0x70000000
/*****************************************************************************
*
* DDR defines .
* DeviceID starts at 230
*/
#define XPAR_XDDR_NUM_INSTANCES 1
#define XPAR_DDR_0_DEVICE_ID 230
#define XPAR_DDR_0_BASEADDR 0
#define XPAR_DDR_0_INTERRUPT_PRESENT 0
/*****************************************************************************
*
* EmacLite defines .
* DeviceID starts at 240
*/
#define XPAR_XEMACLITE_NUM_INSTANCES 1
#define XPAR_EMACLITE_0_DEVICE_ID 240
#define XPAR_EMACLITE_0_BASEADDR 0
#define XPAR_EMACLITE_0_TX_PING_PONG 0
#define XPAR_EMACLITE_0_RX_PING_PONG 0
/*****************************************************************************
*
* DSDAC defines .
* DeviceID starts at 250
*/
#define XPAR_XDSDAC_NUM_INSTANCES 1
#define XPAR_DSDAC_0_DEVICE_ID 250
#define XPAR_DSDAC_0_BASEADDR 0
/*****************************************************************************
*
* DSADC defines .
* DeviceID starts at 260
*/
#define XPAR_XDSADC_NUM_INSTANCES 1
#define XPAR_DSADC_0_DEVICE_ID 260
#define XPAR_DSADC_0_BASEADDR 0
/*****************************************************************************
*
* PCI Arbiter defines.
* DeviceID starts at 270
*/
#define XPAR_XPCIARB_NUM_INSTANCES 1
#define XPAR_OPB_PCI_ARBITER_0_DEVICE_ID 270
#define XPAR_OPB_PCI_ARBITER_0_BASEADDR 0
#define XPAR_OPB_PCI_ARBITER_0_NUM_PCI_MSTRS 2
/*****************************************************************************
*
* TEMAC defines .
* DeviceID starts at 280
*/
#define XPAR_XTEMAC_NUM_INSTANCES 1
#define XPAR_TEMAC_0_DEVICE_ID 280
#define XPAR_TEMAC_0_BASEADDR 0
#define XPAR_TEMAC_0_DMA_TYPE 3
#define XPAR_TEMAC_0_RDFIFO_DEPTH 131072
#define XPAR_TEMAC_0_WRFIFO_DEPTH 131072
#define XPAR_TEMAC_0_MAC_FIFO_DEPTH 16
#define XPAR_TEMAC_0_TEMAC_DCR_HOST 0
#define XPAR_TEMAC_0_DRE 0
/*****************************************************************************
*
* DMACENTRAL defines .
* DeviceID starts at 290
*/
#define XPAR_XDMACENTRAL_NUM_INSTANCES 1
#define XPAR_DMACENTRAL_0_DEVICE_ID 290
#define XPAR_DMACENTRAL_0_BASEADDR 0
#define XPAR_DMACENTRAL_0_READ_OPTIONAL_REGS 0
/*****************************************************************************
*
* CAN defines
* DeviceID starts at 300
*/
#define XPAR_XCAN_NUM_INSTANCES 1
#define XPAR_CAN_0_DEVICE_ID 300
/* Definitions for FLEXRAY Driver */
#define XPAR_XFLEXRAY_NUM_INSTANCES 1
#define XPAR_OPB_FLEXRAY_0_DEVICE_ID 0
#define XPAR_OPB_FLEXRAY_0_BASEADDR 0x7D80E000
#define XPAR_OPB_FLEXRAY_MAX_PAYLOAD_SIZE 254
#define XPAR_OPB_FLEXRAY_NO_OF_TX_BUFFERS 128
#define XPAR_OPB_FLEXRAY_NO_OF_RX_BUFFERS 128
#define XPAR_OPB_FLEXRAY_RX_FIFO_DEPTH 16
/* Definitions for MOST driver */
#define XPAR_XMOST_NUM_INSTANCES 1
#define XPAR_MOST_0_DEVICE_ID 0
#define XPAR_MOST_0_BASEADDR 0x7D810000
#define XPAR_MOST_OPMODE 0
#define XPAR_MOST_FWC 16
#define XPAR_MOST_EWC 16
/* Definitions for USB driver */
#define XPAR_XUSB_NUM_INSTANCES 1
#define XPAR_USB_0_DEVICE_ID 0
#define XPAR_USB_0_BASEADDR 0x7D813000
/*****************************************************************************
*
* HWICAP defines .
*/
#define XPAR_XHWICAP_NUM_INSTANCES 1
#define XPAR_OPB_HWICAP_0_DEVICE_ID 0
#define XPAR_OPB_HWICAP_0_BASEADDR 0xFFFFFFFF
/*****************************************************************************
*
* LLTEMAC and LLFIFO defines .
*/
#define XPAR_XLLTEMAC_NUM_INSTANCES 1
#define XPAR_XLLFIFO_NUM_INSTANCES 1
/*****************************************************************************
*
* PCIe defines .
*/
#define XPAR_XPCIE_NUM_INSTANCES 1
/*****************************************************************************
*
* MPMC defines .
*/
#define XPAR_XMPMC_NUM_INSTANCES 1
/*****************************************************************************
*
* SYSMON defines .
*/
#define XPAR_XSYSMON_NUM_INSTANCES 1
/*****************************************************************************
*
* AXI Ethernet defines .
*/
#define XPAR_XAXIETHERNET_NUM_INSTANCES 1
/*****************************************************************************
*
* TFT defines .
*/
#define XPAR_XTFT_NUM_INSTANCES 1
/*****************************************************************************
*
* MBox defines .
*/
#define XPAR_XMBOX_NUM_INSTANCES 1
#define XPAR_XMBOX_0_DEVICE_ID 0
#define XPAR_XMBOX_0_BASEADDR 0x7D814000
#define XPAR_XMBOX_0_NUM_CHANNELS 1
#define XPAR_XMBOX_0_USE_FSL 0
/*****************************************************************************
*
* Mutex defines .
*/
#define XPAR_XMUTEX_NUM_INSTANCES 1
#define XPAR_XMUTEX_0_DEVICE_ID 0
#define XPAR_XMUTEX_0_BASEADDR 0x7D815000
#define XPAR_XMUTEX_0_NUM_MUTEX 2
#define XPAR_XMUTEX_0_ENABLE_USER 1
/*
* MicroBlaze sets this define but for the build check to
* function it needs to be set here
*/
#define XPAR_CPU_ID 0
/*****************************************************************************
*
* BRAM defines .
*/
#define XPAR_XBRAM_NUM_INSTANCES 1
/*****************************************************************************
*
* AXI PCIE defines .
*/
#define XPAR_XAXIPCIE_NUM_INSTANCES 1
/*****************************************************************************
*
* V6 DDRX efines .
*/
#define XPAR_XV6DDR_NUM_INSTANCES 1
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */

418
software/LED_Controller_bsp/microblaze_mcs/libsrc/common_v1_00_a/src/xstatus.h Executable file
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@@ -0,0 +1,418 @@
/******************************************************************************
*
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
* AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
* SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE,
* OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
* APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
* THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE.
*
* (c) Copyright 2002-2011 Xilinx Inc.
* All rights reserved.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xstatus.h
*
* This file contains Xilinx software status codes. Status codes have their
* own data type called int. These codes are used throughout the Xilinx
* device drivers.
*
******************************************************************************/
#ifndef XSTATUS_H /* prevent circular inclusions */
#define XSTATUS_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xbasic_types.h"
/************************** Constant Definitions *****************************/
/*********************** Common statuses 0 - 500 *****************************/
#define XST_SUCCESS 0L
#define XST_FAILURE 1L
#define XST_DEVICE_NOT_FOUND 2L
#define XST_DEVICE_BLOCK_NOT_FOUND 3L
#define XST_INVALID_VERSION 4L
#define XST_DEVICE_IS_STARTED 5L
#define XST_DEVICE_IS_STOPPED 6L
#define XST_FIFO_ERROR 7L /* an error occurred during an
operation with a FIFO such as
an underrun or overrun, this
error requires the device to
be reset */
#define XST_RESET_ERROR 8L /* an error occurred which requires
the device to be reset */
#define XST_DMA_ERROR 9L /* a DMA error occurred, this error
typically requires the device
using the DMA to be reset */
#define XST_NOT_POLLED 10L /* the device is not configured for
polled mode operation */
#define XST_FIFO_NO_ROOM 11L /* a FIFO did not have room to put
the specified data into */
#define XST_BUFFER_TOO_SMALL 12L /* the buffer is not large enough
to hold the expected data */
#define XST_NO_DATA 13L /* there was no data available */
#define XST_REGISTER_ERROR 14L /* a register did not contain the
expected value */
#define XST_INVALID_PARAM 15L /* an invalid parameter was passed
into the function */
#define XST_NOT_SGDMA 16L /* the device is not configured for
scatter-gather DMA operation */
#define XST_LOOPBACK_ERROR 17L /* a loopback test failed */
#define XST_NO_CALLBACK 18L /* a callback has not yet been
registered */
#define XST_NO_FEATURE 19L /* device is not configured with
the requested feature */
#define XST_NOT_INTERRUPT 20L /* device is not configured for
interrupt mode operation */
#define XST_DEVICE_BUSY 21L /* device is busy */
#define XST_ERROR_COUNT_MAX 22L /* the error counters of a device
have maxed out */
#define XST_IS_STARTED 23L /* used when part of device is
already started i.e.
sub channel */
#define XST_IS_STOPPED 24L /* used when part of device is
already stopped i.e.
sub channel */
#define XST_DATA_LOST 26L /* driver defined error */
#define XST_RECV_ERROR 27L /* generic receive error */
#define XST_SEND_ERROR 28L /* generic transmit error */
#define XST_NOT_ENABLED 29L /* a requested service is not
available because it has not
been enabled */
/***************** Utility Component statuses 401 - 500 *********************/
#define XST_MEMTEST_FAILED 401L /* memory test failed */
/***************** Common Components statuses 501 - 1000 *********************/
/********************* Packet Fifo statuses 501 - 510 ************************/
#define XST_PFIFO_LACK_OF_DATA 501L /* not enough data in FIFO */
#define XST_PFIFO_NO_ROOM 502L /* not enough room in FIFO */
#define XST_PFIFO_BAD_REG_VALUE 503L /* self test, a register value
was invalid after reset */
#define XST_PFIFO_ERROR 504L /* generic packet FIFO error */
#define XST_PFIFO_DEADLOCK 505L /* packet FIFO is reporting
* empty and full simultaneously
*/
/************************** DMA statuses 511 - 530 ***************************/
#define XST_DMA_TRANSFER_ERROR 511L /* self test, DMA transfer
failed */
#define XST_DMA_RESET_REGISTER_ERROR 512L /* self test, a register value
was invalid after reset */
#define XST_DMA_SG_LIST_EMPTY 513L /* scatter gather list contains
no buffer descriptors ready
to be processed */
#define XST_DMA_SG_IS_STARTED 514L /* scatter gather not stopped */
#define XST_DMA_SG_IS_STOPPED 515L /* scatter gather not running */
#define XST_DMA_SG_LIST_FULL 517L /* all the buffer desciptors of
the scatter gather list are
being used */
#define XST_DMA_SG_BD_LOCKED 518L /* the scatter gather buffer
descriptor which is to be
copied over in the scatter
list is locked */
#define XST_DMA_SG_NOTHING_TO_COMMIT 519L /* no buffer descriptors have been
put into the scatter gather
list to be commited */
#define XST_DMA_SG_COUNT_EXCEEDED 521L /* the packet count threshold
specified was larger than the
total # of buffer descriptors
in the scatter gather list */
#define XST_DMA_SG_LIST_EXISTS 522L /* the scatter gather list has
already been created */
#define XST_DMA_SG_NO_LIST 523L /* no scatter gather list has
been created */
#define XST_DMA_SG_BD_NOT_COMMITTED 524L /* the buffer descriptor which was
being started was not committed
to the list */
#define XST_DMA_SG_NO_DATA 525L /* the buffer descriptor to start
has already been used by the
hardware so it can't be reused
*/
#define XST_DMA_SG_LIST_ERROR 526L /* general purpose list access
error */
#define XST_DMA_BD_ERROR 527L /* general buffer descriptor
error */
/************************** IPIF statuses 531 - 550 ***************************/
#define XST_IPIF_REG_WIDTH_ERROR 531L /* an invalid register width
was passed into the function */
#define XST_IPIF_RESET_REGISTER_ERROR 532L /* the value of a register at
reset was not valid */
#define XST_IPIF_DEVICE_STATUS_ERROR 533L /* a write to the device interrupt
status register did not read
back correctly */
#define XST_IPIF_DEVICE_ACK_ERROR 534L /* the device interrupt status
register did not reset when
acked */
#define XST_IPIF_DEVICE_ENABLE_ERROR 535L /* the device interrupt enable
register was not updated when
other registers changed */
#define XST_IPIF_IP_STATUS_ERROR 536L /* a write to the IP interrupt
status register did not read
back correctly */
#define XST_IPIF_IP_ACK_ERROR 537L /* the IP interrupt status register
did not reset when acked */
#define XST_IPIF_IP_ENABLE_ERROR 538L /* IP interrupt enable register was
not updated correctly when other
registers changed */
#define XST_IPIF_DEVICE_PENDING_ERROR 539L /* The device interrupt pending
register did not indicate the
expected value */
#define XST_IPIF_DEVICE_ID_ERROR 540L /* The device interrupt ID register
did not indicate the expected
value */
#define XST_IPIF_ERROR 541L /* generic ipif error */
/****************** Device specific statuses 1001 - 4095 *********************/
/********************* Ethernet statuses 1001 - 1050 *************************/
#define XST_EMAC_MEMORY_SIZE_ERROR 1001L /* Memory space is not big enough
* to hold the minimum number of
* buffers or descriptors */
#define XST_EMAC_MEMORY_ALLOC_ERROR 1002L /* Memory allocation failed */
#define XST_EMAC_MII_READ_ERROR 1003L /* MII read error */
#define XST_EMAC_MII_BUSY 1004L /* An MII operation is in progress */
#define XST_EMAC_OUT_OF_BUFFERS 1005L /* Driver is out of buffers */
#define XST_EMAC_PARSE_ERROR 1006L /* Invalid driver init string */
#define XST_EMAC_COLLISION_ERROR 1007L /* Excess deferral or late
* collision on polled send */
/*********************** UART statuses 1051 - 1075 ***************************/
#define XST_UART
#define XST_UART_INIT_ERROR 1051L
#define XST_UART_START_ERROR 1052L
#define XST_UART_CONFIG_ERROR 1053L
#define XST_UART_TEST_FAIL 1054L
#define XST_UART_BAUD_ERROR 1055L
#define XST_UART_BAUD_RANGE 1056L
/************************ IIC statuses 1076 - 1100 ***************************/
#define XST_IIC_SELFTEST_FAILED 1076 /* self test failed */
#define XST_IIC_BUS_BUSY 1077 /* bus found busy */
#define XST_IIC_GENERAL_CALL_ADDRESS 1078 /* mastersend attempted with */
/* general call address */
#define XST_IIC_STAND_REG_RESET_ERROR 1079 /* A non parameterizable reg */
/* value after reset not valid */
#define XST_IIC_TX_FIFO_REG_RESET_ERROR 1080 /* Tx fifo included in design */
/* value after reset not valid */
#define XST_IIC_RX_FIFO_REG_RESET_ERROR 1081 /* Rx fifo included in design */
/* value after reset not valid */
#define XST_IIC_TBA_REG_RESET_ERROR 1082 /* 10 bit addr incl in design */
/* value after reset not valid */
#define XST_IIC_CR_READBACK_ERROR 1083 /* Read of the control register */
/* didn't return value written */
#define XST_IIC_DTR_READBACK_ERROR 1084 /* Read of the data Tx reg */
/* didn't return value written */
#define XST_IIC_DRR_READBACK_ERROR 1085 /* Read of the data Receive reg */
/* didn't return value written */
#define XST_IIC_ADR_READBACK_ERROR 1086 /* Read of the data Tx reg */
/* didn't return value written */
#define XST_IIC_TBA_READBACK_ERROR 1087 /* Read of the 10 bit addr reg */
/* didn't return written value */
#define XST_IIC_NOT_SLAVE 1088 /* The device isn't a slave */
/*********************** ATMC statuses 1101 - 1125 ***************************/
#define XST_ATMC_ERROR_COUNT_MAX 1101L /* the error counters in the ATM
controller hit the max value
which requires the statistics
to be cleared */
/*********************** Flash statuses 1126 - 1150 **************************/
#define XST_FLASH_BUSY 1126L /* Flash is erasing or programming
*/
#define XST_FLASH_READY 1127L /* Flash is ready for commands */
#define XST_FLASH_ERROR 1128L /* Flash had detected an internal
error. Use XFlash_DeviceControl
to retrieve device specific codes
*/
#define XST_FLASH_ERASE_SUSPENDED 1129L /* Flash is in suspended erase state
*/
#define XST_FLASH_WRITE_SUSPENDED 1130L /* Flash is in suspended write state
*/
#define XST_FLASH_PART_NOT_SUPPORTED 1131L /* Flash type not supported by
driver */
#define XST_FLASH_NOT_SUPPORTED 1132L /* Operation not supported */
#define XST_FLASH_TOO_MANY_REGIONS 1133L /* Too many erase regions */
#define XST_FLASH_TIMEOUT_ERROR 1134L /* Programming or erase operation
aborted due to a timeout */
#define XST_FLASH_ADDRESS_ERROR 1135L /* Accessed flash outside its
addressible range */
#define XST_FLASH_ALIGNMENT_ERROR 1136L /* Write alignment error */
#define XST_FLASH_BLOCKING_CALL_ERROR 1137L /* Couldn't return immediately from
write/erase function with
XFL_NON_BLOCKING_WRITE/ERASE
option cleared */
#define XST_FLASH_CFI_QUERY_ERROR 1138L /* Failed to query the device */
/*********************** SPI statuses 1151 - 1175 ****************************/
#define XST_SPI_MODE_FAULT 1151 /* master was selected as slave */
#define XST_SPI_TRANSFER_DONE 1152 /* data transfer is complete */
#define XST_SPI_TRANSMIT_UNDERRUN 1153 /* slave underruns transmit register */
#define XST_SPI_RECEIVE_OVERRUN 1154 /* device overruns receive register */
#define XST_SPI_NO_SLAVE 1155 /* no slave has been selected yet */
#define XST_SPI_TOO_MANY_SLAVES 1156 /* more than one slave is being
* selected */
#define XST_SPI_NOT_MASTER 1157 /* operation is valid only as master */
#define XST_SPI_SLAVE_ONLY 1158 /* device is configured as slave-only
*/
#define XST_SPI_SLAVE_MODE_FAULT 1159 /* slave was selected while disabled */
#define XST_SPI_SLAVE_MODE 1160 /* device has been addressed as slave */
#define XST_SPI_RECEIVE_NOT_EMPTY 1161 /* device received data in slave mode */
#define XST_SPI_COMMAND_ERROR 1162 /* unrecognised command - qspi only */
/********************** OPB Arbiter statuses 1176 - 1200 *********************/
#define XST_OPBARB_INVALID_PRIORITY 1176 /* the priority registers have either
* one master assigned to two or more
* priorities, or one master not
* assigned to any priority
*/
#define XST_OPBARB_NOT_SUSPENDED 1177 /* an attempt was made to modify the
* priority levels without first
* suspending the use of priority
* levels
*/
#define XST_OPBARB_PARK_NOT_ENABLED 1178 /* bus parking by id was enabled but
* bus parking was not enabled
*/
#define XST_OPBARB_NOT_FIXED_PRIORITY 1179 /* the arbiter must be in fixed
* priority mode to allow the
* priorities to be changed
*/
/************************ Intc statuses 1201 - 1225 **************************/
#define XST_INTC_FAIL_SELFTEST 1201 /* self test failed */
#define XST_INTC_CONNECT_ERROR 1202 /* interrupt already in use */
/********************** TmrCtr statuses 1226 - 1250 **************************/
#define XST_TMRCTR_TIMER_FAILED 1226 /* self test failed */
/********************** WdtTb statuses 1251 - 1275 ***************************/
#define XST_WDTTB_TIMER_FAILED 1251L
/********************** PlbArb statuses 1276 - 1300 **************************/
#define XST_PLBARB_FAIL_SELFTEST 1276L
/********************** Plb2Opb statuses 1301 - 1325 *************************/
#define XST_PLB2OPB_FAIL_SELFTEST 1301L
/********************** Opb2Plb statuses 1326 - 1350 *************************/
#define XST_OPB2PLB_FAIL_SELFTEST 1326L
/********************** SysAce statuses 1351 - 1360 **************************/
#define XST_SYSACE_NO_LOCK 1351L /* No MPU lock has been granted */
/********************** PCI Bridge statuses 1361 - 1375 **********************/
#define XST_PCI_INVALID_ADDRESS 1361L
/********************** FlexRay constants 1400 - 1409 *************************/
#define XST_FR_TX_ERROR 1400
#define XST_FR_TX_BUSY 1401
#define XST_FR_BUF_LOCKED 1402
#define XST_FR_NO_BUF 1403
/****************** USB constants 1410 - 1420 *******************************/
#define XST_USB_ALREADY_CONFIGURED 1410
#define XST_USB_BUF_ALIGN_ERROR 1411
#define XST_USB_NO_DESC_AVAILABLE 1412
#define XST_USB_BUF_TOO_BIG 1413
#define XST_USB_NO_BUF 1414
/****************** HWICAP constants 1421 - 1429 *****************************/
#define XST_HWICAP_WRITE_DONE 1421
/****************** AXI VDMA constants 1430 - 1440 *****************************/
#define XST_VDMA_MISMATCH_ERROR 1430
/*********************** NAND Flash statuses 1441 - 1459 *********************/
#define XST_NAND_BUSY 1441L /* Flash is erasing or
* programming
*/
#define XST_NAND_READY 1442L /* Flash is ready for commands
*/
#define XST_NAND_ERROR 1443L /* Flash had detected an
* internal error.
*/
#define XST_NAND_PART_NOT_SUPPORTED 1444L /* Flash type not supported by
* driver
*/
#define XST_NAND_OPT_NOT_SUPPORTED 1445L /* Operation not supported
*/
#define XST_NAND_TIMEOUT_ERROR 1446L /* Programming or erase
* operation aborted due to a
* timeout
*/
#define XST_NAND_ADDRESS_ERROR 1447L /* Accessed flash outside its
* addressible range
*/
#define XST_NAND_ALIGNMENT_ERROR 1448L /* Write alignment error
*/
#define XST_NAND_PARAM_PAGE_ERROR 1449L /* Failed to read parameter
* page of the device
*/
#define XST_NAND_CACHE_ERROR 1450L /* Flash page buffer error
*/
#define XST_NAND_WRITE_PROTECTED 1451L /* Flash is write protected
*/
/**************************** Type Definitions *******************************/
typedef int XStatus;
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */

154
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/* $Id: xutil.h,v 1.8 2007/05/04 21:55:59 wre Exp $ */
/******************************************************************************
*
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
* AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
* SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE,
* OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
* APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
* THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE.
*
* (c) Copyright 2002 Xilinx Inc.
* All rights reserved.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xutil.h
*
* This file contains utility functions such as memory test functions.
*
* <b>Memory test description</b>
*
* A subset of the memory tests can be selected or all of the tests can be run
* in order. If there is an error detected by a subtest, the test stops and the
* failure code is returned. Further tests are not run even if all of the tests
* are selected.
*
* Subtest descriptions:
* <pre>
* XUT_ALLMEMTESTS:
* Runs all of the following tests
*
* XUT_INCREMENT:
* Incrementing Value Test.
* This test starts at 'XUT_MEMTEST_INIT_VALUE' and uses the incrementing
* value as the test value for memory.
*
* XUT_WALKONES:
* Walking Ones Test.
* This test uses a walking '1' as the test value for memory.
* location 1 = 0x00000001
* location 2 = 0x00000002
* ...
*
* XUT_WALKZEROS:
* Walking Zero's Test.
* This test uses the inverse value of the walking ones test
* as the test value for memory.
* location 1 = 0xFFFFFFFE
* location 2 = 0xFFFFFFFD
* ...
*
* XUT_INVERSEADDR:
* Inverse Address Test.
* This test uses the inverse of the address of the location under test
* as the test value for memory.
*
* XUT_FIXEDPATTERN:
* Fixed Pattern Test.
* This test uses the provided patters as the test value for memory.
* If zero is provided as the pattern the test uses '0xDEADBEEF".
* </pre>
*
* <i>WARNING</i>
*
* The tests are <b>DESTRUCTIVE</b>. Run before any initialized memory spaces
* have been set up.
*
* The address, Addr, provided to the memory tests is not checked for
* validity except for the NULL case. It is possible to provide a code-space
* pointer for this test to start with and ultimately destroy executable code
* causing random failures.
*
* @note
*
* Used for spaces where the address range of the region is smaller than
* the data width. If the memory range is greater than 2 ** width,
* the patterns used in XUT_WALKONES and XUT_WALKZEROS will repeat on a
* boundry of a power of two making it more difficult to detect addressing
* errors. The XUT_INCREMENT and XUT_INVERSEADDR tests suffer the same
* problem. Ideally, if large blocks of memory are to be tested, break
* them up into smaller regions of memory to allow the test patterns used
* not to repeat over the region tested.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.00a ecm 11/01/01 First release
* 1.00a xd 11/03/04 Improved support for doxygen.
* </pre>
*
******************************************************************************/
#ifndef XUTIL_H /* prevent circular inclusions */
#define XUTIL_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xbasic_types.h"
#include "xstatus.h"
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/* xutil_memtest defines */
#define XUT_MEMTEST_INIT_VALUE 1
/** @name Memory subtests
* @{
*/
/**
* See the detailed description of the subtests in the file description.
*/
#define XUT_ALLMEMTESTS 0
#define XUT_INCREMENT 1
#define XUT_WALKONES 2
#define XUT_WALKZEROS 3
#define XUT_INVERSEADDR 4
#define XUT_FIXEDPATTERN 5
#define XUT_MAXTEST XUT_FIXEDPATTERN
/* @} */
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
/* xutil_memtest prototypes */
int XUtil_MemoryTest32(u32 *Addr, u32 Words, u32 Pattern, u8 Subtest);
int XUtil_MemoryTest16(u16 *Addr, u32 Words, u16 Pattern, u8 Subtest);
int XUtil_MemoryTest8(u8 *Addr, u32 Words, u8 Pattern, u8 Subtest);
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */

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344
software/LED_Controller_bsp/microblaze_mcs/libsrc/common_v1_00_a/src/xversion.c Executable file
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/* $Id: xversion.c,v 1.10 2007/05/07 14:29:23 wre Exp $ */
/******************************************************************************
*
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
* AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
* SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE,
* OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
* APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
* THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE.
*
* (c) Copyright 2002 Xilinx Inc.
* All rights reserved.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xversion.c
*
* This file contains the implementation of the XVersion component. This
* component represents a version ID. It is encapsulated within a component
* so that it's type and implementation can change without affecting users of
* it.
*
* The version is formatted as X.YYZ where X = 0 - 9, Y = 00 - 99, Z = a - z
* X is the major revision, YY is the minor revision, and Z is the
* compatability revision.
*
* Packed versions are also utilized for the configuration ROM such that
* memory is minimized. A packed version consumes only 16 bits and is
* formatted as follows.
*
* <pre>
* Revision Range Bit Positions
*
* Major Revision 0 - 9 Bits 15 - 12
* Minor Revision 0 - 99 Bits 11 - 5
* Compatability Revision a - z Bits 4 - 0
*
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00a xd 11/03/04 Improved support for doxygen.
</pre>
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "xbasic_types.h"
#include "xversion.h"
/************************** Constant Definitions *****************************/
/* the following constants define the masks and shift values to allow the
* revisions to be packed and unpacked, a packed version is packed into a 16
* bit value in the following format, XXXXYYYYYYYZZZZZ, where XXXX is the
* major revision, YYYYYYY is the minor revision, and ZZZZZ is the compatability
* revision
*/
#define XVE_MAJOR_SHIFT_VALUE 12
#define XVE_MINOR_ONLY_MASK 0x0FE0
#define XVE_MINOR_SHIFT_VALUE 5
#define XVE_COMP_ONLY_MASK 0x001F
/* the following constants define the specific characters of a version string
* for each character of the revision, a version string is in the following
* format, "X.YYZ" where X is the major revision (0 - 9), YY is the minor
* revision (00 - 99), and Z is the compatability revision (a - z)
*/
#define XVE_MAJOR_CHAR 0 /* major revision 0 - 9 */
#define XVE_MINOR_TENS_CHAR 2 /* minor revision tens 0 - 9 */
#define XVE_MINOR_ONES_CHAR 3 /* minor revision ones 0 - 9 */
#define XVE_COMP_CHAR 4 /* compatability revision a - z */
#define XVE_END_STRING_CHAR 5
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
static int IsVersionStringValid(char *StringPtr);
/*****************************************************************************/
/**
*
* Unpacks a packed version into the specified version. Versions are packed
* into the configuration ROM to reduce the amount storage. A packed version
* is a binary format as oppossed to a non-packed version which is implemented
* as a string.
*
* @param InstancePtr points to the version to unpack the packed version into.
* @param PackedVersion contains the packed version to unpack.
*
* @return None.
*
* @note None.
*
******************************************************************************/
void XVersion_UnPack(XVersion *InstancePtr, u16 PackedVersion)
{
(void) InstancePtr;
(void) PackedVersion;
/* not implemented yet since CROM related */
}
/*****************************************************************************/
/**
*
* Packs a version into the specified packed version. Versions are packed into
* the configuration ROM to reduce the amount storage.
*
* @param InstancePtr points to the version to pack.
* @param PackedVersionPtr points to the packed version which will receive
* the new packed version.
*
* @return
*
* A status, XST_SUCCESS, indicating the packing was accomplished
* successfully, or an error, XST_INVALID_VERSION, indicating the specified
* input version was not valid such that the pack did not occur
* <br><br>
* The packed version pointed to by PackedVersionPtr is modified with the new
* packed version if the status indicates success.
*
* @note
*
* None.
*
******************************************************************************/
int XVersion_Pack(XVersion *InstancePtr, u16 *PackedVersionPtr)
{
/* not implemented yet since CROM related */
(void) InstancePtr;
(void) PackedVersionPtr;
return XST_SUCCESS;
}
/*****************************************************************************/
/**
*
* Determines if two versions are equal.
*
* @param InstancePtr points to the first version to be compared.
* @param VersionPtr points to a second version to be compared.
*
* @return
*
* TRUE if the versions are equal, FALSE otherwise.
*
* @note
*
* None.
*
******************************************************************************/
int XVersion_IsEqual(XVersion *InstancePtr, XVersion *VersionPtr)
{
u8 *Version1 = (u8 *) InstancePtr;
u8 *Version2 = (u8 *) VersionPtr;
u32 Index;
/* assert to verify input arguments */
XASSERT_NONVOID(InstancePtr != NULL);
XASSERT_NONVOID(VersionPtr != NULL);
/* check each byte of the versions to see if they are the same,
* return at any point a byte differs between them
*/
for (Index = 0; Index < sizeof(XVersion); Index++) {
if (Version1[Index] != Version2[Index]) {
return FALSE;
}
}
/* No byte was found to be different between the versions, so indicate
* the versions are equal
*/
return TRUE;
}
/*****************************************************************************/
/**
*
* Converts a version to a null terminated string.
*
* @param InstancePtr points to the version to convert.
* @param StringPtr points to the string which will be the result of the
* conversion. This does not need to point to a null terminated
* string as an input, but must point to storage which is an adequate
* amount to hold the result string.
*
* @return
*
* The null terminated string is inserted at the location pointed to by
* StringPtr if the status indicates success.
*
* @note
*
* It is necessary for the caller to have already allocated the storage to
* contain the string. The amount of memory necessary for the string is
* specified in the version header file.
*
******************************************************************************/
void XVersion_ToString(XVersion *InstancePtr, char *StringPtr)
{
/* assert to verify input arguments */
XASSERT_VOID(InstancePtr != NULL);
XASSERT_VOID(StringPtr != NULL);
/* since version is implemented as a string, just copy the specified
* input into the specified output
*/
XVersion_Copy(InstancePtr, (XVersion *) StringPtr);
}
/*****************************************************************************/
/**
*
* Initializes a version from a null terminated string. Since the string may not
* be a format which is compatible with the version, an error could occur.
*
* @param InstancePtr points to the version which is to be initialized.
* @param StringPtr points to a null terminated string which will be
* converted to a version. The format of the string must match the
* version string format which is X.YYX where X = 0 - 9, YY = 00 - 99,
* Z = a - z.
*
* @return
*
* A status, XST_SUCCESS, indicating the conversion was accomplished
* successfully, or XST_INVALID_VERSION indicating the version string format
* was not valid.
*
* @note
*
* None.
*
******************************************************************************/
int XVersion_FromString(XVersion *InstancePtr, char *StringPtr)
{
/* assert to verify input arguments */
XASSERT_NONVOID(InstancePtr != NULL);
XASSERT_NONVOID(StringPtr != NULL);
/* if the version string specified is not valid, return an error */
if (!IsVersionStringValid(StringPtr)) {
return XST_INVALID_VERSION;
}
/* copy the specified string into the specified version and indicate the
* conversion was successful
*/
XVersion_Copy((XVersion *) StringPtr, InstancePtr);
return XST_SUCCESS;
}
/*****************************************************************************/
/**
*
* Copies the contents of a version to another version.
*
* @param InstancePtr points to the version which is the source of data for
* the copy operation.
* @param VersionPtr points to another version which is the destination of
* the copy operation.
*
* @return
*
* None.
*
* @note
*
* None.
*
******************************************************************************/
void XVersion_Copy(XVersion *InstancePtr, XVersion *VersionPtr)
{
u8 *Source = (u8 *) InstancePtr;
u8 *Destination = (u8 *) VersionPtr;
u32 Index;
/* assert to verify input arguments */
XASSERT_VOID(InstancePtr != NULL);
XASSERT_VOID(VersionPtr != NULL);
/* copy each byte of the source version to the destination version */
for (Index = 0; Index < sizeof(XVersion); Index++) {
Destination[Index] = Source[Index];
}
}
/*****************************************************************************/
/**
*
* Determines if the specified version is valid.
*
* @param StringPtr points to the string to be validated.
*
* @return
*
* TRUE if the version string is a valid format, FALSE otherwise.
*
* @note
*
* None.
*
******************************************************************************/
static int IsVersionStringValid(char *StringPtr)
{
/* if the input string is not a valid format, "X.YYZ" where X = 0 - 9,
* YY = 00 - 99, and Z = a - z, then indicate it's not valid
*/
if ((StringPtr[XVE_MAJOR_CHAR] < '0') ||
(StringPtr[XVE_MAJOR_CHAR] > '9') ||
(StringPtr[XVE_MINOR_TENS_CHAR] < '0') ||
(StringPtr[XVE_MINOR_TENS_CHAR] > '9') ||
(StringPtr[XVE_MINOR_ONES_CHAR] < '0') ||
(StringPtr[XVE_MINOR_ONES_CHAR] > '9') ||
(StringPtr[XVE_COMP_CHAR] < 'a') ||
(StringPtr[XVE_COMP_CHAR] > 'z')) {
return FALSE;
}
return TRUE;
}

98
software/LED_Controller_bsp/microblaze_mcs/libsrc/common_v1_00_a/src/xversion.h Executable file
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/* $Id: xversion.h,v 1.9 2007/05/07 14:29:23 wre Exp $ */
/******************************************************************************
*
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
* AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
* SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE,
* OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
* APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
* THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE.
*
* (c) Copyright 2002 Xilinx Inc.
* All rights reserved.
*
******************************************************************************/
/*****************************************************************************/
/**
* @file xversion.h
*
* This file contains the interface for the XVersion component. This
* component represents a version ID. It is encapsulated within a component
* so that it's type and implementation can change without affecting users of
* it.
*
* The version is formatted as X.YYZ where X = 0 - 9, Y = 00 - 99, Z = a - z
* X is the major revision, YY is the minor revision, and Z is the
* compatability revision.
*
* Packed versions are also utilized for the configuration ROM such that
* memory is minimized. A packed version consumes only 16 bits and is
* formatted as follows.
*
* <pre>
* Revision Range Bit Positions
*
* Major Revision 0 - 9 Bits 15 - 12
* Minor Revision 0 - 99 Bits 11 - 5
* Compatability Revision a - z Bits 4 - 0
*
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00a xd 11/03/04 Improved support for doxygen.
* </pre>
*
******************************************************************************/
#ifndef XVERSION_H /* prevent circular inclusions */
#define XVERSION_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xbasic_types.h"
#include "xstatus.h"
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/* the following data type is used to hold a null terminated version string
* consisting of the following format, "X.YYX"
*/
typedef char XVersion[6];
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
void XVersion_UnPack(XVersion *InstancePtr, u16 PackedVersion);
int XVersion_Pack(XVersion *InstancePtr, u16 *PackedVersion);
int XVersion_IsEqual(XVersion *InstancePtr, XVersion *VersionPtr);
void XVersion_ToString(XVersion *InstancePtr, char *StringPtr);
int XVersion_FromString(XVersion *InstancePtr, char *StringPtr);
void XVersion_Copy(XVersion *InstancePtr, XVersion *VersionPtr);
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */

27
software/LED_Controller_bsp/microblaze_mcs/libsrc/cpu_v1_15_a/src/Makefile Executable file
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COMPILER=
ARCHIVER=
CP=cp
COMPILER_FLAGS=
EXTRA_COMPILER_FLAGS=
LIB=libxil.a
RELEASEDIR=../../../lib
INCLUDEDIR=../../../include
INCLUDES=-I${INCLUDEDIR}
OUTS = *.o
LIBSOURCES=*.c
INCLUDEFILES=xio.h
libs:
echo "Compiling cpu"
$(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES)
$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS}
make clean
include:
${CP} ${INCLUDEFILES} ${INCLUDEDIR}
clean:
rm -rf ${OUTS}

181
software/LED_Controller_bsp/microblaze_mcs/libsrc/cpu_v1_15_a/src/fsl.h Executable file
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/* $Id: fsl.h,v 1.1.2.2 2010/07/02 16:08:32 haibing Exp $ */
/******************************************************************************
*
* (c) Copyright 2007-2009 Xilinx, Inc. All rights reserved.
*
* This file contains confidential and proprietary information of Xilinx, Inc.
* and is protected under U.S. and international copyright and other
* intellectual property laws.
*
* DISCLAIMER
* This disclaimer is not a license and does not grant any rights to the
* materials distributed herewith. Except as otherwise provided in a valid
* license issued to you by Xilinx, and to the maximum extent permitted by
* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
* and (2) Xilinx shall not be liable (whether in contract or tort, including
* negligence, or under any other theory of liability) for any loss or damage
* of any kind or nature related to, arising under or in connection with these
* materials, including for any direct, or any indirect, special, incidental,
* or consequential loss or damage (including loss of data, profits, goodwill,
* or any type of loss or damage suffered as a result of any action brought by
* a third party) even if such damage or loss was reasonably foreseeable or
* Xilinx had been advised of the possibility of the same.
*
* CRITICAL APPLICATIONS
* Xilinx products are not designed or intended to be fail-safe, or for use in
* any application requiring fail-safe performance, such as life-support or
* safety devices or systems, Class III medical devices, nuclear facilities,
* applications related to the deployment of airbags, or any other applications
* that could lead to death, personal injury, or severe property or
* environmental damage (individually and collectively, "Critical
* Applications"). Customer assumes the sole risk and liability of any use of
* Xilinx products in Critical Applications, subject only to applicable laws
* and regulations governing limitations on product liability.
*
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
* AT ALL TIMES.
*
******************************************************************************/
/*****************************************************************************/
/**
* @file fsl.h
*
* This file contains macros for interfacing to the Fast Simplex Link (FSL)
* interface..
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- ---------------------------------------------------
* 1.00a ecm 06/20/07 Initial version, moved over from bsp area
* 1.11c ecm 08/26/08 Fixed the missing 'FSL_DEFAULT' define that was causing
* assembly errors.
* </pre>
*
* @note
*
* None.
*
******************************************************************************/
#ifndef _FSL_H
#define _FSL_H
/***************************** Include Files *********************************/
#include "xbasic_types.h"
#ifdef __cplusplus
extern "C" {
#endif
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/* if these have not been defined already, define here */
#ifndef stringify
/* necessary for pre-processor */
#define stringify(s) tostring(s)
#define tostring(s) #s
#endif /* stringify */
/* Extended FSL macros. These now replace all of the previous FSL macros */
#define FSL_DEFAULT
#define FSL_NONBLOCKING n
#define FSL_EXCEPTION e
#define FSL_CONTROL c
#define FSL_ATOMIC a
#define FSL_NONBLOCKING_EXCEPTION ne
#define FSL_NONBLOCKING_CONTROL nc
#define FSL_NONBLOCKING_ATOMIC na
#define FSL_EXCEPTION_CONTROL ec
#define FSL_EXCEPTION_ATOMIC ea
#define FSL_CONTROL_ATOMIC ca
#define FSL_NONBLOCKING_EXCEPTION_CONTROL nec
#define FSL_NONBLOCKING_EXCEPTION_ATOMIC nea
#define FSL_NONBLOCKING_CONTROL_ATOMIC nca
#define FSL_EXCEPTION_CONTROL_ATOMIC eca
#define FSL_NONBLOCKING_EXCEPTION_CONTROL_ATOMIC neca
#define getfslx(val, id, flags) asm volatile (stringify(flags) "get\t%0,rfsl" stringify(id) : "=d" (val))
#define putfslx(val, id, flags) asm volatile (stringify(flags) "put\t%0,rfsl" stringify(id) :: "d" (val))
#define tgetfslx(val, id, flags) asm volatile ("t" stringify(flags) "get\t%0,rfsl" stringify(id) : "=d" (val))
#define tputfslx(id, flags) asm volatile ("t" stringify(flags) "put\trfsl" stringify(id))
#define getdfslx(val, var, flags) asm volatile (stringify(flags) "getd\t%0,%1" : "=d" (val) : "d" (var))
#define putdfslx(val, var, flags) asm volatile (stringify(flags) "putd\t%0,%1" :: "d" (val), "d" (var))
#define tgetdfslx(val, var, flags) asm volatile ("t" stringify(flags) "getd\t%0,%1" : "=d" (val) : "d" (var))
#define tputdfslx(var, flags) asm volatile ("t" stringify(flags) "putd\t%0" :: "d" (var))
/* if the mb_interface.h file has been included already, the following are not needed and will not be defined */
/* Legacy FSL Access Macros */
#ifndef getfsl
/* Blocking Data Read and Write to FSL no. id */
#define getfsl(val, id) asm volatile ("get\t%0,rfsl" stringify(id) : "=d" (val))
#define putfsl(val, id) asm volatile ("put\t%0,rfsl" stringify(id) :: "d" (val))
/* Non-blocking Data Read and Write to FSL no. id */
#define ngetfsl(val, id) asm volatile ("nget\t%0,rfsl" stringify(id) : "=d" (val))
#define nputfsl(val, id) asm volatile ("nput\t%0,rfsl" stringify(id) :: "d" (val))
/* Blocking Control Read and Write to FSL no. id */
#define cgetfsl(val, id) asm volatile ("cget\t%0,rfsl" stringify(id) : "=d" (val))
#define cputfsl(val, id) asm volatile ("cput\t%0,rfsl" stringify(id) :: "d" (val))
/* Non-blocking Control Read and Write to FSL no. id */
#define ncgetfsl(val, id) asm volatile ("ncget\t%0,rfsl" stringify(id) : "=d" (val))
#define ncputfsl(val, id) asm volatile ("ncput\t%0,rfsl" stringify(id) :: "d" (val))
/* Polling versions of FSL access macros. This makes the FSL access interruptible */
#define getfsl_interruptible(val, id) asm volatile ("\n1:\n\tnget\t%0,rfsl" stringify(id) "\n\t" \
"addic\tr18,r0,0\n\t" \
"bnei\tr18,1b\n" \
: "=d" (val) :: "r18")
#define putfsl_interruptible(val, id) asm volatile ("\n1:\n\tnput\t%0,rfsl" stringify(id) "\n\t" \
"addic\tr18,r0,0\n\t" \
"bnei\tr18,1b\n" \
:: "d" (val) : "r18")
#define cgetfsl_interruptible(val, id) asm volatile ("\n1:\n\tncget\t%0,rfsl" stringify(id) "\n\t" \
"addic\tr18,r0,0\n\t" \
"bnei\tr18,1b\n" \
: "=d" (val) :: "r18")
#define cputfsl_interruptible(val, id) asm volatile ("\n1:\n\tncput\t%0,rfsl" stringify(id) "\n\t" \
"addic\tr18,r0,0\n\t" \
"bnei\tr18,1b\n" \
:: "d" (val) : "r18")
/* FSL valid and error check macros. */
#define fsl_isinvalid(result) asm volatile ("addic\t%0,r0,0" : "=d" (result))
#define fsl_iserror(error) asm volatile ("mfs\t%0,rmsr\n\t" \
"andi\t%0,%0,0x10" : "=d" (error))
#endif /* legacy FSL defines */
/************************** Function Prototypes ******************************/
/************************** Variable Definitions *****************************/
#ifdef __cplusplus
}
#endif
#endif /* _FSL_H */

236
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@@ -0,0 +1,236 @@
/* $Id: xio.c,v 1.1.2.1 2010/06/16 08:09:08 sadanan Exp $ */
/******************************************************************************
*
* (c) Copyright 2007-2009 Xilinx, Inc. All rights reserved.
*
* This file contains confidential and proprietary information of Xilinx, Inc.
* and is protected under U.S. and international copyright and other
* intellectual property laws.
*
* DISCLAIMER
* This disclaimer is not a license and does not grant any rights to the
* materials distributed herewith. Except as otherwise provided in a valid
* license issued to you by Xilinx, and to the maximum extent permitted by
* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
* and (2) Xilinx shall not be liable (whether in contract or tort, including
* negligence, or under any other theory of liability) for any loss or damage
* of any kind or nature related to, arising under or in connection with these
* materials, including for any direct, or any indirect, special, incidental,
* or consequential loss or damage (including loss of data, profits, goodwill,
* or any type of loss or damage suffered as a result of any action brought by
* a third party) even if such damage or loss was reasonably foreseeable or
* Xilinx had been advised of the possibility of the same.
*
* CRITICAL APPLICATIONS
* Xilinx products are not designed or intended to be fail-safe, or for use in
* any application requiring fail-safe performance, such as life-support or
* safety devices or systems, Class III medical devices, nuclear facilities,
* applications related to the deployment of airbags, or any other applications
* that could lead to death, personal injury, or severe property or
* environmental damage (individually and collectively, "Critical
* Applications"). Customer assumes the sole risk and liability of any use of
* Xilinx products in Critical Applications, subject only to applicable laws
* and regulations governing limitations on product liability.
*
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
* AT ALL TIMES.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xio.c
*
* Contains I/O functions for memory-mapped or non-memory-mapped I/O
* architectures. These functions encapsulate generic CPU I/O requirements.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00a rpm 11/07/03 Added InSwap/OutSwap routines for endian conversion
* 1.01a ecm 02/24/06 CR225908 corrected the extra curly braces in macros
* and bumped version to 1.01.a.
* 2.11a mta 03/21/07 Updated to new coding style.
*
* </pre>
*
* @note
*
* This file may contain architecture-dependent code.
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "xio.h"
#include "xbasic_types.h"
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
/*****************************************************************************/
/**
*
* Performs a 16-bit endian converion.
*
* @param Source contains the value to be converted.
* @param DestPtr contains a pointer to the location to put the
* converted value.
*
* @return None.
*
* @note None.
*
******************************************************************************/
void XIo_EndianSwap16(u16 Source, u16 *DestPtr)
{
*DestPtr = (u16) (((Source & 0xFF00) >> 8) | ((Source & 0x00FF) << 8));
}
/*****************************************************************************/
/**
*
* Performs a 32-bit endian converion.
*
* @param Source contains the value to be converted.
* @param DestPtr contains a pointer to the location to put the
* converted value.
*
* @return None.
*
* @note None.
*
******************************************************************************/
void XIo_EndianSwap32(u32 Source, u32 *DestPtr)
{
/* get each of the half words from the 32 bit word */
u16 LoWord = (u16) (Source & 0x0000FFFF);
u16 HiWord = (u16) ((Source & 0xFFFF0000) >> 16);
/* byte swap each of the 16 bit half words */
LoWord = (((LoWord & 0xFF00) >> 8) | ((LoWord & 0x00FF) << 8));
HiWord = (((HiWord & 0xFF00) >> 8) | ((HiWord & 0x00FF) << 8));
/* swap the half words before returning the value */
*DestPtr = (u32) ((LoWord << 16) | HiWord);
}
/*****************************************************************************/
/**
*
* Performs an input operation for a 16-bit memory location by reading from the
* specified address and returning the byte-swapped value read from that
* address.
*
* @param InAddress contains the address to perform the input
* operation at.
*
* @return The byte-swapped value read from the specified input address.
*
* @note None.
*
******************************************************************************/
u16 XIo_InSwap16(XIo_Address InAddress)
{
u16 InData;
/* get the data then swap it */
InData = XIo_In16(InAddress);
return (u16) (((InData & 0xFF00) >> 8) | ((InData & 0x00FF) << 8));
}
/*****************************************************************************/
/**
*
* Performs an input operation for a 32-bit memory location by reading from the
* specified address and returning the byte-swapped value read from that
* address.
*
* @param InAddress contains the address to perform the input
* operation at.
*
* @return The byte-swapped value read from the specified input address.
*
* @note None.
*
******************************************************************************/
u32 XIo_InSwap32(XIo_Address InAddress)
{
u32 InData;
u32 SwapData;
/* get the data then swap it */
InData = XIo_In32(InAddress);
XIo_EndianSwap32(InData, &SwapData);
return SwapData;
}
/*****************************************************************************/
/**
*
* Performs an output operation for a 16-bit memory location by writing the
* specified value to the the specified address. The value is byte-swapped
* before being written.
*
* @param OutAddress contains the address to perform the output
* operation at.
* @param Value contains the value to be output at the specified address.
*
* @return None.
*
* @note None.
*
******************************************************************************/
void XIo_OutSwap16(XIo_Address OutAddress, u16 Value)
{
u16 OutData;
/* swap the data then output it */
OutData = (u16) (((Value & 0xFF00) >> 8) | ((Value & 0x00FF) << 8));
XIo_Out16(OutAddress, OutData);
}
/*****************************************************************************/
/**
*
* Performs an output operation for a 32-bit memory location by writing the
* specified value to the the specified address. The value is byte-swapped
* before being written.
*
* @param OutAddress contains the address at which the
* output operation has to be done.
* @param Value contains the value to be output at the specified address.
*
* @return None.
*
* @note None.
*
******************************************************************************/
void XIo_OutSwap32(XIo_Address OutAddress, u32 Value)
{
u32 OutData;
/* swap the data then output it */
XIo_EndianSwap32(Value, &OutData);
XIo_Out32(OutAddress, OutData);
}

266
software/LED_Controller_bsp/microblaze_mcs/libsrc/cpu_v1_15_a/src/xio.h Executable file
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@@ -0,0 +1,266 @@
/* $Id: xio.h,v 1.1.2.2 2010/06/16 11:15:32 sadanan Exp $ */
/******************************************************************************
*
* (c) Copyright 2007-2009 Xilinx, Inc. All rights reserved.
*
* This file contains confidential and proprietary information of Xilinx, Inc.
* and is protected under U.S. and international copyright and other
* intellectual property laws.
*
* DISCLAIMER
* This disclaimer is not a license and does not grant any rights to the
* materials distributed herewith. Except as otherwise provided in a valid
* license issued to you by Xilinx, and to the maximum extent permitted by
* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
* and (2) Xilinx shall not be liable (whether in contract or tort, including
* negligence, or under any other theory of liability) for any loss or damage
* of any kind or nature related to, arising under or in connection with these
* materials, including for any direct, or any indirect, special, incidental,
* or consequential loss or damage (including loss of data, profits, goodwill,
* or any type of loss or damage suffered as a result of any action brought by
* a third party) even if such damage or loss was reasonably foreseeable or
* Xilinx had been advised of the possibility of the same.
*
* CRITICAL APPLICATIONS
* Xilinx products are not designed or intended to be fail-safe, or for use in
* any application requiring fail-safe performance, such as life-support or
* safety devices or systems, Class III medical devices, nuclear facilities,
* applications related to the deployment of airbags, or any other applications
* that could lead to death, personal injury, or severe property or
* environmental damage (individually and collectively, "Critical
* Applications"). Customer assumes the sole risk and liability of any use of
* Xilinx products in Critical Applications, subject only to applicable laws
* and regulations governing limitations on product liability.
*
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
* AT ALL TIMES.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xio.h
*
* This file contains the interface for the XIo component, which encapsulates
* the Input/Output functions for processors that do not require any special
* I/O handling.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00a rpm 11/07/03 Added InSwap/OutSwap routines for endian conversion
* 1.00a xd 11/04/04 Improved support for doxygen
* 1.01a ecm 02/24/06 CR225908 corrected the extra curly braces in macros
* and bumped version to 1.01.a.
* 1.11a mta 03/21/07 Updated to new coding style.
* 1.11b va 04/17/08 Updated Tcl for better CORE_CLOCK_FREQ_HZ definition
* 1.11a sdm 03/12/09 Updated Tcl to define correct value for CORE_CLOCK_FREQ_HZ
* (CR #502010)
* 1.13a sdm 03/12/09 Updated the Tcl to pull appropriate libraries for Little
* Endian Microblaze
*
* </pre>
*
* @note
*
* This file may contain architecture-dependent items (memory-mapped or
* non-memory-mapped I/O).
*
******************************************************************************/
#ifndef XIO_H /* prevent circular inclusions */
#define XIO_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xbasic_types.h"
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/**
* Typedef for an I/O address. Typically correlates to the width of the
* address bus.
*/
typedef u32 XIo_Address;
/***************** Macros (Inline Functions) Definitions *********************/
/*
* The following macros allow optimized I/O operations for memory mapped I/O.
* It should be noted that macros cannot be used if synchronization of the I/O
* operation is needed as it will likely break some code.
*/
/*****************************************************************************/
/**
*
* Performs an input operation for an 8-bit memory location by reading from the
* specified address and returning the value read from that address.
*
* @param InputPtr contains the address to perform the input operation at.
*
* @return The value read from the specified input address.
*
* @note None.
*
******************************************************************************/
#define XIo_In8(InputPtr) (*(volatile u8 *)(InputPtr))
/*****************************************************************************/
/**
*
* Performs an input operation for a 16-bit memory location by reading from the
* specified address and returning the value read from that address.
*
* @param InputPtr contains the address to perform the input operation at.
*
* @return The value read from the specified input address.
*
* @note None.
*
******************************************************************************/
#define XIo_In16(InputPtr) (*(volatile u16 *)(InputPtr))
/*****************************************************************************/
/**
*
* Performs an input operation for a 32-bit memory location by reading from the
* specified address and returning the value read from that address.
*
* @param InputPtr contains the address to perform the input operation at.
*
* @return The value read from the specified input address.
*
* @note None.
*
******************************************************************************/
#define XIo_In32(InputPtr) (*(volatile u32 *)(InputPtr))
/*****************************************************************************/
/**
*
* Performs an output operation for an 8-bit memory location by writing the
* specified value to the the specified address.
*
* @param OutputPtr contains the address to perform the output operation
* at.
* @param Value contains the value to be output at the specified address.
*
* @return None
*
* @note None.
*
******************************************************************************/
#define XIo_Out8(OutputPtr, Value) \
(*(volatile u8 *)((OutputPtr)) = (Value))
/*****************************************************************************/
/**
*
* Performs an output operation for a 16-bit memory location by writing the
* specified value to the the specified address.
*
* @param OutputPtr contains the address to perform the output operation
* at.
* @param Value contains the value to be output at the specified address.
*
* @return None
*
* @note None.
*
******************************************************************************/
#define XIo_Out16(OutputPtr, Value) \
(*(volatile u16 *)((OutputPtr)) = (Value))
/*****************************************************************************/
/**
*
* Performs an output operation for a 32-bit memory location by writing the
* specified value to the the specified address.
*
* @param OutputPtr contains the address to perform the output operation
* at.
* @param Value contains the value to be output at the specified address.
*
* @return None
*
* @note None.
*
******************************************************************************/
#define XIo_Out32(OutputPtr, Value) \
(*(volatile u32 *)((OutputPtr)) = (Value))
/* The following macros allow the software to be transportable across
* processors which use big or little endian memory models.
*
* Defined first is a no-op endian conversion macro. This macro is not to
* be used directly by software. Instead, the XIo_To/FromLittleEndianXX and
* XIo_To/FromBigEndianXX macros below are to be used to allow the endian
* conversion to only be performed when necessary
*/
#define XIo_EndianNoop(Source, DestPtr) (*DestPtr = Source)
#ifdef XLITTLE_ENDIAN
#define XIo_ToLittleEndian16 XIo_EndianNoop
#define XIo_ToLittleEndian32 XIo_EndianNoop
#define XIo_FromLittleEndian16 XIo_EndianNoop
#define XIo_FromLittleEndian32 XIo_EndianNoop
#define XIo_ToBigEndian16(Source, DestPtr) XIo_EndianSwap16(Source, DestPtr)
#define XIo_ToBigEndian32(Source, DestPtr) XIo_EndianSwap32(Source, DestPtr)
#define XIo_FromBigEndian16 XIo_ToBigEndian16
#define XIo_FromBigEndian32 XIo_ToBigEndian32
#else
#define XIo_ToLittleEndian16(Source, DestPtr) XIo_EndianSwap16(Source, DestPtr)
#define XIo_ToLittleEndian32(Source, DestPtr) XIo_EndianSwap32(Source, DestPtr)
#define XIo_FromLittleEndian16 XIo_ToLittleEndian16
#define XIo_FromLittleEndian32 XIo_ToLittleEndian32
#define XIo_ToBigEndian16 XIo_EndianNoop
#define XIo_ToBigEndian32 XIo_EndianNoop
#define XIo_FromBigEndian16 XIo_EndianNoop
#define XIo_FromBigEndian32 XIo_EndianNoop
#endif
/************************** Function Prototypes ******************************/
/* The following functions allow the software to be transportable across
* processors which use big or little endian memory models. These functions
* should not be directly called, but the macros XIo_To/FromLittleEndianXX and
* XIo_To/FromBigEndianXX should be used to allow the endian conversion to only
* be performed when necessary.
*/
void XIo_EndianSwap16(u16 Source, u16 *DestPtr);
void XIo_EndianSwap32(u32 Source, u32 *DestPtr);
/* The following functions handle IO addresses where data must be swapped
* They cannot be implemented as macros
*/
u16 XIo_InSwap16(XIo_Address InAddress);
u32 XIo_InSwap32(XIo_Address InAddress);
void XIo_OutSwap16(XIo_Address OutAddress, u16 Value);
void XIo_OutSwap32(XIo_Address OutAddress, u32 Value);
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */

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software/LED_Controller_bsp/microblaze_mcs/libsrc/iomodule_v1_04_a/src/Makefile Normal file
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COMPILER=
ARCHIVER=
CP=cp
COMPILER_FLAGS=
EXTRA_COMPILER_FLAGS=
LIB=libxil.a
LEVEL=0
RELEASEDIR=../../../lib
INCLUDEDIR=../../../include
INCLUDES=-I./. -I${INCLUDEDIR}
INCLUDEFILES=*.h
LIBSOURCES=*.c
OUTS = *.o
libs:
echo "Compiling iomodule"
$(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES)
$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS}
make clean
include:
${CP} $(INCLUDEFILES) $(INCLUDEDIR)
clean:
rm -rf ${OUTS}

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software/LED_Controller_bsp/microblaze_mcs/libsrc/iomodule_v1_04_a/src/xiomodule.h Normal file
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/* $Id$ */
/******************************************************************************
*
* (c) Copyright 2011,2012 Xilinx, Inc. All rights reserved.
*
* This file contains confidential and proprietary information of Xilinx, Inc.
* and is protected under U.S. and international copyright and other
* intellectual property laws.
*
* DISCLAIMER
* This disclaimer is not a license and does not grant any rights to the
* materials distributed herewith. Except as otherwise provided in a valid
* license issued to you by Xilinx, and to the maximum extent permitted by
* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
* and (2) Xilinx shall not be liable (whether in contract or tort, including
* negligence, or under any other theory of liability) for any loss or damage
* of any kind or nature related to, arising under or in connection with these
* materials, including for any direct, or any indirect, special, incidental,
* or consequential loss or damage (including loss of data, profits, goodwill,
* or any type of loss or damage suffered as a result of any action brought by
* a third party) even if such damage or loss was reasonably foreseeable or
* Xilinx had been advised of the possibility of the same.
*
* CRITICAL APPLICATIONS
* Xilinx products are not designed or intended to be fail-safe, or for use in
* any application requiring fail-safe performance, such as life-support or
* safety devices or systems, Class III medical devices, nuclear facilities,
* applications related to the deployment of airbags, or any other applications
* that could lead to death, personal injury, or severe property or
* environmental damage (individually and collectively, "Critical
* Applications"). Customer assumes the sole risk and liability of any use of
* Xilinx products in Critical Applications, subject only to applicable laws
* and regulations governing limitations on product liability.
*
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
* AT ALL TIMES.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xiomodule.h
*
* The Xilinx IO Module driver component. This component supports the
* IO Module. The IO Module provides:
* <ol>
* <li>Universal Asynchronous Receiver Transmitter (UART)</li>
* <li>Fixed Interval Timer (FIT)</li>
* <li>Programmable Interval Timer (PIT)</li>
* <li>General Purpose Output (GPO)</li>
* <li>General Purpose Input (GPI)</li>
* <li>Interrupt controller (INTC)</li>
* <li>IO bus (IO)</li>
* </ol>
*
* <b>Universal Asynchronous Receiver Transmitter (UART):</b>
* This UART is a minimal hardware implementation with minimal features. Most
* of the features, including parity, and number of data bits are only
* configurable when the hardware device is built, rather than at run time by
* software. The UART has an internal baud rate generator that is clocked at a
* specified input clock frequency. The baud rate can either be fixed, or
* programmable. Not all programmed baud rates can be generated from some clock
* frequencies. The requested baud rate is checked using the provided clock for
* the system, and checked against the acceptable error range. An error may be
* returned from some functions indicating the baud rate was in error because
* it could not be generated.
*
* The device has support for interrupts: a transmit interrupt, a receive
* interrupt, and an error interrupt. The interrupts are individually
* configurable when the hardware device is built.
*
* The driver defaults to no interrupts at initialization such that interrupts
* must be enabled if desired. An interrupt is generated when the transmitter
* transitions from having data to being empty, when any data is contained in
* the receive register, or when an error occurs in received data.
*
* In order to use interrupts, it's necessary for the user to connect the driver
* interrupt handler, XIOModule_InterruptHandler, to the interrupt system of the
* application. This function does not save and restore the processor context
* such that the user must provide it. Send and receive handlers may be set for
* the driver such that the handlers are called when transmit and receive
* interrupts occur. The handlers are called from interrupt context and are
* designed to allow application specific processing to be performed.
*
* The functions, XIOModule_Send and XIOModule_Recv, are provided in the driver
* to allow data to be sent and received. They are designed to be used in
* polled or interrupt modes.
*
* The driver provides a status for each received byte indicating any parity
* frame or overrun error. The driver provides statistics which allow visibility
* into these errors.
*
* <b>Fixed Interval Timer (FIT):</b>
* The fixed interval timer supports the following features:
* - Interrupt driven mode
*
* The timer has a hardware programmed time period, which can be configured to
* cause a periodic interrupt. The driver only provides the ability to handle
* such interrupts.
*
* <b>Programmable Interval Timer (PIT):</b>
* The programmable interval timer supports the following features:
* - Polled mode
* - Interrupt driven mode
* - Enabling and disabling
* - Automatic reload
*
* The timer operates in compare mode. The timer always counts down.
*
* Compare mode is typically used for creating a single time period or multiple
* repeating time periods in the auto reload mode, such as a periodic interrupt.
* When started, the timer loads an initial value, referred to as the load
* value, into the timer and starts counting down. The timer expires when it
* rolls under. An external Output signal may be configured such that a pulse
* is generated with this signal when it rolls under.
*
* The timer can be configured to cause an interrupt when the count reaches
* zero. An external output is also toggled when the count reaches zero.
*
* <b>Interrupts</b>
*
* It is the responsibility of the application to connect the interrupt
* handler of the timer to the interrupt source. The interrupt handler function,
* XIOModule_InterruptHandler, is visible such that the user can connect it to
* the interrupt source. Note that this interrupt handler does not provide
* interrupt context save and restore processing, the user must perform this
* processing.
*
* The driver services interrupts and passes timeouts to the upper layer
* software through callback functions. The upper layer software must register
* its callback functions during initialization. The driver requires callback
* functions for timers.
*
* <b>General Purpose Output (GPO):</b>
* The GPO has support for up to 32 I/O discrete outputs for each channel (128
* bits total).
*
* <b>IO Bus (IO):</b>
* The IO Bus provides a generic mechanism to extend the IO Module
* functionality by providing a memory mapped IO area. Reading and writing of
* byte, halfword and word data is provided.
*
* <b>General Purpose Input (GPI):</b>
* The GPI has support for up to 32 I/O discrete outputs for each channel (128
* bits total). An interrupt can be generated when any bit in a GPI changes.
*
* <b>Interrupt controller (INTC):</b>
* The interrupt controller driver uses the idea of priority for the various
* handlers. Priority is an integer within the range of 0 and 31 inclusive with
* 0 being the highest priority interrupt source.
*
* The Xilinx interrupt controller supports the following features:
*
* - specific individual interrupt enabling/disabling
* - specific individual interrupt acknowledging
* - attaching specific callback function to handle interrupt source
* - master enable/disable
* - single callback per interrupt or all pending interrupts handled for
* each interrupt of the processor
*
* The acknowledgement of the interrupt within the interrupt controller is
* selectable, either prior to the device's handler being called or after
* the handler is called. This is necessary to support interrupt signal inputs
* which are either edge or level signals. Edge driven interrupt signals
* require that the interrupt is acknowledged prior to the interrupt being
* serviced in order to prevent the loss of interrupts which are occurring
* extremely close together. A level driven interrupt input signal requires
* the interrupt to acknowledged after servicing the interrupt to ensure that
* the interrupt only generates a single interrupt condition.
*
* Details about connecting the interrupt handler of the driver are contained
* in the source file specific to interrupt processing, xiomodule_intr.c.
*
* This driver is intended to be RTOS and processor independent. It works with
* physical addresses only. Any needs for dynamic memory management, threads
* or thread mutual exclusion, virtual memory, or cache control must be
* satisfied by the layer above this driver.
*
* <b>Interrupt Vector Tables</b>
*
* The interrupt vector table for each interrupt controller device is declared
* statically in xiomodule_g.c within the configuration data for each instance.
* The device ID of the interrupt controller device is used by the driver as a
* direct index into the configuration data table - to retrieve the vector table
* for an instance of the interrupt controller. The user should populate the
* vector table with handlers and callbacks at run-time using the
* XIOModule_Connect() and XIOModule_Disconnect() functions.
*
* Each vector table entry corresponds to a device that can generate an
* interrupt. Each entry contains an interrupt handler function and an argument
* to be passed to the handler when an interrupt occurs. The tools default this
* argument to the base address of the interrupting device. Note that the
* device driver interrupt handlers given in this file do not take a base
* address as an argument, but instead take a pointer to the driver instance.
* This means that although the table is created statically, the user must still
* use XIOModule_Connect() when the interrupt handler takes an argument other
* than the base address. This is only to say that the existence of the static
* vector tables should not mislead the user into thinking they no longer need
* to register/connect interrupt handlers with this driver.
*
* With fast interrupts enabled, the XIOModule_ConnectFastHandler() function
* should be used instead of XIOModule_Connect(). Note that the function pointer
* parameter Handler, must be a declared with the fast_interrupt attribute:
*
* void Handler() __attribute__((fast_interrupt));
*
* The routine defined by XIOModule_Connect() can be used by setting normal
* interrupt mode, using XIOModule_SetNormalIntrMode().
*
* @note
*
* This API utilizes 32 bit I/O to the registers. With less than 32 bits, the
* unused bits from registers are read as zero and written as don't cares.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00a sa 07/15/11 First release
* 1.01a sa 04/10/12 Updated with fast interrupt
* 1.02a sa 07/25/12 Updated with GPI interrupts and programmable baudrate
* </pre>
*
******************************************************************************/
#ifndef IOMODULE_H /* prevent circular inclusions */
#define IOMODULE_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xbasic_types.h"
#include "xparameters.h"
#include "xstatus.h"
#include "xiomodule_l.h"
/************************** Constant Definitions *****************************/
/**
* @name Configuration options
* These options are used in XIOModule_SetOptions() to configure the
* device.
* @{
*/
/**
* Used to configure the Programmable Interval Timer.
* <pre>
* XTC_INT_MODE_OPTION Dummy compatibility option. Enable interrupt
* output.
* XTC_AUTO_RELOAD_OPTION In compare mode, configures the timer to reload
* from the load value. The default mode causes
* the timer to hold after it rolls under.
* </pre>
*/
#define XTC_INT_MODE_OPTION 0
#define XTC_AUTO_RELOAD_OPTION 0x00000002UL
/**
* Used to configure the Interrupt Controller.
* <pre>
* XIN_SVC_SGL_ISR_OPTION Service the highest priority pending interrupt
* and then return.
* XIN_SVC_ALL_ISRS_OPTION Service all of the pending interrupts and then
* return.
* </pre>
*/
#define XIN_SVC_SGL_ISR_OPTION 1UL
#define XIN_SVC_ALL_ISRS_OPTION 2UL
/*@}*/
/**
* @name Hardware configuration mnemonics
* These mnemonics are used when accessing hardware configuration parameters.
* @{
*/
/**
* Mnemonics for the Programmable Interval Timer hardware configuration.
* <pre>
* XTC_PRESCALER_* Define the prescaler configured in hardware.
* </pre>
*/
#define XTC_PRESCALER_NONE 0
#define XTC_PRESCALER_FIT1 1
#define XTC_PRESCALER_FIT2 2
#define XTC_PRESCALER_FIT3 3
#define XTC_PRESCALER_FIT4 4
#define XTC_PRESCALER_PIT1 5
#define XTC_PRESCALER_PIT2 6
#define XTC_PRESCALER_PIT3 7
#define XTC_PRESCALER_PIT4 8
#define XTC_PRESCALER_EXTERNAL 9
/*@}*/
/**************************** Type Definitions *******************************/
/**
* Callback function. The first argument is a callback reference passed in by
* the upper layer when setting the callback functions, and passed back to the
* upper layer when the callback is invoked.
* The second argument is the ByteCount which is the number of bytes that
* actually moved from/to the buffer provided in the _Send/_Receive call.
*/
typedef void (*XIOModule_Handler)(void *CallBackRef,
unsigned int ByteCount);
/**
* This typedef contains configuration information for the device.
*/
typedef struct {
u16 DeviceId; /**< Unique ID of device */
u32 BaseAddress; /**< Unique identifier */
u32 IoBaseAddress; /**< IO Bus Base Address */
u32 FastIntr; /**< Fast Interrupt enabled */
u32 BaseVector; /**< Relocatable base vector */
u32 AckBeforeService; /**< Ack location per interrupt */
u32 Options; /**< Device options */
u32 InputClockHz; /**< Input clock frequency (Hz) */
u32 BaudRate; /**< Current baud rate */
u8 PitUsed[XTC_DEVICE_TIMER_COUNT]; /**< PIT is used */
u8 PitSize[XTC_DEVICE_TIMER_COUNT]; /**< PIT timer counter size */
u8 PitPrescaler[XTC_DEVICE_TIMER_COUNT]; /**< PIT prescaler */
u8 PitReadable[XTC_DEVICE_TIMER_COUNT]; /**< PIT readable */
u32 GpoInit[XGPO_DEVICE_COUNT]; /**< GPO initial value */
XIOModule_VectorTableEntry
HandlerTable[XPAR_IOMODULE_INTC_MAX_INTR_SIZE];
/**< Static vector table of interrupt handlers */
} XIOModule_Config;
/**
* Statistics for the UART
*/
typedef struct {
u32 TransmitInterrupts; /**< Number of transmit interrupts */
u32 ReceiveInterrupts; /**< Number of receive interrupts */
u32 CharactersTransmitted; /**< Number of characters transmitted */
u32 CharactersReceived; /**< Number of characters received */
u32 ReceiveOverrunErrors; /**< Number of receive overruns */
u32 ReceiveParityErrors; /**< Number of receive parity errors */
u32 ReceiveFramingErrors; /**< Number of receive framing errors */
} XIOModule_Uart_Stats;
/**
* The following data type is used to manage the buffers that are handled
* when sending and receiving UART data in the interrupt mode. It is intended
* for internal use only.
*/
typedef struct {
u8 *NextBytePtr;
unsigned int RequestedBytes;
unsigned int RemainingBytes;
} XIOModule_Buffer;
/**
* Signature for the timer callback function.
*
* @param CallBackRef is a callback reference passed in by the upper
* layer when setting the callback functions, and passed back to
* the upper layer when the callback is invoked. Its type is
* unimportant to the driver, so it is a void pointer.
* @param TimerNumber is the number of the timer within the device. The
* device typically contains from one to four timers. The timer
* number is a zero based number with a range of 0 to
* (XTC_DEVICE_TIMER_COUNT - 1).
*/
typedef void (*XIOModule_Timer_Handler) (void *CallBackRef, u8 TimerNumber);
/**
* Programmable Interval Timer statistics
*/
typedef struct {
u32 Interrupts; /**< Number of timer interrupts that have occurred */
} XIOModule_Timer_Stats;
/**
* The XIOModule driver instance data. The user is required to allocate a
* variable of this type for every iomodule device in the system. A pointer
* to a variable of this type is then passed to the driver API functions.
*/
typedef struct {
u32 BaseAddress; /**< Base address of registers */
u32 IsReady; /**< Device initialized and ready */
u32 IsStarted; /**< Device has been started */
XIOModule_Config *CfgPtr; /**< Pointer to inst config entry */
XIOModule_Uart_Stats Uart_Stats; /**< UART Statistics */
XIOModule_Buffer SendBuffer; /**< UART Send buffer */
XIOModule_Buffer ReceiveBuffer; /**< UART Receive buffer */
XIOModule_Handler RecvHandler; /**< UART Receive Handler */
void *RecvCallBackRef; /**< Callback ref for recv handler */
XIOModule_Handler SendHandler; /**< UART Send Handler */
void *SendCallBackRef; /**< Callback ref for send handler */
u32 CurrentUBRR; /**< UART Baud Rate Register value */
u32 UnhandledInterrupts; /**< Iomodule Interrupt Statistics */
u32 CurrentIER; /**< Interrupt Enable Register value*/
u32 CurrentIMR; /**< Interrupt Mode Register value */
XIOModule_Timer_Stats Timer_Stats[XTC_DEVICE_TIMER_COUNT];
/**< Timer statistics */
u32 CurrentTLR[XTC_DEVICE_TIMER_COUNT];
/**< Timer Load Register values */
u8 CurrentTCSR[XTC_DEVICE_TIMER_COUNT];
/**< Timer Control Register values */
XIOModule_Timer_Handler Handler; /**< Timer Callback function */
void *CallBackRef; /**< Timer Callback handler ref */
u32 GpoValue[XGPO_DEVICE_COUNT]; /**< GPO current value */
u32 IoBaseAddress; /**< Base address of IO Bus */
} XIOModule;
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
/*
* Required functions in xiomodule.c
*/
int XIOModule_Initialize(XIOModule * InstancePtr, u16 DeviceId);
int XIOModule_Timer_Initialize(XIOModule * InstancePtr, u16 DeviceId);
int XIOModule_Start(XIOModule * InstancePtr);
void XIOModule_Stop(XIOModule * InstancePtr);
int XIOModule_Connect(XIOModule * InstancePtr, u8 Id,
XInterruptHandler Handler, void *CallBackRef);
void XIOModule_Disconnect(XIOModule * InstancePtr, u8 Id);
void XIOModule_Enable(XIOModule * InstancePtr, u8 Id);
void XIOModule_Disable(XIOModule * InstancePtr, u8 Id);
void XIOModule_Acknowledge(XIOModule * InstancePtr, u8 Id);
XIOModule_Config *XIOModule_LookupConfig(u16 DeviceId);
int XIOModule_ConnectFastHandler(XIOModule *InstancePtr, u8 Id,
XFastInterruptHandler Handler);
void XIOModule_SetNormalIntrMode(XIOModule *InstancePtr, u8 Id);
/*
* API Basic functions for GPI and GPO implemented in xiomodule.c
*/
u32 XIOModule_DiscreteRead(XIOModule *InstancePtr, unsigned Channel);
void XIOModule_DiscreteWrite(XIOModule *InstancePtr,
unsigned Channel,
u32 Mask);
/*
* API Functions for GPI and GPO implemented in xiomodule_extra.c
*/
void XIOModule_DiscreteSet(XIOModule *InstancePtr, unsigned Channel, u32 Mask);
void XIOModule_DiscreteClear(XIOModule *InstancePtr,
unsigned Channel,
u32 Mask);
/*
* Required functions, in file xiomodule_uart.c
*/
int XIOModule_CfgInitialize(XIOModule *InstancePtr,
XIOModule_Config *Config,
u32 EffectiveAddr);
void XIOModule_ResetFifos(XIOModule *InstancePtr); /* Dummy */
unsigned int XIOModule_Send(XIOModule *InstancePtr, u8 *DataBufferPtr,
unsigned int NumBytes);
unsigned int XIOModule_Recv(XIOModule *InstancePtr, u8 *DataBufferPtr,
unsigned int NumBytes);
int XIOModule_IsSending(XIOModule *InstancePtr);
int XIOModule_SetBaudRate(XIOModule *InstancePtr, u32 BaudRate);
/*
* Functions for statistics, in file xiomodule_stats.c
*/
void XIOModule_GetStats(XIOModule *InstancePtr,
XIOModule_Uart_Stats *StatsPtr);
void XIOModule_ClearStats(XIOModule *InstancePtr);
/*
* Interrupt functions in xiomodule_intr.c
*/
void XIOModule_VoidInterruptHandler();
void XIOModule_InterruptHandler(XIOModule * InstancePtr);
void XIOModule_Uart_EnableInterrupt(XIOModule *InstancePtr);
void XIOModule_Uart_DisableInterrupt(XIOModule *InstancePtr);
void XIOModule_SetRecvHandler(XIOModule *InstancePtr, XIOModule_Handler FuncPtr,
void *CallBackRef);
void XIOModule_SetSendHandler(XIOModule *InstancePtr, XIOModule_Handler FuncPtr,
void *CallBackRef);
void XIOModule_Uart_InterruptHandler(XIOModule *InstancePtr);
/*
* Options functions in xiomodule_options.c
*/
int XIOModule_SetOptions(XIOModule * InstancePtr, u32 Options);
u32 XIOModule_GetOptions(XIOModule * InstancePtr);
/*
* Self-test functions in xiomodule_selftest.c
*/
int XIOModule_SelfTest(XIOModule * InstancePtr);
/*
* Required functions, in file xiomodule.c
*/
void XIOModule_Timer_Start(XIOModule * InstancePtr, u8 TimerNumber);
void XIOModule_Timer_Stop(XIOModule * InstancePtr, u8 TimerNumber);
u32 XIOModule_GetValue(XIOModule * InstancePtr, u8 TimerNumber);
void XIOModule_SetResetValue(XIOModule * InstancePtr, u8 TimerNumber,
u32 ResetValue);
u32 XIOModule_GetCaptureValue(XIOModule * InstancePtr, u8 TimerNumber);
int XIOModule_IsExpired(XIOModule * InstancePtr, u8 TimerNumber);
void XIOModule_Reset(XIOModule * InstancePtr, u8 TimerNumber);
/*
* Functions for options, in file xiomodule_options.c
*/
void XIOModule_Timer_SetOptions(XIOModule * InstancePtr, u8 TimerNumber,
u32 Options);
u32 XIOModule_Timer_GetOptions(XIOModule * InstancePtr, u8 TimerNumber);
/*
* Functions for statistics, in file xiomodule_stats.c
*/
void XIOModule_Timer_GetStats(XIOModule * InstancePtr,
XIOModule_Timer_Stats * StatsPtr);
void XIOModule_Timer_ClearStats(XIOModule * InstancePtr);
/*
* Functions for self-test, in file xiomodule_selftest.c
*/
int XIOModule_Timer_SelfTest(XIOModule * InstancePtr, u8 IOModuleNumber);
/*
* Functions for interrupts, in file xiomodule_intr.c
*/
void XIOModule_SetHandler(XIOModule * InstancePtr,
XIOModule_Timer_Handler FuncPtr,
void *CallBackRef);
void XIOModule_Timer_InterruptHandler(void *InstancePtr);
/*
* Basic functions for IO Bus read and write implemented in xiomodule.c
*/
u32 XIOModule_IoReadWord(XIOModule *InstancePtr, u32 ByteOffset);
u16 XIOModule_IoReadHalfword(XIOModule *InstancePtr, u32 ByteOffset);
u8 XIOModule_IoReadByte(XIOModule *InstancePtr, u32 ByteOffset);
void XIOModule_IoWriteWord(XIOModule *InstancePtr, u32 ByteOffset, u32 Data);
void XIOModule_IoWriteHalfword(XIOModule *InstancePtr, u32 ByteOffset, u16 Data);
void XIOModule_IoWriteByte(XIOModule *InstancePtr, u32 ByteOffset, u8 Data);
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */

158
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/* $Id$ */
/******************************************************************************
*
* (c) Copyright 2011 Xilinx, Inc. All rights reserved.
*
* This file contains confidential and proprietary information of Xilinx, Inc.
* and is protected under U.S. and international copyright and other
* intellectual property laws.
*
* DISCLAIMER
* This disclaimer is not a license and does not grant any rights to the
* materials distributed herewith. Except as otherwise provided in a valid
* license issued to you by Xilinx, and to the maximum extent permitted by
* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
* and (2) Xilinx shall not be liable (whether in contract or tort, including
* negligence, or under any other theory of liability) for any loss or damage
* of any kind or nature related to, arising under or in connection with these
* materials, including for any direct, or any indirect, special, incidental,
* or consequential loss or damage (including loss of data, profits, goodwill,
* or any type of loss or damage suffered as a result of any action brought by
* a third party) even if such damage or loss was reasonably foreseeable or
* Xilinx had been advised of the possibility of the same.
*
* CRITICAL APPLICATIONS
* Xilinx products are not designed or intended to be fail-safe, or for use in
* any application requiring fail-safe performance, such as life-support or
* safety devices or systems, Class III medical devices, nuclear facilities,
* applications related to the deployment of airbags, or any other applications
* that could lead to death, personal injury, or severe property or
* environmental damage (individually and collectively, "Critical
* Applications"). Customer assumes the sole risk and liability of any use of
* Xilinx products in Critical Applications, subject only to applicable laws
* and regulations governing limitations on product liability.
*
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
* AT ALL TIMES.
*
******************************************************************************/
/*****************************************************************************/
/**
* @file xiomodule_extra.c
*
* The implementation of the XIOModule component's advanced discrete
* functions. See xiomodule.h for more information about the component.
*
* @note
*
* None
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.00a sa 07/15/11 First release
* </pre>
*
*****************************************************************************/
/***************************** Include Files ********************************/
#include "xiomodule.h"
#include "xiomodule_i.h"
/************************** Constant Definitions ****************************/
/**************************** Type Definitions ******************************/
/***************** Macros (Inline Functions) Definitions ********************/
/************************** Variable Definitions ****************************/
/************************** Function Prototypes *****************************/
/****************************************************************************/
/**
* Set output discrete(s) to logic 1 for the specified GPO channel.
*
* @param InstancePtr is a pointer to an XIOModule instance to be
* worked on.
* @param Channel contains the channel of the GPIO (1, 2, 3 or 4) to
* operate on.
* @param Mask is the set of bits that will be set to 1 in the discrete
* data register. All other bits in the data register are
* unaffected.
*
* @return None.
*
*****************************************************************************/
void XIOModule_DiscreteSet(XIOModule * InstancePtr, unsigned Channel, u32 Mask)
{
u32 Current;
unsigned DataOffset;
XASSERT_VOID(InstancePtr != NULL);
XASSERT_VOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
XASSERT_VOID((Channel >= 1) && (Channel <= XGPO_DEVICE_COUNT));
/*
* Calculate the offset to the data register of the GPO
*/
DataOffset = ((Channel - 1) * XGPO_CHAN_OFFSET) + XGPO_DATA_OFFSET;
/*
* Read the contents from the instance, merge in Mask and write
* back results
*/
Current = InstancePtr->GpoValue[Channel - 1];
Current |= Mask;
XIOModule_WriteReg(InstancePtr->BaseAddress, DataOffset, Current);
InstancePtr->GpoValue[Channel - 1] = Current;
}
/****************************************************************************/
/**
* Set output discrete(s) to logic 0 for the specified GPO channel.
*
* @param InstancePtr is a pointer to an XIOModule instance to be
* worked on.
* @param Channel contains the channel of the GPIO (1, 2, 3 or 4) to
* operate on.
* @param Mask is the set of bits that will be set to 0 in the discrete
* data register. All other bits in the data register are
* unaffected.
*
* @return None.
*
*****************************************************************************/
void XIOModule_DiscreteClear(XIOModule * InstancePtr,
unsigned Channel,
u32 Mask)
{
u32 Current;
unsigned DataOffset;
XASSERT_VOID(InstancePtr != NULL);
XASSERT_VOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
XASSERT_VOID((Channel >= 1) && (Channel <= XGPO_DEVICE_COUNT));
/*
* Calculate the offset to the data register of the GPO
*/
DataOffset = ((Channel - 1) * XGPO_CHAN_OFFSET) + XGPO_DATA_OFFSET;
/*
* Read the contents from the instance, merge in Mask and write
* back results
*/
Current = InstancePtr->GpoValue[Channel - 1];
Current &= ~Mask;
XIOModule_WriteReg(InstancePtr->BaseAddress, DataOffset, Current);
InstancePtr->GpoValue[Channel - 1] = Current;
}

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/*******************************************************************
*
* CAUTION: This file is automatically generated by libgen.
* Version: Xilinx EDK 14.7 EDK_P.20131013
* DO NOT EDIT.
*
* Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
*
* Description: Driver configuration
*
*******************************************************************/
#include "xparameters.h"
#include "xiomodule.h"
/*
* The configuration table for devices
*/
XIOModule_Config XIOModule_ConfigTable[] =
{
{
XPAR_IOMODULE_0_DEVICE_ID,
XPAR_IOMODULE_0_BASEADDR,
XPAR_IOMODULE_0_IO_BASEADDR,
XPAR_IOMODULE_0_INTC_HAS_FAST,
XPAR_IOMODULE_0_INTC_BASE_VECTORS,
((XPAR_IOMODULE_0_INTC_LEVEL_EDGE << 16) | 0x7FF),
XIN_SVC_SGL_ISR_OPTION,
XPAR_IOMODULE_0_FREQ,
XPAR_IOMODULE_0_UART_BAUDRATE,
{
XPAR_IOMODULE_0_USE_PIT1,
XPAR_IOMODULE_0_USE_PIT2,
XPAR_IOMODULE_0_USE_PIT3,
XPAR_IOMODULE_0_USE_PIT4,
},
{
XPAR_IOMODULE_0_PIT1_SIZE,
XPAR_IOMODULE_0_PIT2_SIZE,
XPAR_IOMODULE_0_PIT3_SIZE,
XPAR_IOMODULE_0_PIT4_SIZE,
},
{
XPAR_IOMODULE_0_PIT1_PRESCALER,
XPAR_IOMODULE_0_PIT2_PRESCALER,
XPAR_IOMODULE_0_PIT3_PRESCALER,
XPAR_IOMODULE_0_PIT4_PRESCALER,
},
{
XPAR_IOMODULE_0_PIT1_READABLE,
XPAR_IOMODULE_0_PIT2_READABLE,
XPAR_IOMODULE_0_PIT3_READABLE,
XPAR_IOMODULE_0_PIT4_READABLE,
},
{
XPAR_IOMODULE_0_GPO1_INIT,
XPAR_IOMODULE_0_GPO2_INIT,
XPAR_IOMODULE_0_GPO3_INIT,
XPAR_IOMODULE_0_GPO4_INIT,
},
{
{
XNullHandler,
(void *)XNULL
},
{
XNullHandler,
(void *)XNULL
},
{
XNullHandler,
(void *)XNULL
},
{
XNullHandler,
(void *)XNULL
},
{
XNullHandler,
(void *)XNULL
},
{
XNullHandler,
(void *)XNULL
},
{
XNullHandler,
(void *)XNULL
},
{
XNullHandler,
(void *)XNULL
},
{
XNullHandler,
(void *)XNULL
},
{
XNullHandler,
(void *)XNULL
},
{
XNullHandler,
(void *)XNULL
},
{
XNullHandler,
(void *)XNULL
},
{
XNullHandler,
(void *)XNULL
}
}
}
};

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/* $Id$ */
/******************************************************************************
*
* (c) Copyright 2011 Xilinx, Inc. All rights reserved.
*
* This file contains confidential and proprietary information of Xilinx, Inc.
* and is protected under U.S. and international copyright and other
* intellectual property laws.
*
* DISCLAIMER
* This disclaimer is not a license and does not grant any rights to the
* materials distributed herewith. Except as otherwise provided in a valid
* license issued to you by Xilinx, and to the maximum extent permitted by
* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
* and (2) Xilinx shall not be liable (whether in contract or tort, including
* negligence, or under any other theory of liability) for any loss or damage
* of any kind or nature related to, arising under or in connection with these
* materials, including for any direct, or any indirect, special, incidental,
* or consequential loss or damage (including loss of data, profits, goodwill,
* or any type of loss or damage suffered as a result of any action brought by
* a third party) even if such damage or loss was reasonably foreseeable or
* Xilinx had been advised of the possibility of the same.
*
* CRITICAL APPLICATIONS
* Xilinx products are not designed or intended to be fail-safe, or for use in
* any application requiring fail-safe performance, such as life-support or
* safety devices or systems, Class III medical devices, nuclear facilities,
* applications related to the deployment of airbags, or any other applications
* that could lead to death, personal injury, or severe property or
* environmental damage (individually and collectively, "Critical
* Applications"). Customer assumes the sole risk and liability of any use of
* Xilinx products in Critical Applications, subject only to applicable laws
* and regulations governing limitations on product liability.
*
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
* AT ALL TIMES.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xiomodule_i.h
*
* This file contains data which is shared between files and internal to the
* XIOModule component. It is intended for internal use only.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00a sa 07/15/11 First release
* 1.02a sa 07/25/12 Added UART prototypes
* </pre>
*
******************************************************************************/
#ifndef XIOMODULE_I_H /* prevent circular inclusions */
#define XIOMODULE_I_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xbasic_types.h"
#include "xiomodule.h"
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/****************************************************************************
*
* Update the statistics of the instance.
*
* @param InstancePtr is a pointer to the XIOMOdule instance.
* @param StatusRegister contains the contents of the UART status
* register to update the statistics with.
*
* @return None.
*
* @note
*
* Signature: void XIOModule_UpdateStats(XIOModule *InstancePtr,
* u32 StatusRegister)
*
*****************************************************************************/
#define XIOModule_UpdateStats(InstancePtr, StatusRegister) \
{ \
if ((StatusRegister) & XUL_SR_OVERRUN_ERROR) \
{ \
(InstancePtr)->Uart_Stats.ReceiveOverrunErrors++; \
} \
if ((StatusRegister) & XUL_SR_PARITY_ERROR) \
{ \
(InstancePtr)->Uart_Stats.ReceiveParityErrors++; \
} \
if ((StatusRegister) & XUL_SR_FRAMING_ERROR) \
{ \
(InstancePtr)->Uart_Stats.ReceiveFramingErrors++; \
} \
}
/************************** Function Prototypes ******************************/
unsigned int XIOModule_SendBuffer(XIOModule *InstancePtr);
unsigned int XIOModule_ReceiveBuffer(XIOModule *InstancePtr);
/************************** Variable Definitions *****************************/
extern u32 XIOModule_BitPosMask[];
extern XIOModule_Config XIOModule_ConfigTable[];
#ifdef __cplusplus
}
#endif
#endif

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/* $Id$ */
/******************************************************************************
*
* (c) Copyright 2011-2012 Xilinx, Inc. All rights reserved.
*
* This file contains confidential and proprietary information of Xilinx, Inc.
* and is protected under U.S. and international copyright and other
* intellectual property laws.
*
* DISCLAIMER
* This disclaimer is not a license and does not grant any rights to the
* materials distributed herewith. Except as otherwise provided in a valid
* license issued to you by Xilinx, and to the maximum extent permitted by
* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
* and (2) Xilinx shall not be liable (whether in contract or tort, including
* negligence, or under any other theory of liability) for any loss or damage
* of any kind or nature related to, arising under or in connection with these
* materials, including for any direct, or any indirect, special, incidental,
* or consequential loss or damage (including loss of data, profits, goodwill,
* or any type of loss or damage suffered as a result of any action brought by
* a third party) even if such damage or loss was reasonably foreseeable or
* Xilinx had been advised of the possibility of the same.
*
* CRITICAL APPLICATIONS
* Xilinx products are not designed or intended to be fail-safe, or for use in
* any application requiring fail-safe performance, such as life-support or
* safety devices or systems, Class III medical devices, nuclear facilities,
* applications related to the deployment of airbags, or any other applications
* that could lead to death, personal injury, or severe property or
* environmental damage (individually and collectively, "Critical
* Applications"). Customer assumes the sole risk and liability of any use of
* Xilinx products in Critical Applications, subject only to applicable laws
* and regulations governing limitations on product liability.
*
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
* AT ALL TIMES.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xiomodule_intr.c
*
* This file contains the interrupt processing for the XIOModule component
* which is the driver for the Xilinx IO Module interrupt. The interrupt
* processing is partitioned seperately such that users are not required to
* use the provided interrupt processing. This file requires other files of
* the driver to be linked in also.
*
* Two different interrupt handlers are provided for this driver such that the
* user must select the appropriate handler for the application. The first
* interrupt handler, XIOModule_VoidInterruptHandler, is provided for
* systems which use only a single interrupt controller or for systems that
* cannot otherwise provide an argument to the XIOModule interrupt handler
* (e.g., the RTOS interrupt vector handler may not provide such a facility).
* The constant XPAR_IOMODULE_SINGLE_DEVICE_ID must be defined for this
* handler to be included in the driver. The second interrupt handler,
* XIOModule_InterruptHandler, uses an input argument which is an instance
* pointer to an interrupt controller driver such that multiple interrupt
* controllers can be supported. This handler requires the calling function
* to pass it the appropriate argument, so another level of indirection may be
* required.
*
* Note that both of these handlers are now only provided for backward
* compatibility. The handler defined in xiomodule_l.c is the recommended
* handler.
*
* The interrupt processing may be used by connecting one of the interrupt
* handlers to the interrupt system. These handlers do not save and restore
* the processor context but only handle the processing of the Interrupt
* Controller. The two handlers are provided as working examples. The user is
* encouraged to supply their own interrupt handler when performance tuning is
* deemed necessary.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- ---------------------------------------------------------
* 1.00a sa 07/15/11 First release
* 1.02a sa 07/25/12 Added UART interrupt related functions
* 1.03a sa 10/16/12 Moved UART interrupt related functions to separate file
* </pre>
*
* @internal
*
* This driver assumes that the context of the processor has been saved prior to
* the calling of the IO Module interrupt handler and then restored
* after the handler returns. This requires either the running RTOS to save the
* state of the machine or that a wrapper be used as the destination of the
* interrupt vector to save the state of the processor and restore the state
* after the interrupt handler returns.
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "xbasic_types.h"
#include "xparameters.h"
#include "xiomodule.h"
/************************** Constant Definitions *****************************/
/*
* Array of masks associated with the bit position, improves performance
* in the ISR, this table is shared between all instances of the driver
*/
u32 XIOModule_TimerBitPosMask[XTC_DEVICE_TIMER_COUNT] = {
1 << XIN_IOMODULE_PIT_1_INTERRUPT_INTR,
1 << XIN_IOMODULE_PIT_2_INTERRUPT_INTR,
1 << XIN_IOMODULE_PIT_3_INTERRUPT_INTR,
1 << XIN_IOMODULE_PIT_4_INTERRUPT_INTR
};
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
/************************** Variable Definitions *****************************/
/*****************************************************************************/
/**
*
* Interrupt handler for the driver used when there can be no argument passed
* to the handler. This function is provided mostly for backward compatibility.
* The user should use XIOModule_DeviceInterruptHandler(), defined in
* xiomodule_l.c, if possible.
*
* The user must connect this function to the interrupt system such that it is
* called whenever the devices which are connected to it cause an interrupt.
*
* @return None.
*
* @note
*
* The constant XPAR_IOMODULE_SINGLE_DEVICE_ID must be defined for this handler
* to be included in the driver compilation.
*
******************************************************************************/
#ifdef XPAR_IOMODULE_SINGLE_DEVICE_ID
void XIOModule_VoidInterruptHandler()
{
/* Use the single instance to call the main interrupt handler */
XIOModule_DeviceInterruptHandler(
(void *) XPAR_IOMODULE_SINGLE_DEVICE_ID);
}
#endif
/*****************************************************************************/
/**
*
* The interrupt handler for the driver. This function is provided mostly for
* backward compatibility. The user should use
* XIOModule_DeviceInterruptHandler(), defined in xiomodule_l.c when
* possible and pass the device ID of the interrupt controller device as its
* argument.
*
* The user must connect this function to the interrupt system such that it is
* called whenever the devices which are connected to it cause an interrupt.
*
* @param InstancePtr is a pointer to the XIOModule instance to be
* worked on.
*
* @return None.
*
* @note None.
*
******************************************************************************/
void XIOModule_InterruptHandler(XIOModule * InstancePtr)
{
/* Assert that the pointer to the instance is valid
*/
XASSERT_VOID(InstancePtr != NULL);
/* Use the instance's device ID to call the main interrupt handler.
* (the casts are to avoid a compiler warning)
*/
XIOModule_DeviceInterruptHandler((void *)
((u32) (InstancePtr->CfgPtr->DeviceId)));
}
/*****************************************************************************/
/**
*
* Sets the timer callback function, which the driver calls when the specified
* timer times out.
*
* @param InstancePtr is a pointer to the XIOModule instance.
* @param CallBackRef is the upper layer callback reference passed back
* when the callback function is invoked.
* @param FuncPtr is the pointer to the callback function.
*
* @return None.
*
* @note
*
* The handler is called within interrupt context so the function that is
* called should either be short or pass the more extensive processing off
* to another task to allow the interrupt to return and normal processing
* to continue.
*
* This function is provided for compatibility, and only allows setting a
* single handler for all Programmable Interval Timers.
*
******************************************************************************/
void XIOModule_SetHandler(XIOModule * InstancePtr,
XIOModule_Timer_Handler FuncPtr,
void *CallBackRef)
{
u8 Index;
XASSERT_VOID(InstancePtr != NULL);
XASSERT_VOID(FuncPtr != NULL);
XASSERT_VOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
InstancePtr->Handler = FuncPtr;
InstancePtr->CallBackRef = CallBackRef;
for (Index = XIN_IOMODULE_PIT_1_INTERRUPT_INTR;
Index <= XIN_IOMODULE_PIT_4_INTERRUPT_INTR; Index++) {
InstancePtr->CfgPtr->HandlerTable[Index].Handler =
XIOModule_Timer_InterruptHandler;
}
}
/*****************************************************************************/
/**
*
* Interrupt Service Routine (ISR) for the driver. This function only performs
* processing for the Programmable Interval Timere and does not save and restore
* the interrupt context.
*
* @param InstancePtr contains a pointer to the IO Module instance for
* the interrupt.
*
* @return None.
*
* @note None.
*
******************************************************************************/
void XIOModule_Timer_InterruptHandler(void *InstancePtr)
{
XIOModule *IOModulePtr = NULL;
u8 Index;
u32 IntPendingReg, ModeMask;
/*
* Verify that each of the inputs are valid.
*/
XASSERT_VOID(InstancePtr != NULL);
/*
* Convert the non-typed pointer to an IO Module instance pointer
* such that there is access to the IO Module
*/
IOModulePtr = (XIOModule *) InstancePtr;
/*
* Read the pending interrupts to be able to check if interrupt occurred
*/
IntPendingReg = XIOModule_ReadReg(IOModulePtr->BaseAddress,
XIN_IPR_OFFSET);
ModeMask = ~IOModulePtr->CurrentIMR;
/*
* Loop thru each timer in the device and call the callback function
* for each timer which has caused an interrupt, but only if not fast
*/
for (Index = 0; Index < XTC_DEVICE_TIMER_COUNT; Index++) {
/*
* Check if timer is enabled
*/
if (IOModulePtr->CfgPtr->PitUsed[Index]) {
/*
* Check if timer expired and interrupt occured,
* but only if it is not a fast interrupt
*/
if (IntPendingReg & ModeMask & XIOModule_TimerBitPosMask[Index]) {
/*
* Increment statistics for the number of interrupts and call
* the callback to handle any application specific processing
*/
IOModulePtr->Timer_Stats[Index].Interrupts++;
IOModulePtr->Handler(IOModulePtr->CallBackRef, Index);
/*
* Acknowledge the interrupt in the interrupt controller
* acknowledge register to mark it as handled
*/
XIOModule_WriteReg(IOModulePtr->BaseAddress,
XIN_IAR_OFFSET,
XIOModule_TimerBitPosMask[Index]);
}
}
}
}

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/* $Id$ */
/******************************************************************************
*
* (c) Copyright 2011 Xilinx, Inc. All rights reserved.
*
* This file contains confidential and proprietary information of Xilinx, Inc.
* and is protected under U.S. and international copyright and other
* intellectual property laws.
*
* DISCLAIMER
* This disclaimer is not a license and does not grant any rights to the
* materials distributed herewith. Except as otherwise provided in a valid
* license issued to you by Xilinx, and to the maximum extent permitted by
* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
* and (2) Xilinx shall not be liable (whether in contract or tort, including
* negligence, or under any other theory of liability) for any loss or damage
* of any kind or nature related to, arising under or in connection with these
* materials, including for any direct, or any indirect, special, incidental,
* or consequential loss or damage (including loss of data, profits, goodwill,
* or any type of loss or damage suffered as a result of any action brought by
* a third party) even if such damage or loss was reasonably foreseeable or
* Xilinx had been advised of the possibility of the same.
*
* CRITICAL APPLICATIONS
* Xilinx products are not designed or intended to be fail-safe, or for use in
* any application requiring fail-safe performance, such as life-support or
* safety devices or systems, Class III medical devices, nuclear facilities,
* applications related to the deployment of airbags, or any other applications
* that could lead to death, personal injury, or severe property or
* environmental damage (individually and collectively, "Critical
* Applications"). Customer assumes the sole risk and liability of any use of
* Xilinx products in Critical Applications, subject only to applicable laws
* and regulations governing limitations on product liability.
*
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
* AT ALL TIMES.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xiomodule_io.h
*
* This header file contains identifiers and low-level driver functions (or
* macros) that can be used to access the device. The user should refer to the
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------------
* 1.00a sa 07/15/11 First release
* </pre>
*
******************************************************************************/
#ifndef XIOMODULE_IO_H /* prevent circular inclusions */
#define XIOMODULE_IO_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xil_io.h"
/***************** Macros (Inline Functions) Definitions *********************/
#define XIomodule_In32 Xil_In32
#define XIomodule_Out32 Xil_Out32
#define XIomodule_In16 Xil_In16
#define XIomodule_Out16 Xil_Out16
#define XIomodule_In8 Xil_In8
#define XIomodule_Out8 Xil_Out8
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */

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/* $Id$ */
/******************************************************************************
*
* (c) Copyright 2011 Xilinx, Inc. All rights reserved.
*
* This file contains confidential and proprietary information of Xilinx, Inc.
* and is protected under U.S. and international copyright and other
* intellectual property laws.
*
* DISCLAIMER
* This disclaimer is not a license and does not grant any rights to the
* materials distributed herewith. Except as otherwise provided in a valid
* license issued to you by Xilinx, and to the maximum extent permitted by
* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
* and (2) Xilinx shall not be liable (whether in contract or tort, including
* negligence, or under any other theory of liability) for any loss or damage
* of any kind or nature related to, arising under or in connection with these
* materials, including for any direct, or any indirect, special, incidental,
* or consequential loss or damage (including loss of data, profits, goodwill,
* or any type of loss or damage suffered as a result of any action brought by
* a third party) even if such damage or loss was reasonably foreseeable or
* Xilinx had been advised of the possibility of the same.
*
* CRITICAL APPLICATIONS
* Xilinx products are not designed or intended to be fail-safe, or for use in
* any application requiring fail-safe performance, such as life-support or
* safety devices or systems, Class III medical devices, nuclear facilities,
* applications related to the deployment of airbags, or any other applications
* that could lead to death, personal injury, or severe property or
* environmental damage (individually and collectively, "Critical
* Applications"). Customer assumes the sole risk and liability of any use of
* Xilinx products in Critical Applications, subject only to applicable laws
* and regulations governing limitations on product liability.
*
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
* AT ALL TIMES.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xiomodule_l.c
*
* This file contains low-level driver functions that can be used to access the
* device. The user should refer to the hardware device specification for more
* details of the device operation.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00a sa 07/15/11 First release
* </pre>
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "xparameters.h"
#include "xbasic_types.h"
#include "xiomodule.h"
#include "xiomodule_i.h"
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
static XIOModule_Config *LookupConfigByBaseAddress(u32 BaseAddress);
/************************** Variable Definitions *****************************/
/*****************************************************************************/
/**
*
* This is the interrupt handler for the driver interface provided in this file
* when there can be no argument passed to the handler. In this case, we just
* use the globally defined device ID for the interrupt controller. This function
* is provided mostly for backward compatibility. The user should use
* XIOModule_DeviceInterruptHandler() if possible.
*
* This function does not support multiple interrupt controller instances to be
* handled.
*
* The user must connect this function to the interrupt system such that it is
* called whenever the devices which are connected to it cause an interrupt.
*
* @return None.
*
* @note
*
* The constant XPAR_IOMODULE_SINGLE_DEVICE_ID must be defined for this handler
* to be included in the driver compilation.
*
******************************************************************************/
#ifdef XPAR_IOMODULE_SINGLE_DEVICE_ID
void XIOModule_LowLevelInterruptHandler(void)
{
/*
* A level of indirection here because the interrupt handler used with
* the driver interface given in this file needs to remain void - no
* arguments. So we need the globally defined device ID of THE
* interrupt controller.
*/
XIOModule_DeviceInterruptHandler((void *) XPAR_IOMODULE_SINGLE_DEVICE_ID);
}
#endif
/*****************************************************************************/
/**
*
* This function is the primary interrupt handler for the driver. It must be
* connected to the interrupt source such that is called when an interrupt of
* the interrupt controller is active. It will resolve which interrupts are
* active and enabled and call the appropriate interrupt handler. It uses
* the AckBeforeService flag in the configuration data to determine when to
* acknowledge the interrupt. Highest priority interrupts are serviced first.
* The driver can be configured to service only the highest priority interrupt
* or all pending interrupts using the {XIOModule_SetOptions()} function or
* the {XIOModule_SetIntrSrvOption()} function.
*
* This function assumes that an interrupt vector table has been previously
* initialized. It does not verify that entries in the table are valid before
* calling an interrupt handler, except skipping null handlers that indicate
* use of fast interrupts where the hardware directly jumps to the handler.
*
* @param DeviceId is the zero-based device ID defined in xparameters.h
* of the interrupting interrupt controller. It is used as a direct
* index into the configuration data, which contains the vector
* table for the interrupt controller. Note that even though the
* argument is a void pointer, the value is not a pointer but the
* actual device ID. The void pointer type is necessary to meet
* the XInterruptHandler typedef for interrupt handlers.
*
* @return None.
*
* @note
*
* The constant XPAR_IOMODULE_MAX_INTR_SIZE must be setup for this to compile.
* Interrupt IDs range from 0 - 31 and correspond to the interrupt input signals
* for the interrupt controller. XPAR_IOMODULE_MAX_INTR_SIZE specifies the
* highest numbered interrupt input signal that is used.
*
******************************************************************************/
void XIOModule_DeviceInterruptHandler(void *DeviceId)
{
u32 IntrStatus;
u32 IntrMask = 1;
int IntrNumber;
volatile u32 Register; /* used as bit bucket */
XIOModule_Config *CfgPtr;
XIOModule_VectorTableEntry *TablePtr;
/* Get the configuration data using the device ID */
CfgPtr = &XIOModule_ConfigTable[(u32) DeviceId];
/* Get the interrupts that are waiting to be serviced
*/
IntrStatus = XIOModule_GetIntrStatus(CfgPtr->BaseAddress);
/* Service each interrupt that is active and enabled by checking each
* bit in the register from LSB to MSB which corresponds to an interrupt
* input signal. Skip fast interrupts, indicated by null handler.
*/
for (IntrNumber = 0; IntrNumber < XPAR_IOMODULE_INTC_MAX_INTR_SIZE;
IntrNumber++) {
TablePtr = &(CfgPtr->HandlerTable[IntrNumber]);
if ((IntrStatus & 1) && (TablePtr->Handler != NULL)) {
/* If the interrupt has been setup to acknowledge it
* before servicing the interrupt, then ack it
*/
if (CfgPtr->AckBeforeService & IntrMask) {
XIOModule_AckIntr(CfgPtr->BaseAddress, IntrMask);
}
/* The interrupt is active and enabled, call the
* interrupt handler that was setup with the specified
* parameter
*/
TablePtr->Handler(TablePtr->CallBackRef);
/* If the interrupt has been setup to acknowledge it
* after it has been serviced then ack it
*/
if ((CfgPtr->AckBeforeService & IntrMask) == 0) {
XIOModule_AckIntr(CfgPtr->BaseAddress, IntrMask);
}
/*
* Read the ISR again to handle architectures with
* posted write bus access issues.
*/
Register = XIOModule_GetIntrStatus(CfgPtr->BaseAddress);
/*
* If only the highest priority interrupt is to be
* serviced, exit loop and return after servicing
* the interrupt
*/
if (CfgPtr->Options == XIN_SVC_SGL_ISR_OPTION) {
return;
}
}
/* Move to the next interrupt to check */
IntrMask <<= 1;
IntrStatus >>= 1;
/* If there are no other bits set indicating that all interrupts
* have been serviced, then exit the loop
*/
if (IntrStatus == 0) {
break;
}
}
}
/*****************************************************************************/
/**
*
* Set the interrupt service option, which can configure the driver so that it
* services only a single interrupt at a time when an interrupt occurs, or
* services all pending interrupts when an interrupt occurs. The default
* behavior when using the driver interface given in xintc.h file is to service
* only a single interrupt, whereas the default behavior when using the driver
* interface given in this file is to service all outstanding interrupts when an
* interrupt occurs.
*
* @param BaseAddress is the unique identifier for a device.
* @param Option is XIN_SVC_SGL_ISR_OPTION if you want only a single
* interrupt serviced when an interrupt occurs, or
* XIN_SVC_ALL_ISRS_OPTION if you want all pending interrupts
* serviced when an interrupt occurs.
*
* @return None.
*
* @note
*
* Note that this function has no effect if the input base address is invalid.
*
******************************************************************************/
void XIOModule_SetIntrSvcOption(u32 BaseAddress, int Option)
{
XIOModule_Config *CfgPtr;
CfgPtr = LookupConfigByBaseAddress(BaseAddress);
if (CfgPtr != NULL) {
CfgPtr->Options = Option;
}
}
/*****************************************************************************/
/**
*
* Register a handler function for a specific interrupt ID. The vector table
* of the interrupt controller is updated, overwriting any previous handler.
* The handler function will be called when an interrupt occurs for the given
* interrupt ID.
*
* This function can also be used to remove a handler from the vector table
* by passing in the XIOModule_DefaultHandler() as the handler and NULL as the
* callback reference.
*
* @param BaseAddress is the base address of the interrupt controller
* whose vector table will be modified.
* @param InterruptId is the interrupt ID to be associated with the input
* handler.
* @param Handler is the function pointer that will be added to
* the vector table for the given interrupt ID. It adheres to the
* XInterruptHandler signature found in xbasic_types.h.
* @param CallBackRef is the argument that will be passed to the new
* handler function when it is called. This is user-specific.
*
* @return None.
*
* @note Only used with normal interrupt mode.
* Does not restore normal interrupt mode.
*
* Note that this function has no effect if the input base address is invalid.
*
******************************************************************************/
void XIOModule_RegisterHandler(u32 BaseAddress, int InterruptId,
XInterruptHandler Handler, void *CallBackRef)
{
XIOModule_Config *CfgPtr;
CfgPtr = LookupConfigByBaseAddress(BaseAddress);
if (CfgPtr != NULL) {
CfgPtr->HandlerTable[InterruptId].Handler = Handler;
CfgPtr->HandlerTable[InterruptId].CallBackRef = CallBackRef;
}
}
/*****************************************************************************/
/**
*
* Looks up the device configuration based on the base address of the device.
* A table contains the configuration info for each device in the system.
*
* @param BaseAddress is the unique identifier for a device.
*
* @return
*
* A pointer to the configuration structure for the specified device, or
* NULL if the device was not found.
*
* @note None.
*
******************************************************************************/
static XIOModule_Config *LookupConfigByBaseAddress(u32 BaseAddress)
{
XIOModule_Config *CfgPtr = NULL;
int i;
for (i = 0; i < XPAR_XIOMODULE_NUM_INSTANCES; i++) {
if (XIOModule_ConfigTable[i].BaseAddress == BaseAddress) {
CfgPtr = &XIOModule_ConfigTable[i];
break;
}
}
return CfgPtr;
}
/****************************************************************************/
/**
*
* This functions sends a single byte using the UART. It is blocking in that it
* waits for the transmitter to become non-full before it writes the byte to
* the transmit register.
*
* @param BaseAddress is the base address of the device
* @param Data is the byte of data to send
*
* @return None.
*
* @note None.
*
******************************************************************************/
void XIOModule_SendByte(u32 BaseAddress, u8 Data)
{
while (XIOModule_IsTransmitFull(BaseAddress));
XIomodule_Out32(BaseAddress + XUL_TX_OFFSET, Data);
}
/****************************************************************************/
/**
*
* This functions receives a single byte using the UART. It is blocking in that
* it waits for the receiver to become non-empty before it reads from the
* receive register.
*
* @param BaseAddress is the base address of the device
*
* @return The byte of data received.
*
* @note None.
*
******************************************************************************/
u8 XIOModule_RecvByte(u32 BaseAddress)
{
while (XIOModule_IsReceiveEmpty(BaseAddress));
return (u8)XIomodule_In32(BaseAddress + XUL_RX_OFFSET);
}

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/* $Id$ */
/******************************************************************************
*
* (c) Copyright 2011,2012 Xilinx, Inc. All rights reserved.
*
* This file contains confidential and proprietary information of Xilinx, Inc.
* and is protected under U.S. and international copyright and other
* intellectual property laws.
*
* DISCLAIMER
* This disclaimer is not a license and does not grant any rights to the
* materials distributed herewith. Except as otherwise provided in a valid
* license issued to you by Xilinx, and to the maximum extent permitted by
* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
* and (2) Xilinx shall not be liable (whether in contract or tort, including
* negligence, or under any other theory of liability) for any loss or damage
* of any kind or nature related to, arising under or in connection with these
* materials, including for any direct, or any indirect, special, incidental,
* or consequential loss or damage (including loss of data, profits, goodwill,
* or any type of loss or damage suffered as a result of any action brought by
* a third party) even if such damage or loss was reasonably foreseeable or
* Xilinx had been advised of the possibility of the same.
*
* CRITICAL APPLICATIONS
* Xilinx products are not designed or intended to be fail-safe, or for use in
* any application requiring fail-safe performance, such as life-support or
* safety devices or systems, Class III medical devices, nuclear facilities,
* applications related to the deployment of airbags, or any other applications
* that could lead to death, personal injury, or severe property or
* environmental damage (individually and collectively, "Critical
* Applications"). Customer assumes the sole risk and liability of any use of
* Xilinx products in Critical Applications, subject only to applicable laws
* and regulations governing limitations on product liability.
*
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
* AT ALL TIMES.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xiomodule_l.h
*
* This header file contains identifiers and low-level driver functions (or
* macros) that can be used to access the device. The user should refer to the
* hardware device specification for more details of the device operation.
*
*
* Note that users of the driver interface given in this file can register
* an interrupt handler dynamically (at run-time) using the
* XIntc_RegisterHandler() function.
* User of the driver interface given in xiomodule.h should still use
* XIntc_Connect(), as always.
* Also see the discussion of the interrupt vector tables in xiomodule.h.
*
* There are currently two interrupt handlers specified in this interface.
*
* - XIOModule_LowLevelInterruptHandler() is a handler without any arguments
* that is used in cases where there is a single interrupt controller device
* in the system and the handler cannot be passed an argument. This function
* is provided mostly for backward compatibility.
*
* - XIOModule_DeviceInterruptHandler() is a handler that takes a device ID
* as an argument, indicating which interrupt controller device in the system
* is causing the interrupt - thereby supporting multiple interrupt
* controllers.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------------
* 1.00a sa 07/15/11 First release
* 1.01a sa 04/10/12 Updated with fast interrupt
* 1.02a sa 07/25/12 Updated with GPI interrupt support
* </pre>
*
******************************************************************************/
#ifndef XIOMODULE_L_H /* prevent circular inclusions */
#define XIOMODULE_L_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xbasic_types.h"
#include "xparameters.h"
#include "xiomodule_io.h"
#include "xio.h"
/************************** Constant Definitions *****************************/
/**
* Defines the number of timer counters within a single hardware device. This
* number is not currently parameterized in the hardware but may be in the
* future.
*/
#define XTC_DEVICE_TIMER_COUNT 4
/**
* Each timer counter consumes 16 bytes of address space.
*/
#define XTC_TIMER_COUNTER_OFFSET 16
#define XTC_TIMER_COUNTER_SHIFT 4
/**
* Define the offsets from the base address for all the registers of the
* IO module, some registers may be optional in the hardware device.
*/
#define XUL_RX_OFFSET 0x00000000 /**< UART Receive Register - R */
#define XUL_TX_OFFSET 0x00000004 /**< UART Transmit Register - W */
#define XUL_STATUS_REG_OFFSET 0x00000008 /**< UART Status Register - R */
#define XUL_BAUDRATE_OFFSET 0x0000004C /**< UART Baud Rate Register - W */
#define XIN_IMR_OFFSET 0x0000000C /**< Intr Mode Register - W */
#define XGO_OUT_OFFSET 0x00000010 /**< General Purpose Output - W */
#define XGI_IN_OFFSET 0x00000020 /**< General Purpose Input - R */
#define XIN_ISR_OFFSET 0x00000030 /**< Intr Status Register - R */
#define XIN_IPR_OFFSET 0x00000034 /**< Intr Pending Register - R */
#define XIN_IER_OFFSET 0x00000038 /**< Intr Enable Register - W */
#define XIN_IAR_OFFSET 0x0000003C /**< Intr Acknowledge Register - W */
#define XTC_TLR_OFFSET 0x00000040 /**< Timer Load register - W */
#define XTC_TCR_OFFSET 0x00000044 /**< Timer counter register - R */
#define XTC_TCSR_OFFSET 0x00000048 /**< Timer Control register - W */
#define XIN_IVAR_OFFSET 0x00000080 /**< Intr Vector Address Register,
Interrupt 0 offset, present
only for Fast Interrupt - W */
/**
* UART status register bit position masks
*/
#define XUL_SR_PARITY_ERROR 0x80
#define XUL_SR_FRAMING_ERROR 0x40
#define XUL_SR_OVERRUN_ERROR 0x20
#define XUL_SR_INTR_ENABLED 0x10 /**< UART Interrupt enabled */
#define XUL_SR_TX_FIFO_FULL 0x08 /**< UART Transmit FIFO full */
#define XUL_SR_RX_FIFO_VALID_DATA 0x01 /**< UART Data Register valid */
/**
* UART stop bits are fixed at 1. Baud, parity, and data bits are fixed on a
* per instance basis.
*/
#define XUL_STOP_BITS 1
/**
* UART Parity definitions.
*/
#define XUL_PARITY_NONE 0
#define XUL_PARITY_ODD 1
#define XUL_PARITY_EVEN 2
/**
* Defines the number of GPI and GPO within a single hardware device. This
* number is not currently parameterized in the hardware but may be in the
* future.
* @{
*/
#define XGPI_DEVICE_COUNT 4
#define XGPO_DEVICE_COUNT 4
/**
* The following constants describe the offset of each GPI and GPO channel's
* data from the base address.
*/
#define XGPI_CHAN_OFFSET 0x00004
#define XGPI_DATA_OFFSET 0x00020
#define XGPO_CHAN_OFFSET 0x00004
#define XGPO_DATA_OFFSET 0x00010
/**
* Interrupt register bit position masks.
*/
#define XIN_IOMODULE_GPI_4_INTERRUPT_INTR 14
#define XIN_IOMODULE_GPI_3_INTERRUPT_INTR 13
#define XIN_IOMODULE_GPI_2_INTERRUPT_INTR 12
#define XIN_IOMODULE_GPI_1_INTERRUPT_INTR 11
#define XIN_IOMODULE_FIT_4_INTERRUPT_INTR 10
#define XIN_IOMODULE_FIT_3_INTERRUPT_INTR 9
#define XIN_IOMODULE_FIT_2_INTERRUPT_INTR 8
#define XIN_IOMODULE_FIT_1_INTERRUPT_INTR 7
#define XIN_IOMODULE_PIT_4_INTERRUPT_INTR 6
#define XIN_IOMODULE_PIT_3_INTERRUPT_INTR 5
#define XIN_IOMODULE_PIT_2_INTERRUPT_INTR 4
#define XIN_IOMODULE_PIT_1_INTERRUPT_INTR 3
#define XIN_IOMODULE_UART_RX_INTERRUPT_INTR 2
#define XIN_IOMODULE_UART_TX_INTERRUPT_INTR 1
#define XIN_IOMODULE_UART_ERROR_INTERRUPT_INTR 0
#define XIN_IOMODULE_EXTERNAL_INTERRUPT_INTR 16
/* @} */
/**
* @name Control Status Register Bit Definitions
* Control Status Register bit masks
* Used to configure the timer counter device.
* @{
*/
#define XTC_CSR_ENABLE_TMR_MASK 0x00000001 /**< Enables the timer */
#define XTC_CSR_AUTO_RELOAD_MASK 0x00000002 /**< In compare mode,
configures the timer
reload from the Load
Register. The default
mode causes the timer
counter to hold when it
rolls under. */
/* @} */
/**************************** Type Definitions *******************************/
/* The following data type defines each entry in an interrupt vector table.
* The callback reference is the base address of the interrupting device
* for the driver interface given in this file and an instance pointer for the
* driver interface given in xintc.h file.
*/
typedef struct {
XInterruptHandler Handler;
void *CallBackRef;
} XIOModule_VectorTableEntry;
typedef void (*XFastInterruptHandler) (void);
/***************** Macros (Inline Functions) Definitions *********************/
/****************************************************************************/
/**
*
* Enable specific interrupt(s) in the interrupt controller.
*
* @param BaseAddress is the base address of the device
* @param EnableMask is the 32-bit value to write to the enable register.
* Each bit of the mask corresponds to an interrupt input signal
* that is connected to the interrupt controller (INT0 = LSB).
* Only the bits which are set in the mask will enable interrupts.
*
* @return None.
*
* @note C-style signature:
* void XIOModule_EnableIntr(u32 BaseAddress, u32 EnableMask);
*
*****************************************************************************/
#define XIOModule_EnableIntr(BaseAddress, EnableMask) \
XIomodule_Out32((BaseAddress) + XIN_IER_OFFSET, (EnableMask))
/****************************************************************************/
/**
*
* Disable specific interrupt(s) in the interrupt controller.
*
* @param BaseAddress is the base address of the device
* @param DisableMask is the 32-bit value to write to enable register.
* Each bit of the mask corresponds to an interrupt input signal
* that is connected to the interrupt controller (INT0 = LSB).
* Only bits which are set in the mask will disable interrupts.
*
* @return None.
*
* @note C-style signature:
* void XIOModule_DisableIntr(u32 BaseAddress, u32 DisableMask);
*
*****************************************************************************/
#define XIOModule_DisableIntr(BaseAddress, DisableMask) \
XIomodule_Out32((BaseAddress) + XIN_IER_OFFSET, ~(DisableMask))
/****************************************************************************/
/**
*
* Acknowledge specific interrupt(s) in the interrupt controller.
*
* @param BaseAddress is the base address of the device
* @param AckMask is the 32-bit value to write to the acknowledge
* register. Each bit of the mask corresponds to an interrupt
* input signal that is connected to the interrupt controller
* (INT0 = LSB). Only the bits which are set in the mask will
* acknowledge interrupts.
*
* @return None.
*
* @note C-style signature:
* void XIOModule_AckIntr(u32 BaseAddress, u32 AckMask);
*
*****************************************************************************/
#define XIOModule_AckIntr(BaseAddress, AckMask) \
XIomodule_Out32((BaseAddress) + XIN_IAR_OFFSET, (AckMask))
/****************************************************************************/
/**
*
* Get the interrupt status from the interrupt controller which indicates
* which interrupts are active and enabled.
*
* @param BaseAddress is the base address of the device
*
* @return The 32-bit contents of the interrupt status register. Each bit
* corresponds to an interrupt input signal that is connected to
* the interrupt controller (INT0 = LSB). Bits which are set
* indicate an active interrupt which is also enabled.
*
* @note C-style signature:
* u32 XIOModule_GetIntrStatus(u32 BaseAddress);
*
*****************************************************************************/
#define XIOModule_GetIntrStatus(BaseAddress) \
(XIomodule_In32((BaseAddress) + XIN_IPR_OFFSET))
/****************************************************************************/
/**
*
* Get the contents of the UART status register. Use the XUL_SR_* constants
* defined above to interpret the bit-mask returned.
*
* @param BaseAddress is the base address of the device
*
* @return A 32-bit value representing the contents of the status
* register.
*
* @note C-style Signature:
* u32 XIOModule_GetStatusReg(u32 BaseAddress);
*
*****************************************************************************/
#define XIOModule_GetStatusReg(BaseAddress) \
XIomodule_In32((BaseAddress) + XUL_STATUS_REG_OFFSET)
/****************************************************************************/
/**
*
* Check to see if the UART receiver has data.
*
* @param BaseAddress is the base address of the device
*
* @return TRUE if the receiver is empty, FALSE if there is data present.
*
* @note C-style Signature:
* int XIOModule_IsReceiveEmpty(u32 BaseAddress);
*
*****************************************************************************/
#define XIOModule_IsReceiveEmpty(BaseAddress) \
((XIOModule_GetStatusReg((BaseAddress)) & XUL_SR_RX_FIFO_VALID_DATA) != \
XUL_SR_RX_FIFO_VALID_DATA)
/****************************************************************************/
/**
*
* Check to see if the transmitter is full.
*
* @param BaseAddress is the base address of the device
*
* @return TRUE if the transmitter is full, FALSE otherwise.
*
* @note C-style Signature:
* int XIOModule_IsTransmitFull(u32 BaseAddress);
*
*****************************************************************************/
#define XIOModule_IsTransmitFull(BaseAddress) \
((XIOModule_GetStatusReg((BaseAddress)) & XUL_SR_TX_FIFO_FULL) == \
XUL_SR_TX_FIFO_FULL)
/****************************************************************************/
/**
*
* Write a value to a GPO register. A 32 bit write is performed. If the
* GPO component is implemented in a smaller width, only the least
* significant data is written.
*
* @param BaseAddress is the base address of the GPO device.
* @param RegOffset is the register offset from the base to write to.
* @param Data is the data written to the register.
*
* @return None.
*
* @note C-style signature:
* void XIOModule_WriteReg(u32 BaseAddress,
* unsigned RegOffset, u32 Data)
*
****************************************************************************/
#define XIOModule_WriteReg(BaseAddress, RegOffset, Data) \
XIomodule_Out32((BaseAddress) + (RegOffset), (u32)(Data))
/****************************************************************************/
/**
*
* Read a value from a GPI register. A 32 bit read is performed. If the
* GPI component is implemented in a smaller width, only the least
* significant data is read from the register. The most significant data
* will be read as 0.
*
* @param BaseAddress is the base address of the GPI device.
* @param RegOffset is the register offset from the base to read from.
*
* @return Data read from the register.
*
* @note C-style signature:
* u32 XIOModule_ReadReg(u32 BaseAddress, unsigned RegOffset)
*
******************************************************************************/
#define XIOModule_ReadReg(BaseAddress, RegOffset) \
XIomodule_In32((BaseAddress) + (RegOffset))
/************************** Function Prototypes ******************************/
/*
* UART standard in and standard out handlers, to be connected to generic
* I/O handling code.
*/
void XIOModule_SendByte(u32 BaseAddress, u8 Data);
u8 XIOModule_RecvByte(u32 BaseAddress);
/*
* Interrupt controller handlers, to be connected to processor exception
* handling code.
*/
void XIOModule_LowLevelInterruptHandler(void);
void XIOModule_DeviceInterruptHandler(void *DeviceId);
/* Various configuration functions */
void XIOModule_SetIntrSvcOption(u32 BaseAddress, int Option);
void XIOModule_RegisterHandler(u32 BaseAddress,
int InterruptId,
XInterruptHandler Handler,
void *CallBackRef);
/************************** Variable Definitions *****************************/
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */

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/* $Id$ */
/******************************************************************************
*
* (c) Copyright 2011 Xilinx, Inc. All rights reserved.
*
* This file contains confidential and proprietary information of Xilinx, Inc.
* and is protected under U.S. and international copyright and other
* intellectual property laws.
*
* DISCLAIMER
* This disclaimer is not a license and does not grant any rights to the
* materials distributed herewith. Except as otherwise provided in a valid
* license issued to you by Xilinx, and to the maximum extent permitted by
* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
* and (2) Xilinx shall not be liable (whether in contract or tort, including
* negligence, or under any other theory of liability) for any loss or damage
* of any kind or nature related to, arising under or in connection with these
* materials, including for any direct, or any indirect, special, incidental,
* or consequential loss or damage (including loss of data, profits, goodwill,
* or any type of loss or damage suffered as a result of any action brought by
* a third party) even if such damage or loss was reasonably foreseeable or
* Xilinx had been advised of the possibility of the same.
*
* CRITICAL APPLICATIONS
* Xilinx products are not designed or intended to be fail-safe, or for use in
* any application requiring fail-safe performance, such as life-support or
* safety devices or systems, Class III medical devices, nuclear facilities,
* applications related to the deployment of airbags, or any other applications
* that could lead to death, personal injury, or severe property or
* environmental damage (individually and collectively, "Critical
* Applications"). Customer assumes the sole risk and liability of any use of
* Xilinx products in Critical Applications, subject only to applicable laws
* and regulations governing limitations on product liability.
*
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
* AT ALL TIMES.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xiomodule_options.c
*
* Contains option functions for the XIOModule driver. These functions allow the
* user to configure an instance of the XIOModule driver. This file requires
* other files of the component to be linked in also.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------------
* 1.00a sa 07/15/11 First release
* </pre>
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "xbasic_types.h"
#include "xiomodule.h"
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/*
* The following data type maps an option to a register mask such that getting
* and setting the options may be table driven.
*/
typedef struct {
u32 Option;
u32 Mask;
} Mapping;
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
/************************** Variable Definitions *****************************/
/*
* Create the table which contains options which are to be processed to get/set
* the options. These options are table driven to allow easy maintenance and
* expansion of the options.
*/
static Mapping OptionsTable[] = {
{XTC_INT_MODE_OPTION, 0},
{XTC_AUTO_RELOAD_OPTION, XTC_CSR_AUTO_RELOAD_MASK}
};
/* Create a constant for the number of entries in the table */
#define XTC_NUM_OPTIONS (sizeof(OptionsTable) / sizeof(Mapping))
/*****************************************************************************/
/**
*
* Set the options for the interrupt controller driver.
*
* @param InstancePtr is a pointer to the XIOModule instance to be
* worked on.
* @param Options to be set. The available options are described in
* xiomodule.h.
*
* @return
* - XST_SUCCESS if the options were set successfully
* - XST_INVALID_PARAM if the specified option was not valid
*
* @note None.
*
****************************************************************************/
int XIOModule_SetOptions(XIOModule * InstancePtr, u32 Options)
{
XASSERT_NONVOID(InstancePtr != NULL);
XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
/*
* Make sure option request is valid
*/
if ((Options == XIN_SVC_SGL_ISR_OPTION) ||
(Options == XIN_SVC_ALL_ISRS_OPTION)) {
InstancePtr->CfgPtr->Options = Options;
return XST_SUCCESS;
}
else {
return XST_INVALID_PARAM;
}
}
/*****************************************************************************/
/**
*
* Return the currently set options.
*
* @param InstancePtr is a pointer to the XIOModule instance to be
* worked on.
*
* @return The currently set options. The options are described in
* xiomodule.h.
*
* @note None.
*
****************************************************************************/
u32 XIOModule_GetOptions(XIOModule * InstancePtr)
{
/*
* Assert the arguments
*/
XASSERT_NONVOID(InstancePtr != NULL);
XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
return InstancePtr->CfgPtr->Options;
}
/*****************************************************************************/
/**
*
* Enables the specified options for the specified timer . This function
* sets the options without regard to the current options of the driver. To
* prevent a loss of the current options, the user should call
* XIOModule_Timer_GetOptions() prior to this function and modify the retrieved
* options to pass into this function to prevent loss of the current options.
*
* @param InstancePtr is a pointer to the XIOModule instance.
* @param TimerNumber is the timer of the device to operate on.
* Each device may contain multiple timers. The timer
* number is a zero based number with a range of
* 0 to (XTC_DEVICE_TIMER_COUNT - 1).
* @param Options contains the desired options to be set or cleared.
* Setting the option to '1' enables the option, clearing the to
* '0' disables the option. The options are bit masks such that
* multiple options may be set or cleared. The options are
* described in xiomodule.h.
*
* @return None.
*
* @note None.
*
******************************************************************************/
void XIOModule_Timer_SetOptions(XIOModule * InstancePtr, u8 TimerNumber,
u32 Options)
{
u32 CounterControlReg = 0;
u32 TimerOffset = TimerNumber << XTC_TIMER_COUNTER_SHIFT;
u32 Index;
XASSERT_VOID(InstancePtr != NULL);
XASSERT_VOID(TimerNumber <= XTC_DEVICE_TIMER_COUNT);
XASSERT_VOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
/*
* Loop through the Options table, turning the enable on or off
* depending on whether the bit is set in the incoming Options flag.
*/
for (Index = 0; Index < XTC_NUM_OPTIONS; Index++) {
if (Options & OptionsTable[Index].Option) {
/*
* Turn the option on
*/
CounterControlReg |= OptionsTable[Index].Mask;
}
else {
/*
* Turn the option off
*/
CounterControlReg &= ~OptionsTable[Index].Mask;
}
}
/*
* Write out the updated value to the actual register
*/
XIOModule_WriteReg(InstancePtr->BaseAddress,
TimerOffset + XTC_TCSR_OFFSET,
CounterControlReg);
InstancePtr->CurrentTCSR[TimerNumber] = CounterControlReg;
}
/*****************************************************************************/
/**
*
* Get the options for the specified timer.
*
* @param InstancePtr is a pointer to the XIOModule instance.
* @param TimerNumber is the timer of the device to operate on
* Each device may contain multiple timer. The timer
* number is a zero based number with a range of
* 0 to (XTC_DEVICE_TIMER_COUNT - 1).
*
* @return
*
* The currently set options. An option which is set to a '1' is enabled and
* set to a '0' is disabled. The options are bit masks such that multiple
* options may be set or cleared. The options are described in xiomodule.h.
*
* @note None.
*
******************************************************************************/
u32 XIOModel_Timer_GetOptions(XIOModule * InstancePtr, u8 TimerNumber)
{
u32 TimerOffset = TimerNumber << XTC_TIMER_COUNTER_SHIFT;
u32 Options = 0;
u32 CounterControlReg;
u32 Index;
XASSERT_NONVOID(InstancePtr != NULL);
XASSERT_NONVOID(TimerNumber < XTC_DEVICE_TIMER_COUNT);
XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
/*
* Get the current contents of the control status register to allow
* the current options to be determined
*/
CounterControlReg = InstancePtr->CurrentTCSR[TimerNumber];
/*
* Loop through the Options table, turning the enable on or off
* depending on whether the bit is set in current register settings.
*/
for (Index = 0; Index < XTC_NUM_OPTIONS; Index++) {
if (CounterControlReg & OptionsTable[Index].Mask) {
Options |= OptionsTable[Index].Option; /* turn on */
}
else {
Options &= ~OptionsTable[Index].Option; /* turn off */
}
}
return Options;
}

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/* $Id$ */
/******************************************************************************
*
* (c) Copyright 2011 Xilinx, Inc. All rights reserved.
*
* This file contains confidential and proprietary information of Xilinx, Inc.
* and is protected under U.S. and international copyright and other
* intellectual property laws.
*
* DISCLAIMER
* This disclaimer is not a license and does not grant any rights to the
* materials distributed herewith. Except as otherwise provided in a valid
* license issued to you by Xilinx, and to the maximum extent permitted by
* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
* and (2) Xilinx shall not be liable (whether in contract or tort, including
* negligence, or under any other theory of liability) for any loss or damage
* of any kind or nature related to, arising under or in connection with these
* materials, including for any direct, or any indirect, special, incidental,
* or consequential loss or damage (including loss of data, profits, goodwill,
* or any type of loss or damage suffered as a result of any action brought by
* a third party) even if such damage or loss was reasonably foreseeable or
* Xilinx had been advised of the possibility of the same.
*
* CRITICAL APPLICATIONS
* Xilinx products are not designed or intended to be fail-safe, or for use in
* any application requiring fail-safe performance, such as life-support or
* safety devices or systems, Class III medical devices, nuclear facilities,
* applications related to the deployment of airbags, or any other applications
* that could lead to death, personal injury, or severe property or
* environmental damage (individually and collectively, "Critical
* Applications"). Customer assumes the sole risk and liability of any use of
* Xilinx products in Critical Applications, subject only to applicable laws
* and regulations governing limitations on product liability.
*
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
* AT ALL TIMES.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xiomodule_selftest.c
*
* Contains diagnostic self-test functions for the XIOModule component. This
* file requires other files of the component to be linked in also.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.00a sa 07/15/11 First release
* </pre>
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "xbasic_types.h"
#include "xiomodule.h"
#include "xiomodule_i.h"
#include "xiomodule_io.h"
#include <stdio.h>
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
/************************** Variable Definitions *****************************/
/*****************************************************************************/
/**
*
* Run a self-test on the interrupt controller driver/device. This is a
* destructive test.
*
* This involves forcing interrupts into the controller (if possible, given
* the IO Module configuration) and verifying that they are recognized and can
* be acknowledged.
*
* @param InstancePtr is a pointer to the XIOModule instance to be
* worked on.
*
* @return
* - XST_SUCCESS if self-test is successful.
* - XST_INTC_FAIL_SELFTEST if the Interrupt controller
* fails the self-test. It will fail the self test if the
* device has previously been started in real mode.
*
* @note None.
*
******************************************************************************/
int XIOModule_Intc_SelfTest(XIOModule * InstancePtr)
{
u32 CurrentISR;
u32 Temp;
/*
* Assert the arguments
*/
XASSERT_NONVOID(InstancePtr != NULL);
XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
/*
* Acknowledge all pending interrupts by reading the interrupt status
* register and writing the value to the acknowledge register
*/
Temp = XIomodule_In32(InstancePtr->BaseAddress + XIN_ISR_OFFSET);
XIomodule_Out32(InstancePtr->BaseAddress + XIN_IAR_OFFSET, Temp);
/*
* Verify that there are no interrupts by reading the interrupt status
*/
CurrentISR = XIomodule_In32(InstancePtr->BaseAddress + XIN_ISR_OFFSET);
/*
* ISR for internal interrupts should be zero after all interrupts
* are acknowledged. Skip checking external interrupts, since they may
* occur at any time.
*/
if ((CurrentISR & 0xffff) != 0) {
return XST_INTC_FAIL_SELFTEST;
}
return XST_SUCCESS;
}
/*****************************************************************************/
/**
*
* Runs a self-test on the timer driver/device. This test verifies that the
* specified programmable interval timer of the device can be enabled and
* increments.
*
* @param InstancePtr is a pointer to the XIOMOdule instance.
* @param TimerNumber is the timer of the device to operate on.
* Each device may contain multiple timers. The timer
* number is a zero based number with a range of
* 0 to (XTC_DEVICE_TIMER_COUNT - 1).
*
* @return
* - XST_SUCCESS if self-test was successful
* - XST_FAILURE if the timer is not incrementing.
*
* @note
*
* This is a destructive test using the provided timer. The current settings
* of the timer are returned to the initialized values and all settings at the
* time this function is called are overwritten.
*
******************************************************************************/
int XIOModule_Timer_SelfTest(XIOModule * InstancePtr, u8 TimerNumber)
{
u32 TimerCount1 = 0;
u32 TimerCount2 = 0;
u16 Count = 0;
/*
* Assert the arguments
*/
XASSERT_NONVOID(InstancePtr != NULL);
XASSERT_NONVOID(TimerNumber < XTC_DEVICE_TIMER_COUNT);
XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
/*
* Set the Load register most significant bit to 1.
*/
XIOModule_SetResetValue(InstancePtr, TimerNumber,
1 << (InstancePtr->CfgPtr->PitSize[TimerNumber] - 1));
/*
* Reset the timer and the interrupt
*/
XIOModule_Timer_SetOptions(InstancePtr, TimerNumber, 0);
/*
* Set the control/status register to enable timer
*/
XIOModule_Timer_Start(InstancePtr, TimerNumber);
/*
* Read the timer
*/
TimerCount1 = XIOModule_GetValue(InstancePtr, TimerNumber);
/*
* Make sure timer is decrementing if the Count rolls under zero
* and the timer still has not decremented an error is returned
*/
do {
TimerCount2 = XIOModule_GetValue(InstancePtr, TimerNumber);
Count++;
}
while ((TimerCount1 == TimerCount2) && (Count != 0));
/*
* Set the control/status register to 0 to complete initialization
* this disables the timer completely and allows it to be used again
*/
XIOModule_Timer_Stop(InstancePtr, TimerNumber);
if (TimerCount1 == TimerCount2) {
return XST_FAILURE;
}
else {
return XST_SUCCESS;
}
}
int XIOModule_SelfTest(XIOModule * InstancePtr)
{
XStatus Status;
u8 Timer;
XIOModule_Config *CfgPtr;
/*
* Assert the arguments
*/
XASSERT_NONVOID(InstancePtr != NULL);
XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
/*
* Perform the interrupt controller self test.
*/
Status = XIOModule_Intc_SelfTest(InstancePtr);
if (Status != XST_SUCCESS)
{
return XST_FAILURE;
}
/*
* Perform the Programmable Interval Timer (PIT) self test.
*
* Skip unused timers,timers with prescaler (since they may
* have very long expiration times), timers without readable
* counters, and timers with small size (since the counter
* may not change when sampled).
*/
CfgPtr = InstancePtr->CfgPtr;
for (Timer = 0; Timer < XTC_DEVICE_TIMER_COUNT; Timer++) {
if (CfgPtr->PitUsed[Timer] &&
CfgPtr->PitPrescaler[Timer] == XTC_PRESCALER_NONE &&
CfgPtr->PitReadable[Timer] &&
CfgPtr->PitSize[Timer] > 8) {
Status = XIOModule_Timer_SelfTest(InstancePtr, Timer);
if (Status != XST_SUCCESS)
{
return XST_FAILURE;
}
}
}
return XST_SUCCESS;
}

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/* $Id$ */
/******************************************************************************
*
* (c) Copyright 2011 Xilinx, Inc. All rights reserved.
*
* This file contains confidential and proprietary information of Xilinx, Inc.
* and is protected under U.S. and international copyright and other
* intellectual property laws.
*
* DISCLAIMER
* This disclaimer is not a license and does not grant any rights to the
* materials distributed herewith. Except as otherwise provided in a valid
* license issued to you by Xilinx, and to the maximum extent permitted by
* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
* and (2) Xilinx shall not be liable (whether in contract or tort, including
* negligence, or under any other theory of liability) for any loss or damage
* of any kind or nature related to, arising under or in connection with these
* materials, including for any direct, or any indirect, special, incidental,
* or consequential loss or damage (including loss of data, profits, goodwill,
* or any type of loss or damage suffered as a result of any action brought by
* a third party) even if such damage or loss was reasonably foreseeable or
* Xilinx had been advised of the possibility of the same.
*
* CRITICAL APPLICATIONS
* Xilinx products are not designed or intended to be fail-safe, or for use in
* any application requiring fail-safe performance, such as life-support or
* safety devices or systems, Class III medical devices, nuclear facilities,
* applications related to the deployment of airbags, or any other applications
* that could lead to death, personal injury, or severe property or
* environmental damage (individually and collectively, "Critical
* Applications"). Customer assumes the sole risk and liability of any use of
* Xilinx products in Critical Applications, subject only to applicable laws
* and regulations governing limitations on product liability.
*
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
* AT ALL TIMES.
*
******************************************************************************/
/****************************************************************************/
/**
*
* @file xiomodule_stats.c
*
* This file contains the statistics functions for the UART module
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.00a sa 07/15/11 First release
* </pre>
*
*****************************************************************************/
/***************************** Include Files ********************************/
#include "xil_types.h"
#include "xil_assert.h"
#include "xiomodule.h"
#include "xiomodule_i.h"
/************************** Constant Definitions ****************************/
/**************************** Type Definitions ******************************/
/***************** Macros (Inline Functions) Definitions ********************/
/************************** Variable Definitions ****************************/
/************************** Function Prototypes *****************************/
/****************************************************************************/
/**
*
* Returns a snapshot of the current statistics in the structure specified.
*
* @param InstancePtr is a pointer to the XIOModule instance.
* @param StatsPtr is a pointer to a XIOModule_Uart_Stats structure to
* where the statistics are to be copied.
*
* @return None.
*
* @note None.
*
*****************************************************************************/
void XIOModule_GetStats(XIOModule *InstancePtr, XIOModule_Uart_Stats *StatsPtr)
{
/*
* Assert validates the input arguments
*/
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(StatsPtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
/* Copy the stats from the instance to the specified stats */
StatsPtr->TransmitInterrupts =
InstancePtr->Uart_Stats.TransmitInterrupts;
StatsPtr->ReceiveInterrupts =
InstancePtr->Uart_Stats.ReceiveInterrupts;
StatsPtr->CharactersTransmitted =
InstancePtr->Uart_Stats.CharactersTransmitted;
StatsPtr->CharactersReceived =
InstancePtr->Uart_Stats.CharactersReceived;
StatsPtr->ReceiveOverrunErrors =
InstancePtr->Uart_Stats.ReceiveOverrunErrors;
StatsPtr->ReceiveFramingErrors =
InstancePtr->Uart_Stats.ReceiveFramingErrors;
StatsPtr->ReceiveParityErrors =
InstancePtr->Uart_Stats.ReceiveParityErrors;
}
/****************************************************************************/
/**
*
* This function zeros the statistics for the given instance.
*
* @param InstancePtr is a pointer to the XIOModule instance.
*
* @return None.
*
* @note None.
*
*****************************************************************************/
void XIOModule_ClearStats(XIOModule *InstancePtr)
{
/*
* Assert validates the input arguments
*/
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
InstancePtr->Uart_Stats.TransmitInterrupts = 0;
InstancePtr->Uart_Stats.ReceiveInterrupts = 0;
InstancePtr->Uart_Stats.CharactersTransmitted = 0;
InstancePtr->Uart_Stats.CharactersReceived = 0;
InstancePtr->Uart_Stats.ReceiveOverrunErrors = 0;
InstancePtr->Uart_Stats.ReceiveParityErrors = 0;
InstancePtr->Uart_Stats.ReceiveFramingErrors = 0;
}

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/* $Id$ */
/******************************************************************************
*
* (c) Copyright 2012 Xilinx, Inc. All rights reserved.
*
* This file contains confidential and proprietary information of Xilinx, Inc.
* and is protected under U.S. and international copyright and other
* intellectual property laws.
*
* DISCLAIMER
* This disclaimer is not a license and does not grant any rights to the
* materials distributed herewith. Except as otherwise provided in a valid
* license issued to you by Xilinx, and to the maximum extent permitted by
* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
* and (2) Xilinx shall not be liable (whether in contract or tort, including
* negligence, or under any other theory of liability) for any loss or damage
* of any kind or nature related to, arising under or in connection with these
* materials, including for any direct, or any indirect, special, incidental,
* or consequential loss or damage (including loss of data, profits, goodwill,
* or any type of loss or damage suffered as a result of any action brought by
* a third party) even if such damage or loss was reasonably foreseeable or
* Xilinx had been advised of the possibility of the same.
*
* CRITICAL APPLICATIONS
* Xilinx products are not designed or intended to be fail-safe, or for use in
* any application requiring fail-safe performance, such as life-support or
* safety devices or systems, Class III medical devices, nuclear facilities,
* applications related to the deployment of airbags, or any other applications
* that could lead to death, personal injury, or severe property or
* environmental damage (individually and collectively, "Critical
* Applications"). Customer assumes the sole risk and liability of any use of
* Xilinx products in Critical Applications, subject only to applicable laws
* and regulations governing limitations on product liability.
*
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
* AT ALL TIMES.
*
******************************************************************************/
/****************************************************************************/
/**
*
* @file xiomodule_uart.c
*
* Contains required functions for the XIOModule UART driver. See the
* xiomodule.h header file for more details on this driver.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.02a sa 07/25/12 First release
* 1.03a sa 10/16/12 Moved interrupt mode functions to separate file
* </pre>
*
*****************************************************************************/
/***************************** Include Files ********************************/
#include "xil_assert.h"
#include "xiomodule.h"
#include "xiomodule_i.h"
#include "xiomodule_l.h"
/************************** Constant Definitions ****************************/
/* The following constant defines the amount of error that is allowed for
* a specified baud rate. This error is the difference between the actual
* baud rate that will be generated using the specified clock and the
* desired baud rate.
*/
#define XUN_MAX_BAUD_ERROR_RATE 3 /* max % error allowed */
/**************************** Type Definitions ******************************/
/***************** Macros (Inline Functions) Definitions ********************/
/************************** Function Prototypes *****************************/
static void StubHandler(void *CallBackRef, unsigned int ByteCount);
/************************** Variable Definitions ****************************/
/****************************************************************************/
/**
*
* Initialize a XIOModule instance. This function disables the UART
* interrupts. The baud rate and format of the data are fixed in the hardware
* at hardware build time, except if programmable baud rate is selected.
*
* @param InstancePtr is a pointer to the XIOModule instance.
* @param Config is a reference to a structure containing information
* about a specific IO Module device. This function initializes an
* InstancePtr object for a specific device specified by the
* contents of Config. This function can initialize multiple
* instance objects with the use of multiple calls giving different
* Config information on each call.
* @param EffectiveAddr is the device register base address. Use
* Config->BaseAddress for this parameters, passing the physical
* address.
*
* @return
* - XST_SUCCESS if everything starts up as expected.
*
* @note The Config and EffectiveAddress arguments are not used by this
* function, but are provided to keep the function signature
* consistent with other drivers.
*
*****************************************************************************/
int XIOModule_CfgInitialize(XIOModule *InstancePtr, XIOModule_Config *Config,
u32 EffectiveAddr)
{
u32 NewIER;
/*
* Assert validates the input arguments
*/
Xil_AssertNonvoid(InstancePtr != NULL);
/*
* Set some default values, including setting the callback
* handlers to stubs.
*/
InstancePtr->SendBuffer.NextBytePtr = NULL;
InstancePtr->SendBuffer.RemainingBytes = 0;
InstancePtr->SendBuffer.RequestedBytes = 0;
InstancePtr->ReceiveBuffer.NextBytePtr = NULL;
InstancePtr->ReceiveBuffer.RemainingBytes = 0;
InstancePtr->ReceiveBuffer.RequestedBytes = 0;
InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
InstancePtr->RecvHandler = StubHandler;
InstancePtr->SendHandler = StubHandler;
/*
* Modify the IER to disable the UART interrupts
*/
NewIER = InstancePtr->CurrentIER & 0xFFFFFFF8;
XIomodule_Out32(InstancePtr->BaseAddress + XIN_IER_OFFSET, NewIER);
InstancePtr->CurrentIER = NewIER;
/*
* Clear the statistics for this driver
*/
XIOModule_ClearStats(InstancePtr);
return XST_SUCCESS;
}
/****************************************************************************
*
* Sets the baud rate for the specified UART. Checks the input value for
* validity and also verifies that the requested rate can be configured to
* within the 3 percent error range for RS-232 communications. If the provided
* rate is not valid, the current setting is unchanged.
*
* This function is designed to be an internal function only used within the
* XIOModule component. It is necessary for initialization and for the user
* available function that sets the data format.
*
* @param InstancePtr is a pointer to the XIOModule instance.
* @param BaudRate to be set in the hardware.
*
* @return
* - XST_SUCCESS if everything configures as expected
* - XST_UART_BAUD_ERROR if the requested rate is not available
* because there was too much error due to the input clock
*
* @note None.
*
*****************************************************************************/
int XIOModule_SetBaudRate(XIOModule *InstancePtr, u32 BaudRate)
{
u32 Baud8;
u32 Baud16;
u32 InputClockHz;
u32 Divisor;
u32 TargetRate;
u32 Error;
u32 PercentError;
/*
* Assert validates the input arguments
*/
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
/*
* Determine what the divisor should be to get the specified baud
* rate based upon the input clock frequency and a baud clock prescaler
* of 16, rounded to nearest divisor
*/
Baud8 = BaudRate << 3;
Baud16 = Baud8 << 1;
InputClockHz = InstancePtr->CfgPtr->InputClockHz;
Divisor = (InputClockHz + Baud8) / Baud16;
/*
* Check for too much error between the baud rate that will be generated
* using the divisor and the expected baud rate, ensuring that the error
* is positive due to rounding above
*/
TargetRate = Divisor * Baud16;
if (InputClockHz < TargetRate)
Error = TargetRate - InputClockHz;
else
Error = InputClockHz - TargetRate;
/*
* Error has total error now compute the percentage multiplied by 100 to
* avoid floating point calculations, should be less than 3% as per
* RS-232 spec
*/
PercentError = (Error * 100UL) / InputClockHz;
if (PercentError > XUN_MAX_BAUD_ERROR_RATE) {
return XST_UART_BAUD_ERROR;
}
/*
* Write the baud rate divisor to the UART Baud Rate Register
*/
XIOModule_WriteReg(InstancePtr->BaseAddress,
XUL_BAUDRATE_OFFSET,
Divisor - 1);
InstancePtr->CurrentUBRR = Divisor - 1;
/*
* Save the baud rate in the instance so that the get baud rate function
* won't have to calculate it from the divisor
*/
InstancePtr->CfgPtr->BaudRate = BaudRate;
return XST_SUCCESS;
}
/****************************************************************************
*
* This function provides a stub handler such that if the application does not
* define a handler but enables interrupts, this function will be called.
*
* @param CallBackRef has no purpose but is necessary to match the
* interface for a handler.
* @param ByteCount has no purpose but is necessary to match the
* interface for a handler.
*
* @return None.
*
* @note None.
*
*****************************************************************************/
static void StubHandler(void *CallBackRef, unsigned int ByteCount)
{
/*
* Assert occurs always since this is a stub and should never be called
*/
Xil_AssertVoidAlways();
}

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/* $Id$ */
/******************************************************************************
*
* (c) Copyright 2012 Xilinx, Inc. All rights reserved.
*
* This file contains confidential and proprietary information of Xilinx, Inc.
* and is protected under U.S. and international copyright and other
* intellectual property laws.
*
* DISCLAIMER
* This disclaimer is not a license and does not grant any rights to the
* materials distributed herewith. Except as otherwise provided in a valid
* license issued to you by Xilinx, and to the maximum extent permitted by
* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
* and (2) Xilinx shall not be liable (whether in contract or tort, including
* negligence, or under any other theory of liability) for any loss or damage
* of any kind or nature related to, arising under or in connection with these
* materials, including for any direct, or any indirect, special, incidental,
* or consequential loss or damage (including loss of data, profits, goodwill,
* or any type of loss or damage suffered as a result of any action brought by
* a third party) even if such damage or loss was reasonably foreseeable or
* Xilinx had been advised of the possibility of the same.
*
* CRITICAL APPLICATIONS
* Xilinx products are not designed or intended to be fail-safe, or for use in
* any application requiring fail-safe performance, such as life-support or
* safety devices or systems, Class III medical devices, nuclear facilities,
* applications related to the deployment of airbags, or any other applications
* that could lead to death, personal injury, or severe property or
* environmental damage (individually and collectively, "Critical
* Applications"). Customer assumes the sole risk and liability of any use of
* Xilinx products in Critical Applications, subject only to applicable laws
* and regulations governing limitations on product liability.
*
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
* AT ALL TIMES.
*
******************************************************************************/
/****************************************************************************/
/**
*
* @file xiomodule_uart_intr.c
*
* Contains required functions for the XIOModule UART driver interrupt mode.
* See the xiomodule.h header file for more details on this driver.
*
* This file also contains interrupt-related functions for the UART.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.03a sa 10/16/12 First release
* </pre>
*
*****************************************************************************/
/***************************** Include Files ********************************/
#include "xil_assert.h"
#include "xiomodule.h"
#include "xiomodule_i.h"
#include "xiomodule_l.h"
/************************** Constant Definitions ****************************/
/**************************** Type Definitions ******************************/
/***************** Macros (Inline Functions) Definitions ********************/
/************************** Function Prototypes *****************************/
static void ReceiveDataHandler(XIOModule *InstancePtr);
static void SendDataHandler(XIOModule *InstancePtr);
/************************** Variable Definitions ****************************/
typedef void (*Handler)(XIOModule *InstancePtr);
/****************************************************************************/
/**
*
* This functions sends the specified buffer of data using the UART in either
* polled or interrupt driven modes. This function is non-blocking such that it
* will return before the data has been sent by the UART. If the UART is busy
* sending data, it will return and indicate zero bytes were sent.
*
* In a polled mode, this function will only send as much data as the UART can
* buffer in the transmitter. The application may need to call it repeatedly to
* send a buffer.
*
* In interrupt mode, this function will start sending the specified buffer and
* then the interrupt handler of the driver will continue sending data until the
* buffer has been sent. A callback function, as specified by the application,
* will be called to indicate the completion of sending the buffer.
*
* @param InstancePtr is a pointer to the XIOModule instance.
* @param DataBufferPtr is pointer to a buffer of data to be sent.
* @param NumBytes contains the number of bytes to be sent. A value of
* zero will stop a previous send operation that is in progress
* in interrupt mode. Any data that was already put into the
* transmit FIFO will be sent.
*
* @return The number of bytes actually sent.
*
* @note The number of bytes is not asserted so that this function may
* be called with a value of zero to stop an operation that is
* already in progress.
*
******************************************************************************/
unsigned int XIOModule_Send(XIOModule *InstancePtr, u8 *DataBufferPtr,
unsigned int NumBytes)
{
unsigned int BytesSent;
u32 StatusRegister;
/*
* Assert validates the input arguments
*/
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(DataBufferPtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Xil_AssertNonvoid(((signed)NumBytes) >= 0);
/*
* Enter a critical region by disabling the UART interrupts to allow
* this call to stop a previous operation that may be interrupt driven.
*/
StatusRegister = InstancePtr->CurrentIER;
XIomodule_Out32(InstancePtr->BaseAddress + XIN_IER_OFFSET,
StatusRegister & 0xFFFFFFF8);
/*
* Setup the specified buffer to be sent by setting the instance
* variables so it can be sent with polled or interrupt mode
*/
InstancePtr->SendBuffer.RequestedBytes = NumBytes;
InstancePtr->SendBuffer.RemainingBytes = NumBytes;
InstancePtr->SendBuffer.NextBytePtr = DataBufferPtr;
/*
* Restore the interrupt enable register to it's previous value such
* that the critical region is exited.
* This is done here to minimize the amount of time the interrupt is
* disabled since there is only one interrupt and the receive could
* be filling up while interrupts are blocked.
*/
XIomodule_Out32(InstancePtr->BaseAddress + XIN_IER_OFFSET,
(InstancePtr->CurrentIER & 0xFFFFFFF8) | (StatusRegister & 0x7));
/*
* Send the buffer using the UART and return the number of bytes sent
*/
BytesSent = XIOModule_SendBuffer(InstancePtr);
return BytesSent;
}
/****************************************************************************/
/**
*
* This function will attempt to receive a specified number of bytes of data
* from the UART and store it into the specified buffer. This function is
* designed for either polled or interrupt driven modes. It is non-blocking
* such that it will return if no data has already received by the UART.
*
* In a polled mode, this function will only receive as much data as the UART
* can buffer in the receiver. The application may need to call it repeatedly to
* receive a buffer. Polled mode is the default mode of operation for the driver.
*
* In interrupt mode, this function will start receiving and then the interrupt
* handler of the driver will continue receiving data until the buffer has been
* received. A callback function, as specified by the application, will be called
* to indicate the completion of receiving the buffer or when any receive errors
* or timeouts occur.
*
* @param InstancePtr is a pointer to the XIOModule instance.
* @param DataBufferPtr is pointer to buffer for data to be received into.
* @param NumBytes is the number of bytes to be received. A value of zero
* will stop a previous receive operation that is in progress in
* interrupt mode.
*
* @return The number of bytes received.
*
* @note The number of bytes is not asserted so that this function
* may be called with a value of zero to stop an operation
* that is already in progress.
*
*****************************************************************************/
unsigned int XIOModule_Recv(XIOModule *InstancePtr, u8 *DataBufferPtr,
unsigned int NumBytes)
{
unsigned int ReceivedCount;
u32 StatusRegister;
/*
* Assert validates the input arguments
*/
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(DataBufferPtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Xil_AssertNonvoid(((signed)NumBytes) >= 0);
/*
* Enter a critical region by disabling all the UART interrupts to allow
* this call to stop a previous operation that may be interrupt driven
*/
StatusRegister = InstancePtr->CurrentIER;
XIomodule_Out32(InstancePtr->BaseAddress + XIN_IER_OFFSET,
StatusRegister & 0xFFFFFFF8);
/*
* Setup the specified buffer to be received by setting the instance
* variables so it can be received with polled or interrupt mode
*/
InstancePtr->ReceiveBuffer.RequestedBytes = NumBytes;
InstancePtr->ReceiveBuffer.RemainingBytes = NumBytes;
InstancePtr->ReceiveBuffer.NextBytePtr = DataBufferPtr;
/*
* Restore the interrupt enable register to it's previous value such
* that the critical region is exited
*/
XIomodule_Out32(InstancePtr->BaseAddress + XIN_IER_OFFSET,
(InstancePtr->CurrentIER & 0xFFFFFFF8) | (StatusRegister & 0x7));
/*
* Receive the data from the UART and return the number of bytes
* received. This is done here to minimize the amount of time the
* interrupt is disabled.
*/
ReceivedCount = XIOModule_ReceiveBuffer(InstancePtr);
return ReceivedCount;
}
/****************************************************************************/
/**
*
* This function does nothing, since the UART doesn't have any FIFOs. It is
* included for compatibility with the UART Lite driver.
*
* @param InstancePtr is a pointer to the XIOModule instance .
*
* @return None.
*
* @note None.
*
*****************************************************************************/
void XIOModule_ResetFifos(XIOModule *InstancePtr)
{
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
}
/****************************************************************************/
/**
*
* This function determines if the specified UART is sending data. If the
* transmitter register is not empty, it is sending data.
*
* @param InstancePtr is a pointer to the XIOModule instance.
*
* @return A value of TRUE if the UART is sending data, otherwise FALSE.
*
* @note None.
*
*****************************************************************************/
int XIOModule_IsSending(XIOModule *InstancePtr)
{
u32 StatusRegister;
/*
* Assert validates the input arguments
*/
Xil_AssertNonvoid(InstancePtr != NULL);
/*
* Read the status register to determine if the transmitter is empty
*/
StatusRegister = XIOModule_ReadReg(InstancePtr->BaseAddress,
XUL_STATUS_REG_OFFSET);
/*
* If the transmitter is not empty then indicate that the UART is still
* sending some data
*/
return ((StatusRegister & XUL_SR_TX_FIFO_FULL) == XUL_SR_TX_FIFO_FULL);
}
/****************************************************************************/
/**
*
* This function sends a buffer that has been previously specified by setting
* up the instance variables of the instance. This function is designed to be
* an internal function for the XIOModule component such that it may be called
* from a shell function that sets up the buffer or from an interrupt handler.
*
* This function sends the specified buffer of data to the UART in either
* polled or interrupt driven modes. This function is non-blocking such that
* it will return before the data has been sent by the UART.
*
* In a polled mode, this function will only send as much data as the UART can
* buffer in the transmitter. The application may need to call it repeatedly to
* send a buffer.
*
* In interrupt mode, this function will start sending the specified buffer and
* then the interrupt handler of the driver will continue until the buffer
* has been sent. A callback function, as specified by the application, will
* be called to indicate the completion of sending the buffer.
*
* @param InstancePtr is a pointer to the XIOModule instance.
*
* @return NumBytes is the number of bytes actually sent (put into the
* UART transmitter and/or FIFO).
*
* @note None.
*
*****************************************************************************/
unsigned int XIOModule_SendBuffer(XIOModule *InstancePtr)
{
unsigned int SentCount = 0;
u8 StatusRegister;
u8 IntrEnableStatus;
/*
* Read the status register to determine if the transmitter is full
*/
StatusRegister = XIOModule_GetStatusReg(InstancePtr->BaseAddress);
/*
* Enter a critical region by disabling all the UART interrupts to allow
* this call to stop a previous operation that may be interrupt driven
*/
XIomodule_Out32(InstancePtr->BaseAddress + XIN_IER_OFFSET,
StatusRegister & 0xFFFFFFF8);
/*
* Save the status register contents to restore the interrupt enable
* register to it's previous value when that the critical region is
* exited
*/
IntrEnableStatus = StatusRegister;
/*
* Fill the FIFO from the the buffer that was specified
*/
while (((StatusRegister & XUL_SR_TX_FIFO_FULL) == 0) &&
(SentCount < InstancePtr->SendBuffer.RemainingBytes)) {
XIOModule_WriteReg(InstancePtr->BaseAddress,
XUL_TX_OFFSET,
InstancePtr->SendBuffer.NextBytePtr[
SentCount]);
SentCount++;
StatusRegister =
XIOModule_GetStatusReg(InstancePtr->BaseAddress);
}
/*
* Update the buffer to reflect the bytes that were sent from it
*/
InstancePtr->SendBuffer.NextBytePtr += SentCount;
InstancePtr->SendBuffer.RemainingBytes -= SentCount;
/*
* Increment associated counters
*/
InstancePtr->Uart_Stats.CharactersTransmitted += SentCount;
/*
* Restore the interrupt enable register to it's previous value such
* that the critical region is exited
*/
XIomodule_Out32(InstancePtr->BaseAddress + XIN_IER_OFFSET,
(InstancePtr->CurrentIER & 0xFFFFFFF8) | (IntrEnableStatus & 0x7));
/*
* Return the number of bytes that were sent, althought they really were
* only put into the FIFO, not completely sent yet
*/
return SentCount;
}
/****************************************************************************/
/**
*
* This function receives a buffer that has been previously specified by setting
* up the instance variables of the instance. This function is designed to be
* an internal function for the XIOModule component such that it may be called
* from a shell function that sets up the buffer or from an interrupt handler.
*
* This function will attempt to receive a specified number of bytes of data
* from the UART and store it into the specified buffer. This function is
* designed for either polled or interrupt driven modes. It is non-blocking
* such that it will return if there is no data has already received by the
* UART.
*
* In a polled mode, this function will only receive as much data as the UART
* can buffer, either in the receiver or in the FIFO if present and enabled.
* The application may need to call it repeatedly to receive a buffer. Polled
* mode is the default mode of operation for the driver.
*
* In interrupt mode, this function will start receiving and then the interrupt
* handler of the driver will continue until the buffer has been received. A
* callback function, as specified by the application, will be called to indicate
* the completion of receiving the buffer or when any receive errors or timeouts
* occur.
*
* @param InstancePtr is a pointer to the XIOModule instance.
*
* @return The number of bytes received.
*
* @note None.
*
*****************************************************************************/
unsigned int XIOModule_ReceiveBuffer(XIOModule *InstancePtr)
{
u8 StatusRegister;
unsigned int ReceivedCount = 0;
/*
* Loop until there is not more data buffered by the UART or the
* specified number of bytes is received
*/
while (ReceivedCount < InstancePtr->ReceiveBuffer.RemainingBytes) {
/*
* Read the Status Register to determine if there is any data in
* the receiver
*/
StatusRegister =
XIOModule_GetStatusReg(InstancePtr->BaseAddress);
/*
* If there is data ready to be removed, then put the next byte
* received into the specified buffer and update the stats to
* reflect any receive errors for the byte
*/
if (StatusRegister & XUL_SR_RX_FIFO_VALID_DATA) {
InstancePtr->ReceiveBuffer.NextBytePtr[ReceivedCount++]=
XIOModule_ReadReg(InstancePtr->BaseAddress,
XUL_RX_OFFSET);
XIOModule_UpdateStats(InstancePtr, StatusRegister);
}
/*
* There's no more data buffered, so exit such that this
* function does not block waiting for data
*/
else {
break;
}
}
/*
* Enter a critical region by disabling all the UART interrupts to allow
* this call to stop a previous operation that may be interrupt driven
*/
StatusRegister = InstancePtr->CurrentIER;
XIomodule_Out32(InstancePtr->BaseAddress + XIN_IER_OFFSET,
StatusRegister & 0xFFFFFFF8);
/*
* Update the receive buffer to reflect the number of bytes that was
* received
*/
InstancePtr->ReceiveBuffer.NextBytePtr += ReceivedCount;
InstancePtr->ReceiveBuffer.RemainingBytes -= ReceivedCount;
/*
* Increment associated counters in the statistics
*/
InstancePtr->Uart_Stats.CharactersReceived += ReceivedCount;
/*
* Restore the interrupt enable register to it's previous value such
* that the critical region is exited
*/
XIomodule_Out32(InstancePtr->BaseAddress + XIN_IER_OFFSET,
(InstancePtr->CurrentIER & 0xFFFFFFF8) | (StatusRegister & 0x7));
return ReceivedCount;
}
/****************************************************************************/
/**
*
* This function sets the handler that will be called when an event (interrupt)
* occurs in the driver for the UART. The purpose of the handler is to allow
* application specific processing to be performed.
*
* @param InstancePtr is a pointer to the XIOModule instance.
* @param FuncPtr is the pointer to the callback function.
* @param CallBackRef is the upper layer callback reference passed back
* when the callback function is invoked.
*
* @return None.
*
* @note There is no assert on the CallBackRef since the driver doesn't
* know what it is (nor should it)
*
*****************************************************************************/
void XIOModule_SetRecvHandler(XIOModule *InstancePtr,
XIOModule_Handler FuncPtr, void *CallBackRef)
{
/*
* Assert validates the input arguments
* CallBackRef not checked, no way to know what is valid
*/
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(FuncPtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
InstancePtr->RecvHandler = FuncPtr;
InstancePtr->RecvCallBackRef = CallBackRef;
}
/****************************************************************************/
/**
*
* This function sets the handler that will be called when an event (interrupt)
* occurs in the driver for the UART. The purpose of the handler is to allow
* application specific processing to be performed.
*
* @param InstancePtr is a pointer to the XIOModule instance .
* @param FuncPtr is the pointer to the callback function.
* @param CallBackRef is the upper layer callback reference passed back
* when the callback function is invoked.
*
* @return None.
*
* @note There is no assert on the CallBackRef since the driver doesn't
* know what it is (nor should it)
*
*****************************************************************************/
void XIOModule_SetSendHandler(XIOModule *InstancePtr,
XIOModule_Handler FuncPtr, void *CallBackRef)
{
/*
* Assert validates the input arguments
* CallBackRef not checked, no way to know what is valid
*/
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(FuncPtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
InstancePtr->SendHandler = FuncPtr;
InstancePtr->SendCallBackRef = CallBackRef;
}
/****************************************************************************/
/**
*
* This function is the interrupt handler for the UART.
* It must be connected to an interrupt system by the user such that it is
* called when an interrupt for any UART lite occurs. This function
* does not save or restore the processor context such that the user must
* ensure this occurs.
*
* @param InstancePtr contains a pointer to the instance of the IOModule
* that the interrupt is for.
*
* @return None.
*
* @note None.
*
******************************************************************************/
void XIOModule_Uart_InterruptHandler(XIOModule *InstancePtr)
{
u32 IsrStatus;
Xil_AssertVoid(InstancePtr != NULL);
/*
* Read the status register to determine which, could be both,
* interrupt is active
*/
IsrStatus = XIOModule_ReadReg(InstancePtr->BaseAddress,
XIN_IPR_OFFSET);
if ((IsrStatus & XUL_SR_RX_FIFO_VALID_DATA) != 0) {
ReceiveDataHandler(InstancePtr);
}
if (((IsrStatus & XUL_SR_TX_FIFO_FULL) == XUL_SR_TX_FIFO_FULL) &&
(InstancePtr->SendBuffer.RequestedBytes > 0)) {
SendDataHandler(InstancePtr);
}
}
/****************************************************************************/
/**
*
* This function handles the interrupt when data is received, either a single
* byte when FIFOs are not enabled, or multiple bytes with the FIFO.
*
* @param InstancePtr is a pointer to the XIOModule instance.
*
* @return None.
*
* @note None.
*
*****************************************************************************/
static void ReceiveDataHandler(XIOModule *InstancePtr)
{
/*
* If there are bytes still to be received in the specified buffer
* go ahead and receive them
*/
if (InstancePtr->ReceiveBuffer.RemainingBytes != 0) {
XIOModule_ReceiveBuffer(InstancePtr);
}
/*
* If the last byte of a message was received then call the application
* handler, this code should not use an else from the previous check of
* the number of bytes to receive because the call to receive the buffer
* updates the bytes to receive
*/
if (InstancePtr->ReceiveBuffer.RemainingBytes == 0) {
InstancePtr->RecvHandler(InstancePtr->RecvCallBackRef,
InstancePtr->ReceiveBuffer.RequestedBytes -
InstancePtr->ReceiveBuffer.RemainingBytes);
}
/*
* Update the receive stats to reflect the receive interrupt
*/
InstancePtr->Uart_Stats.ReceiveInterrupts++;
}
/****************************************************************************/
/**
*
* This function handles the interrupt when data has been sent, the transmit
* FIFO is empty (transmitter holding register).
*
* @param InstancePtr is a pointer to the XIOModule instance .
*
* @return None.
*
* @note None.
*
*****************************************************************************/
static void SendDataHandler(XIOModule *InstancePtr)
{
/*
* If there are not bytes to be sent from the specified buffer,
* call the callback function
*/
if (InstancePtr->SendBuffer.RemainingBytes == 0) {
int SaveReq;
/*
* Save and zero the requested bytes since transmission
* is complete
*/
SaveReq = InstancePtr->SendBuffer.RequestedBytes;
InstancePtr->SendBuffer.RequestedBytes = 0;
/*
* Call the application handler to indicate
* the data has been sent
*/
InstancePtr->SendHandler(InstancePtr->SendCallBackRef, SaveReq);
}
/*
* Otherwise there is still more data to send in the specified buffer
* so go ahead and send it
*/
else {
XIOModule_SendBuffer(InstancePtr);
}
/*
* Update the transmit stats to reflect the transmit interrupt
*/
InstancePtr->Uart_Stats.TransmitInterrupts++;
}
/*****************************************************************************/
/**
*
* This function disables the UART interrupt. After calling this function,
* data may still be received by the UART but no interrupt will be generated
* since the hardware device has no way to disable the receiver.
*
* @param InstancePtr is a pointer to the XIOModule instance.
*
* @return None.
*
* @note None.
*
*****************************************************************************/
void XIOModule_Uart_DisableInterrupt(XIOModule *InstancePtr)
{
u32 NewIER;
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
/*
* Write to the interupt enable register to disable the UART
* interrupts.
*/
NewIER = InstancePtr->CurrentIER & 0xFFFFFFF8;
XIomodule_Out32(InstancePtr->BaseAddress + XIN_IER_OFFSET, NewIER);
InstancePtr->CurrentIER = NewIER;
}
/*****************************************************************************/
/**
*
* This function enables the UART interrupts such that an interrupt will occur
* when data is received or data has been transmitted.
*
* @param InstancePtr is a pointer to the XIOModule instance.
*
* @return None.
*
* @note None.
*
*****************************************************************************/
void XIOModule_Uart_EnableInterrupt(XIOModule *InstancePtr)
{
u32 NewIER;
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
/*
* Write to the interrupt enable register to enable the interrupts.
*/
NewIER = InstancePtr->CurrentIER | 0x7;
XIomodule_Out32(InstancePtr->BaseAddress + XIN_IER_OFFSET, NewIER);
InstancePtr->CurrentIER = NewIER;
}

62
software/LED_Controller_bsp/microblaze_mcs/libsrc/standalone_v3_11_a/src/Makefile Executable file
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######################################################################
# Copyright (c) 2004 Xilinx, Inc. All rights reserved.
#
# Xilinx, Inc.
# XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
# COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
# ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
# STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
# IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
# FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
# XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
# THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
# ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
# FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
# AND FITNESS FOR A PARTICULAR PURPOSE.
######################################################################
# The following are defined in config.make
# LIBSOURCES - Based on if MicroBlaze support Exceptions
# LIBS - Do Build Profile Libraries
include config.make
AS=mb-as
CC=mb-gcc
AR=mb-ar
CP=cp
COMPILER_FLAGS=-O2 -c
EXTRA_COMPILER_FLAGS=
LIB=libxil.a
CC_FLAGS = $(subst -pg, , $(COMPILER_FLAGS))
ECC_FLAGS = $(subst -pg, , $(EXTRA_COMPILER_FLAGS))
RELEASEDIR=../../../lib
INCLUDEDIR=../../../include
INCLUDES=-I./. -I${INCLUDEDIR}
OUTS = *.o
INCLUDEFILES=*.h
libs: $(LIBS) clean
standalone_libs: $(LIBSOURCES)
echo "Compiling standalone";
$(CC) $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) $^
$(AR) -r ${RELEASEDIR}/${LIB} ${OUTS}
profile_libs:
$(MAKE) -C profile COMPILER_FLAGS="$(COMPILER_FLAGS)" EXTRA_COMPILER_FLAGS="$(EXTRA_COMPILER_FLAGS)" COMPILER="$(CC)" ARCHIVER="$(AR)" AS="$(AS)" libs
include: standalone_includes profile_includes
standalone_includes:
${CP} ${INCLUDEFILES} ${INCLUDEDIR}
profile_includes:
$(MAKE) -C profile COMPILER_FLAGS="$(COMPILER_FLAGS)" EXTRA_COMPILER_FLAGS="$(EXTRA_COMPILER_FLAGS)" COMPILER="$(CC)" ARCHIVER="$(AR)" AS="$(AS)" include
clean:
rm -rf ${OUTS}
$(MAKE) -C profile COMPILER_FLAGS="$(COMPILER_FLAGS)" EXTRA_COMPILER_FLAGS="$(EXTRA_COMPILER_FLAGS)" COMPILER="$(CC)" ARCHIVER="$(AR)" AS="$(AS)" clean

28
software/LED_Controller_bsp/microblaze_mcs/libsrc/standalone_v3_11_a/src/_exit.c Executable file
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////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2004 Xilinx, Inc. All rights reserved.
//
// Xilinx, Inc.
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
// AND FITNESS FOR A PARTICULAR PURPOSE.
//
// $Id: _exit.c,v 1.1.2.1 2011/05/17 04:37:25 sadanan Exp $
////////////////////////////////////////////////////////////////////////////////
#include <unistd.h>
/* _exit - Simple implementation. Does not return.
*/
void _exit (int status)
{
(void) status;
while (1);
}

15
software/LED_Controller_bsp/microblaze_mcs/libsrc/standalone_v3_11_a/src/bspconfig.h Normal file
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@@ -0,0 +1,15 @@
/*******************************************************************
*
* CAUTION: This file is automatically generated by libgen.
* Version: Xilinx EDK 14.7 EDK_P.20131013
* DO NOT EDIT.
*
* Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
*
* Description: Configurations for Standalone BSP
*
*******************************************************************/
#define MICROBLAZE_PVR_NONE

147
software/LED_Controller_bsp/microblaze_mcs/libsrc/standalone_v3_11_a/src/changelog.txt Executable file
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/*****************************************************************************
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- ---------------------------------------------------
* 3.02a sdm 05/30/11 Added Xuint64 typedef and XUINT64_MSW/XUINT64_LSW macros
* 3.02a sdm 06/27/11 Added INST_SYNC and DATA_SYNC macros for all the CPUs
* 3.02a sdm 07/07/11 Updated ppc440 boot.S to set guarded bit for all but
* cacheable regions
* Update ppc440/xil_cache.c to use CACHEABLE_REGION_MASK
* generated by the cpu driver, for enabling caches
* 3.02a sdm 07/08/11 Updated microblaze cache flush APIs based on write-back/
* write-thru caches
* 3.03a sdm 08/20/11 Updated the tag/data RAM latency values for L2CC
* Updated the MMU table to mark OCM in high address space
* as inner cacheable and reserved space as Invalid
* 3.03a sdm 08/20/11 Changes to support FreeRTOS
* Updated the MMU table to mark upper half of the DDR as
* non-cacheable
* Setup supervisor and abort mode stacks
* Do not initialize/enable L2CC in case of AMP
* Initialize UART1 for 9600bps in case of AMP
* 3.03a sdm 08/27/11 Setup abort and supervisor mode stacks and don't init SMC
* in case of AMP
* 3.03a sdm 09/14/11 Added code for performance monitor and L2CC event
* counters
* 3.03a sdm 11/08/11 Updated microblaze xil_cache.h file to include
* xparameters.h file for CR630532 - Xil_DCacheFlush()/
* Xil_DCacheFlushRange() functions in standalone BSP v3_02a
* for MicroBlaze will invalidate data in the cache instead
* of flushing it for writeback caches
* 3.04a sdm 11/21/11 Updated to initialize stdio device for 115200bps, for PS7
* 3.04a sdm 01/02/12 Updated to clear cp15 regs with unknown reset values
* Remove redundant dsb/dmb instructions in cache maintenance
* APIs
* Remove redundant dsb in mcr instruction
* 3.04a sdm 01/13/12 Updated MMU table to mark DDR memory as Shareable
* 3.05a sdm 02/02/12 Removed some of the defines as they are being generated through
* driver tcl in xparameters.h. Update the gcc/translationtable.s
* for the QSPI complete address range - DT644567
* Removed profile directory for armcc compiler and changed
* profiling setting to false in standalone_v2_1_0.tcl file
* Deleting boot.S file after preprocessing for armcc compiler
* 3.05a asa 03/11/12 Updated the function Xil_EnableMMU in file xil_mmu.c to
* invalidate the caches before enabling back the MMU and
* D cache.
* 3.05a asa 04/15/12 Updated the function Xil_SetTlbAttributes in file
* xil_mmu.c. Now we invalidate UTLB, Branch predictor
* array, flush the D-cache before changing the attributes
* in translation table. The user need not call Xil_DisableMMU
* before calling Xil_SetTlbAttributes.
* 3.06a asa/ 06/17/12 Removed the UART initialization for Zynq. For PEEP, the UART
* sgd initialization is present. Changes for this were done in
* uart.c and xil-crt0.s.
* Made changes in xil_io.c to use volatile pointers.
* Made changes in xil_mmu.c to correct the function
* Xil_SetTlbAttributes.
* Changes are made xil-crt0.s to initialize the static
* C++ constructors.
* Changes are made in boot.s, to fix the TTBR settings,
* correct the L2 Cache Auxiliary register settings, L2 cache
* latency settings.
* 3.07a asa/ 07/16/12 Made changes in cortexa9/xtime_l.c, xtime_l.h, sleep.c
* sgd usleep.c to use global timer intstead of CP15.
* Made changes in cortexa9/gcc/translation_table.s to map
* the peripheral devices as shareable device memory.
* Made changes in cortexa9/gcc/xil-crt0.s to initialize
* the global timer.
* Made changes in cortexa9/armcc/boot.S to initialize
* the global timer.
* Made changes in cortexa9/armcc/translation_table.s to
* map the peripheral devices as shareable device memory.
* Made changes in cortexa9/gcc/boot.S to optimize the
* L2 cache settings. Changes the section properties for
* ".mmu_tbl" and ".boot" sections in cortexa9/gcc/boot.S
* and cortexa9/gcc/translation_table.S.
* Made changes in cortexa9/xil_cache.c to change the
* cache invalidation order.
* 3.07a asa 08/17/12 Made changes across files for Cortexa9 to remove
* compilation/linking issues for C++ compiler.
* Made changes in mb_interface.h to remove compilation/
* linking issues for C++ compiler.
* Added macros for swapb and swaph microblaze instructions
* mb_interface.h
* Remove barrier usage (SYNCHRONIZE_IO) from xil_io.c
* for CortexA9.
* 3.07a asa 08/30/12 Updated for CR 675636 to provide the L2 Base Address
* 3.07a asa 08/31/12 Added xil_printf.h include
* 3.07a sgd 09/18/12 Corrected the L2 cache enable settings
* Corrected L2 cache sequence disable sequence
* 3.07a sgd 10/19/12 SMC NOR and SRAM initialization with compiler option
* 3.09a asa 01/25/13 Updated to push and pop neon registers into stack for
* irq/fiq handling.
* Relocated COUNTS_PER_SECOND from sleep.c to xtime_l.h. This
* fixes the CR #692094.
* 3.09a sgd 02/14/13 Fix for CRs 697094 (SI#687034) and 675552.
* 3.10a srt 04/18/13 Implemented ARM Erratas.
* Cortex A9 Errata - 742230, 743622, 775420, 794073
* L2Cache PL310 Errata - 588369, 727915, 759370
* Please refer to file 'xil_errata.h' for errata
* description.
* 3.10a asa 05/04/13 Added support for L2 cache in MicroBlaze BSP. The older
* cache APIs were corresponding to only Layer 1 cache
* memories. New APIs were now added and the existing cache
* related APIs were changed to provide a uniform interface
* to flush/invalidate/enable/disable the complete cache
* system which includes both L1 and L2 caches. The changes
* for these were done in:
* src/microblaze/xil_cache.c and src/microblaze/xil_cache.h
* files.
* Four new files were added for supporting L2 cache. They are:
* microblaze_flush_cache_ext.S-> Flushes L2 cache
* microblaze_flush_cache_ext_range.S -> Flushes a range of
* memory in L2 cache.
* microblaze_invalidate_cache_ext.S-> Invalidates L2 cache
* microblaze_invalidate_cache_ext_range -> Invalidates a
* range of memory in L2 cache.
* These changes are done to implement PR #697214.
* 3.10a asa 05/13/13 Modified cache disable APIs at src/cortexa9/xil_cache.c to
* fix the CR #706464. L2 cache disabling happens independent
* of L1 data cache disable operation. Changes are done in the
* same file in cache handling APIs to do a L2 cache sync
* (poll reg7_?cache_?sync). This fixes CR #700542.
* 3.10a asa 05/20/13 Added API/Macros for enabling and disabling nested
* interrupts for ARM. These are done to fix the CR#699680.
* 3.10a srt 05/20/13 Made changes in cache maintenance APIs to do a proper cach
* sync operation. This fixes the CR# 716781.
* 3.11a asa 09/07/13 Added support for iccarm toolchain. A new folder "iccarm"
* is added that contains iccarm (iar arm compiler) specific
* BSP initialization code. Changes are done in other source
* files with inline assembly code to add support for armcc.
* Modified BSP tcl to add support for iccarm.
* Updated armcc specific BSP files to have proper support
* for armcc toolchain.
* Modified asm_vectors.S (gcc) and asm_vectors.s (armcc) to
* fix issues related to NEON context saving. The assembly
* routines for IRQ and FIQ handling are modified.
* Deprecated the older BSP (3.10a).
* 3.11a asa 09/22/13 Fix for CR#732704. Cache APIs are modified to avoid
* various potential issues. Made changes in the function
* Xil_SetAttributes in file xil_mmu.c.
* 3.11a asa 09/23/13 Added files xil_misc_psreset_api.c and xil_misc_psreset_api.h
* in src\cortexa9 and src\microblaze folders.
* 3.11a asa 09/28/13 Modified the cache APIs (src\cortexa9) to fix handling of
* L2 cache sync operation and to fix issues around complete
* L2 cache flush/invalidation by ways.
********************************************************************************/

3
software/LED_Controller_bsp/microblaze_mcs/libsrc/standalone_v3_11_a/src/config.make Normal file
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LIBSOURCES = *.c *.s *.S
PROFILE_ARCH_OBJS = profile_mcount_mb.o
LIBS = standalone_libs

12
software/LED_Controller_bsp/microblaze_mcs/libsrc/standalone_v3_11_a/src/errno.c Executable file
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@@ -0,0 +1,12 @@
/* The errno variable is stored in the reentrancy structure. This
function returns its address for use by the macro errno defined in
errno.h. */
#include <errno.h>
#include <reent.h>
int *
__errno ()
{
return &_REENT->_errno;
}

13
software/LED_Controller_bsp/microblaze_mcs/libsrc/standalone_v3_11_a/src/fcntl.c Executable file
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#include <stdio.h>
/*
* fcntl -- Manipulate a file descriptor.
* We don't have a filesystem, so we do nothing.
*/
int fcntl (int fd, int cmd, long arg)
{
(void) fd;
(void) cmd;
(void) arg;
return 0;
}

49
software/LED_Controller_bsp/microblaze_mcs/libsrc/standalone_v3_11_a/src/fsl.h Executable file
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#ifndef _FSL_H
#define _FSL_H
#include "xbasic_types.h"
#include "mb_interface.h" /* Legacy reasons. We just have to include this guy who defines the FSL stuff */
#ifdef __cplusplus
extern "C" {
#endif
/* Extended FSL macros. These now replace all of the previous FSL macros */
#define FSL_DEFAULT
#define FSL_NONBLOCKING n
#define FSL_EXCEPTION e
#define FSL_CONTROL c
#define FSL_ATOMIC a
#define FSL_NONBLOCKING_EXCEPTION ne
#define FSL_NONBLOCKING_CONTROL nc
#define FSL_NONBLOCKING_ATOMIC na
#define FSL_EXCEPTION_CONTROL ec
#define FSL_EXCEPTION_ATOMIC ea
#define FSL_CONTROL_ATOMIC ca
#define FSL_NONBLOCKING_EXCEPTION_CONTROL nec
#define FSL_NONBLOCKING_EXCEPTION_ATOMIC nea
#define FSL_NONBLOCKING_CONTROL_ATOMIC nca
#define FSL_EXCEPTION_CONTROL_ATOMIC eca
#define FSL_NONBLOCKING_EXCEPTION_CONTROL_ATOMIC neca
#define getfslx(val, id, flags) asm volatile (stringify(flags) "get\t%0,rfsl" stringify(id) : "=d" (val))
#define putfslx(val, id, flags) asm volatile (stringify(flags) "put\t%0,rfsl" stringify(id) :: "d" (val))
#define tgetfslx(val, id, flags) asm volatile ("t" stringify(flags) "get\t%0,rfsl" stringify(id) : "=d" (val))
#define tputfslx(id, flags) asm volatile ("t" stringify(flags) "put\trfsl" stringify(id))
#define getdfslx(val, var, flags) asm volatile (stringify(flags) "getd\t%0,%1" : "=d" (val) : "d" (var))
#define putdfslx(val, var, flags) asm volatile (stringify(flags) "putd\t%0,%1" :: "d" (val), "d" (var))
#define tgetdfslx(val, var, flags) asm volatile ("t" stringify(flags) "getd\t%0,%1" : "=d" (val) : "d" (var))
#define tputdfslx(var, flags) asm volatile ("t" stringify(flags) "putd\t%0" :: "d" (var))
#ifdef __cplusplus
}
#endif
#endif /* _FSL_H */

652
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/*///////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2004-2011 Xilinx, Inc. All rights reserved.
//
// Xilinx, Inc.
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
// AND FITNESS FOR A PARTICULAR PURPOSE.
//
// $Id: hw_exception_handler.S,v 1.1.2.1 2011/05/17 04:37:25 sadanan Exp $
//
//////////////////////////////////////////////////////////////////////////////*/
/*
* Microblaze HW Exception Handler
* - Non self-modifying exception handler for the following exception conditions
* - Unalignment
* - Instruction bus error
* - Data bus error
* - Illegal instruction opcode
* - Divide-by-zero
* - Stack protection violation
*/
#include "microblaze_exceptions_g.h"
#include "xparameters.h"
/* Helpful Macros */
#define EX_HANDLER_STACK_SIZ (4*21)
#define RMSR_OFFSET (20 * 4)
#define R17_OFFSET (0)
#define REG_OFFSET(regnum) (4 * (regnum + 1))
#define NUM_TO_REG(num) r ## num
#define R3_TO_STACK(regnum) swi r3, r1, REG_OFFSET(regnum)
#define R3_FROM_STACK(regnum) lwi r3, r1, REG_OFFSET(regnum)
#define PUSH_REG(regnum) swi NUM_TO_REG(regnum), r1, REG_OFFSET(regnum)
#define POP_REG(regnum) lwi NUM_TO_REG(regnum), r1, REG_OFFSET(regnum)
/* Uses r5 */
#define PUSH_MSR \
mfs r5, rmsr; \
swi r5, r1, RMSR_OFFSET;
#define PUSH_MSR_AND_ENABLE_EXC \
mfs r5, rmsr; \
swi r5, r1, RMSR_OFFSET; \
ori r5, r5, 0x100; /* Turn ON the EE bit*/ \
mts rmsr, r5;
/* Uses r5 */
#define POP_MSR \
lwi r5, r1, RMSR_OFFSET; \
mts rmsr, r5;
/* Push r17 */
#define PUSH_R17 swi r17, r1, R17_OFFSET
/* Pop r17 */
#define POP_R17 lwi r17, r1, R17_OFFSET
#define LWREG_NOP \
bri ex_handler_unhandled; \
nop;
#define SWREG_NOP \
bri ex_handler_unhandled; \
nop;
/* r3 is the source */
#define R3_TO_LWREG_V(regnum) \
R3_TO_STACK (regnum); \
bri ex_handler_done;
/* r3 is the source */
#define R3_TO_LWREG(regnum) \
or NUM_TO_REG (regnum), r0, r3; \
bri ex_handler_done;
/* r3 is the target */
#define SWREG_TO_R3_V(regnum) \
R3_FROM_STACK (regnum); \
bri ex_sw_tail;
/* r3 is the target */
#define SWREG_TO_R3(regnum) \
or r3, r0, NUM_TO_REG (regnum); \
bri ex_sw_tail;
/* regnum is the source */
#define FP_EX_OPB_SAVE(regnum) \
swi NUM_TO_REG (regnum), r0, mb_fpex_op_b; \
nop; \
bri handle_fp_ex_opa;
/* regnum is the source */
#define FP_EX_OPB_SAVE_V(regnum) \
R3_FROM_STACK (regnum); \
swi r3, r0, mb_fpex_op_b; \
bri handle_fp_ex_opa;
/* regnum is the source */
#define FP_EX_OPA_SAVE(regnum) \
swi NUM_TO_REG (regnum), r0, mb_fpex_op_a; \
nop; \
bri handle_fp_ex_done;
/* regnum is the source */
#define FP_EX_OPA_SAVE_V(regnum) \
R3_FROM_STACK (regnum); \
swi r3, r0, mb_fpex_op_a; \
bri handle_fp_ex_done;
#define FP_EX_UNHANDLED \
bri fp_ex_unhandled; \
nop; \
nop;
/* ESR masks */
#define ESR_EXC_MASK 0x0000001F
#define ESR_REG_MASK 0x000003E0
#define ESR_LW_SW_MASK 0x00000400
#define ESR_WORD_MASK 0x00000800
#define ESR_DS_MASK 0x00001000
/* Extern declarations */
.extern XNullHandler
#ifdef MICROBLAZE_EXCEPTIONS_ENABLED /* If exceptions are enabled in the processor */
/*
* hw_exception_handler - Handler for unaligned exceptions
* Exception handler notes:
* - Does not handle exceptions other than unaligned exceptions
* - Does not handle exceptions during load into r17, r1, r0.
* - Does not handle exceptions during store from r17 (cannot be done) and r1 (slows down common case)
*
* Relevant register structures
*
* EAR - |----|----|----|----|----|----|----|----|
* - < ## 32 bit faulting address ## >
*
* ESR - |----|----|----|----|----| - | - |-----|-----|
* - W S REG EXC
*
*
* STACK FRAME STRUCTURE
* ---------------------
*
* +-------------+ + 0
* | r17 |
* +-------------+ + 4
* | Args for |
* | next func |
* +-------------+ + 8
* | r1 |
* | . |
* | . |
* | . |
* | . |
* | r18 |
* +-------------+ + 80
* | MSR |
* +-------------+ + 84
* | . |
* | . |
*/
.global _hw_exception_handler
.section .text
.align 2
.ent _hw_exception_handler
.type _hw_exception_handler, @function
_hw_exception_handler:
#if defined(XPAR_MICROBLAZE_USE_STACK_PROTECTION) && (XPAR_MICROBLAZE_USE_STACK_PROTECTION == 1)
/* Immediately halt for stack protection violation exception without using any stack */
swi r3, r0, mb_sp_save_r3; /* Save temporary register */
mfs r3, resr; /* Extract ESR[DS] */
andi r3, r3, ESR_EXC_MASK;
xori r3, r3, 0x7; /* Check for stack protection violation */
bnei r3, ex_handler_not_sp_violation;
ex_handler_sp_violation:
bri 0; /* Halt here if stack protection violation */
ex_handler_not_sp_violation:
lwi r3, r0, mb_sp_save_r3; /* Restore temporary register */
#endif /* defined(XPAR_MICROBLAZE_USE_STACK_PROTECTION) && (XPAR_MICROBLAZE_USE_STACK_PROTECTION == 1) */
addik r1, r1, -(EX_HANDLER_STACK_SIZ); /* Create stack frame */
PUSH_REG(3);
PUSH_REG(4);
PUSH_REG(5);
PUSH_REG(6);
#ifdef MICROBLAZE_CAN_HANDLE_EXCEPTIONS_IN_DELAY_SLOTS
mfs r6, resr;
andi r6, r6, ESR_DS_MASK;
beqi r6, ex_handler_no_ds;
mfs r17, rbtr;
ex_handler_no_ds:
#endif
PUSH_R17;
PUSH_MSR_AND_ENABLE_EXC; /* Exceptions enabled here. This will allow nested exceptions */
mfs r3, resr;
andi r5, r3, ESR_EXC_MASK; /* Extract ESR[EXC] */
#ifndef NO_UNALIGNED_EXCEPTIONS
xori r6, r5, 1; /* 00001 = Unaligned Exception */
bnei r6, handle_ex_regular;
la r4, r0, MB_ExceptionVectorTable; /* Check if user has registered an unaligned exception handler */
lwi r4, r4, 8;
la r6, r0, XNullHandler; /* If exceptionvectortable entry is still XNullHandler, use */
xor r6, r4, r6; /* the default exception handler */
beqi r6, handle_unaligned_ex ;
handle_ex_regular:
#endif /* ! NO_UNALIGNED_EXCEPTIONS */
#if defined (MICROBLAZE_FP_EXCEPTION_ENABLED) && defined (MICROBLAZE_FP_EXCEPTION_DECODE)
xori r6, r5, 6; /* 00110 = FPU exception */
beqi r6, handle_fp_ex; /* Go and decode the FP exception */
#endif /* defined (MICROBLAZE_FP_EXCEPTION_ENABLED) && defined (MICROBLAZE_FP_EXCEPTION_DECODE) */
handle_other_ex: /* Handle Other exceptions here */
ori r6, r0, 20;
cmp r6, r5, r6; /* >= 20 are exceptions we do not handle. */
blei r6, ex_handler_unhandled;
ori r6, r0, 7;
cmp r6, r5, r6; /* Convert MMU exception indices into an ordinal of 7 */
bgti r6, handle_other_ex_tail;
ori r5, r0, 0x7;
handle_other_ex_tail:
PUSH_REG(7); /* Save other volatiles before we make procedure calls below */
PUSH_REG(8);
PUSH_REG(9);
PUSH_REG(10);
PUSH_REG(11);
PUSH_REG(12);
PUSH_REG(15);
PUSH_REG(18);
la r4, r0, MB_ExceptionVectorTable; /* Load the Exception vector table base address */
addk r7, r5, r5; /* Calculate exception vector offset = r5 * 8 */
addk r7, r7, r7;
addk r7, r7, r7;
addk r7, r7, r4; /* Get pointer to exception vector */
lwi r5, r7, 4; /* Load argument to exception handler from table */
lw r7, r7, r0; /* Load vector itself here */
brald r15, r7; /* Branch to handler */
nop;
POP_REG(7); /* Restore other volatiles */
POP_REG(8);
POP_REG(9);
POP_REG(10);
POP_REG(11);
POP_REG(12);
POP_REG(15);
POP_REG(18);
bri ex_handler_done; /* Complete exception handling */
#ifndef NO_UNALIGNED_EXCEPTIONS
handle_unaligned_ex:
andi r6, r3, ESR_REG_MASK; /* Mask and extract the register operand */
srl r6, r6; /* r6 >> 5 */
srl r6, r6;
srl r6, r6;
srl r6, r6;
srl r6, r6;
sbi r6, r0, ex_reg_op; /* Store the register operand in a temporary location */
mfs r4, rear;
andi r6, r3, ESR_LW_SW_MASK; /* Extract ESR[S] */
bnei r6, ex_sw;
ex_lw:
andi r6, r3, ESR_WORD_MASK; /* Extract ESR[W] */
beqi r6, ex_lhw;
lbui r5, r4, 0; /* Exception address in r4 */
sbi r5, r0, ex_tmp_data_loc_0; /* Load a word, byte-by-byte from destination address and save it in tmp space */
lbui r5, r4, 1;
sbi r5, r0, ex_tmp_data_loc_1;
lbui r5, r4, 2;
sbi r5, r0, ex_tmp_data_loc_2;
lbui r5, r4, 3;
sbi r5, r0, ex_tmp_data_loc_3;
lwi r3, r0, ex_tmp_data_loc_0; /* Get the destination register value into r3 */
bri ex_lw_tail;
ex_lhw:
lbui r5, r4, 0; /* Exception address in r4 */
sbi r5, r0, ex_tmp_data_loc_0; /* Load a half-word, byte-by-byte from destination address and save it in tmp space */
lbui r5, r4, 1;
sbi r5, r0, ex_tmp_data_loc_1;
lhui r3, r0, ex_tmp_data_loc_0; /* Get the destination register value into r3 */
ex_lw_tail:
lbui r5, r0, ex_reg_op; /* Get the destination register number into r5 */
la r6, r0, lw_table; /* Form load_word jump table offset (lw_table + (8 * regnum)) */
addk r5, r5, r5;
addk r5, r5, r5;
addk r5, r5, r5;
addk r5, r5, r6;
bra r5;
ex_lw_end: /* Exception handling of load word, ends */
ex_sw:
lbui r5, r0, ex_reg_op; /* Get the destination register number into r5 */
la r6, r0, sw_table; /* Form store_word jump table offset (sw_table + (8 * regnum)) */
add r5, r5, r5;
add r5, r5, r5;
add r5, r5, r5;
add r5, r5, r6;
bra r5;
ex_sw_tail:
mfs r6, resr;
andi r6, r6, ESR_WORD_MASK; /* Extract ESR[W] */
beqi r6, ex_shw;
swi r3, r0, ex_tmp_data_loc_0;
lbui r3, r0, ex_tmp_data_loc_0; /* Store the word, byte-by-byte into destination address */
sbi r3, r4, 0;
lbui r3, r0, ex_tmp_data_loc_1;
sbi r3, r4, 1;
lbui r3, r0, ex_tmp_data_loc_2;
sbi r3, r4, 2;
lbui r3, r0, ex_tmp_data_loc_3;
sbi r3, r4, 3;
bri ex_handler_done;
ex_shw:
swi r3, r0, ex_tmp_data_loc_0; /* Store the lower half-word, byte-by-byte into destination address */
#ifdef __LITTLE_ENDIAN__
lbui r3, r0, ex_tmp_data_loc_0;
#else
lbui r3, r0, ex_tmp_data_loc_2;
#endif
sbi r3, r4, 0;
#ifdef __LITTLE_ENDIAN__
lbui r3, r0, ex_tmp_data_loc_1;
#else
lbui r3, r0, ex_tmp_data_loc_3;
#endif
sbi r3, r4, 1;
ex_sw_end: /* Exception handling of store word, ends. */
bri ex_handler_done;
#endif /* !NO_UNALIGNED_EXCEPTIONS */
#if defined (MICROBLAZE_FP_EXCEPTION_ENABLED) && defined (MICROBLAZE_FP_EXCEPTION_DECODE)
handle_fp_ex:
addik r3, r17, -4; /* r17 contains (addr of exception causing FP instruction + 4) */
lw r4, r0, r3; /* We might find ourselves in a spot here. Unguaranteed load */
handle_fp_ex_opb:
la r6, r0, fp_table_opb; /* Decode opB and store its value in mb_fpex_op_b */
srl r4, r4;
srl r4, r4;
srl r4, r4;
srl r4, r4;
srl r4, r4;
srl r4, r4;
srl r4, r4;
srl r4, r4;
srl r4, r4;
srl r4, r4;
srl r4, r4;
andi r3, r4, 0x1F;
add r3, r3, r3; /* Calculate (fp_table_opb + (regno * 12)) in r5 */
add r3, r3, r3;
add r5, r3, r3;
add r5, r5, r3;
add r5, r5, r6;
bra r5;
handle_fp_ex_opa:
la r6, r0, fp_table_opa; /* Decode opA and store its value in mb_fpex_op_a */
srl r4, r4;
srl r4, r4;
srl r4, r4;
srl r4, r4;
srl r4, r4;
andi r3, r4, 0x1F;
add r3, r3, r3; /* Calculate (fp_table_opb + (regno * 12)) in r5 */
add r3, r3, r3;
add r5, r3, r3;
add r5, r5, r3;
add r5, r5, r6;
bra r5;
handle_fp_ex_done:
ori r5, r0, 6; /* Set exception number back to 6 */
bri handle_other_ex_tail;
fp_ex_unhandled:
bri 0;
#endif /* defined (MICROBLAZE_FP_EXCEPTION_ENABLED) && defined (MICROBLAZE_FP_EXCEPTION_DECODE) */
ex_handler_done:
POP_R17;
POP_MSR;
POP_REG(3);
POP_REG(4);
POP_REG(5);
POP_REG(6);
rted r17, 0
addik r1, r1, (EX_HANDLER_STACK_SIZ); /* Restore stack frame */
ex_handler_unhandled:
bri 0 /* UNHANDLED. TRAP HERE */
.end _hw_exception_handler
#ifndef NO_UNALIGNED_EXCEPTIONS
/*
* hw_exception_handler Jump Table
* - Contains code snippets for each register that caused the unaligned exception.
* - Hence exception handler is NOT self-modifying
* - Separate table for load exceptions and store exceptions.
* - Each table is of size: (8 * 32) = 256 bytes
*/
.section .text
.align 4
lw_table:
lw_r0: R3_TO_LWREG (0);
lw_r1: LWREG_NOP;
lw_r2: R3_TO_LWREG (2);
lw_r3: R3_TO_LWREG_V (3);
lw_r4: R3_TO_LWREG_V (4);
lw_r5: R3_TO_LWREG_V (5);
lw_r6: R3_TO_LWREG_V (6);
lw_r7: R3_TO_LWREG (7);
lw_r8: R3_TO_LWREG (8);
lw_r9: R3_TO_LWREG (9);
lw_r10: R3_TO_LWREG (10);
lw_r11: R3_TO_LWREG (11);
lw_r12: R3_TO_LWREG (12);
lw_r13: R3_TO_LWREG (13);
lw_r14: R3_TO_LWREG (14);
lw_r15: R3_TO_LWREG (15);
lw_r16: R3_TO_LWREG (16);
lw_r17: LWREG_NOP;
lw_r18: R3_TO_LWREG (18);
lw_r19: R3_TO_LWREG (19);
lw_r20: R3_TO_LWREG (20);
lw_r21: R3_TO_LWREG (21);
lw_r22: R3_TO_LWREG (22);
lw_r23: R3_TO_LWREG (23);
lw_r24: R3_TO_LWREG (24);
lw_r25: R3_TO_LWREG (25);
lw_r26: R3_TO_LWREG (26);
lw_r27: R3_TO_LWREG (27);
lw_r28: R3_TO_LWREG (28);
lw_r29: R3_TO_LWREG (29);
lw_r30: R3_TO_LWREG (30);
lw_r31: R3_TO_LWREG (31);
sw_table:
sw_r0: SWREG_TO_R3 (0);
sw_r1: SWREG_NOP;
sw_r2: SWREG_TO_R3 (2);
sw_r3: SWREG_TO_R3_V (3);
sw_r4: SWREG_TO_R3_V (4);
sw_r5: SWREG_TO_R3_V (5);
sw_r6: SWREG_TO_R3_V (6);
sw_r7: SWREG_TO_R3 (7);
sw_r8: SWREG_TO_R3 (8);
sw_r9: SWREG_TO_R3 (9);
sw_r10: SWREG_TO_R3 (10);
sw_r11: SWREG_TO_R3 (11);
sw_r12: SWREG_TO_R3 (12);
sw_r13: SWREG_TO_R3 (13);
sw_r14: SWREG_TO_R3 (14);
sw_r15: SWREG_TO_R3 (15);
sw_r16: SWREG_TO_R3 (16);
sw_r17: SWREG_NOP;
sw_r18: SWREG_TO_R3 (18);
sw_r19: SWREG_TO_R3 (19);
sw_r20: SWREG_TO_R3 (20);
sw_r21: SWREG_TO_R3 (21);
sw_r22: SWREG_TO_R3 (22);
sw_r23: SWREG_TO_R3 (23);
sw_r24: SWREG_TO_R3 (24);
sw_r25: SWREG_TO_R3 (25);
sw_r26: SWREG_TO_R3 (26);
sw_r27: SWREG_TO_R3 (27);
sw_r28: SWREG_TO_R3 (28);
sw_r29: SWREG_TO_R3 (29);
sw_r30: SWREG_TO_R3 (30);
sw_r31: SWREG_TO_R3 (31);
/* Temporary data structures used in the handler */
.section .data
.align 2
ex_tmp_data_loc_0:
.byte 0
ex_tmp_data_loc_1:
.byte 0
ex_tmp_data_loc_2:
.byte 0
ex_tmp_data_loc_3:
.byte 0
ex_reg_op:
.byte 0
#endif /* ! NO_UNALIGNED_EXCEPTIONS */
#if defined (MICROBLAZE_FP_EXCEPTION_ENABLED) && defined (MICROBLAZE_FP_EXCEPTION_DECODE)
/*
* FP exception decode jump table.
* - Contains code snippets for each register that could have been a source operand for an excepting FP instruction
* - Hence exception handler is NOT self-modifying
* - Separate table for opA and opB
* - Each table is of size: (12 * 32) = 384 bytes
*/
.section .text
.align 4
fp_table_opa:
opa_r0: FP_EX_OPA_SAVE (0);
opa_r1: FP_EX_UNHANDLED;
opa_r2: FP_EX_OPA_SAVE (2);
opa_r3: FP_EX_OPA_SAVE_V (3);
opa_r4: FP_EX_OPA_SAVE_V (4);
opa_r5: FP_EX_OPA_SAVE_V (5);
opa_r6: FP_EX_OPA_SAVE_V (6);
opa_r7: FP_EX_OPA_SAVE (7);
opa_r8: FP_EX_OPA_SAVE (8);
opa_r9: FP_EX_OPA_SAVE (9);
opa_r10: FP_EX_OPA_SAVE (10);
opa_r11: FP_EX_OPA_SAVE (11);
opa_r12: FP_EX_OPA_SAVE (12);
opa_r13: FP_EX_OPA_SAVE (13);
opa_r14: FP_EX_UNHANDLED;
opa_r15: FP_EX_UNHANDLED;
opa_r16: FP_EX_UNHANDLED;
opa_r17: FP_EX_UNHANDLED;
opa_r18: FP_EX_OPA_SAVE (18);
opa_r19: FP_EX_OPA_SAVE (19);
opa_r20: FP_EX_OPA_SAVE (20);
opa_r21: FP_EX_OPA_SAVE (21);
opa_r22: FP_EX_OPA_SAVE (22);
opa_r23: FP_EX_OPA_SAVE (23);
opa_r24: FP_EX_OPA_SAVE (24);
opa_r25: FP_EX_OPA_SAVE (25);
opa_r26: FP_EX_OPA_SAVE (26);
opa_r27: FP_EX_OPA_SAVE (27);
opa_r28: FP_EX_OPA_SAVE (28);
opa_r29: FP_EX_OPA_SAVE (29);
opa_r30: FP_EX_OPA_SAVE (30);
opa_r31: FP_EX_OPA_SAVE (31);
fp_table_opb:
opb_r0: FP_EX_OPB_SAVE (0);
opb_r1: FP_EX_UNHANDLED;
opb_r2: FP_EX_OPB_SAVE (2);
opb_r3: FP_EX_OPB_SAVE_V (3);
opb_r4: FP_EX_OPB_SAVE_V (4);
opb_r5: FP_EX_OPB_SAVE_V (5);
opb_r6: FP_EX_OPB_SAVE_V (6);
opb_r7: FP_EX_OPB_SAVE (7);
opb_r8: FP_EX_OPB_SAVE (8);
opb_r9: FP_EX_OPB_SAVE (9);
opb_r10: FP_EX_OPB_SAVE (10);
opb_r11: FP_EX_OPB_SAVE (11);
opb_r12: FP_EX_OPB_SAVE (12);
opb_r13: FP_EX_OPB_SAVE (13);
opb_r14: FP_EX_UNHANDLED;
opb_r15: FP_EX_UNHANDLED;
opb_r16: FP_EX_UNHANDLED;
opb_r17: FP_EX_UNHANDLED;
opb_r18: FP_EX_OPB_SAVE (18);
opb_r19: FP_EX_OPB_SAVE (19);
opb_r20: FP_EX_OPB_SAVE (20);
opb_r21: FP_EX_OPB_SAVE (21);
opb_r22: FP_EX_OPB_SAVE (22);
opb_r23: FP_EX_OPB_SAVE (23);
opb_r24: FP_EX_OPB_SAVE (24);
opb_r25: FP_EX_OPB_SAVE (25);
opb_r26: FP_EX_OPB_SAVE (26);
opb_r27: FP_EX_OPB_SAVE (27);
opb_r28: FP_EX_OPB_SAVE (28);
opb_r29: FP_EX_OPB_SAVE (29);
opb_r30: FP_EX_OPB_SAVE (30);
opb_r31: FP_EX_OPB_SAVE (31);
#endif /* defined (MICROBLAZE_FP_EXCEPTION_ENABLED) && defined (MICROBLAZE_FP_EXCEPTION_DECODE) */
#if defined(MICROBLAZE_FP_EXCEPTION_ENABLED) && defined(MICROBLAZE_FP_EXCEPTION_DECODE)
/* This is where we store the opA and opB of the last excepting FP instruction */
.section .data
.align 2
.global mb_fpex_op_a
.global mb_fpex_op_b
mb_fpex_op_a:
.long 0
mb_fpex_op_b:
.long 0
#endif /* defined (MICROBLAZE_FP_EXCEPTION_ENABLED) && defined (MICROBLAZE_FP_EXCEPTION_DECODE) */
#if defined(XPAR_MICROBLAZE_USE_STACK_PROTECTION) && (XPAR_MICROBLAZE_USE_STACK_PROTECTION == 1)
/* This is where we store the register used to check which exception occurred */
.section .data
.align 2
mb_sp_save_r3:
.long 0
#endif /* defined(XPAR_MICROBLAZE_USE_STACK_PROTECTION) && (XPAR_MICROBLAZE_USE_STACK_PROTECTION == 1) */
/* The exception vector table */
.section .data
.align 2
.global MB_ExceptionVectorTable
MB_ExceptionVectorTable:
.long XNullHandler
.long 0 /* -- FSL Exception -- */
.long XNullHandler
.long 1 /* -- Unaligned Access Exception -- */
.long XNullHandler
.long 2 /* -- Illegal Opcode Exception -- */
.long XNullHandler
.long 3 /* -- Instruction Bus Exception -- */
.long XNullHandler
.long 4 /* -- Data Bus Exception -- */
.long XNullHandler
.long 5 /* -- Div-by-0 Exception -- */
.long XNullHandler
.long 6 /* -- FPU Exception -- */
.long XNullHandler
.long 7 /* -- MMU Exceptions -- */
#else /* Dummy exception handler, in case exceptions are not present in the processor */
.global _hw_exception_handler
.section .text
.align 2
.ent _hw_exception_handler
_hw_exception_handler:
bri 0;
.end _hw_exception_handler
#endif /* MICROBLAZE_EXCEPTIONS_ENABLED */

14
software/LED_Controller_bsp/microblaze_mcs/libsrc/standalone_v3_11_a/src/inbyte.c Normal file
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#include "xparameters.h"
#include "xiomodule_l.h"
#ifdef __cplusplus
extern "C" {
#endif
char inbyte(void);
#ifdef __cplusplus
}
#endif
char inbyte(void) {
return XIOModule_RecvByte(STDIN_BASEADDRESS);
}

361
software/LED_Controller_bsp/microblaze_mcs/libsrc/standalone_v3_11_a/src/mb_interface.h Executable file
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////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2004-2012 Xilinx, Inc. All rights reserved.
//
// Xilinx, Inc.
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
// AND FITNESS FOR A PARTICULAR PURPOSE.
//
//
// Summary:
// Header file for mb_interface
//
//
////////////////////////////////////////////////////////////////////////////////
#ifndef _MICROBLAZE_INTERFACE_H_
#define _MICROBLAZE_INTERFACE_H_
#include "xbasic_types.h"
#ifdef __cplusplus
extern "C" {
#endif
extern void microblaze_enable_interrupts(void); /* Enable Interrupts */
extern void microblaze_disable_interrupts(void); /* Disable Interrupts */
extern void microblaze_enable_icache(void); /* Enable Instruction Cache */
extern void microblaze_disable_icache(void); /* Disable Instruction Cache */
extern void microblaze_enable_dcache(void); /* Enable Instruction Cache */
extern void microblaze_disable_dcache(void); /* Disable Instruction Cache */
extern void microblaze_enable_exceptions(void); /* Enable hardware exceptions */
extern void microblaze_disable_exceptions(void); /* Disable hardware exceptions */
extern void microblaze_register_handler(XInterruptHandler Handler, void *DataPtr); /* Register top level interrupt handler */
extern void microblaze_register_exception_handler(Xuint8 ExceptionId, XExceptionHandler Handler, void *DataPtr); /* Register exception handler */
extern void microblaze_invalidate_icache(void); /* Invalidate the entire icache */
extern void microblaze_invalidate_dcache(void); /* Invalidate the entire dcache */
extern void microblaze_flush_dcache(void); /* Flush the whole dcache */
extern void microblaze_invalidate_icache_range(unsigned int cacheaddr, unsigned int len); /* Invalidate a part of the icache */
extern void microblaze_invalidate_dcache_range(unsigned int cacheaddr, unsigned int len); /* Invalidate a part of the dcache */
extern void microblaze_flush_dcache_range(unsigned int cacheaddr, unsigned int len); /* Flush a part of the dcache */
extern void microblaze_scrub(void); /* Scrub LMB and internal BRAM */
/* Deprecated */
extern void microblaze_update_icache (int , int , int ) __attribute__((deprecated));
extern void microblaze_init_icache_range (int , int ) __attribute__((deprecated));
extern void microblaze_update_dcache (int , int , int ) __attribute__((deprecated));
extern void microblaze_init_dcache_range (int , int ) __attribute__((deprecated));
/* necessary for pre-processor */
#define stringify(s) tostring(s)
#define tostring(s) #s
/* FSL Access Macros */
/* Blocking Data Read and Write to FSL no. id */
#define getfsl(val, id) asm volatile ("get\t%0,rfsl" stringify(id) : "=d" (val))
#define putfsl(val, id) asm volatile ("put\t%0,rfsl" stringify(id) :: "d" (val))
/* Non-blocking Data Read and Write to FSL no. id */
#define ngetfsl(val, id) asm volatile ("nget\t%0,rfsl" stringify(id) : "=d" (val))
#define nputfsl(val, id) asm volatile ("nput\t%0,rfsl" stringify(id) :: "d" (val))
/* Blocking Control Read and Write to FSL no. id */
#define cgetfsl(val, id) asm volatile ("cget\t%0,rfsl" stringify(id) : "=d" (val))
#define cputfsl(val, id) asm volatile ("cput\t%0,rfsl" stringify(id) :: "d" (val))
/* Non-blocking Control Read and Write to FSL no. id */
#define ncgetfsl(val, id) asm volatile ("ncget\t%0,rfsl" stringify(id) : "=d" (val))
#define ncputfsl(val, id) asm volatile ("ncput\t%0,rfsl" stringify(id) :: "d" (val))
/* Polling versions of FSL access macros. This makes the FSL access interruptible */
#define getfsl_interruptible(val, id) asm volatile ("\n1:\n\tnget\t%0,rfsl" stringify(id) "\n\t" \
"addic\tr18,r0,0\n\t" \
"bnei\tr18,1b\n" \
: "=d" (val) :: "r18")
#define putfsl_interruptible(val, id) asm volatile ("\n1:\n\tnput\t%0,rfsl" stringify(id) "\n\t" \
"addic\tr18,r0,0\n\t" \
"bnei\tr18,1b\n" \
:: "d" (val) : "r18")
#define cgetfsl_interruptible(val, id) asm volatile ("\n1:\n\tncget\t%0,rfsl" stringify(id) "\n\t" \
"addic\tr18,r0,0\n\t" \
"bnei\tr18,1b\n" \
: "=d" (val) :: "r18")
#define cputfsl_interruptible(val, id) asm volatile ("\n1:\n\tncput\t%0,rfsl" stringify(id) "\n\t" \
"addic\tr18,r0,0\n\t" \
"bnei\tr18,1b\n" \
:: "d" (val) : "r18")
/* FSL valid and error check macros. */
#define fsl_isinvalid(result) asm volatile ("addic\t%0,r0,0" : "=d" (result))
#define fsl_iserror(error) asm volatile ("mfs\t%0,rmsr\n\t" \
"andi\t%0,%0,0x10" : "=d" (error))
/* Pseudo assembler instructions */
#define clz(v) ({ unsigned int _rval; \
__asm__ __volatile__ ( \
"clz\t%0,%1\n" : "=d"(_rval): "d" (v) \
); \
_rval; \
})
#define mbar(mask) ({ __asm__ __volatile__ ("mbar\t" stringify(mask) ); })
#define mb_sleep() ({ __asm__ __volatile__ ("sleep\t"); })
#define mb_swapb(v) ({ unsigned int _rval; \
__asm__ __volatile__ ( \
"swapb\t%0,%1\n" : "=d"(_rval) : "d" (v) \
); \
_rval; \
})
#define mb_swaph(v) ({ unsigned int _rval; \
__asm__ __volatile__ ( \
"swaph\t%0,%1\n" : "=d"(_rval) : "d" (v) \
); \
_rval; \
})
#define mfgpr(rn) ({ unsigned int _rval; \
__asm__ __volatile__ ( \
"or\t%0,r0," stringify(rn) "\n" : "=d"(_rval) \
); \
_rval; \
})
#define mfmsr() ({ unsigned int _rval; \
__asm__ __volatile__ ( \
"mfs\t%0,rmsr\n" : "=d"(_rval) \
); \
_rval; \
})
#define mfear() ({ unsigned int _rval; \
__asm__ __volatile__ ( \
"mfs\t%0,rear\n" : "=d"(_rval) \
); \
_rval; \
})
#define mfesr() ({ unsigned int _rval; \
__asm__ __volatile__ ( \
"mfs\t%0,resr\n" : "=d"(_rval) \
); \
_rval; \
})
#define mffsr() ({ unsigned int _rval; \
__asm__ __volatile__ ( \
"mfs\t%0,rfsr\n" : "=d"(_rval) \
); \
_rval; \
})
#define mfpvr(rn) ({ unsigned int _rval; \
__asm__ __volatile__ ( \
"mfs\t%0,rpvr" stringify(rn) "\n" : "=d"(_rval) \
); \
_rval; \
})
#define mfbtr() ({ unsigned int _rval; \
__asm__ __volatile__ ( \
"mfs\t%0,rbtr\n" : "=d"(_rval) \
); \
_rval; \
})
#define mfedr() ({ unsigned int _rval; \
__asm__ __volatile__ ( \
"mfs\t%0,redr\n" : "=d"(_rval) \
); \
_rval; \
})
#define mfpid() ({ unsigned int _rval; \
__asm__ __volatile__ ( \
"mfs\t%0,rpid\n" : "=d"(_rval)\
); \
_rval; \
})
#define mfzpr() ({ unsigned int _rval; \
__asm__ __volatile__ ( \
"mfs\t%0,rzpr\n" : "=d"(_rval) \
); \
_rval; \
})
#define mftlbx() ({ unsigned int _rval; \
__asm__ __volatile__ ( \
"mfs\t%0,rtlbx\n" : "=d"(_rval) \
); \
_rval; \
})
#define mftlblo() ({ unsigned int _rval; \
__asm__ __volatile__ ( \
"mfs\t%0,rtlblo\n" : "=d"(_rval) \
); \
_rval; \
})
#define mftlbhi() ({ unsigned int _rval; \
__asm__ __volatile__ ( \
"mfs\t%0,rtlbhi\n" : "=d"(_rval) \
); \
_rval; \
})
#define mfslr() ({ unsigned int _rval; \
__asm__ __volatile__ ( \
"mfs\t%0,rslr\n" : "=d"(_rval) \
); \
_rval; \
})
#define mfshr() ({ unsigned int _rval; \
__asm__ __volatile__ ( \
"mfs\t%0,rshr\n" : "=d"(_rval) \
); \
_rval; \
})
#define mtgpr(rn, v) ({ __asm__ __volatile__ ( \
"or\t" stringify(rn) ",r0,%0\n" :: "d" (v) \
); \
})
#define mtmsr(v) ({ __asm__ __volatile__ ( \
"mts\trmsr,%0\n\tnop\n" :: "d" (v) \
); \
})
#define mtfsr(v) ({ __asm__ __volatile__ ( \
"mts\trfsr,%0\n\tnop\n" :: "d" (v) \
); \
})
#define mtpid(v) ({ __asm__ __volatile__ ( \
"mts\trpid,%0\n\tnop\n" :: "d" (v) \
); \
})
#define mtzpr(v) ({ __asm__ __volatile__ ( \
"mts\trzpr,%0\n\tnop\n" :: "d" (v) \
); \
})
#define mttlbx(v) ({ __asm__ __volatile__ ( \
"mts\trtlbx,%0\n\tnop\n" :: "d" (v) \
); \
})
#define mttlblo(v) ({ __asm__ __volatile__ ( \
"mts\trtlblo,%0\n\tnop\n" :: "d" (v) \
); \
})
#define mttlbhi(v) ({ __asm__ __volatile__ ( \
"mts\trtlbhi,%0\n\tnop\n" :: "d" (v) \
); \
})
#define mttlbsx(v) ({ __asm__ __volatile__ ( \
"mts\trtlbsx,%0\n\tnop\n" :: "d" (v) \
); \
})
#define mtslr(v) ({ __asm__ __volatile__ ( \
"mts\trslr,%0\n\tnop\n" :: "d" (v) \
); \
})
#define mtshr(v) ({ __asm__ __volatile__ ( \
"mts\trshr,%0\n\tnop\n" :: "d" (v) \
); \
})
#define lwx(address) ({ unsigned int _rval; \
__asm__ __volatile__ ( \
"lwx\t%0,%1,r0\n" : "=d"(_rval) : "d" (address) \
); \
_rval; \
})
#define lwr(address) ({ unsigned int _rval; \
__asm__ __volatile__ ( \
"lwr\t%0,%1,r0\n" : "=d"(_rval) : "d" (address) \
); \
_rval; \
})
#define lhur(address) ({ unsigned int _rval; \
__asm__ __volatile__ ( \
"lhur\t%0,%1,r0\n" : "=d"(_rval) : "d" (address) \
); \
_rval; \
})
#define lbur(address) ({ unsigned int _rval; \
__asm__ __volatile__ ( \
"lbur\t%0,%1,r0\n" : "=d"(_rval) : "d" (address) \
); \
_rval; \
})
#define swx(address, data) ({ __asm__ __volatile__ ( \
"swx\t%0,%1,r0\n" :: "d" (data), "d" (address) \
); \
})
#define swr(address, data) ({ __asm__ __volatile__ ( \
"swr\t%0,%1,r0\n" :: "d" (data), "d" (address) \
); \
})
#define shr(address, data) ({ __asm__ __volatile__ ( \
"shr\t%0,%1,r0\n" :: "d" (data), "d" (address) \
); \
})
#define sbr(address, data) ({ __asm__ __volatile__ ( \
"sbr\t%0,%1,r0\n" :: "d" (data), "d" (address) \
); \
})
#define microblaze_getfpex_operand_a() ({ \
extern unsigned int mb_fpex_op_a; \
mb_fpex_op_a; \
})
#define microblaze_getfpex_operand_b() ({ \
extern unsigned int mb_fpex_op_b; \
mb_fpex_op_b; \
})
/* Deprecated MicroBlaze FSL macros */
#define microblaze_bread_datafsl(val, id) getfsl(val,id)
#define microblaze_bwrite_datafsl(val, id) putfsl(val,id)
#define microblaze_nbread_datafsl(val, id) ngetfsl(val,id)
#define microblaze_nbwrite_datafsl(val, id) nputfsl(val,id)
#define microblaze_bread_cntlfsl(val, id) cgetfsl(val,id)
#define microblaze_bwrite_cntlfsl(val, id) cputfsl(val,id)
#define microblaze_nbread_cntlfsl(val, id) ncgetfsl(val,id)
#define microblaze_nbwrite_cntlfsl(val, id) ncputfsl(val,id)
#ifdef __cplusplus
}
#endif
#endif // _MICROBLAZE_INTERFACE_H_

53
software/LED_Controller_bsp/microblaze_mcs/libsrc/standalone_v3_11_a/src/microblaze_disable_dcache.S Executable file
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/******************************************************************************
* Copyright (c) 2008-2013 Xilinx, Inc. All rights reserved.
*
* Xilinx, Inc.
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
* COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
* ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
* STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
* IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
* FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
* XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
* THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
* ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
* FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
* AND FITNESS FOR A PARTICULAR PURPOSE.
*
* File : microblaze_disable_dcache.s
* Date : 2002, March 20.
* Company: Xilinx
* Group : Emerging Software Technologies
*
* Summary:
* Disable the L1 dcache on the microblaze.
*
*******************************************************************************/
#include "xparameters.h"
.text
.globl microblaze_disable_dcache
.ent microblaze_disable_dcache
.align 2
microblaze_disable_dcache:
addik r1, r1, -28
#if XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK != 0
swi r15, r1, 0
brlid r15, microblaze_flush_dcache
nop
#endif
mfs r11, rmsr
andi r11, r11, ~128
mts rmsr, r11
#if XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK != 0
lwi r15, r1, 0
#endif
rtsd r15, 8
addi r1, r1, 28
.end microblaze_disable_dcache

37
software/LED_Controller_bsp/microblaze_mcs/libsrc/standalone_v3_11_a/src/microblaze_disable_exceptions.s Executable file
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##############################################################-*-asm-*-
#
# Copyright (c) 2004 Xilinx, Inc. All rights reserved.
#
# Xilinx, Inc.
# XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
# COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
# ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
# STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
# IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
# FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
# XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
# THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
# ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
# FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
# AND FITNESS FOR A PARTICULAR PURPOSE.
#
# Disable exceptions on microblaze.
#
# $Id: microblaze_disable_exceptions.s,v 1.1.2.1 2011/05/17 04:37:26 sadanan Exp $
#
####################################################################
.section .text
.globl microblaze_disable_exceptions
.ent microblaze_disable_exceptions
.align 2
microblaze_disable_exceptions:
mfs r4, rmsr;
andi r4, r4, ~(0x100); /* Turn OFF the EE bit */
mts rmsr, r4;
rtsd r15, 8;
nop;
.end microblaze_disable_exceptions

49
software/LED_Controller_bsp/microblaze_mcs/libsrc/standalone_v3_11_a/src/microblaze_disable_icache.s Executable file
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######################################################################
# Copyright (c) 2004 Xilinx, Inc. All rights reserved.
#
# Xilinx, Inc.
# XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
# COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
# ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
# STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
# IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
# FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
# XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
# THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
# ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
# FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
# AND FITNESS FOR A PARTICULAR PURPOSE.
#
# File : microblaze_disable_icache.s
# Date : 2002, March 20.
# Company: Xilinx
# Group : Emerging Software Technologies
#
# Summary:
# Disable L1 icache on the microblaze.
#
# $Id: microblaze_disable_icache.s,v 1.1.2.1 2011/05/17 04:37:27 sadanan Exp $
#
####################################################################
.text
.globl microblaze_disable_icache
.ent microblaze_disable_icache
.align 2
microblaze_disable_icache:
#Make space on stack for a temporary
addi r1, r1, -4
#Read the MSR register
mfs r8, rmsr
#Clear the icache enable bit
andi r8, r8, ~32
#Save the MSR register
mts rmsr, r8
#Return
rtsd r15, 8
#Update stack in the delay slot
addi r1, r1, 4
.end microblaze_disable_icache

53
software/LED_Controller_bsp/microblaze_mcs/libsrc/standalone_v3_11_a/src/microblaze_disable_interrupts.s Executable file
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######################################################################
# Copyright (c) 2004 Xilinx, Inc. All rights reserved.
#
# Xilinx, Inc.
# XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
# COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
# ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
# STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
# IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
# FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
# XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
# THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
# ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
# FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
# AND FITNESS FOR A PARTICULAR PURPOSE.
#
# File : microblaze_disable_interrupts.s
# Date : 2002, March 20.
# Company: Xilinx
# Group : Emerging Software Technologies
#
# Summary:
# Disable interrupts on the microblaze.
#
# $Id: microblaze_disable_interrupts.s,v 1.1.2.1 2011/05/17 04:37:27 sadanan Exp $
#
####################################################################
.text
.globl microblaze_disable_interrupts
.ent microblaze_disable_interrupts
.align 2
microblaze_disable_interrupts:
#Make space on stack for a temporary
addi r1, r1, -4
#Save register r12
swi r12, r1, 0
#Read the MSR register
mfs r12, rmsr
#Clear the interrupt enable bit
andi r12, r12, ~2
#Save the MSR register
mts rmsr, r12
#Load register r12
lwi r12, r1, 0
#Return
rtsd r15, 8
#Update stack in the delay slot
addi r1, r1, 4
.end microblaze_disable_interrupts

49
software/LED_Controller_bsp/microblaze_mcs/libsrc/standalone_v3_11_a/src/microblaze_enable_dcache.s Executable file
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######################################################################
# Copyright (c) 2004 Xilinx, Inc. All rights reserved.
#
# Xilinx, Inc.
# XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
# COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
# ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
# STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
# IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
# FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
# XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
# THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
# ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
# FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
# AND FITNESS FOR A PARTICULAR PURPOSE.
#
# File : microblaze_enable_dcache.s
# Date : 2002, March 20.
# Company: Xilinx
# Group : Emerging Software Technologies
#
# Summary:
# Enable L1 dcache on the microblaze.
#
# $Id: microblaze_enable_dcache.s,v 1.1.2.1 2011/05/17 04:37:27 sadanan Exp $
#
####################################################################
.text
.globl microblaze_enable_dcache
.ent microblaze_enable_dcache
.align 2
microblaze_enable_dcache:
#Make space on stack for a temporary
addi r1, r1, -4
#Read the MSR register
mfs r8, rmsr
#Set the interrupt enable bit
ori r8, r8, 128
#Save the MSR register
mts rmsr, r8
#Return
rtsd r15, 8
#Update stack in the delay slot
addi r1, r1, 4
.end microblaze_enable_dcache

37
software/LED_Controller_bsp/microblaze_mcs/libsrc/standalone_v3_11_a/src/microblaze_enable_exceptions.s Executable file
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##############################################################-*-asm-*-
#
# Copyright (c) 2004 Xilinx, Inc. All rights reserved.
#
# Xilinx, Inc.
# XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
# COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
# ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
# STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
# IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
# FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
# XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
# THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
# ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
# FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
# AND FITNESS FOR A PARTICULAR PURPOSE.
#
# Enable exceptions on microblaze.
#
# $Id: microblaze_enable_exceptions.s,v 1.1.2.1 2011/05/17 04:37:27 sadanan Exp $
#
####################################################################
.section .text
.globl microblaze_enable_exceptions
.ent microblaze_enable_exceptions
.align 2
microblaze_enable_exceptions:
mfs r4, rmsr;
ori r4, r4, 0x100; /* Turn ON the EE bit */
mts rmsr, r4;
rtsd r15, 8;
nop;
.end microblaze_enable_exceptions

49
software/LED_Controller_bsp/microblaze_mcs/libsrc/standalone_v3_11_a/src/microblaze_enable_icache.s Executable file
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######################################################################
# Copyright (c) 2004 Xilinx, Inc. All rights reserved.
#
# Xilinx, Inc.
# XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
# COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
# ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
# STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
# IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
# FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
# XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
# THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
# ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
# FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
# AND FITNESS FOR A PARTICULAR PURPOSE.
#
# File : microblaze_enable_icache.s
# Date : 2002, March 20.
# Company: Xilinx
# Group : Emerging Software Technologies
#
# Summary:
# Enable icache on the microblaze.
#
# $Id: microblaze_enable_icache.s,v 1.1.2.1 2011/05/17 04:37:27 sadanan Exp $
#
####################################################################
.text
.globl microblaze_enable_icache
.ent microblaze_enable_icache
.align 2
microblaze_enable_icache:
#Make space on stack for a temporary
addi r1, r1, -4
#Read the MSR register
mfs r8, rmsr
#Set the interrupt enable bit
ori r8, r8, 32
#Save the MSR register
mts rmsr, r8
#Return
rtsd r15, 8
#Update stack in the delay slot
addi r1, r1, 4
.end microblaze_enable_icache

53
software/LED_Controller_bsp/microblaze_mcs/libsrc/standalone_v3_11_a/src/microblaze_enable_interrupts.s Executable file
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######################################################################
# Copyright (c) 2004 Xilinx, Inc. All rights reserved.
#
# Xilinx, Inc.
# XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
# COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
# ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
# STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
# IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
# FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
# XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
# THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
# ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
# FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
# AND FITNESS FOR A PARTICULAR PURPOSE.
#
# File : microblaze_enable_interrupts.s
# Date : 2002, March 20.
# Company: Xilinx
# Group : Emerging Software Technologies
#
# Summary:
# Enable interrupts on the microblaze.
#
# $Id: microblaze_enable_interrupts.s,v 1.1.2.1 2011/05/17 04:37:28 sadanan Exp $
#
####################################################################
.text
.globl microblaze_enable_interrupts
.ent microblaze_enable_interrupts
.align 2
microblaze_enable_interrupts:
#Make space on stack for a temporary
addi r1, r1, -4
#Save register r12
swi r12, r1, 0
#Read the MSR register
mfs r12, rmsr
#Set the interrupt enable bit
ori r12, r12, 2
#Save the MSR register
mts rmsr, r12
#Load register r12
lwi r12, r1, 0
#Return
rtsd r15, 8
#Update stack in the delay slot
addi r1, r1, 4
.end microblaze_enable_interrupts

84
software/LED_Controller_bsp/microblaze_mcs/libsrc/standalone_v3_11_a/src/microblaze_exception_handler.c Executable file
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////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2004 Xilinx, Inc. All rights reserved.
//
// Xilinx, Inc.
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
// AND FITNESS FOR A PARTICULAR PURPOSE.
//
// $Id: microblaze_exception_handler.c,v 1.1.2.1 2011/05/17 04:37:28 sadanan Exp $
////////////////////////////////////////////////////////////////////////////////
/*****************************************************************************/
/**
*
* @file microblaze_exception_handler.c
*
* This file contains exception handler registration routines for
* the MicroBlaze processor.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Date Changes
* ----- -------- -----------------------------------------------
* 1.00b 06/24/04 First release
* </pre>
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "microblaze_exceptions_i.h"
#include "microblaze_exceptions_g.h"
#ifdef MICROBLAZE_EXCEPTIONS_ENABLED /* If exceptions are enabled in the processor */
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
/************************** Variable Definitions *****************************/
extern MB_ExceptionVectorTableEntry MB_ExceptionVectorTable[];
/****************************************************************************/
/*****************************************************************************/
/**
*
* Registers an exception handler for the MicroBlaze. The
* argument provided in this call as the DataPtr is used as the argument
* for the handler when it is called.
*
* @param ExceptionId is the id of the exception to register this handler
* for.
* @param Top level handler.
* @param DataPtr is a reference to data that will be passed to the handler
* when it gets called.
* @return None.
*
* @note
*
* None.
*
****************************************************************************/
void microblaze_register_exception_handler(Xuint8 ExceptionId, XExceptionHandler Handler, void *DataPtr)
{
MB_ExceptionVectorTable[ExceptionId].Handler = Handler;
MB_ExceptionVectorTable[ExceptionId].CallBackRef = DataPtr;
}
#endif /* MICROBLAZE_EXCEPTIONS_ENABLED */

14
software/LED_Controller_bsp/microblaze_mcs/libsrc/standalone_v3_11_a/src/microblaze_exceptions_g.h Normal file
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/*******************************************************************
*
* CAUTION: This file is automatically generated by libgen.
* Version: Xilinx EDK 14.7 EDK_P.20131013
* DO NOT EDIT.
*
* Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
*
* Description: Exception Handling Header for MicroBlaze Processor
*
*******************************************************************/

73
software/LED_Controller_bsp/microblaze_mcs/libsrc/standalone_v3_11_a/src/microblaze_exceptions_i.h Executable file
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////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2004-2011 Xilinx, Inc. All rights reserved.
//
// Xilinx, Inc.
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
// AND FITNESS FOR A PARTICULAR PURPOSE.
//
// $Id: microblaze_exceptions_i.h,v 1.1.2.1 2011/05/17 04:37:29 sadanan Exp $
////////////////////////////////////////////////////////////////////////////////
/*****************************************************************************/
/**
*
* @file microblaze_exceptions_i.h
*
* This header file contains defines for structures used by the microblaze
* hardware exception handler.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Date Changes
* ----- -------- -----------------------------------------------
* 1.00a 06/24/04 First release
* </pre>
*
******************************************************************************/
#ifndef MICROBLAZE_EXCEPTIONS_I_H /* prevent circular inclusions */
#define MICROBLAZE_EXCEPTIONS_I_H /* by using protection macros */
/***************************** Include Files *********************************/
#include "xbasic_types.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef struct
{
XExceptionHandler Handler;
void *CallBackRef;
} MB_ExceptionVectorTableEntry;
/* Exception IDs */
#define XEXC_ID_FSL 0
#define XEXC_ID_UNALIGNED_ACCESS 1
#define XEXC_ID_ILLEGAL_OPCODE 2
#define XEXC_ID_M_AXI_I_EXCEPTION 3
#define XEXC_ID_IPLB_EXCEPTION 3
#define XEXC_ID_M_AXI_D_EXCEPTION 4
#define XEXC_ID_DPLB_EXCEPTION 4
#define XEXC_ID_DIV_BY_ZERO 5
#define XEXC_ID_FPU 6
#define XEXC_ID_STACK_VIOLATION 7
#define XEXC_ID_MMU 7
void microblaze_register_exception_handler(Xuint8 ExceptionId, XExceptionHandler Handler, void *DataPtr);
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */

51
software/LED_Controller_bsp/microblaze_mcs/libsrc/standalone_v3_11_a/src/microblaze_flush_cache_ext.S Executable file
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/******************************************************************************
* Copyright (c) 2008-2013 Xilinx, Inc. All rights reserved.
*
* Xilinx, Inc.
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
* COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
* ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
* STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
* IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
* FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
* XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
* THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
* ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
* FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
* AND FITNESS FOR A PARTICULAR PURPOSE.
*
* microblaze_flush_cache_ext()
*
* Flush the entire L2 Cache
*
*
*******************************************************************************/
#include "xparameters.h"
#define XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN 16
.text
.globl microblaze_flush_cache_ext
.ent microblaze_flush_cache_ext
.align 2
microblaze_flush_cache_ext:
#if ((XPAR_MICROBLAZE_INTERCONNECT==3) && (XPAR_MICROBLAZE_USE_DCACHE==1))
addik r5, r0, XPAR_MICROBLAZE_DCACHE_BASEADDR & (-(4 * XPAR_MICROBLAZE_DCACHE_LINE_LEN))
addik r6, r0, XPAR_MICROBLAZE_DCACHE_BYTE_SIZE-(4 * XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN)
andi r6, r6, -(4 * XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN)
Loop_start:
wdc.ext.flush r5, r6
bgtid r6,Loop_start
addik r6, r6,-(4 * XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN)
#endif
rtsd r15, 8
nop
.end microblaze_flush_cache_ext

60
software/LED_Controller_bsp/microblaze_mcs/libsrc/standalone_v3_11_a/src/microblaze_flush_cache_ext_range.S Executable file
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/******************************************************************************
* Copyright (c) 2008-2013 Xilinx, Inc. All rights reserved.
*
* Xilinx, Inc.
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
* COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
* ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
* STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
* IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
* FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
* XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
* THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
* ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
* FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
* AND FITNESS FOR A PARTICULAR PURPOSE.
*
* microblaze_flush_cache_ext_range (unsigned int cacheaddr, unsigned int len)
*
*Flush a L2 Cache range
*
*Parameters:
* 'cacheaddr' - address in the L2 cache where the flush begins
* 'len ' - length (in bytes) worth of L2 cache to be flushed
*
*******************************************************************************/
#include "xparameters.h"
#define XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN 16
.text
.globl microblaze_flush_cache_ext_range
.ent microblaze_flush_cache_ext_range
.align 2
microblaze_flush_cache_ext_range:
#if ((XPAR_MICROBLAZE_INTERCONNECT==3) && (XPAR_MICROBLAZE_USE_DCACHE==1))
beqi r6, Loop_done
addik r6, r6, -1
add r6, r5, r6
andi r6, r6, -(4 * XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN)
andi r5, r5, -(4 * XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN)
rsubk r6, r5, r6
Loop_start:
wdc.ext.flush r5, r6
bneid r6, Loop_start
addik r6, r6, -(4 * XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN)
Loop_done:
#endif
rtsd r15, 8
nop
.end microblaze_flush_cache_ext_range

56
software/LED_Controller_bsp/microblaze_mcs/libsrc/standalone_v3_11_a/src/microblaze_flush_dcache.S Executable file
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/******************************************************************************
* Copyright (c) 2008-2013 Xilinx, Inc. All rights reserved.
*
* Xilinx, Inc.
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
* COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
* ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
* STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
* IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
* FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
* XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
* THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
* ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
* FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
* AND FITNESS FOR A PARTICULAR PURPOSE.
*
* microblaze_flush_dcache()
*
* Flush the L1 DCache
*
*******************************************************************************/
#include "xparameters.h"
#define MICROBLAZE_MSR_DCACHE_ENABLE 0x00000080
#define MICROBLAZE_MSR_INTR_ENABLE 0x00000002
#ifndef XPAR_MICROBLAZE_DCACHE_LINE_LEN
#define XPAR_MICROBLAZE_DCACHE_LINE_LEN 1
#endif
.text
.globl microblaze_flush_dcache
.ent microblaze_flush_dcache
.align 2
microblaze_flush_dcache:
addik r5, r0, XPAR_MICROBLAZE_DCACHE_BASEADDR & (-(4 * XPAR_MICROBLAZE_DCACHE_LINE_LEN)) /* Align to cache line */
addik r6, r5, XPAR_MICROBLAZE_DCACHE_BYTE_SIZE & (-(4 * XPAR_MICROBLAZE_DCACHE_LINE_LEN)) /* Compute end */
L_start:
wdc.flush r5, r0 /* Flush the Cache */
cmpu r18, r5, r6 /* Are we at the end? */
blei r18, L_done
brid L_start /* Branch to the beginning of the loop */
addik r5, r5, (XPAR_MICROBLAZE_DCACHE_LINE_LEN * 4) /* Increment the addrees by 4 (delay slot) */
L_done:
rtsd r15, 8 /* Return */
nop
.end microblaze_flush_dcache

94
software/LED_Controller_bsp/microblaze_mcs/libsrc/standalone_v3_11_a/src/microblaze_flush_dcache_range.S Executable file
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/******************************************************************************
* Copyright (c) 2008-2013 Xilinx, Inc. All rights reserved.
*
* Xilinx, Inc.
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
* COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
* ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
* STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
* IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
* FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
* XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
* THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
* ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
* FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
* AND FITNESS FOR A PARTICULAR PURPOSE.
*
* microblaze_flush_dcache_range (unsigned int cacheaddr, unsigned int len)
*
* Flush a L1 DCache range
*
* Parameters:
* 'cacheaddr' - address in the Dcache where the flush begins
* 'len ' - length (in bytes) worth of Dcache to be flushed
*
*******************************************************************************/
#include "xparameters.h"
#define MICROBLAZE_MSR_DCACHE_ENABLE 0x00000080
#define MICROBLAZE_MSR_INTR_ENABLE 0x00000002
#ifndef XPAR_MICROBLAZE_DCACHE_LINE_LEN
#define XPAR_MICROBLAZE_DCACHE_LINE_LEN 1
#endif
#ifndef XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK
#define MB_VERSION_LT_v720
#define MB_HAS_WRITEBACK_SET 0
#else
#define MB_HAS_WRITEBACK_SET XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK
#endif
.text
.globl microblaze_flush_dcache_range
.ent microblaze_flush_dcache_range
.align 2
microblaze_flush_dcache_range:
#ifdef MB_VERSION_LT_v720 /* Disable Dcache and interrupts before invalidating */
mfs r9, rmsr
andi r10, r9, ~(MICROBLAZE_MSR_DCACHE_ENABLE | MICROBLAZE_MSR_INTR_ENABLE)
mts rmsr, r10
#endif
beqi r6, L_done /* Skip loop if size is zero */
add r6, r5, r6 /* Compute end address */
addik r6, r6, -1
andi r6, r6, -(4 * XPAR_MICROBLAZE_DCACHE_LINE_LEN) /* Align end down to cache line */
andi r5, r5, -(4 * XPAR_MICROBLAZE_DCACHE_LINE_LEN) /* Align start down to cache line */
#if MB_HAS_WRITEBACK_SET == 0 /* Use a different scheme for MB version < v7.20 or when caches are write-through */
L_start:
cmpu r18, r5, r6 /* Are we at the end? */
blti r18, L_done
wdc r5, r0 /* Invalidate the cache line */
brid L_start /* Branch to the beginning of the loop */
addik r5, r5, (XPAR_MICROBLAZE_DCACHE_LINE_LEN * 4) /* Increment the addrees by 4 (delay slot) */
#else
rsubk r6, r5, r6
/* r6 will now contain (count of bytes - (4 * XPAR_MICROBLAZE_DCACHE_LINE_LEN)) */
L_start:
wdc.flush r5, r6 /* Flush the cache line */
bneid r6, L_start
addik r6, r6, -(XPAR_MICROBLAZE_DCACHE_LINE_LEN * 4)
#endif
L_done:
rtsd r15, 8
#ifdef MB_VERSION_LT_v720 /* restore MSR only for MB version < v7.20 */
mts rmsr, r9
#else
nop
#endif
.end microblaze_flush_dcache_range

69
software/LED_Controller_bsp/microblaze_mcs/libsrc/standalone_v3_11_a/src/microblaze_init_dcache_range.S Executable file
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/******************************************************************************
* Copyright (c) 2006 Xilinx, Inc. All rights reserved.
*
* Xilinx, Inc.
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
* COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
* ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
* STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
* IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
* FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
* XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
* THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
* ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
* FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
* AND FITNESS FOR A PARTICULAR PURPOSE.
*
* microblaze_init_dcache_range (unsigned int cache_start, unsigned int cache_len)
*
* Invalidate dcache on the microblaze
*
* Parameters:
* 'cache_start' - address in the Dcache where invalidation begins
* 'cache_len' - length (in bytes) worth of Dcache to be invalidated
*
* $Id: microblaze_init_dcache_range.S,v 1.1.2.1 2011/05/17 04:37:29 sadanan Exp $
*
*******************************************************************************/
#include "xparameters.h"
#define MICROBLAZE_MSR_DCACHE_ENABLE 0x00000080
#define MICROBLAZE_MSR_INTR_ENABLE 0x00000002
#ifndef XPAR_MICROBLAZE_DCACHE_LINE_LEN
#define XPAR_MICROBLAZE_DCACHE_LINE_LEN 1
#endif
.text
.globl microblaze_init_dcache_range
.ent microblaze_init_dcache_range
.align 2
microblaze_init_dcache_range:
mfs r9, rmsr /* Disable Dcache and interrupts before invalidating */
andi r10, r9, ~(MICROBLAZE_MSR_DCACHE_ENABLE | MICROBLAZE_MSR_INTR_ENABLE)
mts rmsr, r10
andi r5, r5, -(4 * XPAR_MICROBLAZE_DCACHE_LINE_LEN) /* Align to cache line */
add r6, r5, r6 /* Compute end */
andi r6, r6, -(4 * XPAR_MICROBLAZE_DCACHE_LINE_LEN) /* Align to cache line */
L_start:
wdc r5, r0 /* Invalidate the Cache (delay slot) */
cmpu r18, r5, r6 /* Are we at the end ? */
blei r18, L_done
brid L_start /* Branch to the beginning of the loop */
addik r5, r5, (XPAR_MICROBLAZE_DCACHE_LINE_LEN * 4) /* Increment the addrees by 4 (delay slot) */
L_done:
rtsd r15, 8 /* Return */
mts rmsr, r9
.end microblaze_init_dcache_range

69
software/LED_Controller_bsp/microblaze_mcs/libsrc/standalone_v3_11_a/src/microblaze_init_icache_range.S Executable file
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/******************************************************************************
* Copyright (c) 2006 Xilinx, Inc. All rights reserved.
*
* Xilinx, Inc.
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
* COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
* ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
* STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
* IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
* FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
* XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
* THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
* ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
* FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
* AND FITNESS FOR A PARTICULAR PURPOSE.
*
* microblaze_init_icache_range (unsigned int cache_start, unsigned int cache_len)
*
* Invalidate icache on the microblaze
*
* Parameters:
* 'cache_start' - address in the Icache where invalidation begins
* 'cache_len' - length (in bytes) worth of Icache to be invalidated
*
* $Id: microblaze_init_icache_range.S,v 1.1.2.1 2011/05/17 04:37:30 sadanan Exp $
*
*******************************************************************************/
#include "xparameters.h"
#define MICROBLAZE_MSR_ICACHE_ENABLE 0x00000020
#define MICROBLAZE_MSR_INTR_ENABLE 0x00000002
#ifndef XPAR_MICROBLAZE_ICACHE_LINE_LEN
#define XPAR_MICROBLAZE_ICACHE_LINE_LEN 1
#endif
.text
.globl microblaze_init_icache_range
.ent microblaze_init_icache_range
.align 2
microblaze_init_icache_range:
mfs r9, rmsr /* Disable Icache and interrupts before invalidating */
andi r10, r9, ~(MICROBLAZE_MSR_ICACHE_ENABLE | MICROBLAZE_MSR_INTR_ENABLE)
mts rmsr, r10
andi r5, r5, -(4 * XPAR_MICROBLAZE_ICACHE_LINE_LEN) /* Align to cache line */
add r6, r5, r6 /* Compute end */
andi r6, r6, -(4 * XPAR_MICROBLAZE_ICACHE_LINE_LEN) /* Align to cache line */
L_start:
wic r5, r0 /* Invalidate the Cache (delay slot) */
cmpu r18, r5, r6 /* Are we at the end ? */
blei r18, L_done
brid L_start /* Branch to the beginning of the loop */
addik r5, r5, (XPAR_MICROBLAZE_ICACHE_LINE_LEN * 4) /* Increment the addrees by 4 (delay slot) */
L_done:
rtsd r15, 8 /* Return */
mts rmsr, r9
.end microblaze_init_icache_range

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software/LED_Controller_bsp/microblaze_mcs/libsrc/standalone_v3_11_a/src/microblaze_interrupt_handler.c Executable file
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////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2004-2010 Xilinx, Inc. All rights reserved.
//
// Xilinx, Inc.
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
// AND FITNESS FOR A PARTICULAR PURPOSE.
//
// $Id: microblaze_interrupt_handler.c,v 1.1.2.1 2011/05/17 04:37:30 sadanan Exp $
////////////////////////////////////////////////////////////////////////////////
/*****************************************************************************/
/**
*
* @file microblaze_interrupt_handler.c
*
* This file contains the standard interrupt handler for the MicroBlaze processor.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Date Changes
* ----- -------- -----------------------------------------------
* 1.00b 10/03/03 First release
* </pre>
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "microblaze_interrupts_i.h"
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
void __interrupt_handler (void) __attribute__ ((interrupt_handler));
/************************** Variable Definitions *****************************/
extern MB_InterruptVectorTableEntry MB_InterruptVectorTable;
/*****************************************************************************/
/**
*
* This function is the standard interrupt handler used by the MicroBlaze processor.
* It saves all volatile registers, calls the users top level interrupt handler.
* When this returns, it restores all registers, and returns using a rtid instruction.
*
* @param
*
* None
*
* @return
*
* None.
*
* @note
*
* None.
*
******************************************************************************/
void __interrupt_handler(void)
{
/* The compiler saves all volatiles and the MSR */
MB_InterruptVectorTable.Handler(MB_InterruptVectorTable.CallBackRef);
/* The compiler restores all volatiles and MSR, and returns from interrupt */
}
/****************************************************************************/
/*****************************************************************************/
/**
*
* Registers a top-level interrupt handler for the MicroBlaze. The
* argument provided in this call as the DataPtr is used as the argument
* for the handler when it is called.
*
* @param Top level handler.
* @param DataPtr is a reference to data that will be passed to the handler
* when it gets called.
* @return None.
*
* @note
*
* None.
*
****************************************************************************/
void microblaze_register_handler(XInterruptHandler Handler, void *DataPtr)
{
MB_InterruptVectorTable.Handler = Handler;
MB_InterruptVectorTable.CallBackRef = DataPtr;
}

30
software/LED_Controller_bsp/microblaze_mcs/libsrc/standalone_v3_11_a/src/microblaze_interrupts_g.c Normal file
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/*******************************************************************
*
* CAUTION: This file is automatically generated by libgen.
* Version: Xilinx EDK 14.7 EDK_P.20131013
* DO NOT EDIT.
*
* Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
*
* Description: Interrupt Handler Table for MicroBlaze Processor
*
*******************************************************************/
#include "microblaze_interrupts_i.h"
#include "xparameters.h"
extern void XNullHandler (void *);
/*
* The interrupt handler table for microblaze processor
*/
MB_InterruptVectorTableEntry MB_InterruptVectorTable[] =
{
{ XNullHandler,
(void*) XNULL}
};

61
software/LED_Controller_bsp/microblaze_mcs/libsrc/standalone_v3_11_a/src/microblaze_interrupts_i.h Executable file
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////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2004 Xilinx, Inc. All rights reserved.
//
// Xilinx, Inc.
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
// AND FITNESS FOR A PARTICULAR PURPOSE.
//
// $Id: microblaze_interrupts_i.h,v 1.1.2.1 2011/05/17 04:37:31 sadanan Exp $
////////////////////////////////////////////////////////////////////////////////
/*****************************************************************************/
/**
*
* @file microblaze_interrupts_i.h
*
* This header file contains identifiers and low-level driver functions (or
* macros) that can be used to access the device. The user should refer to the
* hardware device specification for more details of the device operation.
* High-level driver functions are defined in xintc.h.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Date Changes
* ----- -------- -----------------------------------------------
* 1.00b 10/03/03 First release
* </pre>
*
******************************************************************************/
#ifndef MICROBLAZE_INTERRUPTS_I_H /* prevent circular inclusions */
#define MICROBLAZE_INTERRUPTS_I_H /* by using protection macros */
/***************************** Include Files *********************************/
#include "xbasic_types.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef struct
{
XInterruptHandler Handler;
void *CallBackRef;
} MB_InterruptVectorTableEntry;
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */

52
software/LED_Controller_bsp/microblaze_mcs/libsrc/standalone_v3_11_a/src/microblaze_invalidate_cache_ext.S Executable file
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/******************************************************************************
* Copyright (c) 2008-2013 Xilinx, Inc. All rights reserved.
*
* Xilinx, Inc.
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
* COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
* ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
* STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
* IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
* FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
* XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
* THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
* ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
* FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
* AND FITNESS FOR A PARTICULAR PURPOSE.
*
* microblaze_invalidate_cache_ext()
*
*Invalidate the entire L2 Cache
*
*
*******************************************************************************/
#include "xparameters.h"
#define XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN 16
.text
.globl microblaze_invalidate_cache_ext
.ent microblaze_invalidate_cache_ext
.align 2
microblaze_invalidate_cache_ext:
#if ((XPAR_MICROBLAZE_INTERCONNECT==3) && (XPAR_MICROBLAZE_USE_DCACHE==1))
addik r5, r0, XPAR_MICROBLAZE_DCACHE_BASEADDR & (-(4 * XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN))
addik r6, r0, XPAR_MICROBLAZE_DCACHE_BYTE_SIZE-(4 * XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN)
andi r6, r6, -(4 * XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN)
Loop_start:
wdc.ext.clear r5, r6
bgtid r6,Loop_start
addik r6, r6,-(4 * XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN)
#endif
rtsd r15, 8
nop
.end microblaze_invalidate_cache_ext

61
software/LED_Controller_bsp/microblaze_mcs/libsrc/standalone_v3_11_a/src/microblaze_invalidate_cache_ext_range.S Executable file
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/******************************************************************************
* Copyright (c) 2008-2013 Xilinx, Inc. All rights reserved.
*
* Xilinx, Inc.
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
* COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
* ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
* STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
* IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
* FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
* XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
* THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
* ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
* FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
* AND FITNESS FOR A PARTICULAR PURPOSE.
*
* microblaze_invalidate_cache_ext_range (unsigned int cacheaddr, unsigned int len)
*
*Invalidate an L2 cache range
*
*Parameters:
* 'cacheaddr' - address in the L2 cache where invalidation begins
* 'len ' - length (in bytes) worth of Dcache to be invalidated
*
*******************************************************************************/
#include "xparameters.h"
#define XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN 16
.text
.globl microblaze_invalidate_cache_ext_range
.ent microblaze_invalidate_cache_ext_range
.align 2
microblaze_invalidate_cache_ext_range:
#if ((XPAR_MICROBLAZE_INTERCONNECT==3) && (XPAR_MICROBLAZE_USE_DCACHE==1))
beqi r6, Loop_done
add r6, r5, r6
addik r6, r6, -1
andi r6, r6, -(4 * XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN)
andi r5, r5, -(4 * XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN)
rsubk r6, r5, r6
Loop_start:
wdc.ext.clear r5, r6
bneid r6, Loop_start
addik r6, r6, -(4 * XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN)
Loop_done:
#endif
rtsd r15, 8
nop
.end microblaze_invalidate_cache_ext_range

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software/LED_Controller_bsp/microblaze_mcs/libsrc/standalone_v3_11_a/src/microblaze_invalidate_dcache.S Executable file
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/******************************************************************************
* Copyright (c) 2008-2013 Xilinx, Inc. All rights reserved.
*
* Xilinx, Inc.
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
* COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
* ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
* STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
* IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
* FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
* XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
* THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
* ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
* FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
* AND FITNESS FOR A PARTICULAR PURPOSE.
*
* microblaze_invalidate_dcache()
*
* Invalidate the entire L1 DCache
*
*
*******************************************************************************/
#include "xparameters.h"
#define MICROBLAZE_MSR_DCACHE_ENABLE 0x00000080
#define MICROBLAZE_MSR_INTR_ENABLE 0x00000002
#ifndef XPAR_MICROBLAZE_DCACHE_LINE_LEN
#define XPAR_MICROBLAZE_DCACHE_LINE_LEN 1
#endif
#ifndef XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK
#define MB_VERSION_LT_v720
#endif
.text
.globl microblaze_invalidate_dcache
.ent microblaze_invalidate_dcache
.align 2
microblaze_invalidate_dcache:
#ifdef MB_VERSION_LT_v720 /* Disable Dcache and interrupts before invalidating */
mfs r9, rmsr
andi r10, r9, ~(MICROBLAZE_MSR_DCACHE_ENABLE | MICROBLAZE_MSR_INTR_ENABLE)
mts rmsr, r10
#endif
addik r5, r0, XPAR_MICROBLAZE_DCACHE_BASEADDR & (-(4 * XPAR_MICROBLAZE_DCACHE_LINE_LEN))
addik r6, r5, XPAR_MICROBLAZE_DCACHE_BYTE_SIZE & (-(4 * XPAR_MICROBLAZE_DCACHE_LINE_LEN)) /* Compute end */
L_start:
wdc r5, r0 /* Invalidate the Cache */
cmpu r18, r5, r6 /* Are we at the end? */
blei r18, L_done
brid L_start /* Branch to the beginning of the loop */
addik r5, r5, (XPAR_MICROBLAZE_DCACHE_LINE_LEN * 4) /* Increment the addrees by 4 (delay slot) */
L_done:
rtsd r15, 8 /* Return */
#ifdef MB_VERSION_LT_v720 /* restore MSR only for MB version < v7.20 */
mts rmsr, r9
#else
nop
#endif
.end microblaze_invalidate_dcache

98
software/LED_Controller_bsp/microblaze_mcs/libsrc/standalone_v3_11_a/src/microblaze_invalidate_dcache_range.S Executable file
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/******************************************************************************
* Copyright (c) 2008 Xilinx, Inc. All rights reserved.
*
* Xilinx, Inc.
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
* COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
* ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
* STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
* IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
* FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
* XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
* THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
* ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
* FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
* AND FITNESS FOR A PARTICULAR PURPOSE.
*
* microblaze_invalidate_dcache_range (unsigned int cacheaddr, unsigned int len)
*
* Invalidate a Dcache range
*
* Parameters:
* 'cacheaddr' - address in the Dcache where invalidation begins
* 'len ' - length (in bytes) worth of Dcache to be invalidated
*
* $Id: microblaze_invalidate_dcache_range.S,v 1.1.2.1 2011/05/17 04:37:31 sadanan Exp $
*
*******************************************************************************/
#include "xparameters.h"
#define MICROBLAZE_MSR_DCACHE_ENABLE 0x00000080
#define MICROBLAZE_MSR_INTR_ENABLE 0x00000002
#ifndef XPAR_MICROBLAZE_DCACHE_LINE_LEN
#define XPAR_MICROBLAZE_DCACHE_LINE_LEN 1
#endif
#ifndef XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK
#define MB_VERSION_LT_v720
#define MB_HAS_WRITEBACK_SET 0
#else
#define MB_HAS_WRITEBACK_SET XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK
#endif
.text
.globl microblaze_invalidate_dcache_range
.ent microblaze_invalidate_dcache_range
.align 2
microblaze_invalidate_dcache_range:
#ifdef MB_VERSION_LT_v720 /* Disable Dcache and interrupts before invalidating */
mfs r9, rmsr
andi r10, r9, ~(MICROBLAZE_MSR_DCACHE_ENABLE | MICROBLAZE_MSR_INTR_ENABLE)
mts rmsr, r10
#endif
beqi r6, L_done /* Skip loop if size is zero */
add r6, r5, r6 /* Compute end address */
addik r6, r6, -1
andi r6, r6, -(4 * XPAR_MICROBLAZE_DCACHE_LINE_LEN) /* Align end down to cache line */
andi r5, r5, -(4 * XPAR_MICROBLAZE_DCACHE_LINE_LEN) /* Align start down to cache line */
#if MB_HAS_WRITEBACK_SET == 0 /* Use a different scheme for MB version < v7.20 or when caches are write-through */
L_start:
cmpu r18, r5, r6 /* Are we at the end? */
blti r18, L_done
wdc r5, r0
brid L_start /* Branch to the beginning of the loop */
addik r5, r5, (XPAR_MICROBLAZE_DCACHE_LINE_LEN * 4) /* Increment the addrees by 4 (delay slot) */
#else
rsubk r6, r5, r6
/* r6 will now contain (count of bytes - (4 * XPAR_MICROBLAZE_DCACHE_LINE_LEN)) */
L_start:
wdc.clear r5, r6 /* Invalidate the cache line only if the address matches */
bneid r6, L_start
addik r6, r6, -(XPAR_MICROBLAZE_DCACHE_LINE_LEN * 4)
#endif
L_done:
rtsd r15, 8
#ifdef MB_VERSION_LT_v720 /* restore MSR only for MB version < v7.20 */
mts rmsr, r9
#else
nop
#endif
.end microblaze_invalidate_dcache_range

72
software/LED_Controller_bsp/microblaze_mcs/libsrc/standalone_v3_11_a/src/microblaze_invalidate_icache.S Executable file
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/******************************************************************************
* Copyright (c) 2008 Xilinx, Inc. All rights reserved.
*
* Xilinx, Inc.
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
* COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
* ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
* STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
* IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
* FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
* XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
* THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
* ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
* FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
* AND FITNESS FOR A PARTICULAR PURPOSE.
*
* microblaze_invalidate_icache()
*
* Invalidate the entire ICache
*
* $Id: microblaze_invalidate_icache.S,v 1.1.2.1 2011/05/17 04:37:31 sadanan Exp $
*
*******************************************************************************/
#include "xparameters.h"
#define MICROBLAZE_MSR_ICACHE_ENABLE 0x00000020
#define MICROBLAZE_MSR_INTR_ENABLE 0x00000002
#ifndef XPAR_MICROBLAZE_ICACHE_LINE_LEN
#define XPAR_MICROBLAZE_ICACHE_LINE_LEN 1
#endif
#ifndef XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK
#define MB_VERSION_LT_v720
#endif
.text
.globl microblaze_invalidate_icache
.ent microblaze_invalidate_icache
.align 2
microblaze_invalidate_icache:
#ifdef MB_VERSION_LT_v720 /* Disable Icache and interrupts before invalidating */
mfs r9, rmsr
andi r10, r9, ~(MICROBLAZE_MSR_ICACHE_ENABLE | MICROBLAZE_MSR_INTR_ENABLE)
mts rmsr, r10
#endif
addik r5, r0, XPAR_MICROBLAZE_ICACHE_BASEADDR & (-(4 * XPAR_MICROBLAZE_ICACHE_LINE_LEN)) /* Align to cache line */
addik r6, r5, XPAR_MICROBLAZE_CACHE_BYTE_SIZE & (-(4 * XPAR_MICROBLAZE_ICACHE_LINE_LEN)) /* Compute end */
L_start:
wic r5, r0 /* Invalidate the Cache */
cmpu r18, r5, r6 /* Are we at the end? */
blei r18, L_done
brid L_start /* Branch to the beginning of the loop */
addik r5, r5, (XPAR_MICROBLAZE_ICACHE_LINE_LEN * 4) /* Increment the addrees by 4 (delay slot) */
L_done:
rtsd r15, 8 /* Return */
#ifdef MB_VERSION_LT_v720 /* restore MSR only for MB version < v7.20 */
mts rmsr, r9
#else
nop
#endif
.end microblaze_invalidate_icache

82
software/LED_Controller_bsp/microblaze_mcs/libsrc/standalone_v3_11_a/src/microblaze_invalidate_icache_range.S Executable file
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/******************************************************************************
* Copyright (c) 2008 Xilinx, Inc. All rights reserved.
*
* Xilinx, Inc.
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
* COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
* ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
* STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
* IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
* FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
* XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
* THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
* ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
* FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
* AND FITNESS FOR A PARTICULAR PURPOSE.
*
* microblaze_invalidate_icache_range(unsigned int cacheaddr, unsigned int len)
*
* Invalidate an ICache range
*
* Parameters:
* 'cacheaddr' - address in the Icache where invalidation begins
* 'len' - length (in bytes) worth of Icache to be invalidated
*
* $Id: microblaze_invalidate_icache_range.S,v 1.1.2.1 2011/05/17 04:37:31 sadanan Exp $
*
*******************************************************************************/
#include "xparameters.h"
#define MICROBLAZE_MSR_ICACHE_ENABLE 0x00000020
#define MICROBLAZE_MSR_INTR_ENABLE 0x00000002
#ifndef XPAR_MICROBLAZE_ICACHE_LINE_LEN
#define XPAR_MICROBLAZE_ICACHE_LINE_LEN 1
#endif
#ifndef XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK
#define MB_VERSION_LT_v720
#endif
.text
.globl microblaze_invalidate_icache_range
.ent microblaze_invalidate_icache_range
.align 2
microblaze_invalidate_icache_range:
#ifdef MB_VERSION_LT_v720 /* Disable Icache and interrupts before invalidating */
mfs r9, rmsr
andi r10, r9, ~(MICROBLAZE_MSR_ICACHE_ENABLE | MICROBLAZE_MSR_INTR_ENABLE)
mts rmsr, r10
#endif
beqi r6, L_done /* Skip loop if size is zero */
add r6, r5, r6 /* Compute end address */
addik r6, r6, -1
andi r6, r6, -(4 * XPAR_MICROBLAZE_ICACHE_LINE_LEN) /* Align end down to cache line */
andi r5, r5, -(4 * XPAR_MICROBLAZE_ICACHE_LINE_LEN) /* Align start down to cache line */
L_start:
cmpu r18, r5, r6 /* Are we at the end? */
blti r18, L_done
wic r5, r0 /* Invalidate the cache line */
brid L_start /* Branch to the beginning of the loop */
addik r5, r5, (XPAR_MICROBLAZE_ICACHE_LINE_LEN * 4) /* Increment the addrees by 4 (delay slot) */
L_done:
rtsd r15, 8 /* Return */
#ifdef MB_VERSION_LT_v720 /* restore MSR only for MB version < v7.20 */
mts rmsr, r9
#else
nop
#endif
.end microblaze_invalidate_icache_range

195
software/LED_Controller_bsp/microblaze_mcs/libsrc/standalone_v3_11_a/src/microblaze_scrub.S Executable file
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/******************************************************************************
* Copyright (c) 2011 Xilinx, Inc. All rights reserved.
*
* Xilinx, Inc.
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
* COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
* ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
* STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
* IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
* FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
* XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
* THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
* ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
* FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
* AND FITNESS FOR A PARTICULAR PURPOSE.
*
* microblaze_scrub ()
*
* Scrub LMB memory and all internal BRAMs (data cache, instruction cache,
* MMU UTLB and branch target cache) in MicroBlaze to reduce the possibility
* of an uncorrectable error when fault tolerance support is enabled.
*
* This routine assumes that the processor is in privileged mode when it is
* called, if the MMU is enabled.
*
* Call this routine regularly from a timer interrupt.
*
* Parameters:
* None
*
* $Id: microblaze_scrub.S,v 1.1.2.1 2011/05/17 04:37:32 sadanan Exp $
*
*******************************************************************************/
#include "xparameters.h"
/* Define if fault tolerance is used */
#ifdef XPAR_MICROBLAZE_FAULT_TOLERANT
#if XPAR_MICROBLAZE_FAULT_TOLERANT > 0
#define FAULT_TOLERANT
#endif
#endif
/* Define if LMB is used and can be scrubbed */
#if defined(XPAR_MICROBLAZE_D_LMB) && \
defined(XPAR_DLMB_CNTLR_BASEADDR) && \
defined(XPAR_DLMB_CNTLR_HIGHADDR)
#if XPAR_MICROBLAZE_D_LMB == 1
#define HAS_SCRUBBABLE_LMB
#define DLMB_MASK (XPAR_DLMB_CNTLR_HIGHADDR - XPAR_DLMB_CNTLR_BASEADDR)
#endif
#endif
/* Set default cache line lengths */
#ifndef XPAR_MICROBLAZE_DCACHE_LINE_LEN
#define XPAR_MICROBLAZE_DCACHE_LINE_LEN 4
#endif
#ifndef XPAR_MICROBLAZE_ICACHE_LINE_LEN
#define XPAR_MICROBLAZE_ICACHE_LINE_LEN 4
#endif
/* Define if internal Data Cache BRAMs are used */
#if defined(XPAR_MICROBLAZE_USE_DCACHE) && defined(XPAR_MICROBLAZE_DCACHE_BYTE_SIZE)
#if XPAR_MICROBLAZE_USE_DCACHE == 1 && XPAR_MICROBLAZE_DCACHE_BYTE_SIZE > 1024
#define HAS_BRAM_DCACHE
#define DCACHE_INCREMENT (XPAR_MICROBLAZE_DCACHE_LINE_LEN * 4)
#define DCACHE_MASK (XPAR_MICROBLAZE_DCACHE_BYTE_SIZE - 1)
#endif
#endif
/* Define if internal Instruction Cache BRAMs are used */
#if defined(XPAR_MICROBLAZE_USE_ICACHE) && defined(XPAR_MICROBLAZE_CACHE_BYTE_SIZE)
#if XPAR_MICROBLAZE_USE_ICACHE == 1 && XPAR_MICROBLAZE_CACHE_BYTE_SIZE > 1024
#define HAS_BRAM_ICACHE
#define ICACHE_INCREMENT (XPAR_MICROBLAZE_ICACHE_LINE_LEN * 4)
#define ICACHE_MASK (XPAR_MICROBLAZE_CACHE_BYTE_SIZE - 1)
#endif
#endif
/* Define if internal MMU UTLB BRAM is used */
#ifdef XPAR_MICROBLAZE_USE_MMU
#if XPAR_MICROBLAZE_USE_MMU > 1
#define HAS_BRAM_MMU_UTLB
#endif
#endif
/* Define if internal BTC BRAM is used, and match BTC clear to a complete cache scrub */
#if defined(XPAR_MICROBLAZE_USE_BRANCH_TARGET_CACHE) && \
defined(XPAR_MICROBLAZE_BRANCH_TARGET_CACHE_SIZE)
#if XPAR_MICROBLAZE_USE_BRANCH_TARGET_CACHE == 1
#if XPAR_MICROBLAZE_BRANCH_TARGET_CACHE_SIZE == 0 || \
XPAR_MICROBLAZE_BRANCH_TARGET_CACHE_SIZE > 4
#define HAS_BRAM_BRANCH_TARGET_CACHE
#ifdef HAS_BRAM_DCACHE
#define BTC_MASK_D (XPAR_MICROBLAZE_DCACHE_BYTE_SIZE/DCACHE_INCREMENT-1)
#else
#define BTC_MASK_D 256
#endif
#ifdef HAS_BRAM_ICACHE
#define BTC_MASK_I (XPAR_MICROBLAZE_CACHE_BYTE_SIZE/ICACHE_INCREMENT-1)
#else
#define BTC_MASK_I 256
#endif
#if BTC_MASK_D > BTC_MASK_I
#define BTC_MASK BTC_MASK_D
#else
#define BTC_MASK BTC_MASK_I
#endif
#endif
#endif
#endif
/* Define index offsets to persistent data used by this routine */
#define DLMB_INDEX_OFFSET 0
#define DCACHE_INDEX_OFFSET 4
#define ICACHE_INDEX_OFFSET 8
#define MMU_INDEX_OFFSET 12
#define BTC_CALL_COUNT_OFFSET 16
.text
.globl microblaze_scrub
.ent microblaze_scrub
.align 2
microblaze_scrub:
#ifdef FAULT_TOLERANT
la r6, r0, L_persistent_data /* Get pointer to data */
#ifdef HAS_SCRUBBABLE_LMB
L_dlmb:
lwi r5, r6, DLMB_INDEX_OFFSET /* Get dlmb index */
lw r7, r5, r0 /* Load and store */
sw r7, r5, r0
addik r5, r5, 4 /* Increment and save dlmb index */
andi r5, r5, DLMB_MASK
swi r5, r6, DLMB_INDEX_OFFSET
#endif /* HAS_SCRUBBABLE_LMB */
#ifdef HAS_BRAM_DCACHE
L_dcache:
lwi r5, r6, DCACHE_INDEX_OFFSET /* Get dcache line index */
wdc r5, r0 /* Invalidate data cache line */
addik r5, r5, DCACHE_INCREMENT /* Increment and save entry index */
andi r5, r5, DCACHE_MASK
swi r5, r6, DCACHE_INDEX_OFFSET
#endif /* HAS_BRAM_DCACHE */
#ifdef HAS_BRAM_ICACHE
L_icache:
lwi r5, r6, ICACHE_INDEX_OFFSET /* Get icache line index */
wic r5, r0 /* Invalidate data cache line */
addik r5, r5, ICACHE_INCREMENT /* Increment and save entry index */
andi r5, r5, ICACHE_MASK
swi r5, r6, ICACHE_INDEX_OFFSET
#endif /* HAS_BRAM_ICACHE */
#ifdef HAS_BRAM_MMU_UTLB
L_mmu:
lwi r5, r6, MMU_INDEX_OFFSET /* Get UTLB entry index */
mts rtlbx, r5 /* Access next entry in UTLB */
mts rtlbhi, r0 /* Clear the UTLB entry */
addik r5, r5, 1 /* Increment and save entry index */
andi r5, r5, 0x3F
swi r5, r6, MMU_INDEX_OFFSET
#endif /* HAS_BRAM_MMU_UTLB */
#ifdef HAS_BRAM_BRANCH_TARGET_CACHE
L_btc:
lwi r5, r6, BTC_CALL_COUNT_OFFSET /* Get BTC call count offset */
addik r5, r5, 1 /* Increment and save call count */
andi r5, r5, BTC_MASK
swi r5, r6, BTC_CALL_COUNT_OFFSET
bnei r5, L_skip_btc_scrub /* Skip scrub unless count wrap */
bri 4 /* Clear branch target cache */
L_skip_btc_scrub:
#endif /* HAS_BRAM_BRANCH_TARGET_CACHE */
#endif /* FAULT_TOLERANT */
L_done:
rtsd r15, 8 /* Return */
nop
.end microblaze_scrub
/* Persistent data used by this routine */
.data
.align 2
L_persistent_data:
.long 0 /* dlmb index */
.long 0 /* dcache index */
.long 0 /* icache index */
.long 0 /* mmu entry index */
.long 0 /* btc call count */

89
software/LED_Controller_bsp/microblaze_mcs/libsrc/standalone_v3_11_a/src/microblaze_update_dcache.S Executable file
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/*********************************************************************************
* Copyright (c) 2006 Xilinx, Inc. All rights reserved.
*
* Xilinx, Inc.
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
* COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
* ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
* STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
* IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
* FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
* XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
* THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
* ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
* FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
* AND FITNESS FOR A PARTICULAR PURPOSE.
*
* File : microblaze_update_dcache.s
* Date : 2003, September 24
* Company: Xilinx
* Group : Emerging Software Technologies
*
* Summary:
* Update dcache on the microblaze.
* Takes in three parameters
* r5 : Cache Tag Line
* r6 : Cache Data
* r7 : Lock/Valid information
* Bit 30 is Lock [ 1 indicates locked ]
* Bit 31 is Valid [ 1 indicates valid ]
*
* --------------------------------------------------------------
* | Lock | Valid | Effect
* --------------------------------------------------------------
* | 0 | 0 | Invalidate Cache
* | 0 | 1 | Valid, but unlocked cacheline
* | 1 | 0 | Invalidate Cache, No effect of lock
* | 1 | 1 | Valid cache. Locked to a
* | | | particular addrees
* --------------------------------------------------------------
*
* $Id: microblaze_update_dcache.S,v 1.1.2.1 2011/05/17 04:37:32 sadanan Exp $
*
**********************************************************************************/
#include "xparameters.h"
#ifndef XPAR_MICROBLAZE_DCACHE_LINE_LEN
#define XPAR_MICROBLAZE_DCACHE_LINE_LEN 1
#endif
.text
.globl microblaze_update_dcache
.ent microblaze_update_dcache
.align 2
microblaze_update_dcache:
#if XPAR_MICROBLAZE_DCACHE_LINE_LEN == 1
/* Read the MSR register into a temp register */
mfs r18, rmsr
/* Clear the dcache enable bit to disable the cache
Register r10,r18 are volatile registers and hence do not need to be saved before use */
andi r10, r18, ~128
mts rmsr, r10
/* Update the lock and valid info */
andi r5, r5, 0xfffffffc
or r5, r5, r7
/* Update dcache */
wdc r5, r6
/* Return */
rtsd r15, 8
mts rmsr, r18
#else
/* The only valid usage of this routine for larger cache line lengths is to invalidate a data cache line
So call microblaze_init_dcache_range appropriately to do the job */
brid microblaze_init_dcache_range
addik r6, r0, (XPAR_MICROBLAZE_DCACHE_LINE_LEN * 4)
/* We don't have a return instruction here. This is tail call optimization :) */
#endif /* XPAR_MICROBLAZE_DCACHE_LINE_LEN == 1 */
.end microblaze_update_dcache

90
software/LED_Controller_bsp/microblaze_mcs/libsrc/standalone_v3_11_a/src/microblaze_update_icache.S Executable file
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/*********************************************************************************
* Copyright (c) 2006 Xilinx, Inc. All rights reserved.
*
* Xilinx, Inc.
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
* COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
* ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
* STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
* IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
* FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
* XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
* THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
* ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
* FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
* AND FITNESS FOR A PARTICULAR PURPOSE.
*
* File : microblaze_update_icache.s
* Date : 2003, September 24
* Company: Xilinx
* Group : Emerging Software Technologies
*
* Summary:
* Update icache on the microblaze.
* Takes in three parameters
* r5 : Cache Tag Line
* r6 : Cache Data
* r7 : Lock/Valid information
* Bit 30 is Lock [ 1 indicates locked ]
* Bit 31 is Valid [ 1 indicates valid ]
*
* --------------------------------------------------------------
* | Lock | Valid | Effect
* --------------------------------------------------------------
* | 0 | 0 | Invalidate Cache
* | 0 | 1 | Valid, but unlocked cacheline
* | 1 | 0 | Invalidate Cache, No effect of lock
* | 1 | 1 | Valid cache. Locked to a
* | | | particular addrees
* --------------------------------------------------------------
*
* $Id: microblaze_update_icache.S,v 1.1.2.1 2011/05/17 04:37:33 sadanan Exp $
*
**********************************************************************************/
#include "xparameters.h"
#ifndef XPAR_MICROBLAZE_ICACHE_LINE_LEN
#define XPAR_MICROBLAZE_ICACHE_LINE_LEN 1
#endif
.text
.globl microblaze_update_icache
.ent microblaze_update_icache
.align 2
microblaze_update_icache:
#if XPAR_MICROBLAZE_ICACHE_LINE_LEN == 1
/* Read the MSR register into a temp register */
mfs r18, rmsr
/* Clear the icache enable bit to disable the cache
Register r10,r18 are volatile registers and hence do not need to be saved before use */
andi r10, r18, ~32
mts rmsr, r10
/* Update the lock and valid info */
andi r5, r5, 0xfffffffc
or r5, r5, r7
/* Update icache */
wic r5, r6
/* Return */
rtsd r15, 8
mts rmsr, r18
#else
/* The only valid usage of this routine for larger cache line lengths is to invalidate an instruction cache line
So call microblaze_init_icache_range appropriately to do the job */
brid microblaze_init_icache_range
addik r6, r0, (XPAR_MICROBLAZE_ICACHE_LINE_LEN * 4)
/* We don't have a return instruction here. This is tail call optimization :) */
#endif /* XPAR_MICROBLAZE_ICACHE_LINE_LEN == 1 */
.end microblaze_update_icache

15
software/LED_Controller_bsp/microblaze_mcs/libsrc/standalone_v3_11_a/src/outbyte.c Normal file
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#include "xparameters.h"
#include "xiomodule_l.h"
#ifdef __cplusplus
extern "C" {
#endif
void outbyte(char c);
#ifdef __cplusplus
}
#endif
void outbyte(char c) {
XIOModule_SendByte(STDOUT_BASEADDRESS, c);
}

65
software/LED_Controller_bsp/microblaze_mcs/libsrc/standalone_v3_11_a/src/profile/Makefile Executable file
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#######################################################################
#
# Copyright (c) 2002 Xilinx, Inc. All rights reserved.
# Xilinx, Inc.
#
# XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
# COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
# ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
# STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
# IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
# FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
# XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
# THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
# ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
# FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
# AND FITNESS FOR A PARTICULAR PURPOSE.
#
# $Id: Makefile,v 1.1.2.1 2011/05/17 04:37:55 sadanan Exp $
#
# Makefile for profiler
#
#######################################################################
# PROFILE_ARCH_OBJS - Processor Architecture Dependent files defined here
include ../config.make
AS=mb-as
COMPILER = mb-gcc
ARCHIVER = mb-ar
CP = cp
COMPILER_FLAGS=-O2
EXTRA_COMPILER_FLAGS=
LIB = libxil.a
DUMMYLIB = libxilprofile.a
CC_FLAGS = $(subst -pg, , $(COMPILER_FLAGS))
ECC_FLAGS = $(subst -pg, , $(EXTRA_COMPILER_FLAGS))
RELEASEDIR = ../../../../lib
INCLUDEDIR = ../../../../include
INCLUDES = -I./. -I${INCLUDEDIR}
OBJS = _profile_init.o _profile_clean.o _profile_timer_hw.o profile_hist.o profile_cg.o
DUMMYOBJ = dummy.o
INCLUDEFILES = profile.h mblaze_nt_types.h _profile_timer_hw.h
libs : reallibs dummylibs
reallibs : $(OBJS) $(PROFILE_ARCH_OBJS)
$(ARCHIVER) -r $(RELEASEDIR)/$(LIB) $(OBJS) $(PROFILE_ARCH_OBJS)
dummylibs : $(DUMMYOBJ)
$(ARCHIVER) -r $(RELEASEDIR)/$(DUMMYLIB) $(DUMMYOBJ)
%.o:%.c
$(COMPILER) $(CC_FLAGS) $(ECC_FLAGS) -c $< -o $@ $(INCLUDES)
%.o:%.S
$(COMPILER) $(CC_FLAGS) $(ECC_FLAGS) -c $< -o $@ $(INCLUDES)
include:
$(CP) -rf $(INCLUDEFILES) $(INCLUDEDIR)
clean:
rm -f $(OBJS) $(PROFILE_ARCH_OBJS) $(LIB)

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software/LED_Controller_bsp/microblaze_mcs/libsrc/standalone_v3_11_a/src/profile/_profile_clean.c Executable file
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//
// Copyright (c) 2002 Xilinx, Inc. All rights reserved.
// Xilinx, Inc.
//
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
// AND FITNESS FOR A PARTICULAR PURPOSE.
//
// $Id: _profile_clean.c,v 1.1.2.1 2011/05/17 04:37:55 sadanan Exp $
//
#include "profile.h"
#include "_profile_timer_hw.h"
#include "xil_exception.h"
/*
* This function is the exit routine and is called by the crtinit, when the
* program terminates. The name needs to be changed later..
*/
void _profile_clean( void )
{
Xil_ExceptionDisable();
disable_timer();
}

80
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//////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2002-2011 Xilinx, Inc. All rights reserved.
// Xilinx, Inc.
//
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
// AND FITNESS FOR A PARTICULAR PURPOSE.
//
// $Id: _profile_init.c,v 1.1.2.1 2011/05/17 04:37:56 sadanan Exp $
//
// _program_init.c:
// Initialize the Profiling Structures.
//
//////////////////////////////////////////////////////////////////////
#include "profile.h"
// XMD Initializes the following Global Variables Value during Program
// Download with appropriate values.
#ifdef PROC_MICROBLAZE
extern int microblaze_init(void);
#elif defined PROC_PPC
extern int powerpc405_init(void);
#else
extern int cortexa9_init(void);
#endif
int profile_version = 1; // Version of S/W Intrusive Profiling library
int binsize = BINSIZE; // Histogram Bin Size
unsigned int cpu_clk_freq = CPU_FREQ_HZ ; // CPU Clock Frequency
unsigned int sample_freq_hz = SAMPLE_FREQ_HZ ; // Histogram Sampling Frequency
unsigned int timer_clk_ticks = TIMER_CLK_TICKS ;// Timer Clock Ticks for the Timer
// Structure for Storing the Profiling Data
struct gmonparam *_gmonparam = (struct gmonparam *)0xffffffff;
int n_gmon_sections = 1;
// This is the initialization code, which is called from the crtinit.
//
void _profile_init( void )
{
/* print("Gmon Init called....\r\n") ; */
/* putnum(n_gmon_sections) ; print("\r\n") ; */
/* if( _gmonparam == 0xffffffff ) */
/* printf("Gmonparam is NULL !!\r\n"); */
/* for( i = 0; i < n_gmon_sections; i++ ){ */
/* putnum(_gmonparam[i].lowpc) ; print("\t") ; */
/* putnum(_gmonparam[i].highpc) ; print("\r\n") ; */
/* putnum( _gmonparam[i].textsize ); print("\r\n") ; */
/* putnum( _gmonparam[i].kcountsize * sizeof(unsigned short));print("\r\n"); */
/* } */
#ifdef PROC_MICROBLAZE
microblaze_init();
#elif defined PROC_PPC
powerpc405_init();
#else
cortexa9_init ();
#endif
}

346
software/LED_Controller_bsp/microblaze_mcs/libsrc/standalone_v3_11_a/src/profile/_profile_timer_hw.c Executable file
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//////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2004-2010 Xilinx, Inc. All rights reserved.
// Xilinx, Inc.
//
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
// AND FITNESS FOR A PARTICULAR PURPOSE.
//
// $Id: _profile_timer_hw.c,v 1.1.2.1 2011/05/17 04:37:56 sadanan Exp $
//
// _program_timer_hw.c:
// Timer related functions
//
//////////////////////////////////////////////////////////////////////
#include "profile.h"
#include "_profile_timer_hw.h"
#include "xil_exception.h"
#ifdef PROC_PPC
#include "xtime_l.h"
#include "xpseudo_asm.h"
#endif
#ifdef TIMER_CONNECT_INTC
#include "xintc_l.h"
#include "xintc.h"
#endif // TIMER_CONNECT_INTC
//#ifndef PPC_PIT_INTERRUPT
#if (!defined PPC_PIT_INTERRUPT && !defined PROC_CORTEXA9)
#include "xtmrctr_l.h"
#endif
extern unsigned int timer_clk_ticks ;
//--------------------------------------------------------------------
// PowerPC Target - Timer related functions
//--------------------------------------------------------------------
#ifdef PROC_PPC405
//--------------------------------------------------------------------
// PowerPC PIT Timer Init.
// Defined only if PIT Timer is used for Profiling
//
//--------------------------------------------------------------------
#ifdef PPC_PIT_INTERRUPT
int ppc_pit_init( void )
{
// 1. Register Profile_intr_handler as Interrupt handler
// 2. Set PIT Timer Interrupt and Enable it.
Xil_ExceptionRegisterHandler( XIL_EXCEPTION_ID_PIT_INT,
(Xil_ExceptionHandler)profile_intr_handler,(void *)0);
XTime_PITSetInterval( timer_clk_ticks ) ;
XTime_PITEnableAutoReload() ;
return 0;
}
#endif
//--------------------------------------------------------------------
// PowerPC Timer Initialization functions.
// For PowerPC, PIT and opb_timer can be used for Profiling. This
// is selected by the user in standalone BSP
//
//--------------------------------------------------------------------
int powerpc405_init()
{
Xil_ExceptionInit() ;
Xil_ExceptionDisableMask( XIL_EXCEPTION_NON_CRITICAL ) ;
// Initialize the Timer.
// 1. If PowerPC PIT Timer has to be used, initialize PIT timer.
// 2. Else use opb_timer. It can be directly connected or thru intc to PowerPC
#ifdef PPC_PIT_INTERRUPT
ppc_pit_init();
#else
#ifdef TIMER_CONNECT_INTC
Xil_ExceptionRegisterHandler( XIL_EXCEPTION_ID_NON_CRITICAL_INT,
(Xil_ExceptionHandler)XIntc_DeviceInterruptHandler,(void *)0);
XIntc_RegisterHandler( INTC_BASEADDR, PROFILE_TIMER_INTR_ID,
(XInterruptHandler)profile_intr_handler,(void*)0);
#else
Xil_ExceptionRegisterHandler( XIL_EXCEPTION_ID_NON_CRITICAL_INT,
(Xil_ExceptionHandler)profile_intr_handler,(void *)0);
#endif
// Initialize the timer with Timer Ticks
opb_timer_init() ;
#endif
// Enable Interrupts in the System, if Profile Timer is the only Interrupt
// in the System.
#ifdef ENABLE_SYS_INTR
#ifdef PPC_PIT_INTERRUPT
XTime_PITEnableInterrupt() ;
#elif TIMER_CONNECT_INTC
XIntc_MasterEnable( INTC_BASEADDR );
XIntc_SetIntrSvcOption( INTC_BASEADDR, XIN_SVC_ALL_ISRS_OPTION);
XIntc_EnableIntr( INTC_BASEADDR, PROFILE_TIMER_INTR_MASK );
#endif
Xil_ExceptionEnableMask( XIL_EXCEPTION_NON_CRITICAL ) ;
#endif
return 0;
}
#endif // PROC_PPC
//--------------------------------------------------------------------
// PowerPC440 Target - Timer related functions
//--------------------------------------------------------------------
#ifdef PROC_PPC440
//--------------------------------------------------------------------
// PowerPC DEC Timer Init.
// Defined only if DEC Timer is used for Profiling
//
//--------------------------------------------------------------------
#ifdef PPC_PIT_INTERRUPT
int ppc_dec_init( void )
{
// 1. Register Profile_intr_handler as Interrupt handler
// 2. Set DEC Timer Interrupt and Enable it.
Xil_ExceptionRegisterHandler( XIL_EXCEPTION_ID_DEC_INT,
(Xil_ExceptionHandler)profile_intr_handler,(void *)0);
XTime_DECSetInterval( timer_clk_ticks ) ;
XTime_DECEnableAutoReload() ;
return 0;
}
#endif
//--------------------------------------------------------------------
// PowerPC Timer Initialization functions.
// For PowerPC, DEC and opb_timer can be used for Profiling. This
// is selected by the user in standalone BSP
//
//--------------------------------------------------------------------
int powerpc405_init(void)
{
Xil_ExceptionInit();
Xil_ExceptionDisableMask( XIL_EXCEPTION_NON_CRITICAL ) ;
// Initialize the Timer.
// 1. If PowerPC DEC Timer has to be used, initialize DEC timer.
// 2. Else use opb_timer. It can be directly connected or thru intc to PowerPC
#ifdef PPC_PIT_INTERRUPT
ppc_dec_init();
#else
#ifdef TIMER_CONNECT_INTC
Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_NON_CRITICAL_INT,
(Xil_ExceptionHandler)XIntc_DeviceInterruptHandler,(void *)0);
XIntc_RegisterHandler( INTC_BASEADDR, PROFILE_TIMER_INTR_ID,
(XInterruptHandler)profile_intr_handler,(void*)0);
#else
Xil_ExceptionRegisterHandler( XIL_EXCEPTION_ID_NON_CRITICAL_INT,
(Xil_ExceptionHandler)profile_intr_handler,(void *)0);
Xil_ExceptionRegisterHandler( XIL_EXCEPTION_ID_NON_CRITICAL_INT,
(Xil_ExceptionHandler)profile_intr_handler,(void *)0);
#endif
// Initialize the timer with Timer Ticks
opb_timer_init() ;
#endif
// Enable Interrupts in the System, if Profile Timer is the only Interrupt
// in the System.
#ifdef ENABLE_SYS_INTR
#ifdef PPC_PIT_INTERRUPT
XTime_DECEnableInterrupt() ;
#elif TIMER_CONNECT_INTC
XIntc_MasterEnable( INTC_BASEADDR );
XIntc_SetIntrSvcOption( INTC_BASEADDR, XIN_SVC_ALL_ISRS_OPTION);
XIntc_EnableIntr( INTC_BASEADDR, PROFILE_TIMER_INTR_MASK );
#endif
Xil_ExceptionEnableMask( XEXC_NON_CRITICAL ) ;
#endif
return 0;
}
#endif // PROC_PPC440
//--------------------------------------------------------------------
// opb_timer Initialization for PowerPC and MicroBlaze. This function
// is not needed if DEC timer is used in PowerPC
//
//--------------------------------------------------------------------
//#ifndef PPC_PIT_INTERRUPT
#if (!defined PPC_PIT_INTERRUPT && !defined PROC_CORTEXA9)
int opb_timer_init( void )
{
// set the number of cycles the timer counts before interrupting
XTmrCtr_SetLoadReg(PROFILE_TIMER_BASEADDR, 0, timer_clk_ticks);
// reset the timers, and clear interrupts
XTmrCtr_SetControlStatusReg(PROFILE_TIMER_BASEADDR, 0,
XTC_CSR_INT_OCCURED_MASK | XTC_CSR_LOAD_MASK );
// start the timers
XTmrCtr_SetControlStatusReg(PROFILE_TIMER_BASEADDR, 0, XTC_CSR_ENABLE_TMR_MASK
| XTC_CSR_ENABLE_INT_MASK | XTC_CSR_AUTO_RELOAD_MASK | XTC_CSR_DOWN_COUNT_MASK);
return 0;
}
#endif
//--------------------------------------------------------------------
// MicroBlaze Target - Timer related functions
//--------------------------------------------------------------------
#ifdef PROC_MICROBLAZE
//--------------------------------------------------------------------
// Initialize the Profile Timer for MicroBlaze Target.
// For MicroBlaze, opb_timer is used. The opb_timer can be directly
// connected to MicroBlaze or connected through Interrupt Controller.
//
//--------------------------------------------------------------------
int microblaze_init(void)
{
// Register profile_intr_handler
// 1. If timer is connected to Interrupt Controller, register the handler
// to Interrupt Controllers vector table.
// 2. If timer is directly connected to MicroBlaze, register the handler
// as Interrupt handler
Xil_ExceptionInit();
#ifdef TIMER_CONNECT_INTC
XIntc_RegisterHandler( INTC_BASEADDR, PROFILE_TIMER_INTR_ID,
(XInterruptHandler)profile_intr_handler,(void*)0);
#else
Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
(Xil_ExceptionHandler)profile_intr_handler,
(void *)0) ;
#endif
// Initialize the timer with Timer Ticks
opb_timer_init() ;
// Enable Interrupts in the System, if Profile Timer is the only Interrupt
// in the System.
#ifdef ENABLE_SYS_INTR
#ifdef TIMER_CONNECT_INTC
XIntc_MasterEnable( INTC_BASEADDR );
XIntc_SetIntrSvcOption( INTC_BASEADDR, XIN_SVC_ALL_ISRS_OPTION);
XIntc_EnableIntr( INTC_BASEADDR, PROFILE_TIMER_INTR_MASK );
Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
(Xil_ExceptionHandler)XIntc_DeviceInterruptHandler,(void *)0);
#endif
#endif
Xil_ExceptionEnable();
return 0;
}
#endif // PROC_MICROBLAZE
//--------------------------------------------------------------------
// Cortex A9 Target - Timer related functions
//--------------------------------------------------------------------
#ifdef PROC_CORTEXA9
//--------------------------------------------------------------------
// Initialize the Profile Timer for Cortex A9 Target.
// The scu private timer is connected to the Scu GIC controller.
//
//--------------------------------------------------------------------
int scu_timer_init( void )
{
// set the number of cycles the timer counts before interrupting
// scu timer runs at half the cpu clock
XScuTimer_SetLoadReg(PROFILE_TIMER_BASEADDR, timer_clk_ticks/2);
// clear any pending interrupts
XScuTimer_SetIntrReg(PROFILE_TIMER_BASEADDR, 1);
// enable interrupts, auto-reload mode and start the timer
XScuTimer_SetControlReg(PROFILE_TIMER_BASEADDR, XSCUTIMER_CONTROL_IRQ_ENABLE_MASK |
XSCUTIMER_CONTROL_AUTO_RELOAD_MASK | XSCUTIMER_CONTROL_ENABLE_MASK);
return 0;
}
int cortexa9_init(void)
{
Xil_ExceptionInit();
XScuGic_DeviceInitialize(0);
/*
* Connect the interrupt controller interrupt handler to the hardware
* interrupt handling logic in the processor.
*/
Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_IRQ_INT,
(Xil_ExceptionHandler)XScuGic_DeviceInterruptHandler,
(void *)0);
/*
* Connect the device driver handler that will be called when an
* interrupt for the device occurs, the handler defined above performs
* the specific interrupt processing for the device.
*/
XScuGic_RegisterHandler(SCUGIC_CPU_BASEADDR,
PROFILE_TIMER_INTR_ID,
(Xil_ExceptionHandler)profile_intr_handler,
(void *)0);
/*
* Enable the interrupt for scu timer.
*/
XScuGic_EnableIntr(SCUGIC_DIST_BASEADDR, PROFILE_TIMER_INTR_ID);
/*
* Enable interrupts in the Processor.
*/
Xil_ExceptionEnableMask(XIL_EXCEPTION_IRQ);
/*
* Initialize the timer with Timer Ticks
*/
scu_timer_init() ;
Xil_ExceptionEnable();
return 0;
}
#endif // PROC_CORTEXA9

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//////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2004-11 Xilinx, Inc. All rights reserved.
// Xilinx, Inc.
//
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
// AND FITNESS FOR A PARTICULAR PURPOSE.
//
// $Id: _profile_timer_hw.h,v 1.1.2.2 2011/05/30 06:46:18 svemula Exp $
//
// _program_timer_hw.h:
// Timer related functions
//
//////////////////////////////////////////////////////////////////////
#ifndef _PROFILE_TIMER_HW_H
#define _PROFILE_TIMER_HW_H
#include "profile.h"
#ifdef PROC_PPC
#if defined __GNUC__
# define SYNCHRONIZE_IO __asm__ volatile ("eieio")
#elif defined __DCC__
# define SYNCHRONIZE_IO __asm volatile(" eieio")
#else
# define SYNCHRONIZE_IO
#endif
#endif
#ifdef PROC_PPC
#define ProfIo_In32(InputPtr) (*(volatile u32 *)(InputPtr)); SYNCHRONIZE_IO;
#define ProfIo_Out32(OutputPtr, Value) { (*(volatile u32 *)(OutputPtr) = Value); SYNCHRONIZE_IO; }
#else
#define ProfIo_In32(InputPtr) (*(volatile u32 *)(InputPtr));
#define ProfIo_Out32(OutputPtr, Value) { (*(volatile u32 *)(OutputPtr) = Value); }
#endif
#define ProfTmrCtr_mWriteReg(BaseAddress, TmrCtrNumber, RegOffset, ValueToWrite)\
ProfIo_Out32(((BaseAddress) + XTmrCtr_Offsets[(TmrCtrNumber)] + \
(RegOffset)), (ValueToWrite))
#define ProfTimerCtr_mReadReg(BaseAddress, TmrCtrNumber, RegOffset) \
ProfIo_In32((BaseAddress) + XTmrCtr_Offsets[(TmrCtrNumber)] + (RegOffset))
#define ProfTmrCtr_mSetControlStatusReg(BaseAddress, TmrCtrNumber, RegisterValue)\
ProfTmrCtr_mWriteReg((BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET, \
(RegisterValue))
#define ProfTmrCtr_mGetControlStatusReg(BaseAddress, TmrCtrNumber) \
ProfTimerCtr_mReadReg((BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET)
#ifdef __cplusplus
extern "C" {
#endif
#ifdef PROC_PPC
#include "xexception_l.h"
#include "xtime_l.h"
#include "xpseudo_asm.h"
#endif
#ifdef TIMER_CONNECT_INTC
#include "xintc_l.h"
#include "xintc.h"
#endif // TIMER_CONNECT_INTC
#if (!defined PPC_PIT_INTERRUPT && !defined PROC_CORTEXA9)
#include "xtmrctr_l.h"
#endif
#ifdef PROC_CORTEXA9
#include "xscutimer_hw.h"
#include "xscugic.h"
#endif
extern unsigned int timer_clk_ticks ;
//--------------------------------------------------------------------
// PowerPC Target - Timer related functions
//--------------------------------------------------------------------
#ifdef PROC_PPC
#ifdef PPC_PIT_INTERRUPT
unsigned long timer_lo_clk_ticks ; // Clk ticks when Timer is disabled in CG
#endif
#ifdef PROC_PPC440
#define XREG_TCR_PIT_INTERRUPT_ENABLE XREG_TCR_DEC_INTERRUPT_ENABLE
#define XREG_TSR_PIT_INTERRUPT_STATUS XREG_TSR_DEC_INTERRUPT_STATUS
#define XREG_SPR_PIT XREG_SPR_DEC
#define XEXC_ID_PIT_INT XEXC_ID_DEC_INT
#endif
//--------------------------------------------------------------------
// Disable the Timer - During Profiling
//
// For PIT Timer -
// 1. XTime_PITDisableInterrupt() ;
// 2. Store the remaining timer clk tick
// 3. Stop the PIT Timer
//--------------------------------------------------------------------
#ifdef PPC_PIT_INTERRUPT
#define disable_timer() \
{ \
unsigned long val; \
val=mfspr(XREG_SPR_TCR); \
mtspr(XREG_SPR_TCR, val & ~XREG_TCR_PIT_INTERRUPT_ENABLE); \
timer_lo_clk_ticks = mfspr(XREG_SPR_PIT); \
mtspr(XREG_SPR_PIT, 0); \
}
#else
#define disable_timer() \
{ \
u32 addr = (PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET; \
u32 tmp_v = ProfIo_In32(addr); \
tmp_v = tmp_v & ~XTC_CSR_ENABLE_TMR_MASK; \
ProfIo_Out32((PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET, tmp_v); \
}
#endif
//--------------------------------------------------------------------
// Enable the Timer
//
// For PIT Timer -
// 1. Load the remaining timer clk ticks
// 2. XTime_PITEnableInterrupt() ;
//--------------------------------------------------------------------
#ifdef PPC_PIT_INTERRUPT
#define enable_timer() \
{ \
unsigned long val; \
val=mfspr(XREG_SPR_TCR); \
mtspr(XREG_SPR_PIT, timer_lo_clk_ticks); \
mtspr(XREG_SPR_TCR, val | XREG_TCR_PIT_INTERRUPT_ENABLE); \
}
#else
#define enable_timer() \
{ \
u32 addr = (PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET; \
u32 tmp_v = ProfIo_In32(addr); \
tmp_v = tmp_v | XTC_CSR_ENABLE_TMR_MASK; \
ProfIo_Out32((PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET, tmp_v); \
}
#endif
//--------------------------------------------------------------------
// Send Ack to Timer Interrupt
//
// For PIT Timer -
// 1. Load the timer clk ticks
// 2. Enable AutoReload and Interrupt
// 3. Clear PIT Timer Status bits
//--------------------------------------------------------------------
#ifdef PPC_PIT_INTERRUPT
#define timer_ack() \
{ \
unsigned long val; \
mtspr(XREG_SPR_PIT, timer_clk_ticks); \
mtspr(XREG_SPR_TSR, XREG_TSR_PIT_INTERRUPT_STATUS); \
val=mfspr(XREG_SPR_TCR); \
mtspr(XREG_SPR_TCR, val| XREG_TCR_PIT_INTERRUPT_ENABLE| XREG_TCR_AUTORELOAD_ENABLE); \
}
#else
#define timer_ack() \
{ \
unsigned int csr; \
csr = ProfTmrCtr_mGetControlStatusReg(PROFILE_TIMER_BASEADDR, 0); \
ProfTmrCtr_mSetControlStatusReg(PROFILE_TIMER_BASEADDR, 0, csr); \
}
#endif
//--------------------------------------------------------------------
#endif // PROC_PPC
//--------------------------------------------------------------------
//--------------------------------------------------------------------
// MicroBlaze Target - Timer related functions
//--------------------------------------------------------------------
#ifdef PROC_MICROBLAZE
//--------------------------------------------------------------------
// Disable the Timer during Call-Graph Data collection
//
//--------------------------------------------------------------------
#define disable_timer() \
{ \
u32 addr = (PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET; \
u32 tmp_v = ProfIo_In32(addr); \
tmp_v = tmp_v & ~XTC_CSR_ENABLE_TMR_MASK; \
ProfIo_Out32((PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET, tmp_v); \
}
//--------------------------------------------------------------------
// Enable the Timer after Call-Graph Data collection
//
//--------------------------------------------------------------------
#define enable_timer() \
{ \
u32 addr = (PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET; \
u32 tmp_v = ProfIo_In32(addr); \
tmp_v = tmp_v | XTC_CSR_ENABLE_TMR_MASK; \
ProfIo_Out32((PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET, tmp_v); \
}
//--------------------------------------------------------------------
// Send Ack to Timer Interrupt
//
//--------------------------------------------------------------------
#define timer_ack() \
{ \
unsigned int csr; \
csr = ProfTmrCtr_mGetControlStatusReg(PROFILE_TIMER_BASEADDR, 0); \
ProfTmrCtr_mSetControlStatusReg(PROFILE_TIMER_BASEADDR, 0, csr); \
}
//--------------------------------------------------------------------
#endif // PROC_MICROBLAZE
//--------------------------------------------------------------------
//--------------------------------------------------------------------
// Cortex A9 Target - Timer related functions
//--------------------------------------------------------------------
#ifdef PROC_CORTEXA9
//--------------------------------------------------------------------
// Disable the Timer during Call-Graph Data collection
//
//--------------------------------------------------------------------
#define disable_timer() \
{ \
u32 Reg; \
Reg = Xil_In32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET); \
Reg &= ~XSCUTIMER_CONTROL_ENABLE_MASK;\
Xil_Out32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET, Reg);\
} \
//--------------------------------------------------------------------
// Enable the Timer after Call-Graph Data collection
//
//--------------------------------------------------------------------
#define enable_timer() \
{ \
u32 Reg; \
Reg = Xil_In32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET); \
Reg |= XSCUTIMER_CONTROL_ENABLE_MASK; \
Xil_Out32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET, Reg);\
} \
//--------------------------------------------------------------------
// Send Ack to Timer Interrupt
//
//--------------------------------------------------------------------
#define timer_ack() \
{ \
Xil_Out32(PROFILE_TIMER_BASEADDR + XSCUTIMER_ISR_OFFSET, \
XSCUTIMER_ISR_EVENT_FLAG_MASK);\
}
//--------------------------------------------------------------------
#endif // PROC_CORTEXA9
//--------------------------------------------------------------------
#ifdef __cplusplus
}
#endif
#endif

50
software/LED_Controller_bsp/microblaze_mcs/libsrc/standalone_v3_11_a/src/profile/dummy.S Executable file
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@@ -0,0 +1,50 @@
//
// Copyright (c) 2002 Xilinx, Inc. All rights reserved.
// Xilinx, Inc.
//
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
// AND FITNESS FOR A PARTICULAR PURPOSE.
//
// $Id: dummy.S,v 1.1.2.1 2011/05/17 04:37:56 sadanan Exp $
//
.globl dummy_f
#ifdef PROC_MICROBLAZE
.text
.align 2
.ent dummy_f
dummy_f:
nop
.end dummy_f
#endif
#ifdef PROC_PPC
.section .text
.align 2
.type dummy_f@function
dummy_f:
b dummy_f
#endif
#ifdef PROC_CORTEXA9
.section .text
.align 2
.type dummy_f, %function
dummy_f:
b dummy_f
#endif

51
software/LED_Controller_bsp/microblaze_mcs/libsrc/standalone_v3_11_a/src/profile/mblaze_nt_types.h Executable file
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@@ -0,0 +1,51 @@
//////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2002-11 Xilinx, Inc. All rights reserved.
// Xilinx, Inc.
//
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
// AND FITNESS FOR A PARTICULAR PURPOSE.
//
// $Id: mblaze_nt_types.h,v 1.1.2.2 2011/05/30 06:46:18 svemula Exp $
//
//////////////////////////////////////////////////////////////////////
#ifndef _MBLAZE_NT_TYPES_H
#define _MBLAZE_NT_TYPES_H
#ifdef __cplusplus
extern "C" {
#endif
typedef char byte;
typedef short half;
typedef int word;
typedef unsigned char ubyte;
typedef unsigned short uhalf;
typedef unsigned int uword;
typedef ubyte boolean;
//typedef unsigned char u_char;
//typedef unsigned short u_short;
//typedef unsigned int u_int;
//typedef unsigned long u_long;
typedef short int16_t;
typedef unsigned short uint16_t;
typedef int int32_t;
typedef unsigned int uint32_t;
#ifdef __cplusplus
}
#endif
#endif

127
software/LED_Controller_bsp/microblaze_mcs/libsrc/standalone_v3_11_a/src/profile/profile.h Executable file
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@@ -0,0 +1,127 @@
//////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2002-11 Xilinx, Inc. All rights reserved.
// Xilinx, Inc.
//
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
// AND FITNESS FOR A PARTICULAR PURPOSE.
//
// $Id: profile.h,v 1.1.2.2 2011/05/30 06:46:18 svemula Exp $
//
//////////////////////////////////////////////////////////////////////
#ifndef _PROFILE_H
#define _PROFILE_H 1
#include <stdio.h>
#include "mblaze_nt_types.h"
#include "profile_config.h"
#ifdef __cplusplus
extern "C" {
#endif
void _system_init( void ) ;
void _system_clean( void ) ;
void mcount(unsigned long frompc, unsigned long selfpc);
void profile_intr_handler( void ) ;
/****************************************************************************
* Profiling on hardware - Hash table maintained on hardware and data sent
* to xmd for gmon.out generation.
****************************************************************************/
/*
* histogram counters are unsigned shorts (according to the kernel).
*/
#define HISTCOUNTER unsigned short
struct tostruct {
unsigned long selfpc;
long count;
short link;
unsigned short pad;
};
struct fromstruct {
unsigned long frompc ;
short link ;
unsigned short pad ;
} ;
/*
* general rounding functions.
*/
#define ROUNDDOWN(x,y) (((x)/(y))*(y))
#define ROUNDUP(x,y) ((((x)+(y)-1)/(y))*(y))
/*
* The profiling data structures are housed in this structure.
*/
struct gmonparam {
long int state;
// Histogram Information
unsigned short *kcount; /* No. of bins in histogram */
unsigned long kcountsize; /* Histogram samples */
// Call-graph Information
struct fromstruct *froms;
unsigned long fromssize;
struct tostruct *tos;
unsigned long tossize;
// Initialization I/Ps
unsigned long lowpc;
unsigned long highpc;
unsigned long textsize;
//unsigned long cg_froms;
//unsigned long cg_tos;
};
extern struct gmonparam *_gmonparam;
extern int n_gmon_sections;
/*
* Possible states of profiling.
*/
#define GMON_PROF_ON 0
#define GMON_PROF_BUSY 1
#define GMON_PROF_ERROR 2
#define GMON_PROF_OFF 3
/*
* Sysctl definitions for extracting profiling information from the kernel.
*/
#define GPROF_STATE 0 /* int: profiling enabling variable */
#define GPROF_COUNT 1 /* struct: profile tick count buffer */
#define GPROF_FROMS 2 /* struct: from location hash bucket */
#define GPROF_TOS 3 /* struct: destination/count structure */
#define GPROF_GMONPARAM 4 /* struct: profiling parameters (see above) */
#ifdef __cplusplus
}
#endif
#endif /* _PROFILE_H */

146
software/LED_Controller_bsp/microblaze_mcs/libsrc/standalone_v3_11_a/src/profile/profile_cg.c Executable file
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@@ -0,0 +1,146 @@
//
// Copyright (c) 2002-2010 Xilinx, Inc. All rights reserved.
// Xilinx, Inc.
//
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
// AND FITNESS FOR A PARTICULAR PURPOSE.
//
// $Id: profile_cg.c,v 1.1.2.1 2011/05/17 04:37:57 sadanan Exp $
//
#include "mblaze_nt_types.h"
#include "profile.h"
#include "_profile_timer_hw.h"
/*
* The mcount fucntion is excluded from the library, if the user defines
* PROFILE_NO_GRAPH.
*/
#ifndef PROFILE_NO_GRAPH
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
extern struct gmonparam *_gmonparam;
#ifdef PROFILE_NO_FUNCPTR
int searchpc( struct fromto_struct *cgtable, int cgtable_size, unsigned long frompc )
{
int index = 0 ;
while( (index < cgtable_size) && (cgtable[index].frompc != frompc) ){
index++ ;
}
if( index == cgtable_size )
return -1 ;
else
return index ;
}
#else
int searchpc( struct fromstruct *froms, int fromssize, unsigned long frompc )
{
int index = 0 ;
while( (index < fromssize) && (froms[index].frompc != frompc) ){
index++ ;
}
if( index == fromssize )
return -1 ;
else
return index ;
}
#endif /* PROFILE_NO_FUNCPTR */
void mcount( unsigned long frompc, unsigned long selfpc )
{
register struct gmonparam *p = NULL;
register long toindex, fromindex;
int j;
disable_timer();
//print("CG: "); putnum(frompc); print("->"); putnum(selfpc); print("\r\n");
// check that frompcindex is a reasonable pc value.
// for example: signal catchers get called from the stack,
// not from text space. too bad.
//
for(j = 0; j < n_gmon_sections; j++ ){
if((frompc >= _gmonparam[j].lowpc) && (frompc < _gmonparam[j].highpc)) {
p = &_gmonparam[j];
break;
}
}
if( j == n_gmon_sections )
goto done;
#ifdef PROFILE_NO_FUNCPTR
fromindex = searchpc( p->cgtable, p->cgtable_size, frompc ) ;
if( fromindex == -1 ) {
fromindex = p->cgtable_size ;
p->cgtable_size++ ;
p->cgtable[fromindex].frompc = frompc ;
p->cgtable[fromindex].selfpc = selfpc ;
p->cgtable[fromindex].count = 1 ;
goto done ;
}
p->cgtable[fromindex].count++ ;
#else
fromindex = searchpc( p->froms, p->fromssize, frompc ) ;
if( fromindex == -1 ) {
fromindex = p->fromssize ;
p->fromssize++ ;
//if( fromindex >= N_FROMS ) {
//print("Error : From PC table overflow\r\n") ;
//goto overflow ;
//}
p->froms[fromindex].frompc = frompc ;
p->froms[fromindex].link = -1 ;
}else {
toindex = p->froms[fromindex].link ;
while(toindex != -1) {
toindex = (p->tossize - toindex)-1 ;
if( p->tos[toindex].selfpc == selfpc ) {
p->tos[toindex].count++ ;
goto done ;
}
toindex = p->tos[toindex].link ;
}
}
//if( toindex == -1 ) {
p->tos-- ;
p->tossize++ ;
//if( toindex >= N_TOS ) {
//print("Error : To PC table overflow\r\n") ;
//goto overflow ;
//}
p->tos[0].selfpc = selfpc ;
p->tos[0].count = 1 ;
p->tos[0].link = p->froms[fromindex].link ;
p->froms[fromindex].link = p->tossize-1 ;
#endif
done:
p->state = GMON_PROF_ON;
goto enable_timer ;
//overflow:
p->state = GMON_PROF_ERROR;
enable_timer:
enable_timer();
return ;
}
#endif /* PROFILE_NO_GRAPH */

36
software/LED_Controller_bsp/microblaze_mcs/libsrc/standalone_v3_11_a/src/profile/profile_config.h Executable file
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@@ -0,0 +1,36 @@
//////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2002-11 Xilinx, Inc. All rights reserved.
// Xilinx, Inc.
//
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
// AND FITNESS FOR A PARTICULAR PURPOSE.
//
// $Id: profile_config.h,v 1.1.2.2 2011/05/30 06:46:18 svemula Exp $
//
//////////////////////////////////////////////////////////////////////
#ifndef _PROFILE_CONFIG_H
#define _PROFILE_CONFIG_H
#define BINSIZE 4
#define SAMPLE_FREQ_HZ 100000
#define TIMER_CLK_TICKS 1000
#define PROFILE_NO_FUNCPTR_FLAG 0
#define PROFILE_TIMER_BASEADDR 0x00608000
#define PROFILE_TIMER_INTR_ID 0
#define TIMER_CONNECT_INTC
#endif

53
software/LED_Controller_bsp/microblaze_mcs/libsrc/standalone_v3_11_a/src/profile/profile_hist.c Executable file
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@@ -0,0 +1,53 @@
//
// Copyright (c) 2002-2010 Xilinx, Inc. All rights reserved.
// Xilinx, Inc.
//
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
// AND FITNESS FOR A PARTICULAR PURPOSE.
//
// $Id: profile_hist.c,v 1.1.2.1 2011/05/17 04:37:57 sadanan Exp $
//
#include "profile.h"
#include "mblaze_nt_types.h"
#include "_profile_timer_hw.h"
#ifdef PROC_PPC
#include "xpseudo_asm.h"
#define SPR_SRR0 0x01A
#endif
extern int binsize ;
uint32_t prof_pc ;
void profile_intr_handler( void )
{
int j;
#ifdef PROC_MICROBLAZE
asm( "swi r14, r0, prof_pc" ) ;
#elif defined PROC_PPC
prof_pc = mfspr(SPR_SRR0);
#else
// for cortexa9, lr is saved in asm interrupt handler
#endif
//print("PC: "); putnum(prof_pc); print("\r\n");
for(j = 0; j < n_gmon_sections; j++ ){
if((prof_pc >= _gmonparam[j].lowpc) && (prof_pc < _gmonparam[j].highpc)) {
_gmonparam[j].kcount[(prof_pc-_gmonparam[j].lowpc)/(4 * binsize)]++;
break;
}
}
// Ack the Timer Interrupt
timer_ack();
}

33
software/LED_Controller_bsp/microblaze_mcs/libsrc/standalone_v3_11_a/src/profile/profile_mcount_arm.S Executable file
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@@ -0,0 +1,33 @@
//
// Copyright (c) 2012 Xilinx, Inc. All rights reserved.
// Xilinx, Inc.
//
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
// AND FITNESS FOR A PARTICULAR PURPOSE.
//
// $Id: profile_mcount_arm.S,v 1.1.2.1 2011/05/17 04:37:57 sadanan Exp $
//
// based on "ARM Profiling Implementation" from Sourcery G++ Lite for ARM EABI
.globl __gnu_mcount_nc
.type __gnu_mcount_nc, %function
__gnu_mcount_nc:
push {r0, r1, r2, r3, lr}
subs r1, lr, #0 /* callee - current lr */
ldr r0, [sp, #20] /* caller - at the top of the stack */
bl mcount /* when __gnu_mcount_nc is called */
pop {r0, r1, r2, r3, ip, lr}
bx ip
.end __gnu_mcount_nc

55
software/LED_Controller_bsp/microblaze_mcs/libsrc/standalone_v3_11_a/src/profile/profile_mcount_mb.S Executable file
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@@ -0,0 +1,55 @@
//
// Copyright (c) 2002 Xilinx, Inc. All rights reserved.
// Xilinx, Inc.
//
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
// AND FITNESS FOR A PARTICULAR PURPOSE.
//
// $Id: profile_mcount_mb.S,v 1.1.2.1 2011/05/17 04:37:58 sadanan Exp $
//
.globl _mcount
.text
.align 2
.ent _mcount
#ifndef PROFILE_NO_GRAPH
_mcount:
addi r1, r1, -48
swi r11, r1, 44
swi r12, r1, 40
swi r5, r1, 36
swi r6, r1, 32
swi r7, r1, 28
swi r8, r1, 24
swi r9, r1, 20
swi r10, r1, 16
swi r16, r1, 12
add r5, r0, r15
brlid r15, mcount
add r6, r0, r16
lwi r11, r1, 44
lwi r12, r1, 40
lwi r5, r1, 36
lwi r6, r1, 32
lwi r7, r1, 28
lwi r8, r1, 24
lwi r9, r1, 20
lwi r10, r1, 16
lwi r16, r1, 12
rtbd r16, 4
addi r1, r1, 48
#endif /* PROFILE_NO_GRAPH */
.end _mcount

58
software/LED_Controller_bsp/microblaze_mcs/libsrc/standalone_v3_11_a/src/profile/profile_mcount_ppc.S Executable file
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@@ -0,0 +1,58 @@
//
// Copyright (c) 2002 Xilinx, Inc. All rights reserved.
// Xilinx, Inc.
//
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
// AND FITNESS FOR A PARTICULAR PURPOSE.
//
// $Id: profile_mcount_ppc.S,v 1.1.2.1 2011/05/17 04:37:58 sadanan Exp $
//
.globl _mcount
#define _MCOUNT_STACK_FRAME 48
.section .text
.align 2
.type _mcount@function
_mcount:
stwu 1, -_MCOUNT_STACK_FRAME(1)
stw 3, 8(1)
stw 4, 12(1)
stw 5, 16(1)
stw 6, 20(1)
stw 7, 24(1)
stw 8, 28(1)
stw 9, 32(1)
stw 10, 36(1)
stw 11, 40(1)
stw 12, 44(1)
mflr 4
stw 4, (_MCOUNT_STACK_FRAME+4)(1)
lwz 3, (_MCOUNT_STACK_FRAME)(1)
lwz 3, 4(3)
bl mcount
lwz 4, (_MCOUNT_STACK_FRAME+4)(1)
mtlr 4
lwz 12, 44(1)
lwz 11, 40(1)
lwz 10, 36(1)
lwz 9, 32(1)
lwz 8, 28(1)
lwz 7, 24(1)
lwz 6, 20(1)
lwz 5, 16(1)
lwz 4, 12(1)
lwz 3, 8(1)
addi 1,1, _MCOUNT_STACK_FRAME
blr

70
software/LED_Controller_bsp/microblaze_mcs/libsrc/standalone_v3_11_a/src/pvr.c Executable file
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@@ -0,0 +1,70 @@
////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2006 Xilinx, Inc. All rights reserved.
//
// Xilinx, Inc.
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
// AND FITNESS FOR A PARTICULAR PURPOSE.
//
// $Id: pvr.c,v 1.1.2.1 2011/05/17 04:37:33 sadanan Exp $
////////////////////////////////////////////////////////////////////////////////
/*****************************************************************************/
/**
*
* @file pvr.c
*
* This header file contains defines for structures used by the microblaze
* PVR routines
*
******************************************************************************/
#include "xparameters.h"
#include "pvr.h"
#include <string.h>
/* Definitions */
int microblaze_get_pvr (pvr_t *pvr)
{
if (!pvr)
return -1;
bzero ((void*)pvr, sizeof (pvr_t));
#ifdef MICROBLAZE_PVR_NONE
return -1;
#else
getpvr (0, pvr->pvr[0]);
#endif /* MICROBLAZE_PVR_NONE */
#ifdef MICROBLAZE_PVR_FULL
getpvr (1, pvr->pvr[1]);
getpvr (2, pvr->pvr[2]);
getpvr (3, pvr->pvr[3]);
getpvr (4, pvr->pvr[4]);
getpvr (5, pvr->pvr[5]);
getpvr (6, pvr->pvr[6]);
getpvr (7, pvr->pvr[7]);
getpvr (8, pvr->pvr[8]);
getpvr (9, pvr->pvr[9]);
getpvr (10, pvr->pvr[10]);
getpvr (11, pvr->pvr[11]);
/* getpvr (12, pvr->pvr[12]); */
/* getpvr (13, pvr->pvr[13]); */
/* getpvr (14, pvr->pvr[14]); */
/* getpvr (15, pvr->pvr[15]); */
#endif /* MICROBLAZE_PVR_FULL */
return 0;
}

264
software/LED_Controller_bsp/microblaze_mcs/libsrc/standalone_v3_11_a/src/pvr.h Executable file
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@@ -0,0 +1,264 @@
////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2006-2011 Xilinx, Inc. All rights reserved.
//
// Xilinx, Inc.
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
// AND FITNESS FOR A PARTICULAR PURPOSE.
//
// $Id: pvr.h,v 1.1.2.1 2011/05/17 04:37:34 sadanan Exp $
////////////////////////////////////////////////////////////////////////////////
/*****************************************************************************/
/**
*
* @file pvr.h
*
* This header file contains defines for structures used by the microblaze
* PVR routines
*
******************************************************************************/
#ifndef _PVR_H
#define _PVR_H
#include "xbasic_types.h"
#include "xparameters.h"
#include "mb_interface.h"
#include "bspconfig.h"
#ifdef __cplusplus
extern "C" {
#endif
/* Defs */
typedef struct pvr_s {
#ifdef MICROBLAZE_PVR_FULL
unsigned int pvr[16];
#else
unsigned int pvr[1];
#endif
} pvr_t;
#define getpvr(pvrid, val) asm volatile ("mfs\t%0,rpvr" stringify(pvrid) "\n\t" : "=d" (val))
/* Basic PVR mask */
#define MICROBLAZE_PVR0_PVR_FULL_MASK 0x80000000
#define MICROBLAZE_PVR0_USE_BARREL_MASK 0x40000000
#define MICROBLAZE_PVR0_USE_DIV_MASK 0x20000000
#define MICROBLAZE_PVR0_USE_HW_MUL_MASK 0x10000000
#define MICROBLAZE_PVR0_USE_FPU_MASK 0x08000000
#define MICROBLAZE_PVR0_USE_EXCEPTION_MASK 0x04000000
#define MICROBLAZE_PVR0_USE_ICACHE_MASK 0x02000000
#define MICROBLAZE_PVR0_USE_DCACHE_MASK 0x01000000
#define MICROBLAZE_PVR0_USE_MMU_MASK 0x00800000
#define MICROBLAZE_PVR0_USE_BTC_MASK 0x00400000
#define MICROBLAZE_PVR0_ENDIANNESS_MASK 0x00200000
#define MICROBLAZE_PVR0_FAULT_TOLERANT_MASK 0x00100000
#define MICROBLAZE_PVR0_STACK_PROTECTION_MASK 0x00080000
#define MICROBLAZE_PVR0_MICROBLAZE_VERSION_MASK 0x0000FF00
#define MICROBLAZE_PVR0_USER1_MASK 0x000000FF
/* User 2 PVR mask */
#define MICROBLAZE_PVR1_USER2_MASK 0xFFFFFFFF
/* Configuration PVR masks */
#define MICROBLAZE_PVR2_D_AXI_MASK 0x80000000
#define MICROBLAZE_PVR2_D_LMB_MASK 0x40000000
#define MICROBLAZE_PVR2_D_PLB_MASK 0x02000000
#define MICROBLAZE_PVR2_I_AXI_MASK 0x20000000
#define MICROBLAZE_PVR2_I_LMB_MASK 0x10000000
#define MICROBLAZE_PVR2_I_PLB_MASK 0x01000000
#define MICROBLAZE_PVR2_INTERRUPT_IS_EDGE_MASK 0x08000000
#define MICROBLAZE_PVR2_EDGE_IS_POSITIVE_MASK 0x04000000
#define MICROBLAZE_PVR2_INTERCONNECT_MASK 0x00800000
#define MICROBLAZE_PVR2_STREAM_INTERCONNECT_MASK 0x00400000
#define MICROBLAZE_PVR2_USE_EXTENDED_FSL_INSTR_MASK 0x00080000
#define MICROBLAZE_PVR2_USE_MSR_INSTR_MASK 0x00020000
#define MICROBLAZE_PVR2_USE_PCMP_INSTR_MASK 0x00010000
#define MICROBLAZE_PVR2_AREA_OPTIMIZED_MASK 0x00008000
#define MICROBLAZE_PVR2_USE_BARREL_MASK 0x00004000
#define MICROBLAZE_PVR2_USE_DIV_MASK 0x00002000
#define MICROBLAZE_PVR2_USE_HW_MUL_MASK 0x00001000
#define MICROBLAZE_PVR2_USE_FPU_MASK 0x00000800
#define MICROBLAZE_PVR2_USE_FPU2_MASK 0x00000200
#define MICROBLAZE_PVR2_USE_MUL64_MASK 0x00000400
#define MICROBLAZE_PVR2_OPCODE_0x0_ILLEGAL_MASK 0x00000040
#define MICROBLAZE_PVR2_UNALIGNED_EXCEPTION_MASK 0x00000020
#define MICROBLAZE_PVR2_ILL_OPCODE_EXCEPTION_MASK 0x00000010
#define MICROBLAZE_PVR2_M_AXI_I_BUS_EXCEPTION_MASK 0x00000008
#define MICROBLAZE_PVR2_M_AXI_D_BUS_EXCEPTION_MASK 0x00000004
#define MICROBLAZE_PVR2_IPLB_BUS_EXCEPTION_MASK 0x00000100
#define MICROBLAZE_PVR2_DPLB_BUS_EXCEPTION_MASK 0x00000080
#define MICROBLAZE_PVR2_DIV_ZERO_EXCEPTION_MASK 0x00000002
#define MICROBLAZE_PVR2_FPU_EXCEPTION_MASK 0x00000001
#define MICROBLAZE_PVR2_FSL_EXCEPTION_MASK 0x00040000
/* Debug and exception PVR masks */
#define MICROBLAZE_PVR3_DEBUG_ENABLED_MASK 0x80000000
#define MICROBLAZE_PVR3_NUMBER_OF_PC_BRK_MASK 0x1E000000
#define MICROBLAZE_PVR3_NUMBER_OF_RD_ADDR_BRK_MASK 0x00380000
#define MICROBLAZE_PVR3_NUMBER_OF_WR_ADDR_BRK_MASK 0x0000E000
#define MICROBLAZE_PVR3_FSL_LINKS_MASK 0x00000380
#define MICROBLAZE_PVR3_BTC_SIZE_MASK 0x00000007
/* ICache config PVR masks */
#define MICROBLAZE_PVR4_USE_ICACHE_MASK 0x80000000
#define MICROBLAZE_PVR4_ICACHE_ADDR_TAG_BITS_MASK 0x7C000000
#define MICROBLAZE_PVR4_ICACHE_ALLOW_WR_MASK 0x01000000
#define MICROBLAZE_PVR4_ICACHE_LINE_LEN_MASK 0x00E00000
#define MICROBLAZE_PVR4_ICACHE_BYTE_SIZE_MASK 0x001F0000
#define MICROBLAZE_PVR4_ICACHE_ALWAYS_USED_MASK 0x00008000
#define MICROBLAZE_PVR4_ICACHE_INTERFACE_MASK 0x00002000
#define MICROBLAZE_PVR4_ICACHE_VICTIMS_MASK 0x00001C00
#define MICROBLAZE_PVR4_ICACHE_STREAMS_MASK 0x00000300
#define MICROBLAZE_PVR4_ICACHE_FORCE_TAG_LUTRAM_MASK 0x00000080
#define MICROBLAZE_PVR4_ICACHE_DATA_WIDTH_MASK 0x00000040
/* DCache config PVR masks */
#define MICROBLAZE_PVR5_USE_DCACHE_MASK 0x80000000
#define MICROBLAZE_PVR5_DCACHE_ADDR_TAG_BITS_MASK 0x7C000000
#define MICROBLAZE_PVR5_DCACHE_ALLOW_WR_MASK 0x01000000
#define MICROBLAZE_PVR5_DCACHE_LINE_LEN_MASK 0x00E00000
#define MICROBLAZE_PVR5_DCACHE_BYTE_SIZE_MASK 0x001F0000
#define MICROBLAZE_PVR5_DCACHE_ALWAYS_USED_MASK 0x00008000
#define MICROBLAZE_PVR5_DCACHE_USE_WRITEBACK_MASK 0x00004000
#define MICROBLAZE_PVR5_DCACHE_INTERFACE_MASK 0x00002000
#define MICROBLAZE_PVR5_DCACHE_VICTIMS_MASK 0x00001C00
#define MICROBLAZE_PVR5_DCACHE_FORCE_TAG_LUTRAM_MASK 0x00000080
#define MICROBLAZE_PVR5_DCACHE_DATA_WIDTH_MASK 0x00000040
/* ICache base address PVR mask */
#define MICROBLAZE_PVR6_ICACHE_BASEADDR_MASK 0xFFFFFFFF
/* ICache high address PVR mask */
#define MICROBLAZE_PVR7_ICACHE_HIGHADDR_MASK 0xFFFFFFFF
/* DCache base address PVR mask */
#define MICROBLAZE_PVR8_DCACHE_BASEADDR_MASK 0xFFFFFFFF
/* DCache high address PVR mask */
#define MICROBLAZE_PVR9_DCACHE_HIGHADDR_MASK 0xFFFFFFFF
/* Target family PVR mask */
#define MICROBLAZE_PVR10_TARGET_FAMILY_MASK 0xFF000000
/* MSR Reset value PVR mask */
#define MICROBLAZE_PVR11_MSR_RESET_VALUE_MASK 0x000007FF
/* MMU value PVR mask */
#define MICROBLAZE_PVR11_MMU_MASK 0xC0000000
#define MICROBLAZE_PVR11_MMU_ITLB_SIZE_MASK 0x38000000
#define MICROBLAZE_PVR11_MMU_DTLB_SIZE_MASK 0x07000000
#define MICROBLAZE_PVR11_MMU_TLB_ACCESS_MASK 0x00C00000
#define MICROBLAZE_PVR11_MMU_ZONES_MASK 0x003E0000
#define MICROBLAZE_PVR11_MMU_PRIVILEGED_INSTR_MASK 0x00010000
/* PVR access macros */
#define MICROBLAZE_PVR_IS_FULL(_pvr) (_pvr.pvr[0] & MICROBLAZE_PVR0_PVR_FULL_MASK)
#define MICROBLAZE_PVR_USE_BARREL(_pvr) (_pvr.pvr[0] & MICROBLAZE_PVR0_USE_BARREL_MASK)
#define MICROBLAZE_PVR_USE_DIV(_pvr) (_pvr.pvr[0] & MICROBLAZE_PVR0_USE_DIV_MASK)
#define MICROBLAZE_PVR_USE_HW_MUL(_pvr) (_pvr.pvr[0] & MICROBLAZE_PVR0_USE_HW_MUL_MASK)
#define MICROBLAZE_PVR_USE_FPU(_pvr) (_pvr.pvr[0] & MICROBLAZE_PVR0_USE_FPU_MASK)
#define MICROBLAZE_PVR_USE_ICACHE(_pvr) (_pvr.pvr[0] & MICROBLAZE_PVR0_USE_ICACHE_MASK)
#define MICROBLAZE_PVR_USE_DCACHE(_pvr) (_pvr.pvr[0] & MICROBLAZE_PVR0_USE_DCACHE_MASK)
#define MICROBLAZE_PVR_USE_MMU(_pvr) (_pvr.pvr[0] & MICROBLAZE_PVR0_USE_MMU_MASK)
#define MICROBLAZE_PVR_USE_BTC(_pvr) (_pvr.pvr[0] & MICROBLAZE_PVR0_USE_BTC_MASK)
#define MICROBLAZE_PVR_ENDIANNESS(_pvr) (_pvr.pvr[0] & MICROBLAZE_PVR0_ENDIANNESS_MASK)
#define MICROBLAZE_PVR_FAULT_TOLERANT(_pvr) (_pvr.pvr[0] & MICROBLAZE_PVR0_FAULT_TOLERANT_MASK)
#define MICROBLAZE_PVR_STACK_PROTECTION(_pvr) (_pvr.pvr[0] & MICROBLAZE_PVR0_STACK_PROTECTION_MASK)
#define MICROBLAZE_PVR_MICROBLAZE_VERSION(_pvr) ((_pvr.pvr[0] & MICROBLAZE_PVR0_MICROBLAZE_VERSION_MASK) >> 8)
#define MICROBLAZE_PVR_USER1(_pvr) (_pvr.pvr[0] & MICROBLAZE_PVR0_USER1_MASK)
#define MICROBLAZE_PVR_USER2(_pvr) (_pvr.pvr[1] & MICROBLAZE_PVR1_USER2_MASK)
#define MICROBLAZE_PVR_D_AXI(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_D_AXI_MASK)
#define MICROBLAZE_PVR_D_LMB(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_D_LMB_MASK)
#define MICROBLAZE_PVR_D_PLB(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_D_PLB_MASK)
#define MICROBLAZE_PVR_I_AXI(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_I_AXI_MASK)
#define MICROBLAZE_PVR_I_LMB(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_I_LMB_MASK)
#define MICROBLAZE_PVR_I_PLB(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_I_PLB_MASK)
#define MICROBLAZE_PVR_INTERRUPT_IS_EDGE(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_INTERRUPT_IS_EDGE_MASK)
#define MICROBLAZE_PVR_EDGE_IS_POSITIVE(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_EDGE_IS_POSITIVE_MASK)
#define MICROBLAZE_PVR_INTERCONNECT(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_INTERCONNECT_MASK)
#define MICROBLAZE_PVR_STREAM_INTERCONNECT(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_STREAM_INTERCONNECT_MASK)
#define MICROBLAZE_PVR_USE_EXTENDED_FSL_INSTR(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_USE_EXTENDED_FSL_INSTR_MASK)
#define MICROBLAZE_PVR_USE_MSR_INSTR(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_USE_MSR_INSTR_MASK)
#define MICROBLAZE_PVR_USE_PCMP_INSTR(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_USE_PCMP_INSTR_MASK)
#define MICROBLAZE_PVR_AREA_OPTIMIZED(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_AREA_OPTIMIZED_MASK)
#define MICROBLAZE_PVR_USE_MUL64(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_USE_MUL64_MASK)
#define MICROBLAZE_PVR_OPCODE_0x0_ILLEGAL(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_OPCODE_0x0_ILLEGAL_MASK)
#define MICROBLAZE_PVR_UNALIGNED_EXCEPTION(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_UNALIGNED_EXCEPTION_MASK)
#define MICROBLAZE_PVR_ILL_OPCODE_EXCEPTION(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_ILL_OPCODE_EXCEPTION_MASK)
#define MICROBLAZE_PVR_M_AXI_I_BUS_EXCEPTION(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_M_AXI_I_BUS_EXCEPTION_MASK)
#define MICROBLAZE_PVR_IPLB_BUS_EXCEPTION(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_IPLB_BUS_EXCEPTION_MASK)
#define MICROBLAZE_PVR_M_AXI_D_BUS_EXCEPTION(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_M_AXI_D_BUS_EXCEPTION_MASK)
#define MICROBLAZE_PVR_DPLB_BUS_EXCEPTION(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_DPLB_BUS_EXCEPTION_MASK)
#define MICROBLAZE_PVR_DIV_ZERO_EXCEPTION(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_DIV_ZERO_EXCEPTION_MASK)
#define MICROBLAZE_PVR_FPU_EXCEPTION(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_FPU_EXCEPTION_MASK)
#define MICROBLAZE_PVR_FSL_EXCEPTION(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_FSL_EXCEPTION_MASK)
#define MICROBLAZE_PVR_DEBUG_ENABLED(_pvr) (_pvr.pvr[3] & MICROBLAZE_PVR3_DEBUG_ENABLED_MASK)
#define MICROBLAZE_PVR_NUMBER_OF_PC_BRK(_pvr) ((_pvr.pvr[3] & MICROBLAZE_PVR3_NUMBER_OF_PC_BRK_MASK) >> 25)
#define MICROBLAZE_PVR_NUMBER_OF_RD_ADDR_BRK(_pvr) ((_pvr.pvr[3] & MICROBLAZE_PVR3_NUMBER_OF_RD_ADDR_BRK_MASK) >> 19)
#define MICROBLAZE_PVR_NUMBER_OF_WR_ADDR_BRK(_pvr) ((_pvr.pvr[3] & MICROBLAZE_PVR3_NUMBER_OF_WR_ADDR_BRK_MASK) >> 13)
#define MICROBLAZE_PVR_FSL_LINKS(_pvr) ((_pvr.pvr[3] & MICROBLAZE_PVR3_FSL_LINKS_MASK) >> 7)
#define MICROBLAZE_PVR_BTC_SIZE(_pvr) (_pvr.pvr[3] & MICROBLAZE_PVR3_BTC_SIZE_MASK)
#define MICROBLAZE_PVR_ICACHE_ADDR_TAG_BITS(_pvr) ((_pvr.pvr[4] & MICROBLAZE_PVR4_ICACHE_ADDR_TAG_BITS_MASK) >> 26)
#define MICROBLAZE_PVR_ICACHE_ALLOW_WR(_pvr) (_pvr.pvr[4] & MICROBLAZE_PVR4_ICACHE_ALLOW_WR_MASK)
#define MICROBLAZE_PVR_ICACHE_LINE_LEN(_pvr) (1 << ((_pvr.pvr[4] & MICROBLAZE_PVR4_ICACHE_LINE_LEN_MASK) >> 21))
#define MICROBLAZE_PVR_ICACHE_BYTE_SIZE(_pvr) (1 << ((_pvr.pvr[4] & MICROBLAZE_PVR4_ICACHE_BYTE_SIZE_MASK) >> 16))
#define MICROBLAZE_PVR_ICACHE_ALWAYS_USED(_pvr) (_pvr.pvr[4] & MICROBLAZE_PVR4_ICACHE_ALWAYS_USED_MASK)
#define MICROBLAZE_PVR_ICACHE_INTERFACE(_pvr) (_pvr.pvr[4] & MICROBLAZE_PVR4_ICACHE_INTERFACE_MASK)
#define MICROBLAZE_PVR_ICACHE_VICTIMS(_pvr) ((_pvr.pvr[4] & MICROBLAZE_PVR4_ICACHE_VICTIMS_MASK) >> 10)
#define MICROBLAZE_PVR_ICACHE_STREAMS(_pvr) ((_pvr.pvr[4] & MICROBLAZE_PVR4_ICACHE_STREAMS_MASK) >> 8)
#define MICROBLAZE_PVR_ICACHE_FORCE_TAG_LUTRAM(_pvr) (_pvr.pvr[4] & MICROBLAZE_PVR4_ICACHE_FORCE_TAG_LUTRAM_MASK)
#define MICROBLAZE_PVR_ICACHE_DATA_WIDTH(_pvr) (_pvr.pvr[4] & MICROBLAZE_PVR4_ICACHE_DATA_WIDTH_MASK)
#define MICROBLAZE_PVR_DCACHE_ADDR_TAG_BITS(_pvr) ((_pvr.pvr[5] & MICROBLAZE_PVR5_DCACHE_ADDR_TAG_BITS_MASK) >> 26)
#define MICROBLAZE_PVR_DCACHE_ALLOW_WR(_pvr) (_pvr.pvr[5] & MICROBLAZE_PVR5_DCACHE_ALLOW_WR_MASK)
#define MICROBLAZE_PVR_DCACHE_LINE_LEN(_pvr) (1 << ((_pvr.pvr[5] & MICROBLAZE_PVR5_DCACHE_LINE_LEN_MASK) >> 21))
#define MICROBLAZE_PVR_DCACHE_BYTE_SIZE(_pvr) (1 << ((_pvr.pvr[5] & MICROBLAZE_PVR5_DCACHE_BYTE_SIZE_MASK) >> 16))
#define MICROBLAZE_PVR_DCACHE_ALWAYS_USED(_pvr) (_pvr.pvr[5] & MICROBLAZE_PVR5_DCACHE_ALWAYS_USED_MASK)
#define MICROBLAZE_PVR_DCACHE_USE_WRITEBACK(_pvr) (_pvr.pvr[5] & MICROBLAZE_PVR5_DCACHE_USE_WRITEBACK_MASK)
#define MICROBLAZE_PVR_DCACHE_INTERFACE(_pvr) (_pvr.pvr[5] & MICROBLAZE_PVR5_DCACHE_INTERFACE_MASK)
#define MICROBLAZE_PVR_DCACHE_VICTIMS(_pvr) ((_pvr.pvr[5] & MICROBLAZE_PVR5_DCACHE_VICTIMS_MASK) >> 10)
#define MICROBLAZE_PVR_DCACHE_FORCE_TAG_LUTRAM(_pvr) (_pvr.pvr[5] & MICROBLAZE_PVR5_DCACHE_FORCE_TAG_LUTRAM_MASK)
#define MICROBLAZE_PVR_DCACHE_DATA_WIDTH(_pvr) (_pvr.pvr[5] & MICROBLAZE_PVR5_DCACHE_DATA_WIDTH_MASK)
#define MICROBLAZE_PVR_ICACHE_BASEADDR(_pvr) (_pvr.pvr[6] & MICROBLAZE_PVR6_ICACHE_BASEADDR_MASK)
#define MICROBLAZE_PVR_ICACHE_HIGHADDR(_pvr) (_pvr.pvr[7] & MICROBLAZE_PVR7_ICACHE_HIGHADDR_MASK)
#define MICROBLAZE_PVR_DCACHE_BASEADDR(_pvr) (_pvr.pvr[8] & MICROBLAZE_PVR8_DCACHE_BASEADDR_MASK)
#define MICROBLAZE_PVR_DCACHE_HIGHADDR(_pvr) (_pvr.pvr[9] & MICROBLAZE_PVR9_DCACHE_HIGHADDR_MASK)
#define MICROBLAZE_PVR_TARGET_FAMILY(_pvr) ((_pvr.pvr[10] & MICROBLAZE_PVR10_TARGET_FAMILY_MASK) >> 24)
#define MICROBLAZE_PVR_MSR_RESET_VALUE(_pvr) (_pvr.pvr[11] & MICROBLAZE_PVR11_MSR_RESET_VALUE_MASK)
#define MICROBLAZE_PVR_MMU_TYPE(_pvr) ((_pvr.pvr[11] & MICROBLAZE_PVR11_MMU_MASK) >> 30)
#define MICROBLAZE_PVR_MMU_ITLB_SIZE(_pvr) ((_pvr.pvr[11] & MICROBLAZE_PVR11_MMU_ITLB_SIZE_MASK) >> 27)
#define MICROBLAZE_PVR_MMU_DTLB_SIZE(_pvr) ((_pvr.pvr[11] & MICROBLAZE_PVR11_MMU_DTLB_SIZE_MASK) >> 24)
#define MICROBLAZE_PVR_MMU_TLB_ACCESS(_pvr) ((_pvr.pvr[11] & MICROBLAZE_PVR11_MMU_TLB_ACCESS_MASK) >> 22)
#define MICROBLAZE_PVR_MMU_ZONES(_pvr) ((_pvr.pvr[11] & MICROBLAZE_PVR11_MMU_ZONES_MASK) >> 17)
#define MICROBLAZE_PVR_MMU_PRIVILEGED_INSTR(_pvr) ((_pvr.pvr[11] & MICROBLAZE_PVR11_MMU_PRIVILEGED_INSTR_MASK) >> 16)
/* Protos */
int microblaze_get_pvr (pvr_t *pvr);
#ifdef __cplusplus
}
#endif
#endif /* _PVR_H */

139
software/LED_Controller_bsp/microblaze_mcs/libsrc/standalone_v3_11_a/src/xil_assert.c Executable file
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@@ -0,0 +1,139 @@
/******************************************************************************
*
*
* (c) Copyright 2009 Xilinx, Inc. All rights reserved.
*
* This file contains confidential and proprietary information of Xilinx, Inc.
* and is protected under U.S. and international copyright and other
* intellectual property laws.
*
* DISCLAIMER
* This disclaimer is not a license and does not grant any rights to the
* materials distributed herewith. Except as otherwise provided in a valid
* license issued to you by Xilinx, and to the maximum extent permitted by
* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
* and (2) Xilinx shall not be liable (whether in contract or tort, including
* negligence, or under any other theory of liability) for any loss or damage
* of any kind or nature related to, arising under or in connection with these
* materials, including for any direct, or any indirect, special, incidental,
* or consequential loss or damage (including loss of data, profits, goodwill,
* or any type of loss or damage suffered as a result of any action brought by
* a third party) even if such damage or loss was reasonably foreseeable or
* Xilinx had been advised of the possibility of the same.
*
* CRITICAL APPLICATIONS
* Xilinx products are not designed or intended to be fail-safe, or for use in
* any application requiring fail-safe performance, such as life-support or
* safety devices or systems, Class III medical devices, nuclear facilities,
* applications related to the deployment of airbags, or any other applications
* that could lead to death, personal injury, or severe property or
* environmental damage (individually and collectively, "Critical
* Applications"). Customer assumes the sole risk and liability of any use of
* Xilinx products in Critical Applications, subject only to applicable laws
* and regulations governing limitations on product liability.
*
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
* AT ALL TIMES.
*
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xil_assert.c
*
* This file contains basic assert related functions for Xilinx software IP.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00a hbm 07/14/09 Initial release
* </pre>
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "xil_types.h"
#include "xil_assert.h"
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Variable Definitions *****************************/
/**
* This variable allows testing to be done easier with asserts. An assert
* sets this variable such that a driver can evaluate this variable
* to determine if an assert occurred.
*/
unsigned int Xil_AssertStatus;
/**
* This variable allows the assert functionality to be changed for testing
* such that it does not wait infinitely. Use the debugger to disable the
* waiting during testing of asserts.
*/
int Xil_AssertWait = TRUE;
/* The callback function to be invoked when an assert is taken */
static Xil_AssertCallback Xil_AssertCallbackRoutine = NULL;
/************************** Function Prototypes ******************************/
/*****************************************************************************/
/**
*
* Implement assert. Currently, it calls a user-defined callback function
* if one has been set. Then, it potentially enters an infinite loop depending
* on the value of the Xil_AssertWait variable.
*
* @param file is the name of the filename of the source
* @param line is the linenumber within File
*
* @return None.
*
* @note None.
*
******************************************************************************/
void Xil_Assert(const char *File, int Line)
{
/* if the callback has been set then invoke it */
if (Xil_AssertCallbackRoutine != 0) {
(*Xil_AssertCallbackRoutine)(File, Line);
}
/* if specified, wait indefinitely such that the assert will show up
* in testing
*/
while (Xil_AssertWait) {
}
}
/*****************************************************************************/
/**
*
* Set up a callback function to be invoked when an assert occurs. If there
* was already a callback installed, then it is replaced.
*
* @param routine is the callback to be invoked when an assert is taken
*
* @return None.
*
* @note This function has no effect if NDEBUG is set
*
******************************************************************************/
void Xil_AssertSetCallback(Xil_AssertCallback Routine)
{
Xil_AssertCallbackRoutine = Routine;
}

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