457 lines
14 KiB
C
Executable File
457 lines
14 KiB
C
Executable File
/******************************************************************************
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*
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* (c) Copyright 2009-2013 Xilinx, Inc. All rights reserved.
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*
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* This file contains confidential and proprietary information of Xilinx, Inc.
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* and is protected under U.S. and international copyright and other
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* intellectual property laws.
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*
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* DISCLAIMER
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* This disclaimer is not a license and does not grant any rights to the
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* materials distributed herewith. Except as otherwise provided in a valid
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* license issued to you by Xilinx, and to the maximum extent permitted by
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* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
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* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
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* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
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* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
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* and (2) Xilinx shall not be liable (whether in contract or tort, including
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* negligence, or under any other theory of liability) for any loss or damage
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* of any kind or nature related to, arising under or in connection with these
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* materials, including for any direct, or any indirect, special, incidental,
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* or consequential loss or damage (including loss of data, profits, goodwill,
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* or any type of loss or damage suffered as a result of any action brought by
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* a third party) even if such damage or loss was reasonably foreseeable or
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* Xilinx had been advised of the possibility of the same.
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*
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* CRITICAL APPLICATIONS
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* Xilinx products are not designed or intended to be fail-safe, or for use in
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* any application requiring fail-safe performance, such as life-support or
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* safety devices or systems, Class III medical devices, nuclear facilities,
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* applications related to the deployment of airbags, or any other applications
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* that could lead to death, personal injury, or severe property or
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* environmental damage (individually and collectively, "Critical
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* Applications"). Customer assumes the sole risk and liability of any use of
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* Xilinx products in Critical Applications, subject only to applicable laws
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* and regulations governing limitations on product liability.
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*
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* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
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* AT ALL TIMES.
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*
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******************************************************************************/
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/*****************************************************************************/
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/**
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*
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* @file xil_cache.h
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*
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* This header file contains cache related driver functions (or macros)
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* that can be used to access the device. The user should refer to the
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* hardware device specification for more details of the device operation.
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* The functions in this header file can be used across all Xilinx supported
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* processors.
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*
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* <pre>
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* MODIFICATION HISTORY:
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*
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* Ver Who Date Changes
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* ----- ---- -------- -------------------------------------------------------
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* 1.00 hbm 07/28/09 Initial release
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* 3.02a sdm 10/24/11 Updated the file to include xparameters.h so that
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* the correct cache flush routines are used based on
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* whether the write-back or write-through caches are
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* used (cr #630532).
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* 3.10a asa 05/04/13 This version of MicroBlaze BSP adds support for system
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* cache/L2 cache. The existing/old APIs/macros in this
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* file are renamed to imply that they deal with L1 cache.
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* New macros/APIs are added to address similar features for
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* L2 cache. Users can include this file in their application
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* to use the various cache related APIs. These changes are
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* done for implementing PR #697214.
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*
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* </pre>
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*
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* @note
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*
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* None.
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*
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******************************************************************************/
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#ifndef XIL_CACHE_H
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#define XIL_CACHE_H
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#if defined XENV_VXWORKS
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/* VxWorks environment */
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#error "Unknown processor / architecture. Must be PPC for VxWorks."
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#else
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/* standalone environment */
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#include "mb_interface.h"
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#include "xil_types.h"
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#include "xparameters.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/****************************************************************************/
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/**
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*
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* Invalidate the entire L1 data cache. If the cacheline is modified (dirty),
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* the modified contents are lost.
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*
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* @param None.
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*
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* @return None.
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*
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* @note
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*
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* Processor must be in real mode.
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****************************************************************************/
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#define Xil_L1DCacheInvalidate() microblaze_invalidate_dcache()
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/****************************************************************************/
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/**
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*
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* Invalidate the entire L2 data cache. If the cacheline is modified (dirty),
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* the modified contents are lost.
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*
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* @param None.
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*
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* @return None.
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*
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* @note
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*
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* Processor must be in real mode.
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****************************************************************************/
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#define Xil_L2CacheInvalidate() microblaze_invalidate_cache_ext()
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/****************************************************************************/
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/**
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*
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* Invalidate the L1 data cache for the given address range.
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* If the bytes specified by the address (Addr) are cached by the L1 data cache,
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* the cacheline containing that byte is invalidated. If the cacheline
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* is modified (dirty), the modified contents are lost.
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*
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* @param Addr is address of ragne to be invalidated.
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* @param Len is the length in bytes to be invalidated.
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*
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* @return None.
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*
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* @note
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*
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* Processor must be in real mode.
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****************************************************************************/
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#define Xil_L1DCacheInvalidateRange(Addr, Len) \
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microblaze_invalidate_dcache_range(Addr, Len)
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/****************************************************************************/
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/**
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*
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* Invalidate the L1 data cache for the given address range.
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* If the bytes specified by the address (Addr) are cached by the L1 data cache,
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* the cacheline containing that byte is invalidated. If the cacheline
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* is modified (dirty), the modified contents are lost.
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*
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* @param Addr is address of ragne to be invalidated.
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* @param Len is the length in bytes to be invalidated.
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*
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* @return None.
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*
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* @note
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*
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* Processor must be in real mode.
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****************************************************************************/
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#define Xil_L2CacheInvalidateRange(Addr, Len) \
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microblaze_invalidate_cache_ext_range(Addr, Len)
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/****************************************************************************/
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/**
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* Flush the L1 data cache for the given address range.
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* If the bytes specified by the address (Addr) are cached by the data cache,
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* and is modified (dirty), the cacheline will be written to system memory.
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* The cacheline will also be invalidated.
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*
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* @param Addr is the starting address of the range to be flushed.
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* @param Len is the length in byte to be flushed.
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*
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* @return None.
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*
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****************************************************************************/
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#if (XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK == 1)
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# define Xil_L1DCacheFlushRange(Addr, Len) \
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microblaze_flush_dcache_range(Addr, Len)
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#else
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# define Xil_L1DCacheFlushRange(Addr, Len) \
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microblaze_invalidate_dcache_range(Addr, Len)
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#endif /* XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK */
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/****************************************************************************/
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/**
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* Flush the L2 data cache for the given address range.
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* If the bytes specified by the address (Addr) are cached by the data cache,
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* and is modified (dirty), the cacheline will be written to system memory.
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* The cacheline will also be invalidated.
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*
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* @param Addr is the starting address of the range to be flushed.
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* @param Len is the length in byte to be flushed.
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*
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* @return None.
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*
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****************************************************************************/
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#define Xil_L2CacheFlushRange(Addr, Len) \
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microblaze_flush_cache_ext_range(Addr, Len)
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/****************************************************************************/
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/**
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* Flush the entire L1 data cache. If any cacheline is dirty, the cacheline will be
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* written to system memory. The entire data cache will be invalidated.
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*
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* @return None.
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*
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* @note
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*
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****************************************************************************/
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#if (XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK == 1)
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# define Xil_L1DCacheFlush() microblaze_flush_dcache()
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#else
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# define Xil_L1DCacheFlush() microblaze_invalidate_dcache()
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#endif /* XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK */
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/****************************************************************************/
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/**
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* Flush the entire L2 data cache. If any cacheline is dirty, the cacheline will be
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* written to system memory. The entire data cache will be invalidated.
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*
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* @return None.
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*
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* @note
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*
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****************************************************************************/
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#define Xil_L2CacheFlush() microblaze_flush_cache_ext()
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/****************************************************************************/
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/**
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*
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* Invalidate the instruction cache for the given address range.
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*
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* @param Addr is address of ragne to be invalidated.
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* @param Len is the length in bytes to be invalidated.
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*
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* @return None.
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*
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****************************************************************************/
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#define Xil_L1ICacheInvalidateRange(Addr, Len) \
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microblaze_invalidate_icache_range(Addr, Len)
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/****************************************************************************/
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/**
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*
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* Invalidate the entire instruction cache.
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*
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* @param None
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*
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* @return None.
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*
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****************************************************************************/
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#define Xil_L1ICacheInvalidate() \
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microblaze_invalidate_icache()
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/****************************************************************************/
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/**
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*
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* Enable the L1 data cache.
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*
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* @return None.
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*
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* @note This is processor specific.
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*
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****************************************************************************/
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#define Xil_L1DCacheEnable() \
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microblaze_enable_dcache()
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/****************************************************************************/
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/**
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*
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* Disable the L1 data cache.
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*
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* @return None.
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*
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* @note This is processor specific.
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*
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****************************************************************************/
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#define Xil_L1DCacheDisable() \
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microblaze_disable_dcache()
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/****************************************************************************/
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/**
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*
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* Enable the instruction cache.
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*
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* @return None.
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*
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* @note This is processor specific.
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*
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****************************************************************************/
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#define Xil_L1ICacheEnable() \
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microblaze_enable_icache()
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/****************************************************************************/
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/**
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*
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* Disable the L1 Instruction cache.
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*
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* @return None.
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*
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* @note This is processor specific.
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*
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****************************************************************************/
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#define Xil_L1ICacheDisable() \
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microblaze_disable_icache()
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/****************************************************************************/
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/**
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*
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* Enable the data cache.
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*
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* @param None
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*
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* @return None.
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*
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****************************************************************************/
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#define Xil_DCacheEnable() Xil_L1DCacheEnable()
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/****************************************************************************/
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/**
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*
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* Enable the instruction cache.
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*
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* @param None
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*
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* @return None.
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*
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* @note
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*
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*
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****************************************************************************/
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#define Xil_ICacheEnable() Xil_L1ICacheEnable()
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/****************************************************************************
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*
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* Invalidate the entire Data cache.
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*
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* @param None.
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*
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* @return None.
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*
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* @note None.
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*
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****************************************************************************/
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#define Xil_DCacheInvalidate() \
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Xil_L2CacheInvalidate(); \
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Xil_L1DCacheInvalidate();
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/****************************************************************************
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*
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* Invalidate the Data cache for the given address range.
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* If the bytes specified by the address (adr) are cached by the Data cache,
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* the cacheline containing that byte is invalidated. If the cacheline
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* is modified (dirty), the modified contents are lost and are NOT
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* written to system memory before the line is invalidated.
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*
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* @param Start address of ragne to be invalidated.
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* @param Length of range to be invalidated in bytes.
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*
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* @return None.
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*
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* @note None.
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*
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****************************************************************************/
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#define Xil_DCacheInvalidateRange(Addr, Len) \
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Xil_L2CacheInvalidateRange(Addr, Len); \
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Xil_L1DCacheInvalidateRange(Addr, Len);
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/****************************************************************************
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*
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* Flush the entire Data cache.
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*
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* @param None.
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*
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* @return None.
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*
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* @note None.
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*
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****************************************************************************/
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#define Xil_DCacheFlush() \
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Xil_L2CacheFlush(); \
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Xil_L1DCacheFlush();
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/****************************************************************************
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* Flush the Data cache for the given address range.
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* If the bytes specified by the address (adr) are cached by the Data cache,
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* the cacheline containing that byte is invalidated. If the cacheline
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* is modified (dirty), the written to system memory first before the
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* before the line is invalidated.
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*
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* @param Start address of range to be flushed.
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* @param Length of range to be flushed in bytes.
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*
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* @return None.
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*
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* @note None.
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*
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****************************************************************************/
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#define Xil_DCacheFlushRange(Addr, Len) \
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Xil_L2CacheFlushRange(Addr, Len); \
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Xil_L1DCacheFlushRange(Addr, Len);
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/****************************************************************************
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*
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* Invalidate the entire instruction cache.
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*
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* @param None.
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*
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* @return None.
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*
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* @note None.
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*
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****************************************************************************/
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#define Xil_ICacheInvalidate() \
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Xil_L2CacheInvalidate(); \
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Xil_L1ICacheInvalidate();
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/****************************************************************************
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*
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* Invalidate the instruction cache for the given address range.
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* If the bytes specified by the address (adr) are cached by the Data cache,
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* the cacheline containing that byte is invalidated. If the cacheline
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* is modified (dirty), the modified contents are lost and are NOT
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* written to system memory before the line is invalidated.
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*
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* @param Start address of ragne to be invalidated.
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* @param Length of range to be invalidated in bytes.
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*
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* @return None.
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*
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* @note None.
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*
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****************************************************************************/
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#define Xil_ICacheInvalidateRange(Addr, Len) \
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Xil_L2CacheInvalidateRange(Addr, Len); \
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Xil_L1ICacheInvalidateRange(Addr, Len);
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void Xil_DCacheDisable(void);
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void Xil_ICacheDisable(void);
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#ifdef __cplusplus
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}
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#endif
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#endif
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#endif
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