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Dreaded_X
2020-09-19 23:42:44 +02:00
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78
ipcore_dir/_xmsgs/cg.xmsgs Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="info" file="sim" num="172" delta="old" >Generating IP...
</msg>
<msg type="warning" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">Verilog simulation file type &apos;Behavioral&apos; is not valid for this core. Overriding with simulation file type &apos;Structural&apos;.</arg>
</msg>
<msg type="warning" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">A core named &apos;microblaze_mcs&apos; already exists in the project. Output products for this core may be overwritten.</arg>
</msg>
<msg type="warning" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">Verilog simulation file type &apos;Behavioral&apos; is not valid for this core. Overriding with simulation file type &apos;Structural&apos;.</arg>
</msg>
<msg type="warning" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">A core named &apos;microblaze_mcs&apos; already exists in the project. Output products for this core may be overwritten.</arg>
</msg>
<msg type="info" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">Pre-processing HDL files for &apos;microblaze_mcs&apos;...</arg>
</msg>
<msg type="info" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">Running microblaze_mcs_gen_script.tcl</arg>
</msg>
<msg type="info" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">Please source the &quot;microblaze_mcs_setup.tcl&quot; script in the Tcl Console to complete MicroBlaze MCS core generation</arg>
</msg>
<msg type="warning" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">Verilog simulation file type &apos;Behavioral&apos; is not valid for this core. Overriding with simulation file type &apos;Structural&apos;.</arg>
</msg>
<msg type="warning" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">Verilog simulation file type &apos;Behavioral&apos; is not valid for this core. Overriding with simulation file type &apos;Structural&apos;.</arg>
</msg>
<msg type="info" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">Running microblaze_mcs_sim_script.tcl</arg>
</msg>
<msg type="info" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">C_MICROBLAZE_INSTANCE = microblaze_mcs</arg>
</msg>
<msg type="info" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">Netlist filename = ./_cg/microblaze_mcs.v</arg>
</msg>
<msg type="info" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">Setting INIT_FILE = &quot;microblaze_mcs.lmb_bram_7.mem&quot; for BRAM 7</arg>
</msg>
<msg type="info" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">Setting INIT_FILE = &quot;microblaze_mcs.lmb_bram_6.mem&quot; for BRAM 6</arg>
</msg>
<msg type="info" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">Setting INIT_FILE = &quot;microblaze_mcs.lmb_bram_5.mem&quot; for BRAM 5</arg>
</msg>
<msg type="info" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">Setting INIT_FILE = &quot;microblaze_mcs.lmb_bram_4.mem&quot; for BRAM 4</arg>
</msg>
<msg type="info" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">Setting INIT_FILE = &quot;microblaze_mcs.lmb_bram_3.mem&quot; for BRAM 3</arg>
</msg>
<msg type="info" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">Setting INIT_FILE = &quot;microblaze_mcs.lmb_bram_2.mem&quot; for BRAM 2</arg>
</msg>
<msg type="info" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">Setting INIT_FILE = &quot;microblaze_mcs.lmb_bram_1.mem&quot; for BRAM 1</arg>
</msg>
<msg type="info" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">Setting INIT_FILE = &quot;microblaze_mcs.lmb_bram_0.mem&quot; for BRAM 0</arg>
</msg>
<msg type="info" file="sim" num="949" delta="old" >Finished generation of ASY schematic symbol.
</msg>
<msg type="info" file="sim" num="948" delta="old" >Finished FLIST file generation.
</msg>
</messages>

15
ipcore_dir/_xmsgs/pn_parser.xmsgs Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated -->
<!-- by the Xilinx ISE software. Any direct editing or -->
<!-- changes made to this file may result in unpredictable -->
<!-- behavior or data corruption. It is strongly advised that -->
<!-- users do not edit the contents of this file. -->
<!-- -->
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
<messages>
<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file &quot;/home/tim/Projects/z80/hdmi/ipcore_dir/hdmi_clk.v&quot; into library work</arg>
</msg>
</messages>