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292
software/LED_Controller_bsp/microblaze_mcs/include/_profile_timer_hw.h Executable file
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//////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2004-11 Xilinx, Inc. All rights reserved.
// Xilinx, Inc.
//
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
// AND FITNESS FOR A PARTICULAR PURPOSE.
//
// $Id: _profile_timer_hw.h,v 1.1.2.2 2011/05/30 06:46:18 svemula Exp $
//
// _program_timer_hw.h:
// Timer related functions
//
//////////////////////////////////////////////////////////////////////
#ifndef _PROFILE_TIMER_HW_H
#define _PROFILE_TIMER_HW_H
#include "profile.h"
#ifdef PROC_PPC
#if defined __GNUC__
# define SYNCHRONIZE_IO __asm__ volatile ("eieio")
#elif defined __DCC__
# define SYNCHRONIZE_IO __asm volatile(" eieio")
#else
# define SYNCHRONIZE_IO
#endif
#endif
#ifdef PROC_PPC
#define ProfIo_In32(InputPtr) (*(volatile u32 *)(InputPtr)); SYNCHRONIZE_IO;
#define ProfIo_Out32(OutputPtr, Value) { (*(volatile u32 *)(OutputPtr) = Value); SYNCHRONIZE_IO; }
#else
#define ProfIo_In32(InputPtr) (*(volatile u32 *)(InputPtr));
#define ProfIo_Out32(OutputPtr, Value) { (*(volatile u32 *)(OutputPtr) = Value); }
#endif
#define ProfTmrCtr_mWriteReg(BaseAddress, TmrCtrNumber, RegOffset, ValueToWrite)\
ProfIo_Out32(((BaseAddress) + XTmrCtr_Offsets[(TmrCtrNumber)] + \
(RegOffset)), (ValueToWrite))
#define ProfTimerCtr_mReadReg(BaseAddress, TmrCtrNumber, RegOffset) \
ProfIo_In32((BaseAddress) + XTmrCtr_Offsets[(TmrCtrNumber)] + (RegOffset))
#define ProfTmrCtr_mSetControlStatusReg(BaseAddress, TmrCtrNumber, RegisterValue)\
ProfTmrCtr_mWriteReg((BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET, \
(RegisterValue))
#define ProfTmrCtr_mGetControlStatusReg(BaseAddress, TmrCtrNumber) \
ProfTimerCtr_mReadReg((BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET)
#ifdef __cplusplus
extern "C" {
#endif
#ifdef PROC_PPC
#include "xexception_l.h"
#include "xtime_l.h"
#include "xpseudo_asm.h"
#endif
#ifdef TIMER_CONNECT_INTC
#include "xintc_l.h"
#include "xintc.h"
#endif // TIMER_CONNECT_INTC
#if (!defined PPC_PIT_INTERRUPT && !defined PROC_CORTEXA9)
#include "xtmrctr_l.h"
#endif
#ifdef PROC_CORTEXA9
#include "xscutimer_hw.h"
#include "xscugic.h"
#endif
extern unsigned int timer_clk_ticks ;
//--------------------------------------------------------------------
// PowerPC Target - Timer related functions
//--------------------------------------------------------------------
#ifdef PROC_PPC
#ifdef PPC_PIT_INTERRUPT
unsigned long timer_lo_clk_ticks ; // Clk ticks when Timer is disabled in CG
#endif
#ifdef PROC_PPC440
#define XREG_TCR_PIT_INTERRUPT_ENABLE XREG_TCR_DEC_INTERRUPT_ENABLE
#define XREG_TSR_PIT_INTERRUPT_STATUS XREG_TSR_DEC_INTERRUPT_STATUS
#define XREG_SPR_PIT XREG_SPR_DEC
#define XEXC_ID_PIT_INT XEXC_ID_DEC_INT
#endif
//--------------------------------------------------------------------
// Disable the Timer - During Profiling
//
// For PIT Timer -
// 1. XTime_PITDisableInterrupt() ;
// 2. Store the remaining timer clk tick
// 3. Stop the PIT Timer
//--------------------------------------------------------------------
#ifdef PPC_PIT_INTERRUPT
#define disable_timer() \
{ \
unsigned long val; \
val=mfspr(XREG_SPR_TCR); \
mtspr(XREG_SPR_TCR, val & ~XREG_TCR_PIT_INTERRUPT_ENABLE); \
timer_lo_clk_ticks = mfspr(XREG_SPR_PIT); \
mtspr(XREG_SPR_PIT, 0); \
}
#else
#define disable_timer() \
{ \
u32 addr = (PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET; \
u32 tmp_v = ProfIo_In32(addr); \
tmp_v = tmp_v & ~XTC_CSR_ENABLE_TMR_MASK; \
ProfIo_Out32((PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET, tmp_v); \
}
#endif
//--------------------------------------------------------------------
// Enable the Timer
//
// For PIT Timer -
// 1. Load the remaining timer clk ticks
// 2. XTime_PITEnableInterrupt() ;
//--------------------------------------------------------------------
#ifdef PPC_PIT_INTERRUPT
#define enable_timer() \
{ \
unsigned long val; \
val=mfspr(XREG_SPR_TCR); \
mtspr(XREG_SPR_PIT, timer_lo_clk_ticks); \
mtspr(XREG_SPR_TCR, val | XREG_TCR_PIT_INTERRUPT_ENABLE); \
}
#else
#define enable_timer() \
{ \
u32 addr = (PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET; \
u32 tmp_v = ProfIo_In32(addr); \
tmp_v = tmp_v | XTC_CSR_ENABLE_TMR_MASK; \
ProfIo_Out32((PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET, tmp_v); \
}
#endif
//--------------------------------------------------------------------
// Send Ack to Timer Interrupt
//
// For PIT Timer -
// 1. Load the timer clk ticks
// 2. Enable AutoReload and Interrupt
// 3. Clear PIT Timer Status bits
//--------------------------------------------------------------------
#ifdef PPC_PIT_INTERRUPT
#define timer_ack() \
{ \
unsigned long val; \
mtspr(XREG_SPR_PIT, timer_clk_ticks); \
mtspr(XREG_SPR_TSR, XREG_TSR_PIT_INTERRUPT_STATUS); \
val=mfspr(XREG_SPR_TCR); \
mtspr(XREG_SPR_TCR, val| XREG_TCR_PIT_INTERRUPT_ENABLE| XREG_TCR_AUTORELOAD_ENABLE); \
}
#else
#define timer_ack() \
{ \
unsigned int csr; \
csr = ProfTmrCtr_mGetControlStatusReg(PROFILE_TIMER_BASEADDR, 0); \
ProfTmrCtr_mSetControlStatusReg(PROFILE_TIMER_BASEADDR, 0, csr); \
}
#endif
//--------------------------------------------------------------------
#endif // PROC_PPC
//--------------------------------------------------------------------
//--------------------------------------------------------------------
// MicroBlaze Target - Timer related functions
//--------------------------------------------------------------------
#ifdef PROC_MICROBLAZE
//--------------------------------------------------------------------
// Disable the Timer during Call-Graph Data collection
//
//--------------------------------------------------------------------
#define disable_timer() \
{ \
u32 addr = (PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET; \
u32 tmp_v = ProfIo_In32(addr); \
tmp_v = tmp_v & ~XTC_CSR_ENABLE_TMR_MASK; \
ProfIo_Out32((PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET, tmp_v); \
}
//--------------------------------------------------------------------
// Enable the Timer after Call-Graph Data collection
//
//--------------------------------------------------------------------
#define enable_timer() \
{ \
u32 addr = (PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET; \
u32 tmp_v = ProfIo_In32(addr); \
tmp_v = tmp_v | XTC_CSR_ENABLE_TMR_MASK; \
ProfIo_Out32((PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET, tmp_v); \
}
//--------------------------------------------------------------------
// Send Ack to Timer Interrupt
//
//--------------------------------------------------------------------
#define timer_ack() \
{ \
unsigned int csr; \
csr = ProfTmrCtr_mGetControlStatusReg(PROFILE_TIMER_BASEADDR, 0); \
ProfTmrCtr_mSetControlStatusReg(PROFILE_TIMER_BASEADDR, 0, csr); \
}
//--------------------------------------------------------------------
#endif // PROC_MICROBLAZE
//--------------------------------------------------------------------
//--------------------------------------------------------------------
// Cortex A9 Target - Timer related functions
//--------------------------------------------------------------------
#ifdef PROC_CORTEXA9
//--------------------------------------------------------------------
// Disable the Timer during Call-Graph Data collection
//
//--------------------------------------------------------------------
#define disable_timer() \
{ \
u32 Reg; \
Reg = Xil_In32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET); \
Reg &= ~XSCUTIMER_CONTROL_ENABLE_MASK;\
Xil_Out32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET, Reg);\
} \
//--------------------------------------------------------------------
// Enable the Timer after Call-Graph Data collection
//
//--------------------------------------------------------------------
#define enable_timer() \
{ \
u32 Reg; \
Reg = Xil_In32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET); \
Reg |= XSCUTIMER_CONTROL_ENABLE_MASK; \
Xil_Out32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET, Reg);\
} \
//--------------------------------------------------------------------
// Send Ack to Timer Interrupt
//
//--------------------------------------------------------------------
#define timer_ack() \
{ \
Xil_Out32(PROFILE_TIMER_BASEADDR + XSCUTIMER_ISR_OFFSET, \
XSCUTIMER_ISR_EVENT_FLAG_MASK);\
}
//--------------------------------------------------------------------
#endif // PROC_CORTEXA9
//--------------------------------------------------------------------
#ifdef __cplusplus
}
#endif
#endif

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software/LED_Controller_bsp/microblaze_mcs/include/bspconfig.h Normal file
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/*******************************************************************
*
* CAUTION: This file is automatically generated by libgen.
* Version: Xilinx EDK 14.7 EDK_P.20131013
* DO NOT EDIT.
*
* Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
*
* Description: Configurations for Standalone BSP
*
*******************************************************************/
#define MICROBLAZE_PVR_NONE

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software/LED_Controller_bsp/microblaze_mcs/include/fsl.h Executable file
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#ifndef _FSL_H
#define _FSL_H
#include "xbasic_types.h"
#include "mb_interface.h" /* Legacy reasons. We just have to include this guy who defines the FSL stuff */
#ifdef __cplusplus
extern "C" {
#endif
/* Extended FSL macros. These now replace all of the previous FSL macros */
#define FSL_DEFAULT
#define FSL_NONBLOCKING n
#define FSL_EXCEPTION e
#define FSL_CONTROL c
#define FSL_ATOMIC a
#define FSL_NONBLOCKING_EXCEPTION ne
#define FSL_NONBLOCKING_CONTROL nc
#define FSL_NONBLOCKING_ATOMIC na
#define FSL_EXCEPTION_CONTROL ec
#define FSL_EXCEPTION_ATOMIC ea
#define FSL_CONTROL_ATOMIC ca
#define FSL_NONBLOCKING_EXCEPTION_CONTROL nec
#define FSL_NONBLOCKING_EXCEPTION_ATOMIC nea
#define FSL_NONBLOCKING_CONTROL_ATOMIC nca
#define FSL_EXCEPTION_CONTROL_ATOMIC eca
#define FSL_NONBLOCKING_EXCEPTION_CONTROL_ATOMIC neca
#define getfslx(val, id, flags) asm volatile (stringify(flags) "get\t%0,rfsl" stringify(id) : "=d" (val))
#define putfslx(val, id, flags) asm volatile (stringify(flags) "put\t%0,rfsl" stringify(id) :: "d" (val))
#define tgetfslx(val, id, flags) asm volatile ("t" stringify(flags) "get\t%0,rfsl" stringify(id) : "=d" (val))
#define tputfslx(id, flags) asm volatile ("t" stringify(flags) "put\trfsl" stringify(id))
#define getdfslx(val, var, flags) asm volatile (stringify(flags) "getd\t%0,%1" : "=d" (val) : "d" (var))
#define putdfslx(val, var, flags) asm volatile (stringify(flags) "putd\t%0,%1" :: "d" (val), "d" (var))
#define tgetdfslx(val, var, flags) asm volatile ("t" stringify(flags) "getd\t%0,%1" : "=d" (val) : "d" (var))
#define tputdfslx(var, flags) asm volatile ("t" stringify(flags) "putd\t%0" :: "d" (var))
#ifdef __cplusplus
}
#endif
#endif /* _FSL_H */

361
software/LED_Controller_bsp/microblaze_mcs/include/mb_interface.h Executable file
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////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2004-2012 Xilinx, Inc. All rights reserved.
//
// Xilinx, Inc.
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
// AND FITNESS FOR A PARTICULAR PURPOSE.
//
//
// Summary:
// Header file for mb_interface
//
//
////////////////////////////////////////////////////////////////////////////////
#ifndef _MICROBLAZE_INTERFACE_H_
#define _MICROBLAZE_INTERFACE_H_
#include "xbasic_types.h"
#ifdef __cplusplus
extern "C" {
#endif
extern void microblaze_enable_interrupts(void); /* Enable Interrupts */
extern void microblaze_disable_interrupts(void); /* Disable Interrupts */
extern void microblaze_enable_icache(void); /* Enable Instruction Cache */
extern void microblaze_disable_icache(void); /* Disable Instruction Cache */
extern void microblaze_enable_dcache(void); /* Enable Instruction Cache */
extern void microblaze_disable_dcache(void); /* Disable Instruction Cache */
extern void microblaze_enable_exceptions(void); /* Enable hardware exceptions */
extern void microblaze_disable_exceptions(void); /* Disable hardware exceptions */
extern void microblaze_register_handler(XInterruptHandler Handler, void *DataPtr); /* Register top level interrupt handler */
extern void microblaze_register_exception_handler(Xuint8 ExceptionId, XExceptionHandler Handler, void *DataPtr); /* Register exception handler */
extern void microblaze_invalidate_icache(void); /* Invalidate the entire icache */
extern void microblaze_invalidate_dcache(void); /* Invalidate the entire dcache */
extern void microblaze_flush_dcache(void); /* Flush the whole dcache */
extern void microblaze_invalidate_icache_range(unsigned int cacheaddr, unsigned int len); /* Invalidate a part of the icache */
extern void microblaze_invalidate_dcache_range(unsigned int cacheaddr, unsigned int len); /* Invalidate a part of the dcache */
extern void microblaze_flush_dcache_range(unsigned int cacheaddr, unsigned int len); /* Flush a part of the dcache */
extern void microblaze_scrub(void); /* Scrub LMB and internal BRAM */
/* Deprecated */
extern void microblaze_update_icache (int , int , int ) __attribute__((deprecated));
extern void microblaze_init_icache_range (int , int ) __attribute__((deprecated));
extern void microblaze_update_dcache (int , int , int ) __attribute__((deprecated));
extern void microblaze_init_dcache_range (int , int ) __attribute__((deprecated));
/* necessary for pre-processor */
#define stringify(s) tostring(s)
#define tostring(s) #s
/* FSL Access Macros */
/* Blocking Data Read and Write to FSL no. id */
#define getfsl(val, id) asm volatile ("get\t%0,rfsl" stringify(id) : "=d" (val))
#define putfsl(val, id) asm volatile ("put\t%0,rfsl" stringify(id) :: "d" (val))
/* Non-blocking Data Read and Write to FSL no. id */
#define ngetfsl(val, id) asm volatile ("nget\t%0,rfsl" stringify(id) : "=d" (val))
#define nputfsl(val, id) asm volatile ("nput\t%0,rfsl" stringify(id) :: "d" (val))
/* Blocking Control Read and Write to FSL no. id */
#define cgetfsl(val, id) asm volatile ("cget\t%0,rfsl" stringify(id) : "=d" (val))
#define cputfsl(val, id) asm volatile ("cput\t%0,rfsl" stringify(id) :: "d" (val))
/* Non-blocking Control Read and Write to FSL no. id */
#define ncgetfsl(val, id) asm volatile ("ncget\t%0,rfsl" stringify(id) : "=d" (val))
#define ncputfsl(val, id) asm volatile ("ncput\t%0,rfsl" stringify(id) :: "d" (val))
/* Polling versions of FSL access macros. This makes the FSL access interruptible */
#define getfsl_interruptible(val, id) asm volatile ("\n1:\n\tnget\t%0,rfsl" stringify(id) "\n\t" \
"addic\tr18,r0,0\n\t" \
"bnei\tr18,1b\n" \
: "=d" (val) :: "r18")
#define putfsl_interruptible(val, id) asm volatile ("\n1:\n\tnput\t%0,rfsl" stringify(id) "\n\t" \
"addic\tr18,r0,0\n\t" \
"bnei\tr18,1b\n" \
:: "d" (val) : "r18")
#define cgetfsl_interruptible(val, id) asm volatile ("\n1:\n\tncget\t%0,rfsl" stringify(id) "\n\t" \
"addic\tr18,r0,0\n\t" \
"bnei\tr18,1b\n" \
: "=d" (val) :: "r18")
#define cputfsl_interruptible(val, id) asm volatile ("\n1:\n\tncput\t%0,rfsl" stringify(id) "\n\t" \
"addic\tr18,r0,0\n\t" \
"bnei\tr18,1b\n" \
:: "d" (val) : "r18")
/* FSL valid and error check macros. */
#define fsl_isinvalid(result) asm volatile ("addic\t%0,r0,0" : "=d" (result))
#define fsl_iserror(error) asm volatile ("mfs\t%0,rmsr\n\t" \
"andi\t%0,%0,0x10" : "=d" (error))
/* Pseudo assembler instructions */
#define clz(v) ({ unsigned int _rval; \
__asm__ __volatile__ ( \
"clz\t%0,%1\n" : "=d"(_rval): "d" (v) \
); \
_rval; \
})
#define mbar(mask) ({ __asm__ __volatile__ ("mbar\t" stringify(mask) ); })
#define mb_sleep() ({ __asm__ __volatile__ ("sleep\t"); })
#define mb_swapb(v) ({ unsigned int _rval; \
__asm__ __volatile__ ( \
"swapb\t%0,%1\n" : "=d"(_rval) : "d" (v) \
); \
_rval; \
})
#define mb_swaph(v) ({ unsigned int _rval; \
__asm__ __volatile__ ( \
"swaph\t%0,%1\n" : "=d"(_rval) : "d" (v) \
); \
_rval; \
})
#define mfgpr(rn) ({ unsigned int _rval; \
__asm__ __volatile__ ( \
"or\t%0,r0," stringify(rn) "\n" : "=d"(_rval) \
); \
_rval; \
})
#define mfmsr() ({ unsigned int _rval; \
__asm__ __volatile__ ( \
"mfs\t%0,rmsr\n" : "=d"(_rval) \
); \
_rval; \
})
#define mfear() ({ unsigned int _rval; \
__asm__ __volatile__ ( \
"mfs\t%0,rear\n" : "=d"(_rval) \
); \
_rval; \
})
#define mfesr() ({ unsigned int _rval; \
__asm__ __volatile__ ( \
"mfs\t%0,resr\n" : "=d"(_rval) \
); \
_rval; \
})
#define mffsr() ({ unsigned int _rval; \
__asm__ __volatile__ ( \
"mfs\t%0,rfsr\n" : "=d"(_rval) \
); \
_rval; \
})
#define mfpvr(rn) ({ unsigned int _rval; \
__asm__ __volatile__ ( \
"mfs\t%0,rpvr" stringify(rn) "\n" : "=d"(_rval) \
); \
_rval; \
})
#define mfbtr() ({ unsigned int _rval; \
__asm__ __volatile__ ( \
"mfs\t%0,rbtr\n" : "=d"(_rval) \
); \
_rval; \
})
#define mfedr() ({ unsigned int _rval; \
__asm__ __volatile__ ( \
"mfs\t%0,redr\n" : "=d"(_rval) \
); \
_rval; \
})
#define mfpid() ({ unsigned int _rval; \
__asm__ __volatile__ ( \
"mfs\t%0,rpid\n" : "=d"(_rval)\
); \
_rval; \
})
#define mfzpr() ({ unsigned int _rval; \
__asm__ __volatile__ ( \
"mfs\t%0,rzpr\n" : "=d"(_rval) \
); \
_rval; \
})
#define mftlbx() ({ unsigned int _rval; \
__asm__ __volatile__ ( \
"mfs\t%0,rtlbx\n" : "=d"(_rval) \
); \
_rval; \
})
#define mftlblo() ({ unsigned int _rval; \
__asm__ __volatile__ ( \
"mfs\t%0,rtlblo\n" : "=d"(_rval) \
); \
_rval; \
})
#define mftlbhi() ({ unsigned int _rval; \
__asm__ __volatile__ ( \
"mfs\t%0,rtlbhi\n" : "=d"(_rval) \
); \
_rval; \
})
#define mfslr() ({ unsigned int _rval; \
__asm__ __volatile__ ( \
"mfs\t%0,rslr\n" : "=d"(_rval) \
); \
_rval; \
})
#define mfshr() ({ unsigned int _rval; \
__asm__ __volatile__ ( \
"mfs\t%0,rshr\n" : "=d"(_rval) \
); \
_rval; \
})
#define mtgpr(rn, v) ({ __asm__ __volatile__ ( \
"or\t" stringify(rn) ",r0,%0\n" :: "d" (v) \
); \
})
#define mtmsr(v) ({ __asm__ __volatile__ ( \
"mts\trmsr,%0\n\tnop\n" :: "d" (v) \
); \
})
#define mtfsr(v) ({ __asm__ __volatile__ ( \
"mts\trfsr,%0\n\tnop\n" :: "d" (v) \
); \
})
#define mtpid(v) ({ __asm__ __volatile__ ( \
"mts\trpid,%0\n\tnop\n" :: "d" (v) \
); \
})
#define mtzpr(v) ({ __asm__ __volatile__ ( \
"mts\trzpr,%0\n\tnop\n" :: "d" (v) \
); \
})
#define mttlbx(v) ({ __asm__ __volatile__ ( \
"mts\trtlbx,%0\n\tnop\n" :: "d" (v) \
); \
})
#define mttlblo(v) ({ __asm__ __volatile__ ( \
"mts\trtlblo,%0\n\tnop\n" :: "d" (v) \
); \
})
#define mttlbhi(v) ({ __asm__ __volatile__ ( \
"mts\trtlbhi,%0\n\tnop\n" :: "d" (v) \
); \
})
#define mttlbsx(v) ({ __asm__ __volatile__ ( \
"mts\trtlbsx,%0\n\tnop\n" :: "d" (v) \
); \
})
#define mtslr(v) ({ __asm__ __volatile__ ( \
"mts\trslr,%0\n\tnop\n" :: "d" (v) \
); \
})
#define mtshr(v) ({ __asm__ __volatile__ ( \
"mts\trshr,%0\n\tnop\n" :: "d" (v) \
); \
})
#define lwx(address) ({ unsigned int _rval; \
__asm__ __volatile__ ( \
"lwx\t%0,%1,r0\n" : "=d"(_rval) : "d" (address) \
); \
_rval; \
})
#define lwr(address) ({ unsigned int _rval; \
__asm__ __volatile__ ( \
"lwr\t%0,%1,r0\n" : "=d"(_rval) : "d" (address) \
); \
_rval; \
})
#define lhur(address) ({ unsigned int _rval; \
__asm__ __volatile__ ( \
"lhur\t%0,%1,r0\n" : "=d"(_rval) : "d" (address) \
); \
_rval; \
})
#define lbur(address) ({ unsigned int _rval; \
__asm__ __volatile__ ( \
"lbur\t%0,%1,r0\n" : "=d"(_rval) : "d" (address) \
); \
_rval; \
})
#define swx(address, data) ({ __asm__ __volatile__ ( \
"swx\t%0,%1,r0\n" :: "d" (data), "d" (address) \
); \
})
#define swr(address, data) ({ __asm__ __volatile__ ( \
"swr\t%0,%1,r0\n" :: "d" (data), "d" (address) \
); \
})
#define shr(address, data) ({ __asm__ __volatile__ ( \
"shr\t%0,%1,r0\n" :: "d" (data), "d" (address) \
); \
})
#define sbr(address, data) ({ __asm__ __volatile__ ( \
"sbr\t%0,%1,r0\n" :: "d" (data), "d" (address) \
); \
})
#define microblaze_getfpex_operand_a() ({ \
extern unsigned int mb_fpex_op_a; \
mb_fpex_op_a; \
})
#define microblaze_getfpex_operand_b() ({ \
extern unsigned int mb_fpex_op_b; \
mb_fpex_op_b; \
})
/* Deprecated MicroBlaze FSL macros */
#define microblaze_bread_datafsl(val, id) getfsl(val,id)
#define microblaze_bwrite_datafsl(val, id) putfsl(val,id)
#define microblaze_nbread_datafsl(val, id) ngetfsl(val,id)
#define microblaze_nbwrite_datafsl(val, id) nputfsl(val,id)
#define microblaze_bread_cntlfsl(val, id) cgetfsl(val,id)
#define microblaze_bwrite_cntlfsl(val, id) cputfsl(val,id)
#define microblaze_nbread_cntlfsl(val, id) ncgetfsl(val,id)
#define microblaze_nbwrite_cntlfsl(val, id) ncputfsl(val,id)
#ifdef __cplusplus
}
#endif
#endif // _MICROBLAZE_INTERFACE_H_

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//////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2002-11 Xilinx, Inc. All rights reserved.
// Xilinx, Inc.
//
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
// AND FITNESS FOR A PARTICULAR PURPOSE.
//
// $Id: mblaze_nt_types.h,v 1.1.2.2 2011/05/30 06:46:18 svemula Exp $
//
//////////////////////////////////////////////////////////////////////
#ifndef _MBLAZE_NT_TYPES_H
#define _MBLAZE_NT_TYPES_H
#ifdef __cplusplus
extern "C" {
#endif
typedef char byte;
typedef short half;
typedef int word;
typedef unsigned char ubyte;
typedef unsigned short uhalf;
typedef unsigned int uword;
typedef ubyte boolean;
//typedef unsigned char u_char;
//typedef unsigned short u_short;
//typedef unsigned int u_int;
//typedef unsigned long u_long;
typedef short int16_t;
typedef unsigned short uint16_t;
typedef int int32_t;
typedef unsigned int uint32_t;
#ifdef __cplusplus
}
#endif
#endif

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/*******************************************************************
*
* CAUTION: This file is automatically generated by libgen.
* Version: Xilinx EDK 14.7 EDK_P.20131013
* DO NOT EDIT.
*
* Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
*
* Description: Exception Handling Header for MicroBlaze Processor
*
*******************************************************************/

73
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////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2004-2011 Xilinx, Inc. All rights reserved.
//
// Xilinx, Inc.
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
// AND FITNESS FOR A PARTICULAR PURPOSE.
//
// $Id: microblaze_exceptions_i.h,v 1.1.2.1 2011/05/17 04:37:29 sadanan Exp $
////////////////////////////////////////////////////////////////////////////////
/*****************************************************************************/
/**
*
* @file microblaze_exceptions_i.h
*
* This header file contains defines for structures used by the microblaze
* hardware exception handler.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Date Changes
* ----- -------- -----------------------------------------------
* 1.00a 06/24/04 First release
* </pre>
*
******************************************************************************/
#ifndef MICROBLAZE_EXCEPTIONS_I_H /* prevent circular inclusions */
#define MICROBLAZE_EXCEPTIONS_I_H /* by using protection macros */
/***************************** Include Files *********************************/
#include "xbasic_types.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef struct
{
XExceptionHandler Handler;
void *CallBackRef;
} MB_ExceptionVectorTableEntry;
/* Exception IDs */
#define XEXC_ID_FSL 0
#define XEXC_ID_UNALIGNED_ACCESS 1
#define XEXC_ID_ILLEGAL_OPCODE 2
#define XEXC_ID_M_AXI_I_EXCEPTION 3
#define XEXC_ID_IPLB_EXCEPTION 3
#define XEXC_ID_M_AXI_D_EXCEPTION 4
#define XEXC_ID_DPLB_EXCEPTION 4
#define XEXC_ID_DIV_BY_ZERO 5
#define XEXC_ID_FPU 6
#define XEXC_ID_STACK_VIOLATION 7
#define XEXC_ID_MMU 7
void microblaze_register_exception_handler(Xuint8 ExceptionId, XExceptionHandler Handler, void *DataPtr);
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */

61
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////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2004 Xilinx, Inc. All rights reserved.
//
// Xilinx, Inc.
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
// AND FITNESS FOR A PARTICULAR PURPOSE.
//
// $Id: microblaze_interrupts_i.h,v 1.1.2.1 2011/05/17 04:37:31 sadanan Exp $
////////////////////////////////////////////////////////////////////////////////
/*****************************************************************************/
/**
*
* @file microblaze_interrupts_i.h
*
* This header file contains identifiers and low-level driver functions (or
* macros) that can be used to access the device. The user should refer to the
* hardware device specification for more details of the device operation.
* High-level driver functions are defined in xintc.h.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Date Changes
* ----- -------- -----------------------------------------------
* 1.00b 10/03/03 First release
* </pre>
*
******************************************************************************/
#ifndef MICROBLAZE_INTERRUPTS_I_H /* prevent circular inclusions */
#define MICROBLAZE_INTERRUPTS_I_H /* by using protection macros */
/***************************** Include Files *********************************/
#include "xbasic_types.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef struct
{
XInterruptHandler Handler;
void *CallBackRef;
} MB_InterruptVectorTableEntry;
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */

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//////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2002-11 Xilinx, Inc. All rights reserved.
// Xilinx, Inc.
//
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
// AND FITNESS FOR A PARTICULAR PURPOSE.
//
// $Id: profile.h,v 1.1.2.2 2011/05/30 06:46:18 svemula Exp $
//
//////////////////////////////////////////////////////////////////////
#ifndef _PROFILE_H
#define _PROFILE_H 1
#include <stdio.h>
#include "mblaze_nt_types.h"
#include "profile_config.h"
#ifdef __cplusplus
extern "C" {
#endif
void _system_init( void ) ;
void _system_clean( void ) ;
void mcount(unsigned long frompc, unsigned long selfpc);
void profile_intr_handler( void ) ;
/****************************************************************************
* Profiling on hardware - Hash table maintained on hardware and data sent
* to xmd for gmon.out generation.
****************************************************************************/
/*
* histogram counters are unsigned shorts (according to the kernel).
*/
#define HISTCOUNTER unsigned short
struct tostruct {
unsigned long selfpc;
long count;
short link;
unsigned short pad;
};
struct fromstruct {
unsigned long frompc ;
short link ;
unsigned short pad ;
} ;
/*
* general rounding functions.
*/
#define ROUNDDOWN(x,y) (((x)/(y))*(y))
#define ROUNDUP(x,y) ((((x)+(y)-1)/(y))*(y))
/*
* The profiling data structures are housed in this structure.
*/
struct gmonparam {
long int state;
// Histogram Information
unsigned short *kcount; /* No. of bins in histogram */
unsigned long kcountsize; /* Histogram samples */
// Call-graph Information
struct fromstruct *froms;
unsigned long fromssize;
struct tostruct *tos;
unsigned long tossize;
// Initialization I/Ps
unsigned long lowpc;
unsigned long highpc;
unsigned long textsize;
//unsigned long cg_froms;
//unsigned long cg_tos;
};
extern struct gmonparam *_gmonparam;
extern int n_gmon_sections;
/*
* Possible states of profiling.
*/
#define GMON_PROF_ON 0
#define GMON_PROF_BUSY 1
#define GMON_PROF_ERROR 2
#define GMON_PROF_OFF 3
/*
* Sysctl definitions for extracting profiling information from the kernel.
*/
#define GPROF_STATE 0 /* int: profiling enabling variable */
#define GPROF_COUNT 1 /* struct: profile tick count buffer */
#define GPROF_FROMS 2 /* struct: from location hash bucket */
#define GPROF_TOS 3 /* struct: destination/count structure */
#define GPROF_GMONPARAM 4 /* struct: profiling parameters (see above) */
#ifdef __cplusplus
}
#endif
#endif /* _PROFILE_H */

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////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2006-2011 Xilinx, Inc. All rights reserved.
//
// Xilinx, Inc.
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
// AND FITNESS FOR A PARTICULAR PURPOSE.
//
// $Id: pvr.h,v 1.1.2.1 2011/05/17 04:37:34 sadanan Exp $
////////////////////////////////////////////////////////////////////////////////
/*****************************************************************************/
/**
*
* @file pvr.h
*
* This header file contains defines for structures used by the microblaze
* PVR routines
*
******************************************************************************/
#ifndef _PVR_H
#define _PVR_H
#include "xbasic_types.h"
#include "xparameters.h"
#include "mb_interface.h"
#include "bspconfig.h"
#ifdef __cplusplus
extern "C" {
#endif
/* Defs */
typedef struct pvr_s {
#ifdef MICROBLAZE_PVR_FULL
unsigned int pvr[16];
#else
unsigned int pvr[1];
#endif
} pvr_t;
#define getpvr(pvrid, val) asm volatile ("mfs\t%0,rpvr" stringify(pvrid) "\n\t" : "=d" (val))
/* Basic PVR mask */
#define MICROBLAZE_PVR0_PVR_FULL_MASK 0x80000000
#define MICROBLAZE_PVR0_USE_BARREL_MASK 0x40000000
#define MICROBLAZE_PVR0_USE_DIV_MASK 0x20000000
#define MICROBLAZE_PVR0_USE_HW_MUL_MASK 0x10000000
#define MICROBLAZE_PVR0_USE_FPU_MASK 0x08000000
#define MICROBLAZE_PVR0_USE_EXCEPTION_MASK 0x04000000
#define MICROBLAZE_PVR0_USE_ICACHE_MASK 0x02000000
#define MICROBLAZE_PVR0_USE_DCACHE_MASK 0x01000000
#define MICROBLAZE_PVR0_USE_MMU_MASK 0x00800000
#define MICROBLAZE_PVR0_USE_BTC_MASK 0x00400000
#define MICROBLAZE_PVR0_ENDIANNESS_MASK 0x00200000
#define MICROBLAZE_PVR0_FAULT_TOLERANT_MASK 0x00100000
#define MICROBLAZE_PVR0_STACK_PROTECTION_MASK 0x00080000
#define MICROBLAZE_PVR0_MICROBLAZE_VERSION_MASK 0x0000FF00
#define MICROBLAZE_PVR0_USER1_MASK 0x000000FF
/* User 2 PVR mask */
#define MICROBLAZE_PVR1_USER2_MASK 0xFFFFFFFF
/* Configuration PVR masks */
#define MICROBLAZE_PVR2_D_AXI_MASK 0x80000000
#define MICROBLAZE_PVR2_D_LMB_MASK 0x40000000
#define MICROBLAZE_PVR2_D_PLB_MASK 0x02000000
#define MICROBLAZE_PVR2_I_AXI_MASK 0x20000000
#define MICROBLAZE_PVR2_I_LMB_MASK 0x10000000
#define MICROBLAZE_PVR2_I_PLB_MASK 0x01000000
#define MICROBLAZE_PVR2_INTERRUPT_IS_EDGE_MASK 0x08000000
#define MICROBLAZE_PVR2_EDGE_IS_POSITIVE_MASK 0x04000000
#define MICROBLAZE_PVR2_INTERCONNECT_MASK 0x00800000
#define MICROBLAZE_PVR2_STREAM_INTERCONNECT_MASK 0x00400000
#define MICROBLAZE_PVR2_USE_EXTENDED_FSL_INSTR_MASK 0x00080000
#define MICROBLAZE_PVR2_USE_MSR_INSTR_MASK 0x00020000
#define MICROBLAZE_PVR2_USE_PCMP_INSTR_MASK 0x00010000
#define MICROBLAZE_PVR2_AREA_OPTIMIZED_MASK 0x00008000
#define MICROBLAZE_PVR2_USE_BARREL_MASK 0x00004000
#define MICROBLAZE_PVR2_USE_DIV_MASK 0x00002000
#define MICROBLAZE_PVR2_USE_HW_MUL_MASK 0x00001000
#define MICROBLAZE_PVR2_USE_FPU_MASK 0x00000800
#define MICROBLAZE_PVR2_USE_FPU2_MASK 0x00000200
#define MICROBLAZE_PVR2_USE_MUL64_MASK 0x00000400
#define MICROBLAZE_PVR2_OPCODE_0x0_ILLEGAL_MASK 0x00000040
#define MICROBLAZE_PVR2_UNALIGNED_EXCEPTION_MASK 0x00000020
#define MICROBLAZE_PVR2_ILL_OPCODE_EXCEPTION_MASK 0x00000010
#define MICROBLAZE_PVR2_M_AXI_I_BUS_EXCEPTION_MASK 0x00000008
#define MICROBLAZE_PVR2_M_AXI_D_BUS_EXCEPTION_MASK 0x00000004
#define MICROBLAZE_PVR2_IPLB_BUS_EXCEPTION_MASK 0x00000100
#define MICROBLAZE_PVR2_DPLB_BUS_EXCEPTION_MASK 0x00000080
#define MICROBLAZE_PVR2_DIV_ZERO_EXCEPTION_MASK 0x00000002
#define MICROBLAZE_PVR2_FPU_EXCEPTION_MASK 0x00000001
#define MICROBLAZE_PVR2_FSL_EXCEPTION_MASK 0x00040000
/* Debug and exception PVR masks */
#define MICROBLAZE_PVR3_DEBUG_ENABLED_MASK 0x80000000
#define MICROBLAZE_PVR3_NUMBER_OF_PC_BRK_MASK 0x1E000000
#define MICROBLAZE_PVR3_NUMBER_OF_RD_ADDR_BRK_MASK 0x00380000
#define MICROBLAZE_PVR3_NUMBER_OF_WR_ADDR_BRK_MASK 0x0000E000
#define MICROBLAZE_PVR3_FSL_LINKS_MASK 0x00000380
#define MICROBLAZE_PVR3_BTC_SIZE_MASK 0x00000007
/* ICache config PVR masks */
#define MICROBLAZE_PVR4_USE_ICACHE_MASK 0x80000000
#define MICROBLAZE_PVR4_ICACHE_ADDR_TAG_BITS_MASK 0x7C000000
#define MICROBLAZE_PVR4_ICACHE_ALLOW_WR_MASK 0x01000000
#define MICROBLAZE_PVR4_ICACHE_LINE_LEN_MASK 0x00E00000
#define MICROBLAZE_PVR4_ICACHE_BYTE_SIZE_MASK 0x001F0000
#define MICROBLAZE_PVR4_ICACHE_ALWAYS_USED_MASK 0x00008000
#define MICROBLAZE_PVR4_ICACHE_INTERFACE_MASK 0x00002000
#define MICROBLAZE_PVR4_ICACHE_VICTIMS_MASK 0x00001C00
#define MICROBLAZE_PVR4_ICACHE_STREAMS_MASK 0x00000300
#define MICROBLAZE_PVR4_ICACHE_FORCE_TAG_LUTRAM_MASK 0x00000080
#define MICROBLAZE_PVR4_ICACHE_DATA_WIDTH_MASK 0x00000040
/* DCache config PVR masks */
#define MICROBLAZE_PVR5_USE_DCACHE_MASK 0x80000000
#define MICROBLAZE_PVR5_DCACHE_ADDR_TAG_BITS_MASK 0x7C000000
#define MICROBLAZE_PVR5_DCACHE_ALLOW_WR_MASK 0x01000000
#define MICROBLAZE_PVR5_DCACHE_LINE_LEN_MASK 0x00E00000
#define MICROBLAZE_PVR5_DCACHE_BYTE_SIZE_MASK 0x001F0000
#define MICROBLAZE_PVR5_DCACHE_ALWAYS_USED_MASK 0x00008000
#define MICROBLAZE_PVR5_DCACHE_USE_WRITEBACK_MASK 0x00004000
#define MICROBLAZE_PVR5_DCACHE_INTERFACE_MASK 0x00002000
#define MICROBLAZE_PVR5_DCACHE_VICTIMS_MASK 0x00001C00
#define MICROBLAZE_PVR5_DCACHE_FORCE_TAG_LUTRAM_MASK 0x00000080
#define MICROBLAZE_PVR5_DCACHE_DATA_WIDTH_MASK 0x00000040
/* ICache base address PVR mask */
#define MICROBLAZE_PVR6_ICACHE_BASEADDR_MASK 0xFFFFFFFF
/* ICache high address PVR mask */
#define MICROBLAZE_PVR7_ICACHE_HIGHADDR_MASK 0xFFFFFFFF
/* DCache base address PVR mask */
#define MICROBLAZE_PVR8_DCACHE_BASEADDR_MASK 0xFFFFFFFF
/* DCache high address PVR mask */
#define MICROBLAZE_PVR9_DCACHE_HIGHADDR_MASK 0xFFFFFFFF
/* Target family PVR mask */
#define MICROBLAZE_PVR10_TARGET_FAMILY_MASK 0xFF000000
/* MSR Reset value PVR mask */
#define MICROBLAZE_PVR11_MSR_RESET_VALUE_MASK 0x000007FF
/* MMU value PVR mask */
#define MICROBLAZE_PVR11_MMU_MASK 0xC0000000
#define MICROBLAZE_PVR11_MMU_ITLB_SIZE_MASK 0x38000000
#define MICROBLAZE_PVR11_MMU_DTLB_SIZE_MASK 0x07000000
#define MICROBLAZE_PVR11_MMU_TLB_ACCESS_MASK 0x00C00000
#define MICROBLAZE_PVR11_MMU_ZONES_MASK 0x003E0000
#define MICROBLAZE_PVR11_MMU_PRIVILEGED_INSTR_MASK 0x00010000
/* PVR access macros */
#define MICROBLAZE_PVR_IS_FULL(_pvr) (_pvr.pvr[0] & MICROBLAZE_PVR0_PVR_FULL_MASK)
#define MICROBLAZE_PVR_USE_BARREL(_pvr) (_pvr.pvr[0] & MICROBLAZE_PVR0_USE_BARREL_MASK)
#define MICROBLAZE_PVR_USE_DIV(_pvr) (_pvr.pvr[0] & MICROBLAZE_PVR0_USE_DIV_MASK)
#define MICROBLAZE_PVR_USE_HW_MUL(_pvr) (_pvr.pvr[0] & MICROBLAZE_PVR0_USE_HW_MUL_MASK)
#define MICROBLAZE_PVR_USE_FPU(_pvr) (_pvr.pvr[0] & MICROBLAZE_PVR0_USE_FPU_MASK)
#define MICROBLAZE_PVR_USE_ICACHE(_pvr) (_pvr.pvr[0] & MICROBLAZE_PVR0_USE_ICACHE_MASK)
#define MICROBLAZE_PVR_USE_DCACHE(_pvr) (_pvr.pvr[0] & MICROBLAZE_PVR0_USE_DCACHE_MASK)
#define MICROBLAZE_PVR_USE_MMU(_pvr) (_pvr.pvr[0] & MICROBLAZE_PVR0_USE_MMU_MASK)
#define MICROBLAZE_PVR_USE_BTC(_pvr) (_pvr.pvr[0] & MICROBLAZE_PVR0_USE_BTC_MASK)
#define MICROBLAZE_PVR_ENDIANNESS(_pvr) (_pvr.pvr[0] & MICROBLAZE_PVR0_ENDIANNESS_MASK)
#define MICROBLAZE_PVR_FAULT_TOLERANT(_pvr) (_pvr.pvr[0] & MICROBLAZE_PVR0_FAULT_TOLERANT_MASK)
#define MICROBLAZE_PVR_STACK_PROTECTION(_pvr) (_pvr.pvr[0] & MICROBLAZE_PVR0_STACK_PROTECTION_MASK)
#define MICROBLAZE_PVR_MICROBLAZE_VERSION(_pvr) ((_pvr.pvr[0] & MICROBLAZE_PVR0_MICROBLAZE_VERSION_MASK) >> 8)
#define MICROBLAZE_PVR_USER1(_pvr) (_pvr.pvr[0] & MICROBLAZE_PVR0_USER1_MASK)
#define MICROBLAZE_PVR_USER2(_pvr) (_pvr.pvr[1] & MICROBLAZE_PVR1_USER2_MASK)
#define MICROBLAZE_PVR_D_AXI(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_D_AXI_MASK)
#define MICROBLAZE_PVR_D_LMB(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_D_LMB_MASK)
#define MICROBLAZE_PVR_D_PLB(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_D_PLB_MASK)
#define MICROBLAZE_PVR_I_AXI(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_I_AXI_MASK)
#define MICROBLAZE_PVR_I_LMB(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_I_LMB_MASK)
#define MICROBLAZE_PVR_I_PLB(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_I_PLB_MASK)
#define MICROBLAZE_PVR_INTERRUPT_IS_EDGE(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_INTERRUPT_IS_EDGE_MASK)
#define MICROBLAZE_PVR_EDGE_IS_POSITIVE(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_EDGE_IS_POSITIVE_MASK)
#define MICROBLAZE_PVR_INTERCONNECT(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_INTERCONNECT_MASK)
#define MICROBLAZE_PVR_STREAM_INTERCONNECT(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_STREAM_INTERCONNECT_MASK)
#define MICROBLAZE_PVR_USE_EXTENDED_FSL_INSTR(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_USE_EXTENDED_FSL_INSTR_MASK)
#define MICROBLAZE_PVR_USE_MSR_INSTR(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_USE_MSR_INSTR_MASK)
#define MICROBLAZE_PVR_USE_PCMP_INSTR(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_USE_PCMP_INSTR_MASK)
#define MICROBLAZE_PVR_AREA_OPTIMIZED(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_AREA_OPTIMIZED_MASK)
#define MICROBLAZE_PVR_USE_MUL64(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_USE_MUL64_MASK)
#define MICROBLAZE_PVR_OPCODE_0x0_ILLEGAL(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_OPCODE_0x0_ILLEGAL_MASK)
#define MICROBLAZE_PVR_UNALIGNED_EXCEPTION(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_UNALIGNED_EXCEPTION_MASK)
#define MICROBLAZE_PVR_ILL_OPCODE_EXCEPTION(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_ILL_OPCODE_EXCEPTION_MASK)
#define MICROBLAZE_PVR_M_AXI_I_BUS_EXCEPTION(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_M_AXI_I_BUS_EXCEPTION_MASK)
#define MICROBLAZE_PVR_IPLB_BUS_EXCEPTION(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_IPLB_BUS_EXCEPTION_MASK)
#define MICROBLAZE_PVR_M_AXI_D_BUS_EXCEPTION(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_M_AXI_D_BUS_EXCEPTION_MASK)
#define MICROBLAZE_PVR_DPLB_BUS_EXCEPTION(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_DPLB_BUS_EXCEPTION_MASK)
#define MICROBLAZE_PVR_DIV_ZERO_EXCEPTION(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_DIV_ZERO_EXCEPTION_MASK)
#define MICROBLAZE_PVR_FPU_EXCEPTION(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_FPU_EXCEPTION_MASK)
#define MICROBLAZE_PVR_FSL_EXCEPTION(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_FSL_EXCEPTION_MASK)
#define MICROBLAZE_PVR_DEBUG_ENABLED(_pvr) (_pvr.pvr[3] & MICROBLAZE_PVR3_DEBUG_ENABLED_MASK)
#define MICROBLAZE_PVR_NUMBER_OF_PC_BRK(_pvr) ((_pvr.pvr[3] & MICROBLAZE_PVR3_NUMBER_OF_PC_BRK_MASK) >> 25)
#define MICROBLAZE_PVR_NUMBER_OF_RD_ADDR_BRK(_pvr) ((_pvr.pvr[3] & MICROBLAZE_PVR3_NUMBER_OF_RD_ADDR_BRK_MASK) >> 19)
#define MICROBLAZE_PVR_NUMBER_OF_WR_ADDR_BRK(_pvr) ((_pvr.pvr[3] & MICROBLAZE_PVR3_NUMBER_OF_WR_ADDR_BRK_MASK) >> 13)
#define MICROBLAZE_PVR_FSL_LINKS(_pvr) ((_pvr.pvr[3] & MICROBLAZE_PVR3_FSL_LINKS_MASK) >> 7)
#define MICROBLAZE_PVR_BTC_SIZE(_pvr) (_pvr.pvr[3] & MICROBLAZE_PVR3_BTC_SIZE_MASK)
#define MICROBLAZE_PVR_ICACHE_ADDR_TAG_BITS(_pvr) ((_pvr.pvr[4] & MICROBLAZE_PVR4_ICACHE_ADDR_TAG_BITS_MASK) >> 26)
#define MICROBLAZE_PVR_ICACHE_ALLOW_WR(_pvr) (_pvr.pvr[4] & MICROBLAZE_PVR4_ICACHE_ALLOW_WR_MASK)
#define MICROBLAZE_PVR_ICACHE_LINE_LEN(_pvr) (1 << ((_pvr.pvr[4] & MICROBLAZE_PVR4_ICACHE_LINE_LEN_MASK) >> 21))
#define MICROBLAZE_PVR_ICACHE_BYTE_SIZE(_pvr) (1 << ((_pvr.pvr[4] & MICROBLAZE_PVR4_ICACHE_BYTE_SIZE_MASK) >> 16))
#define MICROBLAZE_PVR_ICACHE_ALWAYS_USED(_pvr) (_pvr.pvr[4] & MICROBLAZE_PVR4_ICACHE_ALWAYS_USED_MASK)
#define MICROBLAZE_PVR_ICACHE_INTERFACE(_pvr) (_pvr.pvr[4] & MICROBLAZE_PVR4_ICACHE_INTERFACE_MASK)
#define MICROBLAZE_PVR_ICACHE_VICTIMS(_pvr) ((_pvr.pvr[4] & MICROBLAZE_PVR4_ICACHE_VICTIMS_MASK) >> 10)
#define MICROBLAZE_PVR_ICACHE_STREAMS(_pvr) ((_pvr.pvr[4] & MICROBLAZE_PVR4_ICACHE_STREAMS_MASK) >> 8)
#define MICROBLAZE_PVR_ICACHE_FORCE_TAG_LUTRAM(_pvr) (_pvr.pvr[4] & MICROBLAZE_PVR4_ICACHE_FORCE_TAG_LUTRAM_MASK)
#define MICROBLAZE_PVR_ICACHE_DATA_WIDTH(_pvr) (_pvr.pvr[4] & MICROBLAZE_PVR4_ICACHE_DATA_WIDTH_MASK)
#define MICROBLAZE_PVR_DCACHE_ADDR_TAG_BITS(_pvr) ((_pvr.pvr[5] & MICROBLAZE_PVR5_DCACHE_ADDR_TAG_BITS_MASK) >> 26)
#define MICROBLAZE_PVR_DCACHE_ALLOW_WR(_pvr) (_pvr.pvr[5] & MICROBLAZE_PVR5_DCACHE_ALLOW_WR_MASK)
#define MICROBLAZE_PVR_DCACHE_LINE_LEN(_pvr) (1 << ((_pvr.pvr[5] & MICROBLAZE_PVR5_DCACHE_LINE_LEN_MASK) >> 21))
#define MICROBLAZE_PVR_DCACHE_BYTE_SIZE(_pvr) (1 << ((_pvr.pvr[5] & MICROBLAZE_PVR5_DCACHE_BYTE_SIZE_MASK) >> 16))
#define MICROBLAZE_PVR_DCACHE_ALWAYS_USED(_pvr) (_pvr.pvr[5] & MICROBLAZE_PVR5_DCACHE_ALWAYS_USED_MASK)
#define MICROBLAZE_PVR_DCACHE_USE_WRITEBACK(_pvr) (_pvr.pvr[5] & MICROBLAZE_PVR5_DCACHE_USE_WRITEBACK_MASK)
#define MICROBLAZE_PVR_DCACHE_INTERFACE(_pvr) (_pvr.pvr[5] & MICROBLAZE_PVR5_DCACHE_INTERFACE_MASK)
#define MICROBLAZE_PVR_DCACHE_VICTIMS(_pvr) ((_pvr.pvr[5] & MICROBLAZE_PVR5_DCACHE_VICTIMS_MASK) >> 10)
#define MICROBLAZE_PVR_DCACHE_FORCE_TAG_LUTRAM(_pvr) (_pvr.pvr[5] & MICROBLAZE_PVR5_DCACHE_FORCE_TAG_LUTRAM_MASK)
#define MICROBLAZE_PVR_DCACHE_DATA_WIDTH(_pvr) (_pvr.pvr[5] & MICROBLAZE_PVR5_DCACHE_DATA_WIDTH_MASK)
#define MICROBLAZE_PVR_ICACHE_BASEADDR(_pvr) (_pvr.pvr[6] & MICROBLAZE_PVR6_ICACHE_BASEADDR_MASK)
#define MICROBLAZE_PVR_ICACHE_HIGHADDR(_pvr) (_pvr.pvr[7] & MICROBLAZE_PVR7_ICACHE_HIGHADDR_MASK)
#define MICROBLAZE_PVR_DCACHE_BASEADDR(_pvr) (_pvr.pvr[8] & MICROBLAZE_PVR8_DCACHE_BASEADDR_MASK)
#define MICROBLAZE_PVR_DCACHE_HIGHADDR(_pvr) (_pvr.pvr[9] & MICROBLAZE_PVR9_DCACHE_HIGHADDR_MASK)
#define MICROBLAZE_PVR_TARGET_FAMILY(_pvr) ((_pvr.pvr[10] & MICROBLAZE_PVR10_TARGET_FAMILY_MASK) >> 24)
#define MICROBLAZE_PVR_MSR_RESET_VALUE(_pvr) (_pvr.pvr[11] & MICROBLAZE_PVR11_MSR_RESET_VALUE_MASK)
#define MICROBLAZE_PVR_MMU_TYPE(_pvr) ((_pvr.pvr[11] & MICROBLAZE_PVR11_MMU_MASK) >> 30)
#define MICROBLAZE_PVR_MMU_ITLB_SIZE(_pvr) ((_pvr.pvr[11] & MICROBLAZE_PVR11_MMU_ITLB_SIZE_MASK) >> 27)
#define MICROBLAZE_PVR_MMU_DTLB_SIZE(_pvr) ((_pvr.pvr[11] & MICROBLAZE_PVR11_MMU_DTLB_SIZE_MASK) >> 24)
#define MICROBLAZE_PVR_MMU_TLB_ACCESS(_pvr) ((_pvr.pvr[11] & MICROBLAZE_PVR11_MMU_TLB_ACCESS_MASK) >> 22)
#define MICROBLAZE_PVR_MMU_ZONES(_pvr) ((_pvr.pvr[11] & MICROBLAZE_PVR11_MMU_ZONES_MASK) >> 17)
#define MICROBLAZE_PVR_MMU_PRIVILEGED_INSTR(_pvr) ((_pvr.pvr[11] & MICROBLAZE_PVR11_MMU_PRIVILEGED_INSTR_MASK) >> 16)
/* Protos */
int microblaze_get_pvr (pvr_t *pvr);
#ifdef __cplusplus
}
#endif
#endif /* _PVR_H */

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/* $Id: xbasic_types.h,v 1.19.10.4 2011/06/28 11:00:54 sadanan Exp $ */
/******************************************************************************
*
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
* AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
* SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE,
* OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
* APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
* THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE.
*
* (c) Copyright 2002-2007 Xilinx Inc.
* All rights reserved.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xbasic_types.h
*
* This file contains basic types for Xilinx software IP. These types do not
* follow the standard naming convention with respect to using the component
* name in front of each name because they are considered to be primitives.
*
* @note
*
* This file contains items which are architecture dependent.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00a rmm 12/14/01 First release
* rmm 05/09/03 Added "xassert always" macros to rid ourselves of diab
* compiler warnings
* 1.00a rpm 11/07/03 Added XNullHandler function as a stub interrupt handler
* 1.00a rpm 07/21/04 Added XExceptionHandler typedef for processor exceptions
* 1.00a xd 11/03/04 Improved support for doxygen.
* 1.00a wre 01/25/07 Added Linux style data types u32, u16, u8, TRUE, FALSE
* 1.00a rpm 04/02/07 Added ifndef KERNEL around u32, u16, u8 data types
* </pre>
*
******************************************************************************/
#ifndef XBASIC_TYPES_H /* prevent circular inclusions */
#define XBASIC_TYPES_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
/************************** Constant Definitions *****************************/
#ifndef TRUE
# define TRUE 1
#endif
#ifndef FALSE
# define FALSE 0
#endif
#ifndef NULL
#define NULL 0
#endif
/** Xilinx NULL, TRUE and FALSE legacy support. Deprecated. */
#define XNULL NULL
#define XTRUE TRUE
#define XFALSE FALSE
#define XCOMPONENT_IS_READY 0x11111111 /**< component has been initialized */
#define XCOMPONENT_IS_STARTED 0x22222222 /**< component has been started */
/* the following constants and declarations are for unit test purposes and are
* designed to be used in test applications.
*/
#define XTEST_PASSED 0
#define XTEST_FAILED 1
#define XASSERT_NONE 0
#define XASSERT_OCCURRED 1
extern unsigned int XAssertStatus;
extern void XAssert(char *, int);
/**************************** Type Definitions *******************************/
/** @name Legacy types
* Deprecated legacy types.
* @{
*/
typedef unsigned char Xuint8; /**< unsigned 8-bit */
typedef char Xint8; /**< signed 8-bit */
typedef unsigned short Xuint16; /**< unsigned 16-bit */
typedef short Xint16; /**< signed 16-bit */
typedef unsigned long Xuint32; /**< unsigned 32-bit */
typedef long Xint32; /**< signed 32-bit */
typedef float Xfloat32; /**< 32-bit floating point */
typedef double Xfloat64; /**< 64-bit double precision FP */
typedef unsigned long Xboolean; /**< boolean (XTRUE or XFALSE) */
#if !defined __XUINT64__
typedef struct
{
Xuint32 Upper;
Xuint32 Lower;
} Xuint64;
#endif
/** @name New types
* New simple types.
* @{
*/
#ifndef __KERNEL__
#ifndef XIL_TYPES_H
typedef Xuint32 u32;
typedef Xuint16 u16;
typedef Xuint8 u8;
#endif
#else
#include <linux/types.h>
#endif
/*@}*/
/**
* This data type defines an interrupt handler for a device.
* The argument points to the instance of the component
*/
typedef void (*XInterruptHandler) (void *InstancePtr);
/**
* This data type defines an exception handler for a processor.
* The argument points to the instance of the component
*/
typedef void (*XExceptionHandler) (void *InstancePtr);
/**
* This data type defines a callback to be invoked when an
* assert occurs. The callback is invoked only when asserts are enabled
*/
typedef void (*XAssertCallback) (char *FilenamePtr, int LineNumber);
/***************** Macros (Inline Functions) Definitions *********************/
/*****************************************************************************/
/**
* Return the most significant half of the 64 bit data type.
*
* @param x is the 64 bit word.
*
* @return The upper 32 bits of the 64 bit word.
*
* @note None.
*
******************************************************************************/
#define XUINT64_MSW(x) ((x).Upper)
/*****************************************************************************/
/**
* Return the least significant half of the 64 bit data type.
*
* @param x is the 64 bit word.
*
* @return The lower 32 bits of the 64 bit word.
*
* @note None.
*
******************************************************************************/
#define XUINT64_LSW(x) ((x).Lower)
#ifndef NDEBUG
/*****************************************************************************/
/**
* This assert macro is to be used for functions that do not return anything
* (void). This in conjunction with the XWaitInAssert boolean can be used to
* accomodate tests so that asserts which fail allow execution to continue.
*
* @param expression is the expression to evaluate. If it evaluates to
* false, the assert occurs.
*
* @return Returns void unless the XWaitInAssert variable is true, in which
* case no return is made and an infinite loop is entered.
*
* @note None.
*
******************************************************************************/
#define XASSERT_VOID(expression) \
{ \
if (expression) \
{ \
XAssertStatus = XASSERT_NONE; \
} \
else \
{ \
XAssert(__FILE__, __LINE__); \
XAssertStatus = XASSERT_OCCURRED; \
return; \
} \
}
/*****************************************************************************/
/**
* This assert macro is to be used for functions that do return a value. This in
* conjunction with the XWaitInAssert boolean can be used to accomodate tests so
* that asserts which fail allow execution to continue.
*
* @param expression is the expression to evaluate. If it evaluates to false,
* the assert occurs.
*
* @return Returns 0 unless the XWaitInAssert variable is true, in which case
* no return is made and an infinite loop is entered.
*
* @note None.
*
******************************************************************************/
#define XASSERT_NONVOID(expression) \
{ \
if (expression) \
{ \
XAssertStatus = XASSERT_NONE; \
} \
else \
{ \
XAssert(__FILE__, __LINE__); \
XAssertStatus = XASSERT_OCCURRED; \
return 0; \
} \
}
/*****************************************************************************/
/**
* Always assert. This assert macro is to be used for functions that do not
* return anything (void). Use for instances where an assert should always
* occur.
*
* @return Returns void unless the XWaitInAssert variable is true, in which case
* no return is made and an infinite loop is entered.
*
* @note None.
*
******************************************************************************/
#define XASSERT_VOID_ALWAYS() \
{ \
XAssert(__FILE__, __LINE__); \
XAssertStatus = XASSERT_OCCURRED; \
return; \
}
/*****************************************************************************/
/**
* Always assert. This assert macro is to be used for functions that do return
* a value. Use for instances where an assert should always occur.
*
* @return Returns void unless the XWaitInAssert variable is true, in which case
* no return is made and an infinite loop is entered.
*
* @note None.
*
******************************************************************************/
#define XASSERT_NONVOID_ALWAYS() \
{ \
XAssert(__FILE__, __LINE__); \
XAssertStatus = XASSERT_OCCURRED; \
return 0; \
}
#else
#define XASSERT_VOID(expression)
#define XASSERT_VOID_ALWAYS()
#define XASSERT_NONVOID(expression)
#define XASSERT_NONVOID_ALWAYS()
#endif
/************************** Function Prototypes ******************************/
void XAssertSetCallback(XAssertCallback Routine);
void XNullHandler(void *NullParameter);
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */

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/******************************************************************************
*
* (c) Copyright 2006-2013 Xilinx, Inc. All rights reserved.
*
* This file contains confidential and proprietary information of Xilinx, Inc.
* and is protected under U.S. and international copyright and other
* intellectual property laws.
*
* DISCLAIMER
* This disclaimer is not a license and does not grant any rights to the
* materials distributed herewith. Except as otherwise provided in a valid
* license issued to you by Xilinx, and to the maximum extent permitted by
* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
* and (2) Xilinx shall not be liable (whether in contract or tort, including
* negligence, or under any other theory of liability) for any loss or damage
* of any kind or nature related to, arising under or in connection with these
* materials, including for any direct, or any indirect, special, incidental,
* or consequential loss or damage (including loss of data, profits, goodwill,
* or any type of loss or damage suffered as a result of any action brought by
* a third party) even if such damage or loss was reasonably foreseeable or
* Xilinx had been advised of the possibility of the same.
*
* CRITICAL APPLICATIONS
* Xilinx products are not designed or intended to be fail-safe, or for use in
* any application requiring fail-safe performance, such as life-support or
* safety devices or systems, Class III medical devices, nuclear facilities,
* applications related to the deployment of airbags, or any other applications
* that could lead to death, personal injury, or severe property or
* environmental damage (individually and collectively, "Critical
* Applications"). Customer assumes the sole risk and liability of any use of
* Xilinx products in Critical Applications, subject only to applicable laws
* and regulations governing limitations on product liability.
*
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
* AT ALL TIMES.
*
******************************************************************************/
/*****************************************************************************/
/**
* @file xbram.h
*
* If ECC is not enabled, this driver exists only to allow the tools to
* create a memory test application and to populate xparameters.h with memory
* range constants. In this case there is no source code.
*
* If ECC is enabled, this file contains the software API definition of the
* Xilinx BRAM Interface Controller (XBram) device driver.
*
* The Xilinx BRAM controller is a soft IP core designed for Xilinx
* FPGAs and contains the following general features:
* - LMB v2.0 bus interfaces with byte enable support
* - Used in conjunction with bram_block peripheral to provide fast BRAM
* memory solution for MicroBlaze ILMB and DLMB ports
* - Supports byte, half-word, and word transfers
* - Supports optional BRAM error correction and detection.
*
* The driver provides interrupt management functions. Implementation of
* interrupt handlers is left to the user. Refer to the provided interrupt
* example in the examples directory for details.
*
* This driver is intended to be RTOS and processor independent. Any needs for
* dynamic memory management, threads or thread mutual exclusion, virtual
* memory, or cache control must be satisfied by the layer above this driver.
*
* <b>Initialization & Configuration</b>
*
* The XBram_Config structure is used by the driver to configure
* itself. This configuration structure is typically created by the tool-chain
* based on HW build properties.
*
* To support multiple runtime loading and initialization strategies employed
* by various operating systems, the driver instance can be initialized as
* follows:
*
* - XBram_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr) -
* Uses a configuration structure provided by the caller. If running in a
* system with address translation, the provided virtual memory base address
* replaces the physical address present in the configuration structure.
*
* @note
*
* This API utilizes 32 bit I/O to the BRAM registers. With less
* than 32 bits, the unused bits from registers are read as zero and written as
* don't cares.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 3.00a sa 05/11/10 Added ECC support
* 3.01a sa 01/13/12 Changed Selftest API from
* XBram_SelfTest(XBram *InstancePtr) to
* XBram_SelfTest(XBram *InstancePtr, u8 IntMask) and
* fixed a problem with interrupt generation for CR 639274
* Modified Selftest example to return XST_SUCCESS when
* ECC is not enabled and return XST_FAILURE when ECC is
* enabled and Control Base Address is zero (CR 636581)
* Modified Selftest to use correct CorrectableCounterBits
* for CR 635655
* Updated to check CorrectableFailingDataRegs in the case
* of LMB BRAM.
* Added CorrectableFailingDataRegs and
* UncorrectableFailingDataRegs to the config structure to
* distinguish between AXI BRAM and LMB BRAM.
* These registers are not present in the current version of
* the AXI BRAM Controller.
* 3.02a sa 04/16/12 Added test of byte and halfword read-modify-write
* 3.02a sa 04/16/12 Modified driver tcl to sort the address parameters
* to support both xps and vivado designs.
* 3.02a adk 24/4/13 Modified the tcl file to avoid warnings
* when ecc is disabled cr:705002.
* 3.03a bss 05/22/13 Added Xil_DCacheFlushRange in xbram_selftest.c to
* flush the Cache after writing to BRAM in InjectErrors
* API(CR #719011)
* </pre>
*****************************************************************************/
#ifndef XBRAM_H /* prevent circular inclusions */
#define XBRAM_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files ********************************/
#include "xil_types.h"
#include "xil_assert.h"
#include "xstatus.h"
#include "xbram_hw.h"
/************************** Constant Definitions ****************************/
/**************************** Type Definitions ******************************/
/**
* This typedef contains configuration information for the device.
*/
typedef struct {
u16 DeviceId; /**< Unique ID of device */
u32 DataWidth; /**< BRAM data width */
int EccPresent; /**< Is ECC supported in H/W */
int FaultInjectionPresent; /**< Is Fault Injection
* supported in H/W */
int CorrectableFailingRegisters; /**< Is Correctable Failing Registers
* supported in H/W */
int CorrectableFailingDataRegs; /**< Is Correctable Failing Data
* Registers supported in H/W */
int UncorrectableFailingRegisters; /**< Is Un-correctable Failing
* Registers supported in H/W */
int UncorrectableFailingDataRegs; /**< Is Un-correctable Failing Data
* Registers supported in H/W */
int EccStatusInterruptPresent; /**< Are ECC status and interrupts
* supported in H/W */
int CorrectableCounterBits; /**< Number of bits in the
* Correctable Error Counter */
int EccOnOffRegister; /**< Is ECC on/off register supported
* in h/w */
int EccOnOffResetValue; /**< Reset value of the ECC on/off
* register in h/w */
int WriteAccess; /**< Is write access enabled in
* h/w */
u32 MemBaseAddress; /**< Device memory base address */
u32 MemHighAddress; /**< Device memory high address */
u32 CtrlBaseAddress; /**< Device register base address.*/
u32 CtrlHighAddress; /**< Device register base address.*/
} XBram_Config;
/**
* The XBram driver instance data. The user is required to
* allocate a variable of this type for every BRAM device in the
* system. A pointer to a variable of this type is then passed to the driver
* API functions.
*/
typedef struct {
XBram_Config Config; /* BRAM config structure */
u32 IsReady; /* Device is initialized and ready */
} XBram;
/***************** Macros (Inline Functions) Definitions ********************/
/************************** Function Prototypes *****************************/
/*
* Functions in xbram_sinit.c
*/
XBram_Config *XBram_LookupConfig(u16 DeviceId);
/*
* Functions implemented in xbram.c
*/
int XBram_CfgInitialize(XBram *InstancePtr, XBram_Config *Config,
u32 EffectiveAddr);
/*
* Functions implemented in xbram_selftest.c
*/
int XBram_SelfTest(XBram *InstancePtr, u8 IntMask);
/*
* Functions implemented in xbram_intr.c
*/
void XBram_InterruptEnable(XBram *InstancePtr, u32 Mask);
void XBram_InterruptDisable(XBram *InstancePtr, u32 Mask);
void XBram_InterruptClear(XBram *InstancePtr, u32 Mask);
u32 XBram_InterruptGetEnabled(XBram *InstancePtr);
u32 XBram_InterruptGetStatus(XBram *InstancePtr);
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */

415
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/******************************************************************************
*
* (c) Copyright 2011-2013 Xilinx, Inc. All rights reserved.
*
* This file contains confidential and proprietary information of Xilinx, Inc.
* and is protected under U.S. and international copyright and other
* intellectual property laws.
*
* DISCLAIMER
* This disclaimer is not a license and does not grant any rights to the
* materials distributed herewith. Except as otherwise provided in a valid
* license issued to you by Xilinx, and to the maximum extent permitted by
* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
* and (2) Xilinx shall not be liable (whether in contract or tort, including
* negligence, or under any other theory of liability) for any loss or damage
* of any kind or nature related to, arising under or in connection with these
* materials, including for any direct, or any indirect, special, incidental,
* or consequential loss or damage (including loss of data, profits, goodwill,
* or any type of loss or damage suffered as a result of any action brought by
* a third party) even if such damage or loss was reasonably foreseeable or
* Xilinx had been advised of the possibility of the same.
*
* CRITICAL APPLICATIONS
* Xilinx products are not designed or intended to be fail-safe, or for use in
* any application requiring fail-safe performance, such as life-support or
* safety devices or systems, Class III medical devices, nuclear facilities,
* applications related to the deployment of airbags, or any other applications
* that could lead to death, personal injury, or severe property or
* environmental damage (individually and collectively, "Critical
* Applications"). Customer assumes the sole risk and liability of any use of
* Xilinx products in Critical Applications, subject only to applicable laws
* and regulations governing limitations on product liability.
*
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
* AT ALL TIMES.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xbram_hw.h
*
* This header file contains identifiers and driver functions (or
* macros) that can be used to access the device. The user should refer to the
* hardware device specification for more details of the device operation.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.00a sa 24/11/10 First release
* </pre>
*
******************************************************************************/
#ifndef XBRAM_HW_H /* prevent circular inclusions */
#define XBRAM_HW_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xil_types.h"
#include "xil_assert.h"
#include "xil_io.h"
/************************** Constant Definitions *****************************/
/** @name Registers
*
* Register offsets for this device.
* @{
*/
#define XBRAM_ECC_STATUS_OFFSET 0x0 /**< ECC status Register */
#define XBRAM_ECC_EN_IRQ_OFFSET 0x4 /**< ECC interrupt enable Register */
#define XBRAM_ECC_ON_OFF_OFFSET 0x8 /**< ECC on/off register */
#define XBRAM_CE_CNT_OFFSET 0xC /**< Correctable error counter Register */
#define XBRAM_CE_FFD_0_OFFSET 0x100 /**< Correctable error first failing
* data Register, 31-0 */
#define XBRAM_CE_FFD_1_OFFSET 0x104 /**< Correctable error first failing
* data Register, 63-32 */
#define XBRAM_CE_FFD_2_OFFSET 0x108 /**< Correctable error first failing
* data Register, 95-64 */
#define XBRAM_CE_FFD_3_OFFSET 0x10C /**< Correctable error first failing
* data Register, 127-96 */
#define XBRAM_CE_FFD_4_OFFSET 0x110 /**< Correctable error first failing
* data Register, 159-128 */
#define XBRAM_CE_FFD_5_OFFSET 0x114 /**< Correctable error first failing
* data Register, 191-160 */
#define XBRAM_CE_FFD_6_OFFSET 0x118 /**< Correctable error first failing
* data Register, 223-192 */
#define XBRAM_CE_FFD_7_OFFSET 0x11C /**< Correctable error first failing
* data Register, 255-224 */
#define XBRAM_CE_FFD_8_OFFSET 0x120 /**< Correctable error first failing
* data Register, 287-256 */
#define XBRAM_CE_FFD_9_OFFSET 0x124 /**< Correctable error first failing
* data Register, 319-288 */
#define XBRAM_CE_FFD_10_OFFSET 0x128 /**< Correctable error first failing
* data Register, 351-320 */
#define XBRAM_CE_FFD_11_OFFSET 0x12C /**< Correctable error first failing
* data Register, 383-352 */
#define XBRAM_CE_FFD_12_OFFSET 0x130 /**< Correctable error first failing
* data Register, 415-384 */
#define XBRAM_CE_FFD_13_OFFSET 0x134 /**< Correctable error first failing
* data Register, 447-416 */
#define XBRAM_CE_FFD_14_OFFSET 0x138 /**< Correctable error first failing
* data Register, 479-448 */
#define XBRAM_CE_FFD_15_OFFSET 0x13C /**< Correctable error first failing
* data Register, 511-480 */
#define XBRAM_CE_FFD_16_OFFSET 0x140 /**< Correctable error first failing
* data Register, 543-512 */
#define XBRAM_CE_FFD_17_OFFSET 0x144 /**< Correctable error first failing
* data Register, 575-544 */
#define XBRAM_CE_FFD_18_OFFSET 0x148 /**< Correctable error first failing
* data Register, 607-576 */
#define XBRAM_CE_FFD_19_OFFSET 0x14C /**< Correctable error first failing
* data Register, 639-608 */
#define XBRAM_CE_FFD_20_OFFSET 0x150 /**< Correctable error first failing
* data Register, 671-640 */
#define XBRAM_CE_FFD_21_OFFSET 0x154 /**< Correctable error first failing
* data Register, 703-672 */
#define XBRAM_CE_FFD_22_OFFSET 0x158 /**< Correctable error first failing
* data Register, 735-704 */
#define XBRAM_CE_FFD_23_OFFSET 0x15C /**< Correctable error first failing
* data Register, 767-736 */
#define XBRAM_CE_FFD_24_OFFSET 0x160 /**< Correctable error first failing
* data Register, 799-768 */
#define XBRAM_CE_FFD_25_OFFSET 0x164 /**< Correctable error first failing
* data Register, 831-800 */
#define XBRAM_CE_FFD_26_OFFSET 0x168 /**< Correctable error first failing
* data Register, 863-832 */
#define XBRAM_CE_FFD_27_OFFSET 0x16C /**< Correctable error first failing
* data Register, 895-864 */
#define XBRAM_CE_FFD_28_OFFSET 0x170 /**< Correctable error first failing
* data Register, 927-896 */
#define XBRAM_CE_FFD_29_OFFSET 0x174 /**< Correctable error first failing
* data Register, 959-928 */
#define XBRAM_CE_FFD_30_OFFSET 0x178 /**< Correctable error first failing
* data Register, 991-960 */
#define XBRAM_CE_FFD_31_OFFSET 0x17C /**< Correctable error first failing
* data Register, 1023-992 */
#define XBRAM_CE_FFE_0_OFFSET 0x180 /**< Correctable error first failing
* ECC Register, 31-0 */
#define XBRAM_CE_FFE_1_OFFSET 0x184 /**< Correctable error first failing
* ECC Register, 63-32 */
#define XBRAM_CE_FFE_2_OFFSET 0x188 /**< Correctable error first failing
* ECC Register, 95-64 */
#define XBRAM_CE_FFE_3_OFFSET 0x18C /**< Correctable error first failing
* ECC Register, 127-96 */
#define XBRAM_CE_FFE_4_OFFSET 0x190 /**< Correctable error first failing
* ECC Register, 159-128 */
#define XBRAM_CE_FFE_5_OFFSET 0x194 /**< Correctable error first failing
* ECC Register, 191-160 */
#define XBRAM_CE_FFE_6_OFFSET 0x198 /**< Correctable error first failing
* ECC Register, 223-192 */
#define XBRAM_CE_FFE_7_OFFSET 0x19C /**< Correctable error first failing
* ECC Register, 255-224 */
#define XBRAM_CE_FFA_0_OFFSET 0x1C0 /**< Correctable error first failing
* address Register 31-0 */
#define XBRAM_CE_FFA_1_OFFSET 0x1C4 /**< Correctable error first failing
* address Register 63-32 */
#define XBRAM_UE_FFD_0_OFFSET 0x200 /**< Uncorrectable error first failing
* data Register, 31-0 */
#define XBRAM_UE_FFD_1_OFFSET 0x204 /**< Uncorrectable error first failing
* data Register, 63-32 */
#define XBRAM_UE_FFD_2_OFFSET 0x208 /**< Uncorrectable error first failing
* data Register, 95-64 */
#define XBRAM_UE_FFD_3_OFFSET 0x20C /**< Uncorrectable error first failing
* data Register, 127-96 */
#define XBRAM_UE_FFD_4_OFFSET 0x210 /**< Uncorrectable error first failing
* data Register, 159-128 */
#define XBRAM_UE_FFD_5_OFFSET 0x214 /**< Uncorrectable error first failing
* data Register, 191-160 */
#define XBRAM_UE_FFD_6_OFFSET 0x218 /**< Uncorrectable error first failing
* data Register, 223-192 */
#define XBRAM_UE_FFD_7_OFFSET 0x21C /**< Uncorrectable error first failing
* data Register, 255-224 */
#define XBRAM_UE_FFD_8_OFFSET 0x220 /**< Uncorrectable error first failing
* data Register, 287-256 */
#define XBRAM_UE_FFD_9_OFFSET 0x224 /**< Uncorrectable error first failing
* data Register, 319-288 */
#define XBRAM_UE_FFD_10_OFFSET 0x228 /**< Uncorrectable error first failing
* data Register, 351-320 */
#define XBRAM_UE_FFD_11_OFFSET 0x22C /**< Uncorrectable error first failing
* data Register, 383-352 */
#define XBRAM_UE_FFD_12_OFFSET 0x230 /**< Uncorrectable error first failing
* data Register, 415-384 */
#define XBRAM_UE_FFD_13_OFFSET 0x234 /**< Uncorrectable error first failing
* data Register, 447-416 */
#define XBRAM_UE_FFD_14_OFFSET 0x238 /**< Uncorrectable error first failing
* data Register, 479-448 */
#define XBRAM_UE_FFD_15_OFFSET 0x23C /**< Uncorrectable error first failing
* data Register, 511-480 */
#define XBRAM_UE_FFD_16_OFFSET 0x240 /**< Uncorrectable error first failing
* data Register, 543-512 */
#define XBRAM_UE_FFD_17_OFFSET 0x244 /**< Uncorrectable error first failing
* data Register, 575-544 */
#define XBRAM_UE_FFD_18_OFFSET 0x248 /**< Uncorrectable error first failing
* data Register, 607-576 */
#define XBRAM_UE_FFD_19_OFFSET 0x24C /**< Uncorrectable error first failing
* data Register, 639-608 */
#define XBRAM_UE_FFD_20_OFFSET 0x250 /**< Uncorrectable error first failing
* data Register, 671-640 */
#define XBRAM_UE_FFD_21_OFFSET 0x254 /**< Uncorrectable error first failing
* data Register, 703-672 */
#define XBRAM_UE_FFD_22_OFFSET 0x258 /**< Uncorrectable error first failing
* data Register, 735-704 */
#define XBRAM_UE_FFD_23_OFFSET 0x25C /**< Uncorrectable error first failing
* data Register, 767-736 */
#define XBRAM_UE_FFD_24_OFFSET 0x260 /**< Uncorrectable error first failing
* data Register, 799-768 */
#define XBRAM_UE_FFD_25_OFFSET 0x264 /**< Uncorrectable error first failing
* data Register, 831-800 */
#define XBRAM_UE_FFD_26_OFFSET 0x268 /**< Uncorrectable error first failing
* data Register, 863-832 */
#define XBRAM_UE_FFD_27_OFFSET 0x26C /**< Uncorrectable error first failing
* data Register, 895-864 */
#define XBRAM_UE_FFD_28_OFFSET 0x270 /**< Uncorrectable error first failing
* data Register, 927-896 */
#define XBRAM_UE_FFD_29_OFFSET 0x274 /**< Uncorrectable error first failing
* data Register, 959-928 */
#define XBRAM_UE_FFD_30_OFFSET 0x278 /**< Uncorrectable error first failing
* data Register, 991-960 */
#define XBRAM_UE_FFD_31_OFFSET 0x27C /**< Uncorrectable error first failing
* data Register, 1023-992 */
#define XBRAM_UE_FFE_0_OFFSET 0x280 /**< Uncorrectable error first failing
* ECC Register, 31-0 */
#define XBRAM_UE_FFE_1_OFFSET 0x284 /**< Uncorrectable error first failing
* ECC Register, 63-32 */
#define XBRAM_UE_FFE_2_OFFSET 0x288 /**< Uncorrectable error first failing
* ECC Register, 95-64 */
#define XBRAM_UE_FFE_3_OFFSET 0x28C /**< Uncorrectable error first failing
* ECC Register, 127-96 */
#define XBRAM_UE_FFE_4_OFFSET 0x290 /**< Uncorrectable error first failing
* ECC Register, 159-128 */
#define XBRAM_UE_FFE_5_OFFSET 0x294 /**< Uncorrectable error first failing
* ECC Register, 191-160 */
#define XBRAM_UE_FFE_6_OFFSET 0x298 /**< Uncorrectable error first failing
* ECC Register, 223-192 */
#define XBRAM_UE_FFE_7_OFFSET 0x29C /**< Uncorrectable error first failing
* ECC Register, 255-224 */
#define XBRAM_UE_FFA_0_OFFSET 0x2C0 /**< Uncorrectable error first failing
* address Register 31-0 */
#define XBRAM_UE_FFA_1_OFFSET 0x2C4 /**< Uncorrectable error first failing
* address Register 63-32 */
#define XBRAM_FI_D_0_OFFSET 0x300 /**< Fault injection Data Register,
* 31-0 */
#define XBRAM_FI_D_1_OFFSET 0x304 /**< Fault injection Data Register,
* 63-32 */
#define XBRAM_FI_D_2_OFFSET 0x308 /**< Fault injection Data Register,
* 95-64 */
#define XBRAM_FI_D_3_OFFSET 0x30C /**< Fault injection Data Register,
* 127-96 */
#define XBRAM_FI_D_4_OFFSET 0x310 /**< Fault injection Data Register,
* 159-128 */
#define XBRAM_FI_D_5_OFFSET 0x314 /**< Fault injection Data Register,
* 191-160 */
#define XBRAM_FI_D_6_OFFSET 0x318 /**< Fault injection Data Register,
* 223-192 */
#define XBRAM_FI_D_7_OFFSET 0x31C /**< Fault injection Data Register,
* 255-224 */
#define XBRAM_FI_D_8_OFFSET 0x320 /**< Fault injection Data Register,
* 287-256 */
#define XBRAM_FI_D_9_OFFSET 0x324 /**< Fault injection Data Register,
* 319-288 */
#define XBRAM_FI_D_10_OFFSET 0x328 /**< Fault injection Data Register,
* 351-320 */
#define XBRAM_FI_D_11_OFFSET 0x32C /**< Fault injection Data Register,
* 383-352 */
#define XBRAM_FI_D_12_OFFSET 0x330 /**< Fault injection Data Register,
* 415-384 */
#define XBRAM_FI_D_13_OFFSET 0x334 /**< Fault injection Data Register,
* 447-416 */
#define XBRAM_FI_D_14_OFFSET 0x338 /**< Fault injection Data Register,
* 479-448 */
#define XBRAM_FI_D_15_OFFSET 0x33C /**< Fault injection Data Register,
* 511-480 */
#define XBRAM_FI_D_16_OFFSET 0x340 /**< Fault injection Data Register,
* 543-512 */
#define XBRAM_FI_D_17_OFFSET 0x344 /**< Fault injection Data Register,
* 575-544 */
#define XBRAM_FI_D_18_OFFSET 0x348 /**< Fault injection Data Register,
* 607-576 */
#define XBRAM_FI_D_19_OFFSET 0x34C /**< Fault injection Data Register,
* 639-608 */
#define XBRAM_FI_D_20_OFFSET 0x350 /**< Fault injection Data Register,
* 671-640 */
#define XBRAM_FI_D_21_OFFSET 0x354 /**< Fault injection Data Register,
* 703-672 */
#define XBRAM_FI_D_22_OFFSET 0x358 /**< Fault injection Data Register,
* 735-704 */
#define XBRAM_FI_D_23_OFFSET 0x35C /**< Fault injection Data Register,
* 767-736 */
#define XBRAM_FI_D_24_OFFSET 0x360 /**< Fault injection Data Register,
* 799-768 */
#define XBRAM_FI_D_25_OFFSET 0x364 /**< Fault injection Data Register,
* 831-800 */
#define XBRAM_FI_D_26_OFFSET 0x368 /**< Fault injection Data Register,
* 863-832 */
#define XBRAM_FI_D_27_OFFSET 0x36C /**< Fault injection Data Register,
* 895-864 */
#define XBRAM_FI_D_28_OFFSET 0x370 /**< Fault injection Data Register,
* 927-896 */
#define XBRAM_FI_D_29_OFFSET 0x374 /**< Fault injection Data Register,
* 959-928 */
#define XBRAM_FI_D_30_OFFSET 0x378 /**< Fault injection Data Register,
* 991-960 */
#define XBRAM_FI_D_31_OFFSET 0x37C /**< Fault injection Data Register,
* 1023-992 */
#define XBRAM_FI_ECC_0_OFFSET 0x380 /**< Fault injection ECC Register,
* 31-0 */
#define XBRAM_FI_ECC_1_OFFSET 0x384 /**< Fault injection ECC Register,
* 63-32 */
#define XBRAM_FI_ECC_2_OFFSET 0x388 /**< Fault injection ECC Register,
* 95-64 */
#define XBRAM_FI_ECC_3_OFFSET 0x38C /**< Fault injection ECC Register,
* 127-96 */
#define XBRAM_FI_ECC_4_OFFSET 0x390 /**< Fault injection ECC Register,
* 159-128 */
#define XBRAM_FI_ECC_5_OFFSET 0x394 /**< Fault injection ECC Register,
* 191-160 */
#define XBRAM_FI_ECC_6_OFFSET 0x398 /**< Fault injection ECC Register,
* 223-192 */
#define XBRAM_FI_ECC_7_OFFSET 0x39C /**< Fault injection ECC Register,
* 255-224 */
/* @} */
/** @name Interrupt Status and Enable Register bitmaps and masks
*
* Bit definitions for the ECC status register and ECC interrupt enable register.
* @{
*/
#define XBRAM_IR_CE_MASK 0x2 /**< Mask for the correctable error */
#define XBRAM_IR_UE_MASK 0x1 /**< Mask for the uncorrectable error */
#define XBRAM_IR_ALL_MASK 0x3 /**< Mask of all bits */
/*@}*/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
#define XBram_In32 Xil_In32
#define XBram_Out32 Xil_Out32
#define XBram_In16 Xil_In16
#define XBram_Out16 Xil_Out16
#define XBram_In8 Xil_In8
#define XBram_Out8 Xil_Out8
/****************************************************************************/
/**
*
* Write a value to a BRAM register. A 32 bit write is performed.
*
* @param BaseAddress is the base address of the BRAM device register.
* @param RegOffset is the register offset from the base to write to.
* @param Data is the data written to the register.
*
* @return None.
*
* @note C-style signature:
* void XBram_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)
*
****************************************************************************/
#define XBram_WriteReg(BaseAddress, RegOffset, Data) \
XBram_Out32((BaseAddress) + (RegOffset), (u32)(Data))
/****************************************************************************/
/**
*
* Read a value from a BRAM register. A 32 bit read is performed.
*
* @param BaseAddress is the base address of the BRAM device registers.
* @param RegOffset is the register offset from the base to read from.
*
* @return Data read from the register.
*
* @note C-style signature:
* u32 XBram_ReadReg(u32 BaseAddress, u32 RegOffset)
*
****************************************************************************/
#define XBram_ReadReg(BaseAddress, RegOffset) \
XBram_In32((BaseAddress) + (RegOffset))
/************************** Function Prototypes ******************************/
/************************** Variable Definitions *****************************/
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */

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#ifndef XDEBUG
#define XDEBUG
#undef DEBUG
#if defined(DEBUG) && !defined(NDEBUG)
#ifndef XDEBUG_WARNING
#define XDEBUG_WARNING
#warning DEBUG is enabled
#endif
int printf(const char *format, ...);
#define XDBG_DEBUG_ERROR 0x00000001 /* error condition messages */
#define XDBG_DEBUG_GENERAL 0x00000002 /* general debug messages */
#define XDBG_DEBUG_ALL 0xFFFFFFFF /* all debugging data */
#define XDBG_DEBUG_FIFO_REG 0x00000100 /* display register reads/writes */
#define XDBG_DEBUG_FIFO_RX 0x00000101 /* receive debug messages */
#define XDBG_DEBUG_FIFO_TX 0x00000102 /* transmit debug messages */
#define XDBG_DEBUG_FIFO_ALL 0x0000010F /* all fifo debug messages */
#define XDBG_DEBUG_TEMAC_REG 0x00000400 /* display register reads/writes */
#define XDBG_DEBUG_TEMAC_RX 0x00000401 /* receive debug messages */
#define XDBG_DEBUG_TEMAC_TX 0x00000402 /* transmit debug messages */
#define XDBG_DEBUG_TEMAC_ALL 0x0000040F /* all temac debug messages */
#define XDBG_DEBUG_TEMAC_ADPT_RX 0x00000800 /* receive debug messages */
#define XDBG_DEBUG_TEMAC_ADPT_TX 0x00000801 /* transmit debug messages */
#define XDBG_DEBUG_TEMAC_ADPT_IOCTL 0x00000802 /* ioctl debug messages */
#define XDBG_DEBUG_TEMAC_ADPT_MISC 0x00000803 /* debug msg for other routines */
#define XDBG_DEBUG_TEMAC_ADPT_ALL 0x0000080F /* all temac adapter debug messages */
#define xdbg_current_types (XDBG_DEBUG_ERROR)
#define xdbg_stmnt(x) x
/* In VxWorks, if _WRS_GNU_VAR_MACROS is defined, special syntax is needed for
* macros that accept variable number of arguments
*/
#if defined(XENV_VXWORKS) && defined(_WRS_GNU_VAR_MACROS)
#define xdbg_printf(type, args...) (((type) & xdbg_current_types) ? printf (## args) : 0)
#else /* ANSI Syntax */
#define xdbg_printf(type, ...) (((type) & xdbg_current_types) ? printf (__VA_ARGS__) : 0)
#endif
#else /* defined(DEBUG) && !defined(NDEBUG) */
#define xdbg_stmnt(x)
/* See VxWorks comments above */
#if defined(XENV_VXWORKS) && defined(_WRS_GNU_VAR_MACROS)
#define xdbg_printf(type, args...)
#else /* ANSI Syntax */
#define xdbg_printf(...)
#endif
#endif /* defined(DEBUG) && !defined(NDEBUG) */
#endif /* XDEBUG */

177
software/LED_Controller_bsp/microblaze_mcs/include/xenv.h Executable file
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/******************************************************************************
*
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
* AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
* SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE,
* OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
* APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
* THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE.
*
* (c) Copyright 2002 Xilinx Inc.
* All rights reserved.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xenv.h
*
* Defines common services that are typically found in a host operating.
* environment. This include file simply includes an OS specific file based
* on the compile-time constant BUILD_ENV_*, where * is the name of the target
* environment.
*
* All services are defined as macros.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.00b ch 10/24/02 Added XENV_LINUX
* 1.00a rmm 04/17/02 First release
* </pre>
*
******************************************************************************/
#ifndef XENV_H /* prevent circular inclusions */
#define XENV_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/*
* Select which target environment we are operating under
*/
/* VxWorks target environment */
#if defined XENV_VXWORKS
#include "xenv_vxworks.h"
/* Linux target environment */
#elif defined XENV_LINUX
#include "xenv_linux.h"
/* Unit test environment */
#elif defined XENV_UNITTEST
#include "ut_xenv.h"
/* Integration test environment */
#elif defined XENV_INTTEST
#include "int_xenv.h"
/* Standalone environment selected */
#else
#include "xenv_standalone.h"
#endif
/*
* The following comments specify the types and macro wrappers that are
* expected to be defined by the target specific header files
*/
/**************************** Type Definitions *******************************/
/*****************************************************************************/
/**
*
* XENV_TIME_STAMP
*
* A structure that contains a time stamp used by other time stamp macros
* defined below. This structure is processor dependent.
*/
/***************** Macros (Inline Functions) Definitions *********************/
/*****************************************************************************/
/**
*
* XENV_MEM_COPY(void *DestPtr, void *SrcPtr, unsigned Bytes)
*
* Copies a non-overlapping block of memory.
*
* @param DestPtr is the destination address to copy data to.
* @param SrcPtr is the source address to copy data from.
* @param Bytes is the number of bytes to copy.
*
* @return None
*/
/*****************************************************************************/
/**
*
* XENV_MEM_FILL(void *DestPtr, char Data, unsigned Bytes)
*
* Fills an area of memory with constant data.
*
* @param DestPtr is the destination address to set.
* @param Data contains the value to set.
* @param Bytes is the number of bytes to set.
*
* @return None
*/
/*****************************************************************************/
/**
*
* XENV_TIME_STAMP_GET(XTIME_STAMP *StampPtr)
*
* Samples the processor's or external timer's time base counter.
*
* @param StampPtr is the storage for the retrieved time stamp.
*
* @return None
*/
/*****************************************************************************/
/**
*
* XENV_TIME_STAMP_DELTA_US(XTIME_STAMP *Stamp1Ptr, XTIME_STAMP* Stamp2Ptr)
*
* Computes the delta between the two time stamps.
*
* @param Stamp1Ptr - First sampled time stamp.
* @param Stamp1Ptr - Sedond sampled time stamp.
*
* @return An unsigned int value with units of microseconds.
*/
/*****************************************************************************/
/**
*
* XENV_TIME_STAMP_DELTA_MS(XTIME_STAMP *Stamp1Ptr, XTIME_STAMP* Stamp2Ptr)
*
* Computes the delta between the two time stamps.
*
* @param Stamp1Ptr - First sampled time stamp.
* @param Stamp1Ptr - Sedond sampled time stamp.
*
* @return An unsigned int value with units of milliseconds.
*/
/*****************************************************************************//**
*
* XENV_USLEEP(unsigned delay)
*
* Delay the specified number of microseconds.
*
* @param delay is the number of microseconds to delay.
*
* @return None
*/
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */

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/******************************************************************************
*
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
* AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
* SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE,
* OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
* APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
* THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE.
*
* (c) Copyright 2002 Xilinx Inc.
* All rights reserved.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xenv_none.h
*
* This is a legacy file kept for backwards compatibility.
*
* Please modify your code to #include "xenv_standalone.h" instead.
*
*
******************************************************************************/
#warning ********************************************************************
#warning *
#warning * Use of xenv_none.h deprecated.
#warning * Please include the new xenv_standalone.h file instead.
#warning *
#warning ********************************************************************
#include "xenv_standalone.h"

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/******************************************************************************
*
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
* AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
* SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE,
* OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
* APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
* THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE.
*
* (c) Copyright 2002-2008 Xilinx Inc.
* All rights reserved.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xenv_standalone.h
*
* Defines common services specified by xenv.h.
*
* @note
* This file is not intended to be included directly by driver code.
* Instead, the generic xenv.h file is intended to be included by driver
* code.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.00a wgr 02/28/07 Added cache handling macros.
* 1.00a wgr 02/27/07 Simplified code. Deprecated old-style macro names.
* 1.00a rmm 01/24/06 Implemented XENV_USLEEP. Assume implementation is being
* used under Xilinx standalone BSP.
* 1.00a xd 11/03/04 Improved support for doxygen.
* 1.00a rmm 03/21/02 First release
* 1.00a wgr 03/22/07 Converted to new coding style.
* 1.00a rpm 06/29/07 Added udelay macro for standalone
* 1.00a xd 07/19/07 Included xparameters.h as XPAR_ constants are referred
* to in MICROBLAZE section
* 1.00a ecm 09/19/08 updated for v7.20 of Microblaze, new functionality
*
* </pre>
*
*
******************************************************************************/
#ifndef XENV_STANDALONE_H
#define XENV_STANDALONE_H
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
/******************************************************************************
*
* Get the processor dependent includes
*
******************************************************************************/
#include <string.h>
#if defined __MICROBLAZE__
# include "mb_interface.h"
# include "xparameters.h" /* XPAR constants used below in MB section */
#elif defined __PPC__
# include "sleep.h"
# include "xcache_l.h" /* also include xcache_l.h for caching macros */
#endif
/******************************************************************************
*
* MEMCPY / MEMSET related macros.
*
* The following are straight forward implementations of memset and memcpy.
*
* NOTE: memcpy may not work if source and target memory area are overlapping.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* Copies a non-overlapping block of memory.
*
* @param DestPtr
* Destination address to copy data to.
*
* @param SrcPtr
* Source address to copy data from.
*
* @param Bytes
* Number of bytes to copy.
*
* @return None.
*
* @note
* The use of XENV_MEM_COPY is deprecated. Use memcpy() instead.
*
* @note
* This implemention MAY BREAK work if source and target memory
* area are overlapping.
*
*****************************************************************************/
#define XENV_MEM_COPY(DestPtr, SrcPtr, Bytes) \
memcpy((void *) DestPtr, (const void *) SrcPtr, (size_t) Bytes)
/*****************************************************************************/
/**
*
* Fills an area of memory with constant data.
*
* @param DestPtr
* Destination address to copy data to.
*
* @param Data
* Value to set.
*
* @param Bytes
* Number of bytes to copy.
*
* @return None.
*
* @note
* The use of XENV_MEM_FILL is deprecated. Use memset() instead.
*
*****************************************************************************/
#define XENV_MEM_FILL(DestPtr, Data, Bytes) \
memset((void *) DestPtr, (int) Data, (size_t) Bytes)
/******************************************************************************
*
* TIME related macros
*
******************************************************************************/
/**
* A structure that contains a time stamp used by other time stamp macros
* defined below. This structure is processor dependent.
*/
typedef int XENV_TIME_STAMP;
/*****************************************************************************/
/**
*
* Time is derived from the 64 bit PPC timebase register
*
* @param StampPtr is the storage for the retrieved time stamp.
*
* @return None.
*
* @note
*
* Signature: void XENV_TIME_STAMP_GET(XTIME_STAMP *StampPtr)
* <br><br>
* This macro must be implemented by the user.
*
*****************************************************************************/
#define XENV_TIME_STAMP_GET(StampPtr)
/*****************************************************************************/
/**
*
* This macro is not yet implemented and always returns 0.
*
* @param Stamp1Ptr is the first sampled time stamp.
* @param Stamp2Ptr is the second sampled time stamp.
*
* @return 0
*
* @note
*
* This macro must be implemented by the user.
*
*****************************************************************************/
#define XENV_TIME_STAMP_DELTA_US(Stamp1Ptr, Stamp2Ptr) (0)
/*****************************************************************************/
/**
*
* This macro is not yet implemented and always returns 0.
*
* @param Stamp1Ptr is the first sampled time stamp.
* @param Stamp2Ptr is the second sampled time stamp.
*
* @return 0
*
* @note
*
* This macro must be implemented by the user.
*
*****************************************************************************/
#define XENV_TIME_STAMP_DELTA_MS(Stamp1Ptr, Stamp2Ptr) (0)
/*****************************************************************************/
/**
* XENV_USLEEP(unsigned delay)
*
* Delay the specified number of microseconds. Not implemented without OS
* support.
*
* @param delay
* Number of microseconds to delay.
*
* @return None.
*
*****************************************************************************/
#ifdef __PPC__
#define XENV_USLEEP(delay) usleep(delay)
#define udelay(delay) usleep(delay)
#else
#define XENV_USLEEP(delay)
#define udelay(delay)
#endif
/******************************************************************************
*
* CACHE handling macros / mappings
*
******************************************************************************/
/******************************************************************************
*
* Processor independent macros
*
******************************************************************************/
#define XCACHE_ENABLE_CACHE() \
{ XCACHE_ENABLE_DCACHE(); XCACHE_ENABLE_ICACHE(); }
#define XCACHE_DISABLE_CACHE() \
{ XCACHE_DISABLE_DCACHE(); XCACHE_DISABLE_ICACHE(); }
/******************************************************************************
*
* MicroBlaze case
*
* NOTE: Currently the following macros will only work on systems that contain
* only ONE MicroBlaze processor. Also, the macros will only be enabled if the
* system is built using a xparameters.h file.
*
******************************************************************************/
#if defined __MICROBLAZE__
/* Check if MicroBlaze data cache was built into the core.
*/
#if (XPAR_MICROBLAZE_USE_DCACHE == 1)
# define XCACHE_ENABLE_DCACHE() microblaze_enable_dcache()
# define XCACHE_DISABLE_DCACHE() microblaze_disable_dcache()
# define XCACHE_INVALIDATE_DCACHE() microblaze_invalidate_dcache()
# define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len) \
microblaze_invalidate_dcache_range((int)(Addr), (int)(Len))
#if (XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK == 1)
# define XCACHE_FLUSH_DCACHE() microblaze_flush_dcache()
# define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \
microblaze_flush_dcache_range((int)(Addr), (int)(Len))
#else
# define XCACHE_FLUSH_DCACHE() microblaze_invalidate_dcache()
# define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \
microblaze_invalidate_dcache_range((int)(Addr), (int)(Len))
#endif /*XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK*/
#else
# define XCACHE_ENABLE_DCACHE()
# define XCACHE_DISABLE_DCACHE()
# define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len)
# define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len)
#endif /*XPAR_MICROBLAZE_USE_DCACHE*/
/* Check if MicroBlaze instruction cache was built into the core.
*/
#if (XPAR_MICROBLAZE_USE_ICACHE == 1)
# define XCACHE_ENABLE_ICACHE() microblaze_enable_icache()
# define XCACHE_DISABLE_ICACHE() microblaze_disable_icache()
# define XCACHE_INVALIDATE_ICACHE() microblaze_invalidate_icache()
# define XCACHE_INVALIDATE_ICACHE_RANGE(Addr, Len) \
microblaze_invalidate_icache_range((int)(Addr), (int)(Len))
#else
# define XCACHE_ENABLE_ICACHE()
# define XCACHE_DISABLE_ICACHE()
#endif /*XPAR_MICROBLAZE_USE_ICACHE*/
/******************************************************************************
*
* PowerPC case
*
* Note that the XCACHE_ENABLE_xxx functions are hardcoded to enable a
* specific memory region (0x80000001). Each bit (0-30) in the regions
* bitmask stands for 128MB of memory. Bit 31 stands for the upper 2GB
* range.
*
* regions --> cached address range
* ------------|--------------------------------------------------
* 0x80000000 | [0, 0x7FFFFFF]
* 0x00000001 | [0xF8000000, 0xFFFFFFFF]
* 0x80000001 | [0, 0x7FFFFFF],[0xF8000000, 0xFFFFFFFF]
*
******************************************************************************/
#elif defined __PPC__
#define XCACHE_ENABLE_DCACHE() XCache_EnableDCache(0x80000001)
#define XCACHE_DISABLE_DCACHE() XCache_DisableDCache()
#define XCACHE_ENABLE_ICACHE() XCache_EnableICache(0x80000001)
#define XCACHE_DISABLE_ICACHE() XCache_DisableICache()
#define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len) \
XCache_InvalidateDCacheRange((unsigned int)(Addr), (unsigned)(Len))
#define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \
XCache_FlushDCacheRange((unsigned int)(Addr), (unsigned)(Len))
#define XCACHE_INVALIDATE_ICACHE() XCache_InvalidateICache()
/******************************************************************************
*
* Unknown processor / architecture
*
******************************************************************************/
#else
/* #error "Unknown processor / architecture. Must be MicroBlaze or PowerPC." */
#endif
#ifdef __cplusplus
}
#endif
#endif /* #ifndef XENV_STANDALONE_H */

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/******************************************************************************
*
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
* AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
* SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE,
* OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
* APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
* THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE.
*
* (c) Copyright 2002-2007 Xilinx Inc.
* All rights reserved.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xenv_vxworks.h
*
* Defines common services specified by xenv.h.
*
* @note
* This file is not intended to be included directly by driver code.
* Instead, the generic xenv.h file is intended to be included by driver
* code.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.00a wgr 02/28/07 Added cache handling macros.
* 1.00a wgr 02/27/07 Simplified code. Deprecated old-style macro names.
* 1.00a xd 11/03/04 Improved support for doxygen.
* rmm 09/13/03 CR 177068: Fix compiler warning in XENV_MEM_FILL
* rmm 10/24/02 Added XENV_USLEEP macro
* 1.00a rmm 07/16/01 First release
* 1.10a wgr 03/22/07 Converted to new coding style.
* </pre>
*
*
******************************************************************************/
#ifndef XENV_VXWORKS_H
#define XENV_VXWORKS_H
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xbasic_types.h"
#include "vxWorks.h"
#include "vxLib.h"
#include "sysLibExtra.h"
#include "cacheLib.h"
#include <string.h>
/*****************************************************************************/
/**
*
* Copies a non-overlapping block of memory.
*
* @param DestPtr
* Destination address to copy data to.
*
* @param SrcPtr
* Source address to copy data from.
*
* @param Bytes
* Number of bytes to copy.
*
* @return None.
*
* @note XENV_MEM_COPY is deprecated. Use memcpy() instead.
*
*****************************************************************************/
#define XENV_MEM_COPY(DestPtr, SrcPtr, Bytes) \
memcpy((void *) DestPtr, (const void *) SrcPtr, (size_t) Bytes)
/*****************************************************************************/
/**
*
* Fills an area of memory with constant data.
*
* @param DestPtr
* Destination address to copy data to.
*
* @param Data
* Value to set.
*
* @param Bytes
* Number of bytes to copy.
*
* @return None.
*
* @note XENV_MEM_FILL is deprecated. Use memset() instead.
*
*****************************************************************************/
#define XENV_MEM_FILL(DestPtr, Data, Bytes) \
memset((void *) DestPtr, (int) Data, (size_t) Bytes)
#if (CPU_FAMILY==PPC)
/**
* A structure that contains a time stamp used by other time stamp macros
* defined below. This structure is processor dependent.
*/
typedef struct
{
u32 TimeBaseUpper;
u32 TimeBaseLower;
} XENV_TIME_STAMP;
/*****************************************************************************/
/**
*
* Time is derived from the 64 bit PPC timebase register
*
* @param StampPtr is the storage for the retrieved time stamp.
*
* @return None.
*
* @note
*
* Signature: void XENV_TIME_STAMP_GET(XTIME_STAMP *StampPtr)
*
*****************************************************************************/
#define XENV_TIME_STAMP_GET(StampPtr) \
{ \
vxTimeBaseGet((UINT32*)&(StampPtr)->TimeBaseUpper, \
(UINT32*)&(StampPtr)->TimeBaseLower); \
}
/*****************************************************************************/
/**
*
* This macro is not yet implemented and always returns 0.
*
* @param Stamp1Ptr is the first sampled time stamp.
* @param Stamp2Ptr is the second sampled time stamp.
*
* @return 0
*
* @note None.
*
*****************************************************************************/
#define XENV_TIME_STAMP_DELTA_US(Stamp1Ptr, Stamp2Ptr) (0)
/*****************************************************************************/
/**
*
* This macro is not yet implemented and always returns 0.
*
* @param Stamp1Ptr is the first sampled time stamp.
* @param Stamp2Ptr is the second sampled time stamp.
*
* @return 0
*
* @note
*
* None.
*
*****************************************************************************/
#define XENV_TIME_STAMP_DELTA_MS(Stamp1Ptr, Stamp2Ptr) (0)
/* For non-PPC systems the above macros are not defined. Generate a error to
* make the developer aware of the problem.
*/
#else
#error "XENV_TIME_STAMP_GET used in a non-PPC system. Aborting."
#endif
/*****************************************************************************/
/**
*
* Delay the specified number of microseconds.
*
* @param delay
* Number of microseconds to delay.
*
* @return None.
*
*****************************************************************************/
#define XENV_USLEEP(delay) sysUsDelay(delay)
#define udelay(delay) sysUsDelay(delay)
/******************************************************************************
*
* CACHE handling macros / mappings
*
******************************************************************************/
/******************************************************************************
*
* PowerPC case
*
******************************************************************************/
#if (CPU_FAMILY==PPC)
#define XCACHE_ENABLE_CACHE() \
{ XCACHE_ENABLE_DCACHE(); XCACHE_ENABLE_ICACHE(); }
#define XCACHE_DISABLE_CACHE() \
{ XCACHE_DISABLE_DCACHE(); XCACHE_DISABLE_ICACHE(); }
#define XCACHE_ENABLE_DCACHE() cacheEnable(DATA_CACHE)
#define XCACHE_DISABLE_DCACHE() cacheDisable(DATA_CACHE)
#define XCACHE_ENABLE_ICACHE() cacheEnable(INSTRUCTION_CACHE)
#define XCACHE_DISABLE_ICACHE() cacheDisable(INSTRUCTION_CACHE)
#define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len) \
cacheInvalidate(DATA_CACHE, (void *)(Addr), (Len))
#define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \
cacheFlush(DATA_CACHE, (void *)(Addr), (Len))
#define XCACHE_INVALIDATE_ICACHE_RANGE(Addr, Len) \
cacheInvalidate(INSTRUCTION_CACHE, (void *)(Addr), (Len))
#define XCACHE_FLUSH_ICACHE_RANGE(Addr, Len) \
cacheFlush(INSTRUCTION_CACHE, (void *)(Addr), (Len))
/******************************************************************************
*
* Unknown processor / architecture
*
******************************************************************************/
#else
#error "Unknown processor / architecture. Must be PPC for VxWorks."
#endif
#ifdef __cplusplus
}
#endif
#endif /* #ifdef XENV_VXWORKS_H */

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/******************************************************************************
*
* (c) Copyright 2009 Xilinx, Inc. All rights reserved.
*
* This file contains confidential and proprietary information of Xilinx, Inc.
* and is protected under U.S. and international copyright and other
* intellectual property laws.
*
* DISCLAIMER
* This disclaimer is not a license and does not grant any rights to the
* materials distributed herewith. Except as otherwise provided in a valid
* license issued to you by Xilinx, and to the maximum extent permitted by
* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
* and (2) Xilinx shall not be liable (whether in contract or tort, including
* negligence, or under any other theory of liability) for any loss or damage
* of any kind or nature related to, arising under or in connection with these
* materials, including for any direct, or any indirect, special, incidental,
* or consequential loss or damage (including loss of data, profits, goodwill,
* or any type of loss or damage suffered as a result of any action brought by
* a third party) even if such damage or loss was reasonably foreseeable or
* Xilinx had been advised of the possibility of the same.
*
* CRITICAL APPLICATIONS
* Xilinx products are not designed or intended to be fail-safe, or for use in
* any application requiring fail-safe performance, such as life-support or
* safety devices or systems, Class III medical devices, nuclear facilities,
* applications related to the deployment of airbags, or any other applications
* that could lead to death, personal injury, or severe property or
* environmental damage (individually and collectively, "Critical
* Applications"). Customer assumes the sole risk and liability of any use of
* Xilinx products in Critical Applications, subject only to applicable laws
* and regulations governing limitations on product liability.
*
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
* AT ALL TIMES.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xil_assert.h
*
* This file contains assert related functions.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00a hbm 07/14/09 First release
* </pre>
*
******************************************************************************/
#ifndef XIL_ASSERT_H /* prevent circular inclusions */
#define XIL_ASSERT_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
/************************** Constant Definitions *****************************/
#define XIL_ASSERT_NONE 0
#define XIL_ASSERT_OCCURRED 1
extern unsigned int Xil_AssertStatus;
extern void Xil_Assert(const char *, int);
/**
* This data type defines a callback to be invoked when an
* assert occurs. The callback is invoked only when asserts are enabled
*/
typedef void (*Xil_AssertCallback) (const char *File, int Line);
/***************** Macros (Inline Functions) Definitions *********************/
#ifndef NDEBUG
/*****************************************************************************/
/**
* This assert macro is to be used for functions that do not return anything
* (void). This in conjunction with the Xil_AssertWait boolean can be used to
* accomodate tests so that asserts which fail allow execution to continue.
*
* @param expression is the expression to evaluate. If it evaluates to
* false, the assert occurs.
*
* @return Returns void unless the Xil_AssertWait variable is true, in which
* case no return is made and an infinite loop is entered.
*
* @note None.
*
******************************************************************************/
#define Xil_AssertVoid(Expression) \
{ \
if (Expression) { \
Xil_AssertStatus = XIL_ASSERT_NONE; \
} else { \
Xil_Assert(__FILE__, __LINE__); \
Xil_AssertStatus = XIL_ASSERT_OCCURRED; \
return; \
} \
}
/*****************************************************************************/
/**
* This assert macro is to be used for functions that do return a value. This in
* conjunction with the Xil_AssertWait boolean can be used to accomodate tests
* so that asserts which fail allow execution to continue.
*
* @param expression is the expression to evaluate. If it evaluates to false,
* the assert occurs.
*
* @return Returns 0 unless the Xil_AssertWait variable is true, in which
* case no return is made and an infinite loop is entered.
*
* @note None.
*
******************************************************************************/
#define Xil_AssertNonvoid(Expression) \
{ \
if (Expression) { \
Xil_AssertStatus = XIL_ASSERT_NONE; \
} else { \
Xil_Assert(__FILE__, __LINE__); \
Xil_AssertStatus = XIL_ASSERT_OCCURRED; \
return 0; \
} \
}
/*****************************************************************************/
/**
* Always assert. This assert macro is to be used for functions that do not
* return anything (void). Use for instances where an assert should always
* occur.
*
* @return Returns void unless the Xil_AssertWait variable is true, in which
* case no return is made and an infinite loop is entered.
*
* @note None.
*
******************************************************************************/
#define Xil_AssertVoidAlways() \
{ \
Xil_Assert(__FILE__, __LINE__); \
Xil_AssertStatus = XIL_ASSERT_OCCURRED; \
return; \
}
/*****************************************************************************/
/**
* Always assert. This assert macro is to be used for functions that do return
* a value. Use for instances where an assert should always occur.
*
* @return Returns void unless the Xil_AssertWait variable is true, in which
* case no return is made and an infinite loop is entered.
*
* @note None.
*
******************************************************************************/
#define Xil_AssertNonvoidAlways() \
{ \
Xil_Assert(__FILE__, __LINE__); \
Xil_AssertStatus = XIL_ASSERT_OCCURRED; \
return 0; \
}
#else
#define Xil_AssertVoid(Expression)
#define Xil_AssertVoidAlways()
#define Xil_AssertNonvoid(Expression)
#define Xil_AssertNonvoidAlways()
#endif
/************************** Function Prototypes ******************************/
void Xil_AssertSetCallback(Xil_AssertCallback Routine);
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */

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/******************************************************************************
*
* (c) Copyright 2009-2013 Xilinx, Inc. All rights reserved.
*
* This file contains confidential and proprietary information of Xilinx, Inc.
* and is protected under U.S. and international copyright and other
* intellectual property laws.
*
* DISCLAIMER
* This disclaimer is not a license and does not grant any rights to the
* materials distributed herewith. Except as otherwise provided in a valid
* license issued to you by Xilinx, and to the maximum extent permitted by
* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
* and (2) Xilinx shall not be liable (whether in contract or tort, including
* negligence, or under any other theory of liability) for any loss or damage
* of any kind or nature related to, arising under or in connection with these
* materials, including for any direct, or any indirect, special, incidental,
* or consequential loss or damage (including loss of data, profits, goodwill,
* or any type of loss or damage suffered as a result of any action brought by
* a third party) even if such damage or loss was reasonably foreseeable or
* Xilinx had been advised of the possibility of the same.
*
* CRITICAL APPLICATIONS
* Xilinx products are not designed or intended to be fail-safe, or for use in
* any application requiring fail-safe performance, such as life-support or
* safety devices or systems, Class III medical devices, nuclear facilities,
* applications related to the deployment of airbags, or any other applications
* that could lead to death, personal injury, or severe property or
* environmental damage (individually and collectively, "Critical
* Applications"). Customer assumes the sole risk and liability of any use of
* Xilinx products in Critical Applications, subject only to applicable laws
* and regulations governing limitations on product liability.
*
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
* AT ALL TIMES.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xil_cache.h
*
* This header file contains cache related driver functions (or macros)
* that can be used to access the device. The user should refer to the
* hardware device specification for more details of the device operation.
* The functions in this header file can be used across all Xilinx supported
* processors.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00 hbm 07/28/09 Initial release
* 3.02a sdm 10/24/11 Updated the file to include xparameters.h so that
* the correct cache flush routines are used based on
* whether the write-back or write-through caches are
* used (cr #630532).
* 3.10a asa 05/04/13 This version of MicroBlaze BSP adds support for system
* cache/L2 cache. The existing/old APIs/macros in this
* file are renamed to imply that they deal with L1 cache.
* New macros/APIs are added to address similar features for
* L2 cache. Users can include this file in their application
* to use the various cache related APIs. These changes are
* done for implementing PR #697214.
*
* </pre>
*
* @note
*
* None.
*
******************************************************************************/
#ifndef XIL_CACHE_H
#define XIL_CACHE_H
#if defined XENV_VXWORKS
/* VxWorks environment */
#error "Unknown processor / architecture. Must be PPC for VxWorks."
#else
/* standalone environment */
#include "mb_interface.h"
#include "xil_types.h"
#include "xparameters.h"
#ifdef __cplusplus
extern "C" {
#endif
/****************************************************************************/
/**
*
* Invalidate the entire L1 data cache. If the cacheline is modified (dirty),
* the modified contents are lost.
*
* @param None.
*
* @return None.
*
* @note
*
* Processor must be in real mode.
****************************************************************************/
#define Xil_L1DCacheInvalidate() microblaze_invalidate_dcache()
/****************************************************************************/
/**
*
* Invalidate the entire L2 data cache. If the cacheline is modified (dirty),
* the modified contents are lost.
*
* @param None.
*
* @return None.
*
* @note
*
* Processor must be in real mode.
****************************************************************************/
#define Xil_L2CacheInvalidate() microblaze_invalidate_cache_ext()
/****************************************************************************/
/**
*
* Invalidate the L1 data cache for the given address range.
* If the bytes specified by the address (Addr) are cached by the L1 data cache,
* the cacheline containing that byte is invalidated. If the cacheline
* is modified (dirty), the modified contents are lost.
*
* @param Addr is address of ragne to be invalidated.
* @param Len is the length in bytes to be invalidated.
*
* @return None.
*
* @note
*
* Processor must be in real mode.
****************************************************************************/
#define Xil_L1DCacheInvalidateRange(Addr, Len) \
microblaze_invalidate_dcache_range(Addr, Len)
/****************************************************************************/
/**
*
* Invalidate the L1 data cache for the given address range.
* If the bytes specified by the address (Addr) are cached by the L1 data cache,
* the cacheline containing that byte is invalidated. If the cacheline
* is modified (dirty), the modified contents are lost.
*
* @param Addr is address of ragne to be invalidated.
* @param Len is the length in bytes to be invalidated.
*
* @return None.
*
* @note
*
* Processor must be in real mode.
****************************************************************************/
#define Xil_L2CacheInvalidateRange(Addr, Len) \
microblaze_invalidate_cache_ext_range(Addr, Len)
/****************************************************************************/
/**
* Flush the L1 data cache for the given address range.
* If the bytes specified by the address (Addr) are cached by the data cache,
* and is modified (dirty), the cacheline will be written to system memory.
* The cacheline will also be invalidated.
*
* @param Addr is the starting address of the range to be flushed.
* @param Len is the length in byte to be flushed.
*
* @return None.
*
****************************************************************************/
#if (XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK == 1)
# define Xil_L1DCacheFlushRange(Addr, Len) \
microblaze_flush_dcache_range(Addr, Len)
#else
# define Xil_L1DCacheFlushRange(Addr, Len) \
microblaze_invalidate_dcache_range(Addr, Len)
#endif /* XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK */
/****************************************************************************/
/**
* Flush the L2 data cache for the given address range.
* If the bytes specified by the address (Addr) are cached by the data cache,
* and is modified (dirty), the cacheline will be written to system memory.
* The cacheline will also be invalidated.
*
* @param Addr is the starting address of the range to be flushed.
* @param Len is the length in byte to be flushed.
*
* @return None.
*
****************************************************************************/
#define Xil_L2CacheFlushRange(Addr, Len) \
microblaze_flush_cache_ext_range(Addr, Len)
/****************************************************************************/
/**
* Flush the entire L1 data cache. If any cacheline is dirty, the cacheline will be
* written to system memory. The entire data cache will be invalidated.
*
* @return None.
*
* @note
*
****************************************************************************/
#if (XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK == 1)
# define Xil_L1DCacheFlush() microblaze_flush_dcache()
#else
# define Xil_L1DCacheFlush() microblaze_invalidate_dcache()
#endif /* XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK */
/****************************************************************************/
/**
* Flush the entire L2 data cache. If any cacheline is dirty, the cacheline will be
* written to system memory. The entire data cache will be invalidated.
*
* @return None.
*
* @note
*
****************************************************************************/
#define Xil_L2CacheFlush() microblaze_flush_cache_ext()
/****************************************************************************/
/**
*
* Invalidate the instruction cache for the given address range.
*
* @param Addr is address of ragne to be invalidated.
* @param Len is the length in bytes to be invalidated.
*
* @return None.
*
****************************************************************************/
#define Xil_L1ICacheInvalidateRange(Addr, Len) \
microblaze_invalidate_icache_range(Addr, Len)
/****************************************************************************/
/**
*
* Invalidate the entire instruction cache.
*
* @param None
*
* @return None.
*
****************************************************************************/
#define Xil_L1ICacheInvalidate() \
microblaze_invalidate_icache()
/****************************************************************************/
/**
*
* Enable the L1 data cache.
*
* @return None.
*
* @note This is processor specific.
*
****************************************************************************/
#define Xil_L1DCacheEnable() \
microblaze_enable_dcache()
/****************************************************************************/
/**
*
* Disable the L1 data cache.
*
* @return None.
*
* @note This is processor specific.
*
****************************************************************************/
#define Xil_L1DCacheDisable() \
microblaze_disable_dcache()
/****************************************************************************/
/**
*
* Enable the instruction cache.
*
* @return None.
*
* @note This is processor specific.
*
****************************************************************************/
#define Xil_L1ICacheEnable() \
microblaze_enable_icache()
/****************************************************************************/
/**
*
* Disable the L1 Instruction cache.
*
* @return None.
*
* @note This is processor specific.
*
****************************************************************************/
#define Xil_L1ICacheDisable() \
microblaze_disable_icache()
/****************************************************************************/
/**
*
* Enable the data cache.
*
* @param None
*
* @return None.
*
****************************************************************************/
#define Xil_DCacheEnable() Xil_L1DCacheEnable()
/****************************************************************************/
/**
*
* Enable the instruction cache.
*
* @param None
*
* @return None.
*
* @note
*
*
****************************************************************************/
#define Xil_ICacheEnable() Xil_L1ICacheEnable()
/****************************************************************************
*
* Invalidate the entire Data cache.
*
* @param None.
*
* @return None.
*
* @note None.
*
****************************************************************************/
#define Xil_DCacheInvalidate() \
Xil_L2CacheInvalidate(); \
Xil_L1DCacheInvalidate();
/****************************************************************************
*
* Invalidate the Data cache for the given address range.
* If the bytes specified by the address (adr) are cached by the Data cache,
* the cacheline containing that byte is invalidated. If the cacheline
* is modified (dirty), the modified contents are lost and are NOT
* written to system memory before the line is invalidated.
*
* @param Start address of ragne to be invalidated.
* @param Length of range to be invalidated in bytes.
*
* @return None.
*
* @note None.
*
****************************************************************************/
#define Xil_DCacheInvalidateRange(Addr, Len) \
Xil_L2CacheInvalidateRange(Addr, Len); \
Xil_L1DCacheInvalidateRange(Addr, Len);
/****************************************************************************
*
* Flush the entire Data cache.
*
* @param None.
*
* @return None.
*
* @note None.
*
****************************************************************************/
#define Xil_DCacheFlush() \
Xil_L2CacheFlush(); \
Xil_L1DCacheFlush();
/****************************************************************************
* Flush the Data cache for the given address range.
* If the bytes specified by the address (adr) are cached by the Data cache,
* the cacheline containing that byte is invalidated. If the cacheline
* is modified (dirty), the written to system memory first before the
* before the line is invalidated.
*
* @param Start address of range to be flushed.
* @param Length of range to be flushed in bytes.
*
* @return None.
*
* @note None.
*
****************************************************************************/
#define Xil_DCacheFlushRange(Addr, Len) \
Xil_L2CacheFlushRange(Addr, Len); \
Xil_L1DCacheFlushRange(Addr, Len);
/****************************************************************************
*
* Invalidate the entire instruction cache.
*
* @param None.
*
* @return None.
*
* @note None.
*
****************************************************************************/
#define Xil_ICacheInvalidate() \
Xil_L2CacheInvalidate(); \
Xil_L1ICacheInvalidate();
/****************************************************************************
*
* Invalidate the instruction cache for the given address range.
* If the bytes specified by the address (adr) are cached by the Data cache,
* the cacheline containing that byte is invalidated. If the cacheline
* is modified (dirty), the modified contents are lost and are NOT
* written to system memory before the line is invalidated.
*
* @param Start address of ragne to be invalidated.
* @param Length of range to be invalidated in bytes.
*
* @return None.
*
* @note None.
*
****************************************************************************/
#define Xil_ICacheInvalidateRange(Addr, Len) \
Xil_L2CacheInvalidateRange(Addr, Len); \
Xil_L1ICacheInvalidateRange(Addr, Len);
void Xil_DCacheDisable(void);
void Xil_ICacheDisable(void);
#ifdef __cplusplus
}
#endif
#endif
#endif

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/******************************************************************************
*
* (c) Copyright 2009 Xilinx, Inc. All rights reserved.
*
* This file contains confidential and proprietary information of Xilinx, Inc.
* and is protected under U.S. and international copyright and other
* intellectual property laws.
*
* DISCLAIMER
* This disclaimer is not a license and does not grant any rights to the
* materials distributed herewith. Except as otherwise provided in a valid
* license issued to you by Xilinx, and to the maximum extent permitted by
* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
* and (2) Xilinx shall not be liable (whether in contract or tort, including
* negligence, or under any other theory of liability) for any loss or damage
* of any kind or nature related to, arising under or in connection with these
* materials, including for any direct, or any indirect, special, incidental,
* or consequential loss or damage (including loss of data, profits, goodwill,
* or any type of loss or damage suffered as a result of any action brought by
* a third party) even if such damage or loss was reasonably foreseeable or
* Xilinx had been advised of the possibility of the same.
*
* CRITICAL APPLICATIONS
* Xilinx products are not designed or intended to be fail-safe, or for use in
* any application requiring fail-safe performance, such as life-support or
* safety devices or systems, Class III medical devices, nuclear facilities,
* applications related to the deployment of airbags, or any other applications
* that could lead to death, personal injury, or severe property or
* environmental damage (individually and collectively, "Critical
* Applications"). Customer assumes the sole risk and liability of any use of
* Xilinx products in Critical Applications, subject only to applicable laws
* and regulations governing limitations on product liability.
*
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
* AT ALL TIMES.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xil_cache_vxworks.h
*
* Contains the cache related functions for VxWorks that is wrapped by
* xil_cache.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00a hbm 12/11/09 Initial release
*
* </pre>
*
* @note
*
******************************************************************************/
#ifndef XIL_CACHE_VXWORKS_H
#define XIL_CACHE_VXWORKS_H
#ifdef __cplusplus
extern "C" {
#endif
#include "vxWorks.h"
#include "vxLib.h"
#include "sysLibExtra.h"
#include "cacheLib.h"
#if (CPU_FAMILY==PPC)
#define Xil_DCacheEnable() cacheEnable(DATA_CACHE)
#define Xil_DCacheDisable() cacheDisable(DATA_CACHE)
#define Xil_DCacheInvalidateRange(Addr, Len) \
cacheInvalidate(DATA_CACHE, (void *)(Addr), (Len))
#define Xil_DCacheFlushRange(Addr, Len) \
cacheFlush(DATA_CACHE, (void *)(Addr), (Len))
#define Xil_ICacheEnable() cacheEnable(INSTRUCTION_CACHE)
#define Xil_ICacheDisable() cacheDisable(INSTRUCTION_CACHE)
#define Xil_ICacheInvalidateRange(Addr, Len) \
cacheInvalidate(INSTRUCTION_CACHE, (void *)(Addr), (Len))
#else
#error "Unknown processor / architecture. Must be PPC for VxWorks."
#endif
#ifdef __cplusplus
}
#endif
#endif

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/******************************************************************************
*
* (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
*
* This file contains confidential and proprietary information of Xilinx, Inc.
* and is protected under U.S. and international copyright and other
* intellectual property laws.
*
* DISCLAIMER
* This disclaimer is not a license and does not grant any rights to the
* materials distributed herewith. Except as otherwise provided in a valid
* license issued to you by Xilinx, and to the maximum extent permitted by
* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
* and (2) Xilinx shall not be liable (whether in contract or tort, including
* negligence, or under any other theory of liability) for any loss or damage
* of any kind or nature related to, arising under or in connection with these
* materials, including for any direct, or any indirect, special, incidental,
* or consequential loss or damage (including loss of data, profits, goodwill,
* or any type of loss or damage suffered as a result of any action brought by
* a third party) even if such damage or loss was reasonably foreseeable or
* Xilinx had been advised of the possibility of the same.
*
* CRITICAL APPLICATIONS
* Xilinx products are not designed or intended to be fail-safe, or for use in
* any application requiring fail-safe performance, such as life-support or
* safety devices or systems, Class III medical devices, nuclear facilities,
* applications related to the deployment of airbags, or any other applications
* that could lead to death, personal injury, or severe property or
* environmental damage (individually and collectively, "Critical
* Applications"). Customer assumes the sole risk and liability of any use of
* Xilinx products in Critical Applications, subject only to applicable laws
* and regulations governing limitations on product liability.
*
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
* AT ALL TIMES.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xil_exception.h
*
* This header file contains exception related driver functions (or
* macros) that can be used to access the device. The user should refer to the
* hardware device specification for more details of the device operation.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00 hbm 07/28/09 Initial release
*
* </pre>
*
* @note
*
* None.
*
******************************************************************************/
#ifndef XIL_EXCEPTION_H /* prevent circular inclusions */
#define XIL_EXCEPTION_H /* by using protection macros */
#include "xil_types.h"
#ifdef __cplusplus
extern "C" {
#endif
/************************** Constant Definitions *****************************/
/*
* These constants are specific to Microblaze processor.
*/
#define XIL_EXCEPTION_ID_FIRST 0
#define XIL_EXCEPTION_ID_FSL 0
#define XIL_EXCEPTION_ID_UNALIGNED_ACCESS 1
#define XIL_EXCEPTION_ID_ILLEGAL_OPCODE 2
#define XIL_EXCEPTION_ID_M_AXI_I_EXCEPTION 3
#define XIL_EXCEPTION_ID_IPLB_EXCEPTION 3
#define XIL_EXCEPTION_ID_M_AXI_D_EXCEPTION 4
#define XIL_EXCEPTION_ID_DPLB_EXCEPTION 4
#define XIL_EXCEPTION_ID_DIV_BY_ZERO 5
#define XIL_EXCEPTION_ID_FPU 6
#define XIL_EXCEPTION_ID_STACK_VIOLATION 7
#define XIL_EXCEPTION_ID_MMU 7
#define XIL_EXCEPTION_ID_LAST XIL_EXCEPTION_ID_MMU
/*
* XIL_EXCEPTION_ID_INT is defined for all processors, but with different value.
*/
#define XIL_EXCEPTION_ID_INT 16 /**
* exception ID for interrupt
*/
/**************************** Type Definitions *******************************/
/**
* This typedef is the exception handler function.
*/
typedef void (*Xil_ExceptionHandler)(void *Data);
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
extern void Xil_ExceptionRegisterHandler(u32 Id,
Xil_ExceptionHandler Handler,
void *Data);
extern void Xil_ExceptionRemoveHandler(u32 Id);
extern void Xil_ExceptionInit(void);
extern void Xil_ExceptionEnable(void);
extern void Xil_ExceptionDisable(void);
#ifdef __cplusplus
}
#endif
#endif

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/******************************************************************************
*
* (c) Copyright 2009 Xilinx, Inc. All rights reserved.
*
* This file contains confidential and proprietary information of Xilinx, Inc.
* and is protected under U.S. and international copyright and other
* intellectual property laws.
*
* DISCLAIMER
* This disclaimer is not a license and does not grant any rights to the
* materials distributed herewith. Except as otherwise provided in a valid
* license issued to you by Xilinx, and to the maximum extent permitted by
* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
* and (2) Xilinx shall not be liable (whether in contract or tort, including
* negligence, or under any other theory of liability) for any loss or damage
* of any kind or nature related to, arising under or in connection with these
* materials, including for any direct, or any indirect, special, incidental,
* or consequential loss or damage (including loss of data, profits, goodwill,
* or any type of loss or damage suffered as a result of any action brought by
* a third party) even if such damage or loss was reasonably foreseeable or
* Xilinx had been advised of the possibility of the same.
*
* CRITICAL APPLICATIONS
* Xilinx products are not designed or intended to be fail-safe, or for use in
* any application requiring fail-safe performance, such as life-support or
* safety devices or systems, Class III medical devices, nuclear facilities,
* applications related to the deployment of airbags, or any other applications
* that could lead to death, personal injury, or severe property or
* environmental damage (individually and collectively, "Critical
* Applications"). Customer assumes the sole risk and liability of any use of
* Xilinx products in Critical Applications, subject only to applicable laws
* and regulations governing limitations on product liability.
*
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
* AT ALL TIMES.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xil_hal.h
*
* Contains all the HAL header files.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00a hbm 07/28/09 Initial release
*
* </pre>
*
* @note
*
******************************************************************************/
#ifndef XIL_HAL_H
#define XIL_HAL_H
#include "xil_cache.h"
#include "xil_io.h"
#include "xil_assert.h"
#include "xil_exception.h"
#include "xil_types.h"
#endif

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/******************************************************************************
*
* (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
*
* This file contains confidential and proprietary information of Xilinx, Inc.
* and is protected under U.S. and international copyright and other
* intellectual property laws.
*
* DISCLAIMER
* This disclaimer is not a license and does not grant any rights to the
* materials distributed herewith. Except as otherwise provided in a valid
* license issued to you by Xilinx, and to the maximum extent permitted by
* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
* and (2) Xilinx shall not be liable (whether in contract or tort, including
* negligence, or under any other theory of liability) for any loss or damage
* of any kind or nature related to, arising under or in connection with these
* materials, including for any direct, or any indirect, special, incidental,
* or consequential loss or damage (including loss of data, profits, goodwill,
* or any type of loss or damage suffered as a result of any action brought by
* a third party) even if such damage or loss was reasonably foreseeable or
* Xilinx had been advised of the possibility of the same.
*
* CRITICAL APPLICATIONS
* Xilinx products are not designed or intended to be fail-safe, or for use in
* any application requiring fail-safe performance, such as life-support or
* safety devices or systems, Class III medical devices, nuclear facilities,
* applications related to the deployment of airbags, or any other applications
* that could lead to death, personal injury, or severe property or
* environmental damage (individually and collectively, "Critical
* Applications"). Customer assumes the sole risk and liability of any use of
* Xilinx products in Critical Applications, subject only to applicable laws
* and regulations governing limitations on product liability.
*
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
* AT ALL TIMES.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xil_io.h
*
* This file contains the interface for the general IO component, which
* encapsulates the Input/Output functions for processors that do not
* require any special I/O handling.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 3.00a hbm 07/28/09 Initial release
* 3.00a hbm 07/21/10 Added Xil_EndianSwap32/16, Xil_Htonl/s, Xil_Ntohl/s
* 3.03a sdm 08/18/11 Added INST_SYNC and DATA_SYNC macros.
* 3.07a asa 08/31/12 Added xil_printf.h include
*
* </pre>
*
* @note
*
* This file may contain architecture-dependent items.
*
******************************************************************************/
#ifndef XIL_IO_H /* prevent circular inclusions */
#define XIL_IO_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xil_types.h"
#include "mb_interface.h"
#include "xil_printf.h"
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
#if defined __GNUC__
# define INST_SYNC mbar(0)
# define DATA_SYNC mbar(1)
#else
# define INST_SYNC
# define DATA_SYNC
#endif /* __GNUC__ */
/*
* The following macros allow optimized I/O operations for memory mapped I/O.
* It should be noted that macros cannot be used if synchronization of the I/O
* operation is needed as it will likely break some code.
*/
/*****************************************************************************/
/**
*
* Perform an input operation for an 8-bit memory location by reading from the
* specified address and returning the value read from that address.
*
* @param Addr contains the address to perform the input operation at.
*
* @return The value read from the specified input address.
*
* @note None.
*
******************************************************************************/
#define Xil_In8(Addr) (*(volatile u8 *)(Addr))
/*****************************************************************************/
/**
*
* Perform an input operation for a 16-bit memory location by reading from the
* specified address and returning the value read from that address.
*
* @param Addr contains the address to perform the input operation at.
*
* @return The value read from the specified input address.
*
* @note None.
*
******************************************************************************/
#define Xil_In16(Addr) (*(volatile u16 *)(Addr))
/*****************************************************************************/
/**
*
* Perform an input operation for a 32-bit memory location by reading from the
* specified address and returning the value read from that address.
*
* @param Addr contains the address to perform the input operation at.
*
* @return The value read from the specified input address.
*
* @note None.
*
******************************************************************************/
#define Xil_In32(Addr) (*(volatile u32 *)(Addr))
/*****************************************************************************/
/**
*
* Perform an output operation for an 8-bit memory location by writing the
* specified value to the specified address.
*
* @param Addr contains the address to perform the output operation at.
* @param value contains the value to be output at the specified address.
*
* @return None
*
* @note None.
*
******************************************************************************/
#define Xil_Out8(Addr, Value) \
(*(volatile u8 *)((Addr)) = (Value))
/*****************************************************************************/
/**
*
* Perform an output operation for a 16-bit memory location by writing the
* specified value to the specified address.
*
* @param Addr contains the address to perform the output operation at.
* @param value contains the value to be output at the specified address.
*
* @return None
*
* @note None.
*
******************************************************************************/
#define Xil_Out16(Addr, Value) \
(*(volatile u16 *)((Addr)) = (Value))
/*****************************************************************************/
/**
*
* Perform an output operation for a 32-bit memory location by writing the
* specified value to the specified address.
*
* @param addr contains the address to perform the output operation at.
* @param value contains the value to be output at the specified address.
*
* @return None
*
* @note None.
*
******************************************************************************/
#define Xil_Out32(Addr, Value) \
(*(volatile u32 *)((Addr)) = (Value))
extern u16 Xil_EndianSwap16(u16 Data);
extern u32 Xil_EndianSwap32(u32 Data);
#ifndef __LITTLE_ENDIAN__
extern u16 Xil_In16LE(u32 Addr);
extern u32 Xil_In32LE(u32 Addr);
extern void Xil_Out16LE(u32 Addr, u16 Value);
extern void Xil_Out32LE(u32 Addr, u32 Value);
/**
*
* Perform an big-endian input operation for a 16-bit memory location
* by reading from the specified address and returning the value read from
* that address.
*
* @param addr contains the address to perform the input operation at.
*
* @return The value read from the specified input address with the
* proper endianness. The return value has the same endianness
* as that of the processor, i.e. if the processor is
* little-engian, the return value is the byte-swapped value read
* from the address.
*
* @note None.
*
******************************************************************************/
#define Xil_In16BE(Addr) Xil_In16(Addr)
/**
*
* Perform a big-endian input operation for a 32-bit memory location
* by reading from the specified address and returning the value read from
* that address.
*
* @param Addr contains the address to perform the input operation at.
*
* @return The value read from the specified input address with the
* proper endianness. The return value has the same endianness
* as that of the processor, i.e. if the processor is
* little-engian, the return value is the byte-swapped value read
* from the address.
*
*
* @note None.
*
******************************************************************************/
#define Xil_In32BE(Addr) Xil_In32(Addr)
/*****************************************************************************/
/**
*
* Perform a big-endian output operation for a 16-bit memory location
* by writing the specified value to the specified address.
*
* @param Addr contains the address to perform the output operation at.
* @param Value contains the value to be output at the specified address.
* The value has the same endianness as that of the processor.
* If the processor is little-endian, the byte-swapped value is
* written to the address.
*
*
* @return None
*
* @note None.
*
******************************************************************************/
#define Xil_Out16BE(Addr, Value) Xil_Out16(Addr, Value)
/*****************************************************************************/
/**
*
* Perform a big-endian output operation for a 32-bit memory location
* by writing the specified value to the specified address.
*
* @param Addr contains the address to perform the output operation at.
* @param Value contains the value to be output at the specified address.
* The value has the same endianness as that of the processor.
* If the processor is little-endian, the byte-swapped value is
* written to the address.
*
* @return None
*
* @note None.
*
******************************************************************************/
#define Xil_Out32BE(Addr, Value) Xil_Out32(Addr, Value)
#define Xil_Htonl(Data) (Data)
#define Xil_Htons(Data) (Data)
#define Xil_Ntohl(Data) (Data)
#define Xil_Ntohs(Data) (Data)
#else
extern u16 Xil_In16BE(u32 Addr);
extern u32 Xil_In32BE(u32 Addr);
extern void Xil_Out16BE(u32 Addr, u16 Value);
extern void Xil_Out32BE(u32 Addr, u32 Value);
#define Xil_In16LE(Addr) Xil_In16(Addr)
#define Xil_In32LE(Addr) Xil_In32(Addr)
#define Xil_Out16LE(Addr, Value) Xil_Out16(Addr, Value)
#define Xil_Out32LE(Addr, Value) Xil_Out32(Addr, Value)
/*****************************************************************************/
/**
*
* Convert a 32-bit number from host byte order to network byte order.
*
* @param Data the 32-bit number to be converted.
*
* @return The converted 32-bit number in network byte order.
*
* @note None.
*
******************************************************************************/
#define Xil_Htonl(Data) Xil_EndianSwap32(Data)
/*****************************************************************************/
/**
*
* Convert a 16-bit number from host byte order to network byte order.
*
* @param Data the 16-bit number to be converted.
*
* @return The converted 16-bit number in network byte order.
*
* @note None.
*
******************************************************************************/
#define Xil_Htons(Data) Xil_EndianSwap16(Data)
/*****************************************************************************/
/**
*
* Convert a 32-bit number from network byte order to host byte order.
*
* @param Value the 32-bit number to be converted.
*
* @return The converted 32-bit number in host byte order.
*
* @note None.
*
******************************************************************************/
#define Xil_Ntohl(Data) Xil_EndianSwap32(Data)
/*****************************************************************************/
/**
*
* Convert a 16-bit number from network byte order to host byte order.
*
* @param Value the 16-bit number to be converted.
*
* @return The converted 16-bit number in host byte order.
*
* @note None.
*
******************************************************************************/
#define Xil_Ntohs(Data) Xil_EndianSwap16(Data)
#endif
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */

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286
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/******************************************************************************
*
* (c) Copyright 2013 Xilinx, Inc. All rights reserved.
*
* This file contains confidential and proprietary information of Xilinx, Inc.
* and is protected under U.S. and international copyright and other
* intellectual property laws.
*
* DISCLAIMER
* This disclaimer is not a license and does not grant any rights to the
* materials distributed herewith. Except as otherwise provided in a valid
* license issued to you by Xilinx, and to the maximum extent permitted by
* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
* and (2) Xilinx shall not be liable (whether in contract or tort, including
* negligence, or under any other theory of liability) for any loss or damage
* of any kind or nature related to, arising under or in connection with these
* materials, including for any direct, or any indirect, special, incidental,
* or consequential loss or damage (including loss of data, profits, goodwill,
* or any type of loss or damage suffered as a result of any action brought by
* a third party) even if such damage or loss was reasonably foreseeable or
* Xilinx had been advised of the possibility of the same.
*
* CRITICAL APPLICATIONS
* Xilinx products are not designed or intended to be fail-safe, or for use in
* any application requiring fail-safe performance, such as life-support or
* safety devices or systems, Class III medical devices, nuclear facilities,
* applications related to the deployment of airbags, or any other applications
* that could lead to death, personal injury, or severe property or
* environmental damage (individually and collectively, "Critical
* Applications"). Customer assumes the sole risk and liability of any use of
* Xilinx products in Critical Applications, subject only to applicable laws
* and regulations governing limitations on product liability.
*
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
* AT ALL TIMES.
*
******************************************************************************/
/*****************************************************************************/
/**
* @file xil_misc_psreset_api.h
*
* This file contains the various register defintions and function prototypes for
* implementing the reset functionality of zynq ps devices
*
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00b kpc 03/07/13 First release.
* </pre>
*
******************************************************************************/
#ifndef XIL_MISC_RESET_H /* prevent circular inclusions */
#define XIL_MISC_RESET_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xil_types.h"
#include "xil_io.h"
/************************** Constant Definitions *****************************/
#define XDDRC_CTRL_BASEADDR 0xF8006000
#define XSLCR_BASEADDR 0xF8000000
/**< OCM configuration register */
#define XSLCR_OCM_CFG_ADDR (XSLCR_BASEADDR + 0x910)
/**< SLCR unlock register */
#define XSLCR_UNLOCK_ADDR (XSLCR_BASEADDR + 0x8)
/**< SLCR GEM0 rx clock control register */
#define XSLCR_GEM0_RCLK_CTRL_ADDR (XSLCR_BASEADDR + 0x138)
/**< SLCR GEM1 rx clock control register */
#define XSLCR_GEM1_RCLK_CTRL_ADDR (XSLCR_BASEADDR + 0x13C)
/**< SLCR GEM0 clock control register */
#define XSLCR_GEM0_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x140)
/**< SLCR GEM1 clock control register */
#define XSLCR_GEM1_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x144)
/**< SLCR SMC clock control register */
#define XSLCR_SMC_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x148)
/**< SLCR GEM reset control register */
#define XSLCR_GEM_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x214)
/**< SLCR USB0 clock control register */
#define XSLCR_USB0_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x130)
/**< SLCR USB1 clock control register */
#define XSLCR_USB1_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x134)
/**< SLCR USB1 reset control register */
#define XSLCR_USB_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x210)
/**< SLCR SMC reset control register */
#define XSLCR_SMC_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x234)
/**< SLCR Level shifter enable register */
#define XSLCR_LVL_SHFTR_EN_ADDR (XSLCR_BASEADDR + 0x900)
/**< SLCR ARM pll control register */
#define XSLCR_ARM_PLL_CTRL_ADDR (XSLCR_BASEADDR + 0x100)
/**< SLCR DDR pll control register */
#define XSLCR_DDR_PLL_CTRL_ADDR (XSLCR_BASEADDR + 0x104)
/**< SLCR IO pll control register */
#define XSLCR_IO_PLL_CTRL_ADDR (XSLCR_BASEADDR + 0x108)
/**< SLCR ARM pll configuration register */
#define XSLCR_ARM_PLL_CFG_ADDR (XSLCR_BASEADDR + 0x110)
/**< SLCR DDR pll configuration register */
#define XSLCR_DDR_PLL_CFG_ADDR (XSLCR_BASEADDR + 0x114)
/**< SLCR IO pll configuration register */
#define XSLCR_IO_PLL_CFG_ADDR (XSLCR_BASEADDR + 0x118)
/**< SLCR ARM clock control register */
#define XSLCR_ARM_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x120)
/**< SLCR DDR clock control register */
#define XSLCR_DDR_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x124)
/**< SLCR MIO pin address register */
#define XSLCR_MIO_PIN_00_ADDR (XSLCR_BASEADDR + 0x700)
/**< SLCR DMAC reset control address register */
#define XSLCR_DMAC_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x20C)
/**< SLCR USB reset control address register */
#define XSLCR_USB_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x210)
/**< SLCR GEM reset control address register */
#define XSLCR_GEM_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x214)
/**< SLCR SDIO reset control address register */
#define XSLCR_SDIO_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x218)
/**< SLCR SPI reset control address register */
#define XSLCR_SPI_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x21C)
/**< SLCR CAN reset control address register */
#define XSLCR_CAN_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x220)
/**< SLCR I2C reset control address register */
#define XSLCR_I2C_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x224)
/**< SLCR UART reset control address register */
#define XSLCR_UART_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x228)
/**< SLCR GPIO reset control address register */
#define XSLCR_GPIO_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x22C)
/**< SLCR LQSPI reset control address register */
#define XSLCR_LQSPI_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x230)
/**< SLCR SMC reset control address register */
#define XSLCR_SMC_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x234)
/**< SLCR OCM reset control address register */
#define XSLCR_OCM_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x238)
/**< SMC mem controller clear config register */
#define XSMC_MEMC_CLR_CONFIG_OFFSET 0x0C
/**< SMC idlecount configuration register */
#define XSMC_REFRESH_PERIOD_0_OFFSET 0x20
#define XSMC_REFRESH_PERIOD_1_OFFSET 0x24
/**< SMC ECC configuration register */
#define XSMC_ECC_MEMCFG1_OFFSET 0x404
/**< SMC ECC command 1 register */
#define XSMC_ECC_MEMCMD1_OFFSET 0x404
/**< SMC ECC command 2 register */
#define XSMC_ECC_MEMCMD2_OFFSET 0x404
/**< SLCR unlock code */
#define XSLCR_UNLOCK_CODE 0x0000DF0D
/**< SMC mem clear configuration mask */
#define XSMC_MEMC_CLR_CONFIG_MASK 0x5F
/**< SMC ECC memconfig 1 reset value */
#define XSMC_ECC_MEMCFG1_RESET_VAL 0x43
/**< SMC ECC memcommand 1 reset value */
#define XSMC_ECC_MEMCMD1_RESET_VAL 0x01300080
/**< SMC ECC memcommand 2 reset value */
#define XSMC_ECC_MEMCMD2_RESET_VAL 0x01E00585
/**< DDR controller reset bit mask */
#define XDDRPS_CTRL_RESET_MASK 0x1
/**< SLCR OCM configuration reset value*/
#define XSLCR_OCM_CFG_RESETVAL 0x8
/**< SLCR OCM bank selection mask*/
#define XSLCR_OCM_CFG_HIADDR_MASK 0xF
/**< SLCR level shifter enable mask*/
#define XSLCR_LVL_SHFTR_EN_MASK 0xF
/**< SLCR PLL register reset values */
#define XSLCR_ARM_PLL_CTRL_RESET_VAL 0x0001A008
#define XSLCR_DDR_PLL_CTRL_RESET_VAL 0x0001A008
#define XSLCR_IO_PLL_CTRL_RESET_VAL 0x0001A008
#define XSLCR_ARM_PLL_CFG_RESET_VAL 0x00177EA0
#define XSLCR_DDR_PLL_CFG_RESET_VAL 0x00177EA0
#define XSLCR_IO_PLL_CFG_RESET_VAL 0x00177EA0
#define XSLCR_ARM_CLK_CTRL_RESET_VAL 0x1F000400
#define XSLCR_DDR_CLK_CTRL_RESET_VAL 0x18400003
/**< SLCR MIO register default values */
#define XSLCR_MIO_PIN_00_RESET_VAL 0x00001601
#define XSLCR_MIO_PIN_02_RESET_VAL 0x00000601
/**< SLCR Reset control registers default values */
#define XSLCR_DMAC_RST_CTRL_VAL 0x1
#define XSLCR_GEM_RST_CTRL_VAL 0xF3
#define XSLCR_USB_RST_CTRL_VAL 0x3
#define XSLCR_I2C_RST_CTRL_VAL 0x3
#define XSLCR_SPI_RST_CTRL_VAL 0xF
#define XSLCR_UART_RST_CTRL_VAL 0xF
#define XSLCR_QSPI_RST_CTRL_VAL 0x3
#define XSLCR_GPIO_RST_CTRL_VAL 0x1
#define XSLCR_SMC_RST_CTRL_VAL 0x3
#define XSLCR_OCM_RST_CTRL_VAL 0x1
#define XSLCR_SDIO_RST_CTRL_VAL 0x33
#define XSLCR_CAN_RST_CTRL_VAL 0x3
/**************************** Type Definitions *******************************/
/* the following data type is used to hold a null terminated version string
* consisting of the following format, "X.YYX"
*/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
/*
* Performs reset operation to the ddr interface
*/
void XDdr_ResetHw();
/*
* Map the ocm region to post bootrom state
*/
void XOcm_Remap();
/*
* Performs the smc interface reset
*/
void XSmc_ResetHw(u32 BaseAddress);
/*
* updates the MIO registers with reset values
*/
void XSlcr_MioWriteResetValues();
/*
* updates the PLL and clock registers with reset values
*/
void XSlcr_PllWriteResetValues();
/*
* Disables the level shifters
*/
void XSlcr_DisableLevelShifters();
/*
* provides softreset to the GPIO interface
*/
void XSlcr_GpioPsReset(void);
/*
* provides softreset to the DMA interface
*/
void XSlcr_DmaPsReset(void);
/*
* provides softreset to the SMC interface
*/
void XSlcr_SmcPsReset(void);
/*
* provides softreset to the CAN interface
*/
void XSlcr_CanPsReset(void);
/*
* provides softreset to the Uart interface
*/
void XSlcr_UartPsReset(void);
/*
* provides softreset to the I2C interface
*/
void XSlcr_I2cPsReset(void);
/*
* provides softreset to the SPI interface
*/
void XSlcr_SpiPsReset(void);
/*
* provides softreset to the QSPI interface
*/
void XSlcr_QspiPsReset(void);
/*
* provides softreset to the USB interface
*/
void XSlcr_UsbPsReset(void);
/*
* provides softreset to the GEM interface
*/
void XSlcr_EmacPsReset(void);
/*
* provides softreset to the OCM interface
*/
void XSlcr_OcmReset(void);
#ifdef __cplusplus
}
#endif
#endif /* XIL_MISC_RESET_H */

55
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/******************************************************************************
*
* (c) Copyright 2012 Xilinx, Inc. All rights reserved.
*
* This file contains confidential and proprietary information of Xilinx, Inc.
* and is protected under U.S. and international copyright and other
* intellectual property laws.
*
* DISCLAIMER
* This disclaimer is not a license and does not grant any rights to the
* materials distributed herewith. Except as otherwise provided in a valid
* license issued to you by Xilinx, and to the maximum extent permitted by
* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
* and (2) Xilinx shall not be liable (whether in contract or tort, including
* negligence, or under any other theory of liability) for any loss or damage
* of any kind or nature related to, arising under or in connection with these
* materials, including for any direct, or any indirect, special, incidental,
* or consequential loss or damage (including loss of data, profits, goodwill,
* or any type of loss or damage suffered as a result of any action brought by
* a third party) even if such damage or loss was reasonably foreseeable or
* Xilinx had been advised of the possibility of the same.
*
* CRITICAL APPLICATIONS
* Xilinx products are not designed or intended to be fail-safe, or for use in
* any application requiring fail-safe performance, such as life-support or
* safety devices or systems, Class III medical devices, nuclear facilities,
* applications related to the deployment of airbags, or any other applications
* that could lead to death, personal injury, or severe property or
* environmental damage (individually and collectively, "Critical
* Applications"). Customer assumes the sole risk and liability of any use of
* Xilinx products in Critical Applications, subject only to applicable laws
* and regulations governing limitations on product liability.
*
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
* AT ALL TIMES.
*
******************************************************************************/
#ifndef XIL_PRINTF_H
#define XIL_PRINTF_H
#ifdef __cplusplus
extern "C" {
#endif
void xil_printf(const char *ctrl1, ...);
void print(char *ptr);
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */

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software/LED_Controller_bsp/microblaze_mcs/include/xil_testcache.h Executable file
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/******************************************************************************
*
*
* (c) Copyright 2009 Xilinx, Inc. All rights reserved.
*
* This file contains confidential and proprietary information of Xilinx, Inc.
* and is protected under U.S. and international copyright and other
* intellectual property laws.
*
* DISCLAIMER
* This disclaimer is not a license and does not grant any rights to the
* materials distributed herewith. Except as otherwise provided in a valid
* license issued to you by Xilinx, and to the maximum extent permitted by
* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
* and (2) Xilinx shall not be liable (whether in contract or tort, including
* negligence, or under any other theory of liability) for any loss or damage
* of any kind or nature related to, arising under or in connection with these
* materials, including for any direct, or any indirect, special, incidental,
* or consequential loss or damage (including loss of data, profits, goodwill,
* or any type of loss or damage suffered as a result of any action brought by
* a third party) even if such damage or loss was reasonably foreseeable or
* Xilinx had been advised of the possibility of the same.
*
* CRITICAL APPLICATIONS
* Xilinx products are not designed or intended to be fail-safe, or for use in
* any application requiring fail-safe performance, such as life-support or
* safety devices or systems, Class III medical devices, nuclear facilities,
* applications related to the deployment of airbags, or any other applications
* that could lead to death, personal injury, or severe property or
* environmental damage (individually and collectively, "Critical
* Applications"). Customer assumes the sole risk and liability of any use of
* Xilinx products in Critical Applications, subject only to applicable laws
* and regulations governing limitations on product liability.
*
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
* AT ALL TIMES.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xil_testcache.h
*
* This file contains utility functions to test cache.
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.00a hbm 07/29/09 First release
*
******************************************************************************/
#ifndef XIL_TESTCACHE_H /* prevent circular inclusions */
#define XIL_TESTCACHE_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
extern int Xil_TestDCacheRange(void);
extern int Xil_TestDCacheAll(void);
extern int Xil_TestICacheRange(void);
extern int Xil_TestICacheAll(void);
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */

101
software/LED_Controller_bsp/microblaze_mcs/include/xil_testio.h Executable file
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@@ -0,0 +1,101 @@
/******************************************************************************
*
* (c) Copyright 2009 Xilinx, Inc. All rights reserved.
*
* This file contains confidential and proprietary information of Xilinx, Inc.
* and is protected under U.S. and international copyright and other
* intellectual property laws.
*
* DISCLAIMER
* This disclaimer is not a license and does not grant any rights to the
* materials distributed herewith. Except as otherwise provided in a valid
* license issued to you by Xilinx, and to the maximum extent permitted by
* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
* and (2) Xilinx shall not be liable (whether in contract or tort, including
* negligence, or under any other theory of liability) for any loss or damage
* of any kind or nature related to, arising under or in connection with these
* materials, including for any direct, or any indirect, special, incidental,
* or consequential loss or damage (including loss of data, profits, goodwill,
* or any type of loss or damage suffered as a result of any action brought by
* a third party) even if such damage or loss was reasonably foreseeable or
* Xilinx had been advised of the possibility of the same.
*
* CRITICAL APPLICATIONS
* Xilinx products are not designed or intended to be fail-safe, or for use in
* any application requiring fail-safe performance, such as life-support or
* safety devices or systems, Class III medical devices, nuclear facilities,
* applications related to the deployment of airbags, or any other applications
* that could lead to death, personal injury, or severe property or
* environmental damage (individually and collectively, "Critical
* Applications"). Customer assumes the sole risk and liability of any use of
* Xilinx products in Critical Applications, subject only to applicable laws
* and regulations governing limitations on product liability.
*
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
* AT ALL TIMES.
*
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xil_testmemend.h
*
* This file contains utility functions to teach endian related memory
* IO functions.
*
* <b>Memory test description</b>
*
* A subset of the memory tests can be selected or all of the tests can be run
* in order. If there is an error detected by a subtest, the test stops and the
* failure code is returned. Further tests are not run even if all of the tests
* are selected.
*
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.00 hbm 08/05/09 First release
* </pre>
*
******************************************************************************/
#ifndef XIL_TESTIO_H /* prevent circular inclusions */
#define XIL_TESTIO_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xil_types.h"
/************************** Constant Definitions *****************************/
#define XIL_TESTIO_DEFAULT 0
#define XIL_TESTIO_LE 1
#define XIL_TESTIO_BE 2
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
extern int Xil_TestIO8(u8 *Addr, int Len, u8 Value);
extern int Xil_TestIO16(u16 *Addr, int Len, u16 Value, int Kind, int Swap);
extern int Xil_TestIO32(u32 *Addr, int Len, u32 Value, int Kind, int Swap);
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */

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/******************************************************************************
*
*
* (c) Copyright 2009 Xilinx, Inc. All rights reserved.
*
* This file contains confidential and proprietary information of Xilinx, Inc.
* and is protected under U.S. and international copyright and other
* intellectual property laws.
*
* DISCLAIMER
* This disclaimer is not a license and does not grant any rights to the
* materials distributed herewith. Except as otherwise provided in a valid
* license issued to you by Xilinx, and to the maximum extent permitted by
* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
* and (2) Xilinx shall not be liable (whether in contract or tort, including
* negligence, or under any other theory of liability) for any loss or damage
* of any kind or nature related to, arising under or in connection with these
* materials, including for any direct, or any indirect, special, incidental,
* or consequential loss or damage (including loss of data, profits, goodwill,
* or any type of loss or damage suffered as a result of any action brought by
* a third party) even if such damage or loss was reasonably foreseeable or
* Xilinx had been advised of the possibility of the same.
*
* CRITICAL APPLICATIONS
* Xilinx products are not designed or intended to be fail-safe, or for use in
* any application requiring fail-safe performance, such as life-support or
* safety devices or systems, Class III medical devices, nuclear facilities,
* applications related to the deployment of airbags, or any other applications
* that could lead to death, personal injury, or severe property or
* environmental damage (individually and collectively, "Critical
* Applications"). Customer assumes the sole risk and liability of any use of
* Xilinx products in Critical Applications, subject only to applicable laws
* and regulations governing limitations on product liability.
*
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
* AT ALL TIMES.
*
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xil_testmem.h
*
* This file contains utility functions to test memory.
*
* <b>Memory test description</b>
*
* A subset of the memory tests can be selected or all of the tests can be run
* in order. If there is an error detected by a subtest, the test stops and the
* failure code is returned. Further tests are not run even if all of the tests
* are selected.
*
* Subtest descriptions:
* <pre>
* XIL_TESTMEM_ALLMEMTESTS:
* Runs all of the following tests
*
* XIL_TESTMEM_INCREMENT:
* Incrementing Value Test.
* This test starts at 'XIL_TESTMEM_INIT_VALUE' and uses the
* incrementing value as the test value for memory.
*
* XIL_TESTMEM_WALKONES:
* Walking Ones Test.
* This test uses a walking '1' as the test value for memory.
* location 1 = 0x00000001
* location 2 = 0x00000002
* ...
*
* XIL_TESTMEM_WALKZEROS:
* Walking Zero's Test.
* This test uses the inverse value of the walking ones test
* as the test value for memory.
* location 1 = 0xFFFFFFFE
* location 2 = 0xFFFFFFFD
* ...
*
* XIL_TESTMEM_INVERSEADDR:
* Inverse Address Test.
* This test uses the inverse of the address of the location under test
* as the test value for memory.
*
* XIL_TESTMEM_FIXEDPATTERN:
* Fixed Pattern Test.
* This test uses the provided patters as the test value for memory.
* If zero is provided as the pattern the test uses '0xDEADBEEF".
* </pre>
*
* <i>WARNING</i>
*
* The tests are <b>DESTRUCTIVE</b>. Run before any initialized memory spaces
* have been set up.
*
* The address provided to the memory tests is not checked for
* validity except for the NULL case. It is possible to provide a code-space
* pointer for this test to start with and ultimately destroy executable code
* causing random failures.
*
* @note
*
* Used for spaces where the address range of the region is smaller than
* the data width. If the memory range is greater than 2 ** width,
* the patterns used in XIL_TESTMEM_WALKONES and XIL_TESTMEM_WALKZEROS will
* repeat on a boundry of a power of two making it more difficult to detect
* addressing errors. The XIL_TESTMEM_INCREMENT and XIL_TESTMEM_INVERSEADDR
* tests suffer the same problem. Ideally, if large blocks of memory are to be
* tested, break them up into smaller regions of memory to allow the test
* patterns used not to repeat over the region tested.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.00a hbm 08/25/09 First release
* </pre>
*
******************************************************************************/
#ifndef XIL_TESTMEM_H /* prevent circular inclusions */
#define XIL_TESTMEM_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xil_types.h"
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/* xutil_memtest defines */
#define XIL_TESTMEM_INIT_VALUE 1
/** @name Memory subtests
* @{
*/
/**
* See the detailed description of the subtests in the file description.
*/
#define XIL_TESTMEM_ALLMEMTESTS 0
#define XIL_TESTMEM_INCREMENT 1
#define XIL_TESTMEM_WALKONES 2
#define XIL_TESTMEM_WALKZEROS 3
#define XIL_TESTMEM_INVERSEADDR 4
#define XIL_TESTMEM_FIXEDPATTERN 5
#define XIL_TESTMEM_MAXTEST XIL_TESTMEM_FIXEDPATTERN
/* @} */
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
/* xutil_testmem prototypes */
extern int Xil_TestMem32(u32 *Addr, u32 Words, u32 Pattern, u8 Subtest);
extern int Xil_TestMem16(u16 *Addr, u32 Words, u16 Pattern, u8 Subtest);
extern int Xil_TestMem8(u8 *Addr, u32 Words, u8 Pattern, u8 Subtest);
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */

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/******************************************************************************
*
* (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
*
* This file contains confidential and proprietary information of Xilinx, Inc.
* and is protected under U.S. and international copyright and other
* intellectual property laws.
*
* DISCLAIMER
* This disclaimer is not a license and does not grant any rights to the
* materials distributed herewith. Except as otherwise provided in a valid
* license issued to you by Xilinx, and to the maximum extent permitted by
* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
* and (2) Xilinx shall not be liable (whether in contract or tort, including
* negligence, or under any other theory of liability) for any loss or damage
* of any kind or nature related to, arising under or in connection with these
* materials, including for any direct, or any indirect, special, incidental,
* or consequential loss or damage (including loss of data, profits, goodwill,
* or any type of loss or damage suffered as a result of any action brought by
* a third party) even if such damage or loss was reasonably foreseeable or
* Xilinx had been advised of the possibility of the same.
*
* CRITICAL APPLICATIONS
* Xilinx products are not designed or intended to be fail-safe, or for use in
* any application requiring fail-safe performance, such as life-support or
* safety devices or systems, Class III medical devices, nuclear facilities,
* applications related to the deployment of airbags, or any other applications
* that could lead to death, personal injury, or severe property or
* environmental damage (individually and collectively, "Critical
* Applications"). Customer assumes the sole risk and liability of any use of
* Xilinx products in Critical Applications, subject only to applicable laws
* and regulations governing limitations on product liability.
*
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
* AT ALL TIMES.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xil_types.h
*
* This file contains basic types for Xilinx software IP.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00a hbm 07/14/09 First release
* 3.03a sdm 05/30/11 Added Xuint64 typedef and XUINT64_MSW/XUINT64_LSW macros
* </pre>
*
******************************************************************************/
#ifndef XIL_TYPES_H /* prevent circular inclusions */
#define XIL_TYPES_H /* by using protection macros */
/************************** Constant Definitions *****************************/
#ifndef TRUE
# define TRUE 1
#endif
#ifndef FALSE
# define FALSE 0
#endif
#ifndef NULL
#define NULL 0
#endif
#define XIL_COMPONENT_IS_READY 0x11111111 /**< component has been initialized */
#define XIL_COMPONENT_IS_STARTED 0x22222222 /**< component has been started */
/** @name New types
* New simple types.
* @{
*/
#ifndef __KERNEL__
#ifndef XBASIC_TYPES_H
/**
* guarded against xbasic_types.h.
*/
typedef unsigned char u8;
typedef unsigned short u16;
typedef unsigned long u32;
#define __XUINT64__
typedef struct
{
u32 Upper;
u32 Lower;
} Xuint64;
/*****************************************************************************/
/**
* Return the most significant half of the 64 bit data type.
*
* @param x is the 64 bit word.
*
* @return The upper 32 bits of the 64 bit word.
*
* @note None.
*
******************************************************************************/
#define XUINT64_MSW(x) ((x).Upper)
/*****************************************************************************/
/**
* Return the least significant half of the 64 bit data type.
*
* @param x is the 64 bit word.
*
* @return The lower 32 bits of the 64 bit word.
*
* @note None.
*
******************************************************************************/
#define XUINT64_LSW(x) ((x).Lower)
#endif /* XBASIC_TYPES_H */
/**
* xbasic_types.h does not typedef s* or u64
*/
typedef unsigned long long u64;
typedef char s8;
typedef short s16;
typedef long s32;
typedef long long s64;
#else
#include <linux/types.h>
#endif
/*@}*/
/************************** Constant Definitions *****************************/
#ifndef TRUE
#define TRUE 1
#endif
#ifndef FALSE
#define FALSE 0
#endif
#ifndef NULL
#define NULL 0
#endif
#endif /* end of protection macro */

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/* $Id: xio.h,v 1.1.2.2 2010/06/16 11:15:32 sadanan Exp $ */
/******************************************************************************
*
* (c) Copyright 2007-2009 Xilinx, Inc. All rights reserved.
*
* This file contains confidential and proprietary information of Xilinx, Inc.
* and is protected under U.S. and international copyright and other
* intellectual property laws.
*
* DISCLAIMER
* This disclaimer is not a license and does not grant any rights to the
* materials distributed herewith. Except as otherwise provided in a valid
* license issued to you by Xilinx, and to the maximum extent permitted by
* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
* and (2) Xilinx shall not be liable (whether in contract or tort, including
* negligence, or under any other theory of liability) for any loss or damage
* of any kind or nature related to, arising under or in connection with these
* materials, including for any direct, or any indirect, special, incidental,
* or consequential loss or damage (including loss of data, profits, goodwill,
* or any type of loss or damage suffered as a result of any action brought by
* a third party) even if such damage or loss was reasonably foreseeable or
* Xilinx had been advised of the possibility of the same.
*
* CRITICAL APPLICATIONS
* Xilinx products are not designed or intended to be fail-safe, or for use in
* any application requiring fail-safe performance, such as life-support or
* safety devices or systems, Class III medical devices, nuclear facilities,
* applications related to the deployment of airbags, or any other applications
* that could lead to death, personal injury, or severe property or
* environmental damage (individually and collectively, "Critical
* Applications"). Customer assumes the sole risk and liability of any use of
* Xilinx products in Critical Applications, subject only to applicable laws
* and regulations governing limitations on product liability.
*
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
* AT ALL TIMES.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xio.h
*
* This file contains the interface for the XIo component, which encapsulates
* the Input/Output functions for processors that do not require any special
* I/O handling.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00a rpm 11/07/03 Added InSwap/OutSwap routines for endian conversion
* 1.00a xd 11/04/04 Improved support for doxygen
* 1.01a ecm 02/24/06 CR225908 corrected the extra curly braces in macros
* and bumped version to 1.01.a.
* 1.11a mta 03/21/07 Updated to new coding style.
* 1.11b va 04/17/08 Updated Tcl for better CORE_CLOCK_FREQ_HZ definition
* 1.11a sdm 03/12/09 Updated Tcl to define correct value for CORE_CLOCK_FREQ_HZ
* (CR #502010)
* 1.13a sdm 03/12/09 Updated the Tcl to pull appropriate libraries for Little
* Endian Microblaze
*
* </pre>
*
* @note
*
* This file may contain architecture-dependent items (memory-mapped or
* non-memory-mapped I/O).
*
******************************************************************************/
#ifndef XIO_H /* prevent circular inclusions */
#define XIO_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xbasic_types.h"
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/**
* Typedef for an I/O address. Typically correlates to the width of the
* address bus.
*/
typedef u32 XIo_Address;
/***************** Macros (Inline Functions) Definitions *********************/
/*
* The following macros allow optimized I/O operations for memory mapped I/O.
* It should be noted that macros cannot be used if synchronization of the I/O
* operation is needed as it will likely break some code.
*/
/*****************************************************************************/
/**
*
* Performs an input operation for an 8-bit memory location by reading from the
* specified address and returning the value read from that address.
*
* @param InputPtr contains the address to perform the input operation at.
*
* @return The value read from the specified input address.
*
* @note None.
*
******************************************************************************/
#define XIo_In8(InputPtr) (*(volatile u8 *)(InputPtr))
/*****************************************************************************/
/**
*
* Performs an input operation for a 16-bit memory location by reading from the
* specified address and returning the value read from that address.
*
* @param InputPtr contains the address to perform the input operation at.
*
* @return The value read from the specified input address.
*
* @note None.
*
******************************************************************************/
#define XIo_In16(InputPtr) (*(volatile u16 *)(InputPtr))
/*****************************************************************************/
/**
*
* Performs an input operation for a 32-bit memory location by reading from the
* specified address and returning the value read from that address.
*
* @param InputPtr contains the address to perform the input operation at.
*
* @return The value read from the specified input address.
*
* @note None.
*
******************************************************************************/
#define XIo_In32(InputPtr) (*(volatile u32 *)(InputPtr))
/*****************************************************************************/
/**
*
* Performs an output operation for an 8-bit memory location by writing the
* specified value to the the specified address.
*
* @param OutputPtr contains the address to perform the output operation
* at.
* @param Value contains the value to be output at the specified address.
*
* @return None
*
* @note None.
*
******************************************************************************/
#define XIo_Out8(OutputPtr, Value) \
(*(volatile u8 *)((OutputPtr)) = (Value))
/*****************************************************************************/
/**
*
* Performs an output operation for a 16-bit memory location by writing the
* specified value to the the specified address.
*
* @param OutputPtr contains the address to perform the output operation
* at.
* @param Value contains the value to be output at the specified address.
*
* @return None
*
* @note None.
*
******************************************************************************/
#define XIo_Out16(OutputPtr, Value) \
(*(volatile u16 *)((OutputPtr)) = (Value))
/*****************************************************************************/
/**
*
* Performs an output operation for a 32-bit memory location by writing the
* specified value to the the specified address.
*
* @param OutputPtr contains the address to perform the output operation
* at.
* @param Value contains the value to be output at the specified address.
*
* @return None
*
* @note None.
*
******************************************************************************/
#define XIo_Out32(OutputPtr, Value) \
(*(volatile u32 *)((OutputPtr)) = (Value))
/* The following macros allow the software to be transportable across
* processors which use big or little endian memory models.
*
* Defined first is a no-op endian conversion macro. This macro is not to
* be used directly by software. Instead, the XIo_To/FromLittleEndianXX and
* XIo_To/FromBigEndianXX macros below are to be used to allow the endian
* conversion to only be performed when necessary
*/
#define XIo_EndianNoop(Source, DestPtr) (*DestPtr = Source)
#ifdef XLITTLE_ENDIAN
#define XIo_ToLittleEndian16 XIo_EndianNoop
#define XIo_ToLittleEndian32 XIo_EndianNoop
#define XIo_FromLittleEndian16 XIo_EndianNoop
#define XIo_FromLittleEndian32 XIo_EndianNoop
#define XIo_ToBigEndian16(Source, DestPtr) XIo_EndianSwap16(Source, DestPtr)
#define XIo_ToBigEndian32(Source, DestPtr) XIo_EndianSwap32(Source, DestPtr)
#define XIo_FromBigEndian16 XIo_ToBigEndian16
#define XIo_FromBigEndian32 XIo_ToBigEndian32
#else
#define XIo_ToLittleEndian16(Source, DestPtr) XIo_EndianSwap16(Source, DestPtr)
#define XIo_ToLittleEndian32(Source, DestPtr) XIo_EndianSwap32(Source, DestPtr)
#define XIo_FromLittleEndian16 XIo_ToLittleEndian16
#define XIo_FromLittleEndian32 XIo_ToLittleEndian32
#define XIo_ToBigEndian16 XIo_EndianNoop
#define XIo_ToBigEndian32 XIo_EndianNoop
#define XIo_FromBigEndian16 XIo_EndianNoop
#define XIo_FromBigEndian32 XIo_EndianNoop
#endif
/************************** Function Prototypes ******************************/
/* The following functions allow the software to be transportable across
* processors which use big or little endian memory models. These functions
* should not be directly called, but the macros XIo_To/FromLittleEndianXX and
* XIo_To/FromBigEndianXX should be used to allow the endian conversion to only
* be performed when necessary.
*/
void XIo_EndianSwap16(u16 Source, u16 *DestPtr);
void XIo_EndianSwap32(u32 Source, u32 *DestPtr);
/* The following functions handle IO addresses where data must be swapped
* They cannot be implemented as macros
*/
u16 XIo_InSwap16(XIo_Address InAddress);
u32 XIo_InSwap32(XIo_Address InAddress);
void XIo_OutSwap16(XIo_Address OutAddress, u16 Value);
void XIo_OutSwap32(XIo_Address OutAddress, u32 Value);
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */

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/* $Id$ */
/******************************************************************************
*
* (c) Copyright 2011,2012 Xilinx, Inc. All rights reserved.
*
* This file contains confidential and proprietary information of Xilinx, Inc.
* and is protected under U.S. and international copyright and other
* intellectual property laws.
*
* DISCLAIMER
* This disclaimer is not a license and does not grant any rights to the
* materials distributed herewith. Except as otherwise provided in a valid
* license issued to you by Xilinx, and to the maximum extent permitted by
* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
* and (2) Xilinx shall not be liable (whether in contract or tort, including
* negligence, or under any other theory of liability) for any loss or damage
* of any kind or nature related to, arising under or in connection with these
* materials, including for any direct, or any indirect, special, incidental,
* or consequential loss or damage (including loss of data, profits, goodwill,
* or any type of loss or damage suffered as a result of any action brought by
* a third party) even if such damage or loss was reasonably foreseeable or
* Xilinx had been advised of the possibility of the same.
*
* CRITICAL APPLICATIONS
* Xilinx products are not designed or intended to be fail-safe, or for use in
* any application requiring fail-safe performance, such as life-support or
* safety devices or systems, Class III medical devices, nuclear facilities,
* applications related to the deployment of airbags, or any other applications
* that could lead to death, personal injury, or severe property or
* environmental damage (individually and collectively, "Critical
* Applications"). Customer assumes the sole risk and liability of any use of
* Xilinx products in Critical Applications, subject only to applicable laws
* and regulations governing limitations on product liability.
*
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
* AT ALL TIMES.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xiomodule.h
*
* The Xilinx IO Module driver component. This component supports the
* IO Module. The IO Module provides:
* <ol>
* <li>Universal Asynchronous Receiver Transmitter (UART)</li>
* <li>Fixed Interval Timer (FIT)</li>
* <li>Programmable Interval Timer (PIT)</li>
* <li>General Purpose Output (GPO)</li>
* <li>General Purpose Input (GPI)</li>
* <li>Interrupt controller (INTC)</li>
* <li>IO bus (IO)</li>
* </ol>
*
* <b>Universal Asynchronous Receiver Transmitter (UART):</b>
* This UART is a minimal hardware implementation with minimal features. Most
* of the features, including parity, and number of data bits are only
* configurable when the hardware device is built, rather than at run time by
* software. The UART has an internal baud rate generator that is clocked at a
* specified input clock frequency. The baud rate can either be fixed, or
* programmable. Not all programmed baud rates can be generated from some clock
* frequencies. The requested baud rate is checked using the provided clock for
* the system, and checked against the acceptable error range. An error may be
* returned from some functions indicating the baud rate was in error because
* it could not be generated.
*
* The device has support for interrupts: a transmit interrupt, a receive
* interrupt, and an error interrupt. The interrupts are individually
* configurable when the hardware device is built.
*
* The driver defaults to no interrupts at initialization such that interrupts
* must be enabled if desired. An interrupt is generated when the transmitter
* transitions from having data to being empty, when any data is contained in
* the receive register, or when an error occurs in received data.
*
* In order to use interrupts, it's necessary for the user to connect the driver
* interrupt handler, XIOModule_InterruptHandler, to the interrupt system of the
* application. This function does not save and restore the processor context
* such that the user must provide it. Send and receive handlers may be set for
* the driver such that the handlers are called when transmit and receive
* interrupts occur. The handlers are called from interrupt context and are
* designed to allow application specific processing to be performed.
*
* The functions, XIOModule_Send and XIOModule_Recv, are provided in the driver
* to allow data to be sent and received. They are designed to be used in
* polled or interrupt modes.
*
* The driver provides a status for each received byte indicating any parity
* frame or overrun error. The driver provides statistics which allow visibility
* into these errors.
*
* <b>Fixed Interval Timer (FIT):</b>
* The fixed interval timer supports the following features:
* - Interrupt driven mode
*
* The timer has a hardware programmed time period, which can be configured to
* cause a periodic interrupt. The driver only provides the ability to handle
* such interrupts.
*
* <b>Programmable Interval Timer (PIT):</b>
* The programmable interval timer supports the following features:
* - Polled mode
* - Interrupt driven mode
* - Enabling and disabling
* - Automatic reload
*
* The timer operates in compare mode. The timer always counts down.
*
* Compare mode is typically used for creating a single time period or multiple
* repeating time periods in the auto reload mode, such as a periodic interrupt.
* When started, the timer loads an initial value, referred to as the load
* value, into the timer and starts counting down. The timer expires when it
* rolls under. An external Output signal may be configured such that a pulse
* is generated with this signal when it rolls under.
*
* The timer can be configured to cause an interrupt when the count reaches
* zero. An external output is also toggled when the count reaches zero.
*
* <b>Interrupts</b>
*
* It is the responsibility of the application to connect the interrupt
* handler of the timer to the interrupt source. The interrupt handler function,
* XIOModule_InterruptHandler, is visible such that the user can connect it to
* the interrupt source. Note that this interrupt handler does not provide
* interrupt context save and restore processing, the user must perform this
* processing.
*
* The driver services interrupts and passes timeouts to the upper layer
* software through callback functions. The upper layer software must register
* its callback functions during initialization. The driver requires callback
* functions for timers.
*
* <b>General Purpose Output (GPO):</b>
* The GPO has support for up to 32 I/O discrete outputs for each channel (128
* bits total).
*
* <b>IO Bus (IO):</b>
* The IO Bus provides a generic mechanism to extend the IO Module
* functionality by providing a memory mapped IO area. Reading and writing of
* byte, halfword and word data is provided.
*
* <b>General Purpose Input (GPI):</b>
* The GPI has support for up to 32 I/O discrete outputs for each channel (128
* bits total). An interrupt can be generated when any bit in a GPI changes.
*
* <b>Interrupt controller (INTC):</b>
* The interrupt controller driver uses the idea of priority for the various
* handlers. Priority is an integer within the range of 0 and 31 inclusive with
* 0 being the highest priority interrupt source.
*
* The Xilinx interrupt controller supports the following features:
*
* - specific individual interrupt enabling/disabling
* - specific individual interrupt acknowledging
* - attaching specific callback function to handle interrupt source
* - master enable/disable
* - single callback per interrupt or all pending interrupts handled for
* each interrupt of the processor
*
* The acknowledgement of the interrupt within the interrupt controller is
* selectable, either prior to the device's handler being called or after
* the handler is called. This is necessary to support interrupt signal inputs
* which are either edge or level signals. Edge driven interrupt signals
* require that the interrupt is acknowledged prior to the interrupt being
* serviced in order to prevent the loss of interrupts which are occurring
* extremely close together. A level driven interrupt input signal requires
* the interrupt to acknowledged after servicing the interrupt to ensure that
* the interrupt only generates a single interrupt condition.
*
* Details about connecting the interrupt handler of the driver are contained
* in the source file specific to interrupt processing, xiomodule_intr.c.
*
* This driver is intended to be RTOS and processor independent. It works with
* physical addresses only. Any needs for dynamic memory management, threads
* or thread mutual exclusion, virtual memory, or cache control must be
* satisfied by the layer above this driver.
*
* <b>Interrupt Vector Tables</b>
*
* The interrupt vector table for each interrupt controller device is declared
* statically in xiomodule_g.c within the configuration data for each instance.
* The device ID of the interrupt controller device is used by the driver as a
* direct index into the configuration data table - to retrieve the vector table
* for an instance of the interrupt controller. The user should populate the
* vector table with handlers and callbacks at run-time using the
* XIOModule_Connect() and XIOModule_Disconnect() functions.
*
* Each vector table entry corresponds to a device that can generate an
* interrupt. Each entry contains an interrupt handler function and an argument
* to be passed to the handler when an interrupt occurs. The tools default this
* argument to the base address of the interrupting device. Note that the
* device driver interrupt handlers given in this file do not take a base
* address as an argument, but instead take a pointer to the driver instance.
* This means that although the table is created statically, the user must still
* use XIOModule_Connect() when the interrupt handler takes an argument other
* than the base address. This is only to say that the existence of the static
* vector tables should not mislead the user into thinking they no longer need
* to register/connect interrupt handlers with this driver.
*
* With fast interrupts enabled, the XIOModule_ConnectFastHandler() function
* should be used instead of XIOModule_Connect(). Note that the function pointer
* parameter Handler, must be a declared with the fast_interrupt attribute:
*
* void Handler() __attribute__((fast_interrupt));
*
* The routine defined by XIOModule_Connect() can be used by setting normal
* interrupt mode, using XIOModule_SetNormalIntrMode().
*
* @note
*
* This API utilizes 32 bit I/O to the registers. With less than 32 bits, the
* unused bits from registers are read as zero and written as don't cares.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00a sa 07/15/11 First release
* 1.01a sa 04/10/12 Updated with fast interrupt
* 1.02a sa 07/25/12 Updated with GPI interrupts and programmable baudrate
* </pre>
*
******************************************************************************/
#ifndef IOMODULE_H /* prevent circular inclusions */
#define IOMODULE_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xbasic_types.h"
#include "xparameters.h"
#include "xstatus.h"
#include "xiomodule_l.h"
/************************** Constant Definitions *****************************/
/**
* @name Configuration options
* These options are used in XIOModule_SetOptions() to configure the
* device.
* @{
*/
/**
* Used to configure the Programmable Interval Timer.
* <pre>
* XTC_INT_MODE_OPTION Dummy compatibility option. Enable interrupt
* output.
* XTC_AUTO_RELOAD_OPTION In compare mode, configures the timer to reload
* from the load value. The default mode causes
* the timer to hold after it rolls under.
* </pre>
*/
#define XTC_INT_MODE_OPTION 0
#define XTC_AUTO_RELOAD_OPTION 0x00000002UL
/**
* Used to configure the Interrupt Controller.
* <pre>
* XIN_SVC_SGL_ISR_OPTION Service the highest priority pending interrupt
* and then return.
* XIN_SVC_ALL_ISRS_OPTION Service all of the pending interrupts and then
* return.
* </pre>
*/
#define XIN_SVC_SGL_ISR_OPTION 1UL
#define XIN_SVC_ALL_ISRS_OPTION 2UL
/*@}*/
/**
* @name Hardware configuration mnemonics
* These mnemonics are used when accessing hardware configuration parameters.
* @{
*/
/**
* Mnemonics for the Programmable Interval Timer hardware configuration.
* <pre>
* XTC_PRESCALER_* Define the prescaler configured in hardware.
* </pre>
*/
#define XTC_PRESCALER_NONE 0
#define XTC_PRESCALER_FIT1 1
#define XTC_PRESCALER_FIT2 2
#define XTC_PRESCALER_FIT3 3
#define XTC_PRESCALER_FIT4 4
#define XTC_PRESCALER_PIT1 5
#define XTC_PRESCALER_PIT2 6
#define XTC_PRESCALER_PIT3 7
#define XTC_PRESCALER_PIT4 8
#define XTC_PRESCALER_EXTERNAL 9
/*@}*/
/**************************** Type Definitions *******************************/
/**
* Callback function. The first argument is a callback reference passed in by
* the upper layer when setting the callback functions, and passed back to the
* upper layer when the callback is invoked.
* The second argument is the ByteCount which is the number of bytes that
* actually moved from/to the buffer provided in the _Send/_Receive call.
*/
typedef void (*XIOModule_Handler)(void *CallBackRef,
unsigned int ByteCount);
/**
* This typedef contains configuration information for the device.
*/
typedef struct {
u16 DeviceId; /**< Unique ID of device */
u32 BaseAddress; /**< Unique identifier */
u32 IoBaseAddress; /**< IO Bus Base Address */
u32 FastIntr; /**< Fast Interrupt enabled */
u32 BaseVector; /**< Relocatable base vector */
u32 AckBeforeService; /**< Ack location per interrupt */
u32 Options; /**< Device options */
u32 InputClockHz; /**< Input clock frequency (Hz) */
u32 BaudRate; /**< Current baud rate */
u8 PitUsed[XTC_DEVICE_TIMER_COUNT]; /**< PIT is used */
u8 PitSize[XTC_DEVICE_TIMER_COUNT]; /**< PIT timer counter size */
u8 PitPrescaler[XTC_DEVICE_TIMER_COUNT]; /**< PIT prescaler */
u8 PitReadable[XTC_DEVICE_TIMER_COUNT]; /**< PIT readable */
u32 GpoInit[XGPO_DEVICE_COUNT]; /**< GPO initial value */
XIOModule_VectorTableEntry
HandlerTable[XPAR_IOMODULE_INTC_MAX_INTR_SIZE];
/**< Static vector table of interrupt handlers */
} XIOModule_Config;
/**
* Statistics for the UART
*/
typedef struct {
u32 TransmitInterrupts; /**< Number of transmit interrupts */
u32 ReceiveInterrupts; /**< Number of receive interrupts */
u32 CharactersTransmitted; /**< Number of characters transmitted */
u32 CharactersReceived; /**< Number of characters received */
u32 ReceiveOverrunErrors; /**< Number of receive overruns */
u32 ReceiveParityErrors; /**< Number of receive parity errors */
u32 ReceiveFramingErrors; /**< Number of receive framing errors */
} XIOModule_Uart_Stats;
/**
* The following data type is used to manage the buffers that are handled
* when sending and receiving UART data in the interrupt mode. It is intended
* for internal use only.
*/
typedef struct {
u8 *NextBytePtr;
unsigned int RequestedBytes;
unsigned int RemainingBytes;
} XIOModule_Buffer;
/**
* Signature for the timer callback function.
*
* @param CallBackRef is a callback reference passed in by the upper
* layer when setting the callback functions, and passed back to
* the upper layer when the callback is invoked. Its type is
* unimportant to the driver, so it is a void pointer.
* @param TimerNumber is the number of the timer within the device. The
* device typically contains from one to four timers. The timer
* number is a zero based number with a range of 0 to
* (XTC_DEVICE_TIMER_COUNT - 1).
*/
typedef void (*XIOModule_Timer_Handler) (void *CallBackRef, u8 TimerNumber);
/**
* Programmable Interval Timer statistics
*/
typedef struct {
u32 Interrupts; /**< Number of timer interrupts that have occurred */
} XIOModule_Timer_Stats;
/**
* The XIOModule driver instance data. The user is required to allocate a
* variable of this type for every iomodule device in the system. A pointer
* to a variable of this type is then passed to the driver API functions.
*/
typedef struct {
u32 BaseAddress; /**< Base address of registers */
u32 IsReady; /**< Device initialized and ready */
u32 IsStarted; /**< Device has been started */
XIOModule_Config *CfgPtr; /**< Pointer to inst config entry */
XIOModule_Uart_Stats Uart_Stats; /**< UART Statistics */
XIOModule_Buffer SendBuffer; /**< UART Send buffer */
XIOModule_Buffer ReceiveBuffer; /**< UART Receive buffer */
XIOModule_Handler RecvHandler; /**< UART Receive Handler */
void *RecvCallBackRef; /**< Callback ref for recv handler */
XIOModule_Handler SendHandler; /**< UART Send Handler */
void *SendCallBackRef; /**< Callback ref for send handler */
u32 CurrentUBRR; /**< UART Baud Rate Register value */
u32 UnhandledInterrupts; /**< Iomodule Interrupt Statistics */
u32 CurrentIER; /**< Interrupt Enable Register value*/
u32 CurrentIMR; /**< Interrupt Mode Register value */
XIOModule_Timer_Stats Timer_Stats[XTC_DEVICE_TIMER_COUNT];
/**< Timer statistics */
u32 CurrentTLR[XTC_DEVICE_TIMER_COUNT];
/**< Timer Load Register values */
u8 CurrentTCSR[XTC_DEVICE_TIMER_COUNT];
/**< Timer Control Register values */
XIOModule_Timer_Handler Handler; /**< Timer Callback function */
void *CallBackRef; /**< Timer Callback handler ref */
u32 GpoValue[XGPO_DEVICE_COUNT]; /**< GPO current value */
u32 IoBaseAddress; /**< Base address of IO Bus */
} XIOModule;
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
/*
* Required functions in xiomodule.c
*/
int XIOModule_Initialize(XIOModule * InstancePtr, u16 DeviceId);
int XIOModule_Timer_Initialize(XIOModule * InstancePtr, u16 DeviceId);
int XIOModule_Start(XIOModule * InstancePtr);
void XIOModule_Stop(XIOModule * InstancePtr);
int XIOModule_Connect(XIOModule * InstancePtr, u8 Id,
XInterruptHandler Handler, void *CallBackRef);
void XIOModule_Disconnect(XIOModule * InstancePtr, u8 Id);
void XIOModule_Enable(XIOModule * InstancePtr, u8 Id);
void XIOModule_Disable(XIOModule * InstancePtr, u8 Id);
void XIOModule_Acknowledge(XIOModule * InstancePtr, u8 Id);
XIOModule_Config *XIOModule_LookupConfig(u16 DeviceId);
int XIOModule_ConnectFastHandler(XIOModule *InstancePtr, u8 Id,
XFastInterruptHandler Handler);
void XIOModule_SetNormalIntrMode(XIOModule *InstancePtr, u8 Id);
/*
* API Basic functions for GPI and GPO implemented in xiomodule.c
*/
u32 XIOModule_DiscreteRead(XIOModule *InstancePtr, unsigned Channel);
void XIOModule_DiscreteWrite(XIOModule *InstancePtr,
unsigned Channel,
u32 Mask);
/*
* API Functions for GPI and GPO implemented in xiomodule_extra.c
*/
void XIOModule_DiscreteSet(XIOModule *InstancePtr, unsigned Channel, u32 Mask);
void XIOModule_DiscreteClear(XIOModule *InstancePtr,
unsigned Channel,
u32 Mask);
/*
* Required functions, in file xiomodule_uart.c
*/
int XIOModule_CfgInitialize(XIOModule *InstancePtr,
XIOModule_Config *Config,
u32 EffectiveAddr);
void XIOModule_ResetFifos(XIOModule *InstancePtr); /* Dummy */
unsigned int XIOModule_Send(XIOModule *InstancePtr, u8 *DataBufferPtr,
unsigned int NumBytes);
unsigned int XIOModule_Recv(XIOModule *InstancePtr, u8 *DataBufferPtr,
unsigned int NumBytes);
int XIOModule_IsSending(XIOModule *InstancePtr);
int XIOModule_SetBaudRate(XIOModule *InstancePtr, u32 BaudRate);
/*
* Functions for statistics, in file xiomodule_stats.c
*/
void XIOModule_GetStats(XIOModule *InstancePtr,
XIOModule_Uart_Stats *StatsPtr);
void XIOModule_ClearStats(XIOModule *InstancePtr);
/*
* Interrupt functions in xiomodule_intr.c
*/
void XIOModule_VoidInterruptHandler();
void XIOModule_InterruptHandler(XIOModule * InstancePtr);
void XIOModule_Uart_EnableInterrupt(XIOModule *InstancePtr);
void XIOModule_Uart_DisableInterrupt(XIOModule *InstancePtr);
void XIOModule_SetRecvHandler(XIOModule *InstancePtr, XIOModule_Handler FuncPtr,
void *CallBackRef);
void XIOModule_SetSendHandler(XIOModule *InstancePtr, XIOModule_Handler FuncPtr,
void *CallBackRef);
void XIOModule_Uart_InterruptHandler(XIOModule *InstancePtr);
/*
* Options functions in xiomodule_options.c
*/
int XIOModule_SetOptions(XIOModule * InstancePtr, u32 Options);
u32 XIOModule_GetOptions(XIOModule * InstancePtr);
/*
* Self-test functions in xiomodule_selftest.c
*/
int XIOModule_SelfTest(XIOModule * InstancePtr);
/*
* Required functions, in file xiomodule.c
*/
void XIOModule_Timer_Start(XIOModule * InstancePtr, u8 TimerNumber);
void XIOModule_Timer_Stop(XIOModule * InstancePtr, u8 TimerNumber);
u32 XIOModule_GetValue(XIOModule * InstancePtr, u8 TimerNumber);
void XIOModule_SetResetValue(XIOModule * InstancePtr, u8 TimerNumber,
u32 ResetValue);
u32 XIOModule_GetCaptureValue(XIOModule * InstancePtr, u8 TimerNumber);
int XIOModule_IsExpired(XIOModule * InstancePtr, u8 TimerNumber);
void XIOModule_Reset(XIOModule * InstancePtr, u8 TimerNumber);
/*
* Functions for options, in file xiomodule_options.c
*/
void XIOModule_Timer_SetOptions(XIOModule * InstancePtr, u8 TimerNumber,
u32 Options);
u32 XIOModule_Timer_GetOptions(XIOModule * InstancePtr, u8 TimerNumber);
/*
* Functions for statistics, in file xiomodule_stats.c
*/
void XIOModule_Timer_GetStats(XIOModule * InstancePtr,
XIOModule_Timer_Stats * StatsPtr);
void XIOModule_Timer_ClearStats(XIOModule * InstancePtr);
/*
* Functions for self-test, in file xiomodule_selftest.c
*/
int XIOModule_Timer_SelfTest(XIOModule * InstancePtr, u8 IOModuleNumber);
/*
* Functions for interrupts, in file xiomodule_intr.c
*/
void XIOModule_SetHandler(XIOModule * InstancePtr,
XIOModule_Timer_Handler FuncPtr,
void *CallBackRef);
void XIOModule_Timer_InterruptHandler(void *InstancePtr);
/*
* Basic functions for IO Bus read and write implemented in xiomodule.c
*/
u32 XIOModule_IoReadWord(XIOModule *InstancePtr, u32 ByteOffset);
u16 XIOModule_IoReadHalfword(XIOModule *InstancePtr, u32 ByteOffset);
u8 XIOModule_IoReadByte(XIOModule *InstancePtr, u32 ByteOffset);
void XIOModule_IoWriteWord(XIOModule *InstancePtr, u32 ByteOffset, u32 Data);
void XIOModule_IoWriteHalfword(XIOModule *InstancePtr, u32 ByteOffset, u16 Data);
void XIOModule_IoWriteByte(XIOModule *InstancePtr, u32 ByteOffset, u8 Data);
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */

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/* $Id$ */
/******************************************************************************
*
* (c) Copyright 2011 Xilinx, Inc. All rights reserved.
*
* This file contains confidential and proprietary information of Xilinx, Inc.
* and is protected under U.S. and international copyright and other
* intellectual property laws.
*
* DISCLAIMER
* This disclaimer is not a license and does not grant any rights to the
* materials distributed herewith. Except as otherwise provided in a valid
* license issued to you by Xilinx, and to the maximum extent permitted by
* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
* and (2) Xilinx shall not be liable (whether in contract or tort, including
* negligence, or under any other theory of liability) for any loss or damage
* of any kind or nature related to, arising under or in connection with these
* materials, including for any direct, or any indirect, special, incidental,
* or consequential loss or damage (including loss of data, profits, goodwill,
* or any type of loss or damage suffered as a result of any action brought by
* a third party) even if such damage or loss was reasonably foreseeable or
* Xilinx had been advised of the possibility of the same.
*
* CRITICAL APPLICATIONS
* Xilinx products are not designed or intended to be fail-safe, or for use in
* any application requiring fail-safe performance, such as life-support or
* safety devices or systems, Class III medical devices, nuclear facilities,
* applications related to the deployment of airbags, or any other applications
* that could lead to death, personal injury, or severe property or
* environmental damage (individually and collectively, "Critical
* Applications"). Customer assumes the sole risk and liability of any use of
* Xilinx products in Critical Applications, subject only to applicable laws
* and regulations governing limitations on product liability.
*
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
* AT ALL TIMES.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xiomodule_i.h
*
* This file contains data which is shared between files and internal to the
* XIOModule component. It is intended for internal use only.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00a sa 07/15/11 First release
* 1.02a sa 07/25/12 Added UART prototypes
* </pre>
*
******************************************************************************/
#ifndef XIOMODULE_I_H /* prevent circular inclusions */
#define XIOMODULE_I_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xbasic_types.h"
#include "xiomodule.h"
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/****************************************************************************
*
* Update the statistics of the instance.
*
* @param InstancePtr is a pointer to the XIOMOdule instance.
* @param StatusRegister contains the contents of the UART status
* register to update the statistics with.
*
* @return None.
*
* @note
*
* Signature: void XIOModule_UpdateStats(XIOModule *InstancePtr,
* u32 StatusRegister)
*
*****************************************************************************/
#define XIOModule_UpdateStats(InstancePtr, StatusRegister) \
{ \
if ((StatusRegister) & XUL_SR_OVERRUN_ERROR) \
{ \
(InstancePtr)->Uart_Stats.ReceiveOverrunErrors++; \
} \
if ((StatusRegister) & XUL_SR_PARITY_ERROR) \
{ \
(InstancePtr)->Uart_Stats.ReceiveParityErrors++; \
} \
if ((StatusRegister) & XUL_SR_FRAMING_ERROR) \
{ \
(InstancePtr)->Uart_Stats.ReceiveFramingErrors++; \
} \
}
/************************** Function Prototypes ******************************/
unsigned int XIOModule_SendBuffer(XIOModule *InstancePtr);
unsigned int XIOModule_ReceiveBuffer(XIOModule *InstancePtr);
/************************** Variable Definitions *****************************/
extern u32 XIOModule_BitPosMask[];
extern XIOModule_Config XIOModule_ConfigTable[];
#ifdef __cplusplus
}
#endif
#endif

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/* $Id$ */
/******************************************************************************
*
* (c) Copyright 2011 Xilinx, Inc. All rights reserved.
*
* This file contains confidential and proprietary information of Xilinx, Inc.
* and is protected under U.S. and international copyright and other
* intellectual property laws.
*
* DISCLAIMER
* This disclaimer is not a license and does not grant any rights to the
* materials distributed herewith. Except as otherwise provided in a valid
* license issued to you by Xilinx, and to the maximum extent permitted by
* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
* and (2) Xilinx shall not be liable (whether in contract or tort, including
* negligence, or under any other theory of liability) for any loss or damage
* of any kind or nature related to, arising under or in connection with these
* materials, including for any direct, or any indirect, special, incidental,
* or consequential loss or damage (including loss of data, profits, goodwill,
* or any type of loss or damage suffered as a result of any action brought by
* a third party) even if such damage or loss was reasonably foreseeable or
* Xilinx had been advised of the possibility of the same.
*
* CRITICAL APPLICATIONS
* Xilinx products are not designed or intended to be fail-safe, or for use in
* any application requiring fail-safe performance, such as life-support or
* safety devices or systems, Class III medical devices, nuclear facilities,
* applications related to the deployment of airbags, or any other applications
* that could lead to death, personal injury, or severe property or
* environmental damage (individually and collectively, "Critical
* Applications"). Customer assumes the sole risk and liability of any use of
* Xilinx products in Critical Applications, subject only to applicable laws
* and regulations governing limitations on product liability.
*
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
* AT ALL TIMES.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xiomodule_io.h
*
* This header file contains identifiers and low-level driver functions (or
* macros) that can be used to access the device. The user should refer to the
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------------
* 1.00a sa 07/15/11 First release
* </pre>
*
******************************************************************************/
#ifndef XIOMODULE_IO_H /* prevent circular inclusions */
#define XIOMODULE_IO_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xil_io.h"
/***************** Macros (Inline Functions) Definitions *********************/
#define XIomodule_In32 Xil_In32
#define XIomodule_Out32 Xil_Out32
#define XIomodule_In16 Xil_In16
#define XIomodule_Out16 Xil_Out16
#define XIomodule_In8 Xil_In8
#define XIomodule_Out8 Xil_Out8
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */

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/* $Id$ */
/******************************************************************************
*
* (c) Copyright 2011,2012 Xilinx, Inc. All rights reserved.
*
* This file contains confidential and proprietary information of Xilinx, Inc.
* and is protected under U.S. and international copyright and other
* intellectual property laws.
*
* DISCLAIMER
* This disclaimer is not a license and does not grant any rights to the
* materials distributed herewith. Except as otherwise provided in a valid
* license issued to you by Xilinx, and to the maximum extent permitted by
* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
* and (2) Xilinx shall not be liable (whether in contract or tort, including
* negligence, or under any other theory of liability) for any loss or damage
* of any kind or nature related to, arising under or in connection with these
* materials, including for any direct, or any indirect, special, incidental,
* or consequential loss or damage (including loss of data, profits, goodwill,
* or any type of loss or damage suffered as a result of any action brought by
* a third party) even if such damage or loss was reasonably foreseeable or
* Xilinx had been advised of the possibility of the same.
*
* CRITICAL APPLICATIONS
* Xilinx products are not designed or intended to be fail-safe, or for use in
* any application requiring fail-safe performance, such as life-support or
* safety devices or systems, Class III medical devices, nuclear facilities,
* applications related to the deployment of airbags, or any other applications
* that could lead to death, personal injury, or severe property or
* environmental damage (individually and collectively, "Critical
* Applications"). Customer assumes the sole risk and liability of any use of
* Xilinx products in Critical Applications, subject only to applicable laws
* and regulations governing limitations on product liability.
*
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
* AT ALL TIMES.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xiomodule_l.h
*
* This header file contains identifiers and low-level driver functions (or
* macros) that can be used to access the device. The user should refer to the
* hardware device specification for more details of the device operation.
*
*
* Note that users of the driver interface given in this file can register
* an interrupt handler dynamically (at run-time) using the
* XIntc_RegisterHandler() function.
* User of the driver interface given in xiomodule.h should still use
* XIntc_Connect(), as always.
* Also see the discussion of the interrupt vector tables in xiomodule.h.
*
* There are currently two interrupt handlers specified in this interface.
*
* - XIOModule_LowLevelInterruptHandler() is a handler without any arguments
* that is used in cases where there is a single interrupt controller device
* in the system and the handler cannot be passed an argument. This function
* is provided mostly for backward compatibility.
*
* - XIOModule_DeviceInterruptHandler() is a handler that takes a device ID
* as an argument, indicating which interrupt controller device in the system
* is causing the interrupt - thereby supporting multiple interrupt
* controllers.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------------
* 1.00a sa 07/15/11 First release
* 1.01a sa 04/10/12 Updated with fast interrupt
* 1.02a sa 07/25/12 Updated with GPI interrupt support
* </pre>
*
******************************************************************************/
#ifndef XIOMODULE_L_H /* prevent circular inclusions */
#define XIOMODULE_L_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xbasic_types.h"
#include "xparameters.h"
#include "xiomodule_io.h"
#include "xio.h"
/************************** Constant Definitions *****************************/
/**
* Defines the number of timer counters within a single hardware device. This
* number is not currently parameterized in the hardware but may be in the
* future.
*/
#define XTC_DEVICE_TIMER_COUNT 4
/**
* Each timer counter consumes 16 bytes of address space.
*/
#define XTC_TIMER_COUNTER_OFFSET 16
#define XTC_TIMER_COUNTER_SHIFT 4
/**
* Define the offsets from the base address for all the registers of the
* IO module, some registers may be optional in the hardware device.
*/
#define XUL_RX_OFFSET 0x00000000 /**< UART Receive Register - R */
#define XUL_TX_OFFSET 0x00000004 /**< UART Transmit Register - W */
#define XUL_STATUS_REG_OFFSET 0x00000008 /**< UART Status Register - R */
#define XUL_BAUDRATE_OFFSET 0x0000004C /**< UART Baud Rate Register - W */
#define XIN_IMR_OFFSET 0x0000000C /**< Intr Mode Register - W */
#define XGO_OUT_OFFSET 0x00000010 /**< General Purpose Output - W */
#define XGI_IN_OFFSET 0x00000020 /**< General Purpose Input - R */
#define XIN_ISR_OFFSET 0x00000030 /**< Intr Status Register - R */
#define XIN_IPR_OFFSET 0x00000034 /**< Intr Pending Register - R */
#define XIN_IER_OFFSET 0x00000038 /**< Intr Enable Register - W */
#define XIN_IAR_OFFSET 0x0000003C /**< Intr Acknowledge Register - W */
#define XTC_TLR_OFFSET 0x00000040 /**< Timer Load register - W */
#define XTC_TCR_OFFSET 0x00000044 /**< Timer counter register - R */
#define XTC_TCSR_OFFSET 0x00000048 /**< Timer Control register - W */
#define XIN_IVAR_OFFSET 0x00000080 /**< Intr Vector Address Register,
Interrupt 0 offset, present
only for Fast Interrupt - W */
/**
* UART status register bit position masks
*/
#define XUL_SR_PARITY_ERROR 0x80
#define XUL_SR_FRAMING_ERROR 0x40
#define XUL_SR_OVERRUN_ERROR 0x20
#define XUL_SR_INTR_ENABLED 0x10 /**< UART Interrupt enabled */
#define XUL_SR_TX_FIFO_FULL 0x08 /**< UART Transmit FIFO full */
#define XUL_SR_RX_FIFO_VALID_DATA 0x01 /**< UART Data Register valid */
/**
* UART stop bits are fixed at 1. Baud, parity, and data bits are fixed on a
* per instance basis.
*/
#define XUL_STOP_BITS 1
/**
* UART Parity definitions.
*/
#define XUL_PARITY_NONE 0
#define XUL_PARITY_ODD 1
#define XUL_PARITY_EVEN 2
/**
* Defines the number of GPI and GPO within a single hardware device. This
* number is not currently parameterized in the hardware but may be in the
* future.
* @{
*/
#define XGPI_DEVICE_COUNT 4
#define XGPO_DEVICE_COUNT 4
/**
* The following constants describe the offset of each GPI and GPO channel's
* data from the base address.
*/
#define XGPI_CHAN_OFFSET 0x00004
#define XGPI_DATA_OFFSET 0x00020
#define XGPO_CHAN_OFFSET 0x00004
#define XGPO_DATA_OFFSET 0x00010
/**
* Interrupt register bit position masks.
*/
#define XIN_IOMODULE_GPI_4_INTERRUPT_INTR 14
#define XIN_IOMODULE_GPI_3_INTERRUPT_INTR 13
#define XIN_IOMODULE_GPI_2_INTERRUPT_INTR 12
#define XIN_IOMODULE_GPI_1_INTERRUPT_INTR 11
#define XIN_IOMODULE_FIT_4_INTERRUPT_INTR 10
#define XIN_IOMODULE_FIT_3_INTERRUPT_INTR 9
#define XIN_IOMODULE_FIT_2_INTERRUPT_INTR 8
#define XIN_IOMODULE_FIT_1_INTERRUPT_INTR 7
#define XIN_IOMODULE_PIT_4_INTERRUPT_INTR 6
#define XIN_IOMODULE_PIT_3_INTERRUPT_INTR 5
#define XIN_IOMODULE_PIT_2_INTERRUPT_INTR 4
#define XIN_IOMODULE_PIT_1_INTERRUPT_INTR 3
#define XIN_IOMODULE_UART_RX_INTERRUPT_INTR 2
#define XIN_IOMODULE_UART_TX_INTERRUPT_INTR 1
#define XIN_IOMODULE_UART_ERROR_INTERRUPT_INTR 0
#define XIN_IOMODULE_EXTERNAL_INTERRUPT_INTR 16
/* @} */
/**
* @name Control Status Register Bit Definitions
* Control Status Register bit masks
* Used to configure the timer counter device.
* @{
*/
#define XTC_CSR_ENABLE_TMR_MASK 0x00000001 /**< Enables the timer */
#define XTC_CSR_AUTO_RELOAD_MASK 0x00000002 /**< In compare mode,
configures the timer
reload from the Load
Register. The default
mode causes the timer
counter to hold when it
rolls under. */
/* @} */
/**************************** Type Definitions *******************************/
/* The following data type defines each entry in an interrupt vector table.
* The callback reference is the base address of the interrupting device
* for the driver interface given in this file and an instance pointer for the
* driver interface given in xintc.h file.
*/
typedef struct {
XInterruptHandler Handler;
void *CallBackRef;
} XIOModule_VectorTableEntry;
typedef void (*XFastInterruptHandler) (void);
/***************** Macros (Inline Functions) Definitions *********************/
/****************************************************************************/
/**
*
* Enable specific interrupt(s) in the interrupt controller.
*
* @param BaseAddress is the base address of the device
* @param EnableMask is the 32-bit value to write to the enable register.
* Each bit of the mask corresponds to an interrupt input signal
* that is connected to the interrupt controller (INT0 = LSB).
* Only the bits which are set in the mask will enable interrupts.
*
* @return None.
*
* @note C-style signature:
* void XIOModule_EnableIntr(u32 BaseAddress, u32 EnableMask);
*
*****************************************************************************/
#define XIOModule_EnableIntr(BaseAddress, EnableMask) \
XIomodule_Out32((BaseAddress) + XIN_IER_OFFSET, (EnableMask))
/****************************************************************************/
/**
*
* Disable specific interrupt(s) in the interrupt controller.
*
* @param BaseAddress is the base address of the device
* @param DisableMask is the 32-bit value to write to enable register.
* Each bit of the mask corresponds to an interrupt input signal
* that is connected to the interrupt controller (INT0 = LSB).
* Only bits which are set in the mask will disable interrupts.
*
* @return None.
*
* @note C-style signature:
* void XIOModule_DisableIntr(u32 BaseAddress, u32 DisableMask);
*
*****************************************************************************/
#define XIOModule_DisableIntr(BaseAddress, DisableMask) \
XIomodule_Out32((BaseAddress) + XIN_IER_OFFSET, ~(DisableMask))
/****************************************************************************/
/**
*
* Acknowledge specific interrupt(s) in the interrupt controller.
*
* @param BaseAddress is the base address of the device
* @param AckMask is the 32-bit value to write to the acknowledge
* register. Each bit of the mask corresponds to an interrupt
* input signal that is connected to the interrupt controller
* (INT0 = LSB). Only the bits which are set in the mask will
* acknowledge interrupts.
*
* @return None.
*
* @note C-style signature:
* void XIOModule_AckIntr(u32 BaseAddress, u32 AckMask);
*
*****************************************************************************/
#define XIOModule_AckIntr(BaseAddress, AckMask) \
XIomodule_Out32((BaseAddress) + XIN_IAR_OFFSET, (AckMask))
/****************************************************************************/
/**
*
* Get the interrupt status from the interrupt controller which indicates
* which interrupts are active and enabled.
*
* @param BaseAddress is the base address of the device
*
* @return The 32-bit contents of the interrupt status register. Each bit
* corresponds to an interrupt input signal that is connected to
* the interrupt controller (INT0 = LSB). Bits which are set
* indicate an active interrupt which is also enabled.
*
* @note C-style signature:
* u32 XIOModule_GetIntrStatus(u32 BaseAddress);
*
*****************************************************************************/
#define XIOModule_GetIntrStatus(BaseAddress) \
(XIomodule_In32((BaseAddress) + XIN_IPR_OFFSET))
/****************************************************************************/
/**
*
* Get the contents of the UART status register. Use the XUL_SR_* constants
* defined above to interpret the bit-mask returned.
*
* @param BaseAddress is the base address of the device
*
* @return A 32-bit value representing the contents of the status
* register.
*
* @note C-style Signature:
* u32 XIOModule_GetStatusReg(u32 BaseAddress);
*
*****************************************************************************/
#define XIOModule_GetStatusReg(BaseAddress) \
XIomodule_In32((BaseAddress) + XUL_STATUS_REG_OFFSET)
/****************************************************************************/
/**
*
* Check to see if the UART receiver has data.
*
* @param BaseAddress is the base address of the device
*
* @return TRUE if the receiver is empty, FALSE if there is data present.
*
* @note C-style Signature:
* int XIOModule_IsReceiveEmpty(u32 BaseAddress);
*
*****************************************************************************/
#define XIOModule_IsReceiveEmpty(BaseAddress) \
((XIOModule_GetStatusReg((BaseAddress)) & XUL_SR_RX_FIFO_VALID_DATA) != \
XUL_SR_RX_FIFO_VALID_DATA)
/****************************************************************************/
/**
*
* Check to see if the transmitter is full.
*
* @param BaseAddress is the base address of the device
*
* @return TRUE if the transmitter is full, FALSE otherwise.
*
* @note C-style Signature:
* int XIOModule_IsTransmitFull(u32 BaseAddress);
*
*****************************************************************************/
#define XIOModule_IsTransmitFull(BaseAddress) \
((XIOModule_GetStatusReg((BaseAddress)) & XUL_SR_TX_FIFO_FULL) == \
XUL_SR_TX_FIFO_FULL)
/****************************************************************************/
/**
*
* Write a value to a GPO register. A 32 bit write is performed. If the
* GPO component is implemented in a smaller width, only the least
* significant data is written.
*
* @param BaseAddress is the base address of the GPO device.
* @param RegOffset is the register offset from the base to write to.
* @param Data is the data written to the register.
*
* @return None.
*
* @note C-style signature:
* void XIOModule_WriteReg(u32 BaseAddress,
* unsigned RegOffset, u32 Data)
*
****************************************************************************/
#define XIOModule_WriteReg(BaseAddress, RegOffset, Data) \
XIomodule_Out32((BaseAddress) + (RegOffset), (u32)(Data))
/****************************************************************************/
/**
*
* Read a value from a GPI register. A 32 bit read is performed. If the
* GPI component is implemented in a smaller width, only the least
* significant data is read from the register. The most significant data
* will be read as 0.
*
* @param BaseAddress is the base address of the GPI device.
* @param RegOffset is the register offset from the base to read from.
*
* @return Data read from the register.
*
* @note C-style signature:
* u32 XIOModule_ReadReg(u32 BaseAddress, unsigned RegOffset)
*
******************************************************************************/
#define XIOModule_ReadReg(BaseAddress, RegOffset) \
XIomodule_In32((BaseAddress) + (RegOffset))
/************************** Function Prototypes ******************************/
/*
* UART standard in and standard out handlers, to be connected to generic
* I/O handling code.
*/
void XIOModule_SendByte(u32 BaseAddress, u8 Data);
u8 XIOModule_RecvByte(u32 BaseAddress);
/*
* Interrupt controller handlers, to be connected to processor exception
* handling code.
*/
void XIOModule_LowLevelInterruptHandler(void);
void XIOModule_DeviceInterruptHandler(void *DeviceId);
/* Various configuration functions */
void XIOModule_SetIntrSvcOption(u32 BaseAddress, int Option);
void XIOModule_RegisterHandler(u32 BaseAddress,
int InterruptId,
XInterruptHandler Handler,
void *CallBackRef);
/************************** Variable Definitions *****************************/
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */

653
software/LED_Controller_bsp/microblaze_mcs/include/xparameters.h Normal file
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@@ -0,0 +1,653 @@
/*******************************************************************
*
* CAUTION: This file is automatically generated by libgen.
* Version: Xilinx EDK 14.7 EDK_P.20131013
* DO NOT EDIT.
*
* Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
*
* Description: Driver parameters
*
*******************************************************************/
#define STDIN_BASEADDRESS 0x80000000
#define STDOUT_BASEADDRESS 0x80000000
/******************************************************************/
/* Definitions for driver BRAM */
#define XPAR_XBRAM_NUM_INSTANCES 2
/* Definitions for peripheral DLMB_CNTLR */
#define XPAR_DLMB_CNTLR_DEVICE_ID 0
#define XPAR_DLMB_CNTLR_DATA_WIDTH 32
#define XPAR_DLMB_CNTLR_ECC 0
#define XPAR_DLMB_CNTLR_FAULT_INJECT 0
#define XPAR_DLMB_CNTLR_CE_FAILING_REGISTERS 0
#define XPAR_DLMB_CNTLR_UE_FAILING_REGISTERS 0
#define XPAR_DLMB_CNTLR_ECC_STATUS_REGISTERS 0
#define XPAR_DLMB_CNTLR_CE_COUNTER_WIDTH 0
#define XPAR_DLMB_CNTLR_ECC_ONOFF_REGISTER 0
#define XPAR_DLMB_CNTLR_ECC_ONOFF_RESET_VALUE 1
#define XPAR_DLMB_CNTLR_WRITE_ACCESS 2
#define XPAR_DLMB_CNTLR_BASEADDR 0x00000000
#define XPAR_DLMB_CNTLR_HIGHADDR 0x00003FFF
#define XPAR_DLMB_CNTLR_S_AXI_CTRL_BASEADDR 0xFFFFFFFF
#define XPAR_DLMB_CNTLR_S_AXI_CTRL_HIGHADDR 0xFFFFFFFF
/* Definitions for peripheral ILMB_CNTLR */
#define XPAR_ILMB_CNTLR_DEVICE_ID 1
#define XPAR_ILMB_CNTLR_DATA_WIDTH 32
#define XPAR_ILMB_CNTLR_ECC 0
#define XPAR_ILMB_CNTLR_FAULT_INJECT 0
#define XPAR_ILMB_CNTLR_CE_FAILING_REGISTERS 0
#define XPAR_ILMB_CNTLR_UE_FAILING_REGISTERS 0
#define XPAR_ILMB_CNTLR_ECC_STATUS_REGISTERS 0
#define XPAR_ILMB_CNTLR_CE_COUNTER_WIDTH 0
#define XPAR_ILMB_CNTLR_ECC_ONOFF_REGISTER 0
#define XPAR_ILMB_CNTLR_ECC_ONOFF_RESET_VALUE 1
#define XPAR_ILMB_CNTLR_WRITE_ACCESS 2
#define XPAR_ILMB_CNTLR_BASEADDR 0x00000000
#define XPAR_ILMB_CNTLR_HIGHADDR 0x00003FFF
#define XPAR_ILMB_CNTLR_S_AXI_CTRL_BASEADDR 0xFFFFFFFF
#define XPAR_ILMB_CNTLR_S_AXI_CTRL_HIGHADDR 0xFFFFFFFF
/******************************************************************/
/* Canonical definitions for peripheral DLMB_CNTLR */
#define XPAR_BRAM_0_DEVICE_ID XPAR_DLMB_CNTLR_DEVICE_ID
#define XPAR_BRAM_0_DATA_WIDTH 32
#define XPAR_BRAM_0_ECC 0
#define XPAR_BRAM_0_FAULT_INJECT 0
#define XPAR_BRAM_0_CE_FAILING_REGISTERS 0
#define XPAR_BRAM_0_UE_FAILING_REGISTERS 0
#define XPAR_BRAM_0_ECC_STATUS_REGISTERS 0
#define XPAR_BRAM_0_CE_COUNTER_WIDTH 0
#define XPAR_BRAM_0_ECC_ONOFF_REGISTER 0
#define XPAR_BRAM_0_ECC_ONOFF_RESET_VALUE 1
#define XPAR_BRAM_0_WRITE_ACCESS 2
#define XPAR_BRAM_0_BASEADDR 0x00000000
#define XPAR_BRAM_0_HIGHADDR 0x00003FFF
/* Canonical definitions for peripheral ILMB_CNTLR */
#define XPAR_BRAM_1_DEVICE_ID XPAR_ILMB_CNTLR_DEVICE_ID
#define XPAR_BRAM_1_DATA_WIDTH 32
#define XPAR_BRAM_1_ECC 0
#define XPAR_BRAM_1_FAULT_INJECT 0
#define XPAR_BRAM_1_CE_FAILING_REGISTERS 0
#define XPAR_BRAM_1_UE_FAILING_REGISTERS 0
#define XPAR_BRAM_1_ECC_STATUS_REGISTERS 0
#define XPAR_BRAM_1_CE_COUNTER_WIDTH 0
#define XPAR_BRAM_1_ECC_ONOFF_REGISTER 0
#define XPAR_BRAM_1_ECC_ONOFF_RESET_VALUE 1
#define XPAR_BRAM_1_WRITE_ACCESS 2
#define XPAR_BRAM_1_BASEADDR 0x00000000
#define XPAR_BRAM_1_HIGHADDR 0x00003FFF
/******************************************************************/
/* Definitions for driver IOMODULE */
#define XPAR_XIOMODULE_NUM_INSTANCES 1
/* Definitions for peripheral IOMODULE_0 */
#define XPAR_IOMODULE_0_DEVICE_ID 0
#define XPAR_IOMODULE_0_BASEADDR 0x80000000
#define XPAR_IOMODULE_0_HIGHADDR 0x8000007F
#define XPAR_IOMODULE_0_MASK 0xC0000000
#define XPAR_IOMODULE_0_FREQ 150000000
#define XPAR_IOMODULE_0_USE_UART_RX 0
#define XPAR_IOMODULE_0_USE_UART_TX 0
#define XPAR_IOMODULE_0_UART_BAUDRATE 9600
#define XPAR_IOMODULE_0_UART_PROG_BAUDRATE 0
#define XPAR_IOMODULE_0_UART_DATA_BITS 8
#define XPAR_IOMODULE_0_UART_USE_PARITY 0
#define XPAR_IOMODULE_0_UART_ODD_PARITY 0
#define XPAR_IOMODULE_0_UART_RX_INTERRUPT 0
#define XPAR_IOMODULE_0_UART_TX_INTERRUPT 0
#define XPAR_IOMODULE_0_UART_ERROR_INTERRUPT 0
#define XPAR_IOMODULE_0_USE_FIT1 0
#define XPAR_IOMODULE_0_FIT1_NO_CLOCKS 6216
#define XPAR_IOMODULE_0_FIT1_INTERRUPT 0
#define XPAR_IOMODULE_0_USE_FIT2 0
#define XPAR_IOMODULE_0_FIT2_NO_CLOCKS 6216
#define XPAR_IOMODULE_0_FIT2_INTERRUPT 0
#define XPAR_IOMODULE_0_USE_FIT3 0
#define XPAR_IOMODULE_0_FIT3_NO_CLOCKS 6216
#define XPAR_IOMODULE_0_FIT3_INTERRUPT 0
#define XPAR_IOMODULE_0_USE_FIT4 0
#define XPAR_IOMODULE_0_FIT4_NO_CLOCKS 6216
#define XPAR_IOMODULE_0_FIT4_INTERRUPT 0
#define XPAR_IOMODULE_0_USE_PIT1 0
#define XPAR_IOMODULE_0_PIT1_SIZE 32
#define XPAR_IOMODULE_0_PIT1_READABLE 1
#define XPAR_IOMODULE_0_PIT1_PRESCALER 0
#define XPAR_IOMODULE_0_PIT1_INTERRUPT 0
#define XPAR_IOMODULE_0_USE_PIT2 0
#define XPAR_IOMODULE_0_PIT2_SIZE 32
#define XPAR_IOMODULE_0_PIT2_READABLE 1
#define XPAR_IOMODULE_0_PIT2_PRESCALER 0
#define XPAR_IOMODULE_0_PIT2_INTERRUPT 0
#define XPAR_IOMODULE_0_USE_PIT3 0
#define XPAR_IOMODULE_0_PIT3_SIZE 32
#define XPAR_IOMODULE_0_PIT3_READABLE 1
#define XPAR_IOMODULE_0_PIT3_PRESCALER 0
#define XPAR_IOMODULE_0_PIT3_INTERRUPT 0
#define XPAR_IOMODULE_0_USE_PIT4 0
#define XPAR_IOMODULE_0_PIT4_SIZE 32
#define XPAR_IOMODULE_0_PIT4_READABLE 1
#define XPAR_IOMODULE_0_PIT4_PRESCALER 0
#define XPAR_IOMODULE_0_PIT4_INTERRUPT 0
#define XPAR_IOMODULE_0_USE_GPO1 1
#define XPAR_IOMODULE_0_GPO1_SIZE 16
#define XPAR_IOMODULE_0_USE_GPO2 1
#define XPAR_IOMODULE_0_GPO2_SIZE 16
#define XPAR_IOMODULE_0_USE_GPO3 1
#define XPAR_IOMODULE_0_GPO3_SIZE 1
#define XPAR_IOMODULE_0_USE_GPO4 1
#define XPAR_IOMODULE_0_GPO4_SIZE 6
#define XPAR_IOMODULE_0_USE_GPI1 1
#define XPAR_IOMODULE_0_GPI1_SIZE 8
#define XPAR_IOMODULE_0_GPI1_INTERRUPT 0
#define XPAR_IOMODULE_0_USE_GPI2 1
#define XPAR_IOMODULE_0_GPI2_SIZE 1
#define XPAR_IOMODULE_0_GPI2_INTERRUPT 3
#define XPAR_IOMODULE_0_USE_GPI3 1
#define XPAR_IOMODULE_0_GPI3_SIZE 2
#define XPAR_IOMODULE_0_GPI3_INTERRUPT 0
#define XPAR_IOMODULE_0_USE_GPI4 0
#define XPAR_IOMODULE_0_GPI4_SIZE 32
#define XPAR_IOMODULE_0_GPI4_INTERRUPT 0
#define XPAR_IOMODULE_0_INTC_USE_EXT_INTR 0
#define XPAR_IOMODULE_0_INTC_INTR_SIZE 1
#define XPAR_IOMODULE_0_INTC_HAS_FAST 1
#define XPAR_IOMODULE_0_INTC_BASE_VECTORS 0
#define XPAR_IOMODULE_0_USE_IO_BUS 0
#define XPAR_IOMODULE_0_IO_BASEADDR 0xC0000000
#define XPAR_IOMODULE_0_IO_HIGHADDR 0xFFFFFFFF
#define XPAR_IOMODULE_0_IO_MASK 0xC0000000
/******************************************************************/
/* Additional definitions for peripheral IOMODULE_0 */
#define XPAR_IOMODULE_0_GPO1_INIT 0x00000000
#define XPAR_IOMODULE_0_GPO2_INIT 0x00000000
#define XPAR_IOMODULE_0_GPO3_INIT 0x00000000
#define XPAR_IOMODULE_0_GPO4_INIT 0x00000000
#define XPAR_IOMODULE_0_INTC_LEVEL_EDGE 0x0000
#define XPAR_IOMODULE_0_INTC_POSITIVE 0xFFFF
/******************************************************************/
#define XPAR_IOMODULE_INTC_MAX_INTR_SIZE 13
#define XPAR_IOMODULE_SINGLE_BASEADDR 0x80000000
#define XPAR_IOMODULE_SINGLE_HIGHADDR 0x8000007F
#define XPAR_IOMODULE_INTC_SINGLE_DEVICE_ID XPAR_IOMODULE_0_DEVICE_ID
/******************************************************************/
/******************************************************************/
/* Definitions for bus frequencies */
/******************************************************************/
/* Canonical definitions for bus frequencies */
/******************************************************************/
#define XPAR_CPU_CORE_CLOCK_FREQ_HZ 150000000
#define XPAR_MICROBLAZE_CORE_CLOCK_FREQ_HZ 150000000
/******************************************************************/
/* Definitions for peripheral MICROBLAZE_MCS */
#define XPAR_MICROBLAZE_MCS_SCO 0
#define XPAR_MICROBLAZE_MCS_FREQ 150000000
#define XPAR_MICROBLAZE_MCS_DATA_SIZE 32
#define XPAR_MICROBLAZE_MCS_DYNAMIC_BUS_SIZING 1
#define XPAR_MICROBLAZE_MCS_AVOID_PRIMITIVES 0
#define XPAR_MICROBLAZE_MCS_FAULT_TOLERANT 0
#define XPAR_MICROBLAZE_MCS_ECC_USE_CE_EXCEPTION 0
#define XPAR_MICROBLAZE_MCS_LOCKSTEP_SLAVE 0
#define XPAR_MICROBLAZE_MCS_ENDIANNESS 1
#define XPAR_MICROBLAZE_MCS_AREA_OPTIMIZED 1
#define XPAR_MICROBLAZE_MCS_OPTIMIZATION 0
#define XPAR_MICROBLAZE_MCS_INTERCONNECT 2
#define XPAR_MICROBLAZE_MCS_STREAM_INTERCONNECT 0
#define XPAR_MICROBLAZE_MCS_DPLB_DWIDTH 32
#define XPAR_MICROBLAZE_MCS_DPLB_NATIVE_DWIDTH 32
#define XPAR_MICROBLAZE_MCS_DPLB_BURST_EN 0
#define XPAR_MICROBLAZE_MCS_DPLB_P2P 0
#define XPAR_MICROBLAZE_MCS_IPLB_DWIDTH 32
#define XPAR_MICROBLAZE_MCS_IPLB_NATIVE_DWIDTH 32
#define XPAR_MICROBLAZE_MCS_IPLB_BURST_EN 0
#define XPAR_MICROBLAZE_MCS_IPLB_P2P 0
#define XPAR_MICROBLAZE_MCS_M_AXI_DP_SUPPORTS_THREADS 0
#define XPAR_MICROBLAZE_MCS_M_AXI_DP_THREAD_ID_WIDTH 1
#define XPAR_MICROBLAZE_MCS_M_AXI_DP_SUPPORTS_READ 1
#define XPAR_MICROBLAZE_MCS_M_AXI_DP_SUPPORTS_WRITE 1
#define XPAR_MICROBLAZE_MCS_M_AXI_DP_SUPPORTS_NARROW_BURST 0
#define XPAR_MICROBLAZE_MCS_M_AXI_DP_DATA_WIDTH 32
#define XPAR_MICROBLAZE_MCS_M_AXI_DP_ADDR_WIDTH 32
#define XPAR_MICROBLAZE_MCS_M_AXI_DP_PROTOCOL AXI4LITE
#define XPAR_MICROBLAZE_MCS_M_AXI_DP_EXCLUSIVE_ACCESS 0
#define XPAR_MICROBLAZE_MCS_INTERCONNECT_M_AXI_DP_READ_ISSUING 1
#define XPAR_MICROBLAZE_MCS_INTERCONNECT_M_AXI_DP_WRITE_ISSUING 1
#define XPAR_MICROBLAZE_MCS_M_AXI_IP_SUPPORTS_THREADS 0
#define XPAR_MICROBLAZE_MCS_M_AXI_IP_THREAD_ID_WIDTH 1
#define XPAR_MICROBLAZE_MCS_M_AXI_IP_SUPPORTS_READ 1
#define XPAR_MICROBLAZE_MCS_M_AXI_IP_SUPPORTS_WRITE 0
#define XPAR_MICROBLAZE_MCS_M_AXI_IP_SUPPORTS_NARROW_BURST 0
#define XPAR_MICROBLAZE_MCS_M_AXI_IP_DATA_WIDTH 32
#define XPAR_MICROBLAZE_MCS_M_AXI_IP_ADDR_WIDTH 32
#define XPAR_MICROBLAZE_MCS_M_AXI_IP_PROTOCOL AXI4LITE
#define XPAR_MICROBLAZE_MCS_INTERCONNECT_M_AXI_IP_READ_ISSUING 1
#define XPAR_MICROBLAZE_MCS_D_AXI 0
#define XPAR_MICROBLAZE_MCS_D_PLB 0
#define XPAR_MICROBLAZE_MCS_D_LMB 1
#define XPAR_MICROBLAZE_MCS_I_AXI 0
#define XPAR_MICROBLAZE_MCS_I_PLB 0
#define XPAR_MICROBLAZE_MCS_I_LMB 1
#define XPAR_MICROBLAZE_MCS_USE_MSR_INSTR 0
#define XPAR_MICROBLAZE_MCS_USE_PCMP_INSTR 0
#define XPAR_MICROBLAZE_MCS_USE_BARREL 0
#define XPAR_MICROBLAZE_MCS_USE_DIV 0
#define XPAR_MICROBLAZE_MCS_USE_HW_MUL 0
#define XPAR_MICROBLAZE_MCS_USE_FPU 0
#define XPAR_MICROBLAZE_MCS_USE_REORDER_INSTR 0
#define XPAR_MICROBLAZE_MCS_UNALIGNED_EXCEPTIONS 0
#define XPAR_MICROBLAZE_MCS_ILL_OPCODE_EXCEPTION 0
#define XPAR_MICROBLAZE_MCS_M_AXI_I_BUS_EXCEPTION 0
#define XPAR_MICROBLAZE_MCS_M_AXI_D_BUS_EXCEPTION 0
#define XPAR_MICROBLAZE_MCS_IPLB_BUS_EXCEPTION 0
#define XPAR_MICROBLAZE_MCS_DPLB_BUS_EXCEPTION 0
#define XPAR_MICROBLAZE_MCS_DIV_ZERO_EXCEPTION 0
#define XPAR_MICROBLAZE_MCS_FPU_EXCEPTION 0
#define XPAR_MICROBLAZE_MCS_FSL_EXCEPTION 0
#define XPAR_MICROBLAZE_MCS_USE_STACK_PROTECTION 0
#define XPAR_MICROBLAZE_MCS_PVR 0
#define XPAR_MICROBLAZE_MCS_PVR_USER1 0x00
#define XPAR_MICROBLAZE_MCS_PVR_USER2 0x00000000
#define XPAR_MICROBLAZE_MCS_DEBUG_ENABLED 0
#define XPAR_MICROBLAZE_MCS_NUMBER_OF_PC_BRK 1
#define XPAR_MICROBLAZE_MCS_NUMBER_OF_RD_ADDR_BRK 0
#define XPAR_MICROBLAZE_MCS_NUMBER_OF_WR_ADDR_BRK 0
#define XPAR_MICROBLAZE_MCS_INTERRUPT_IS_EDGE 0
#define XPAR_MICROBLAZE_MCS_EDGE_IS_POSITIVE 1
#define XPAR_MICROBLAZE_MCS_RESET_MSR 0x00000000
#define XPAR_MICROBLAZE_MCS_OPCODE_0X0_ILLEGAL 0
#define XPAR_MICROBLAZE_MCS_FSL_LINKS 0
#define XPAR_MICROBLAZE_MCS_FSL_DATA_SIZE 32
#define XPAR_MICROBLAZE_MCS_USE_EXTENDED_FSL_INSTR 0
#define XPAR_MICROBLAZE_MCS_M0_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_MCS_S0_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_MCS_M1_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_MCS_S1_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_MCS_M2_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_MCS_S2_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_MCS_M3_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_MCS_S3_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_MCS_M4_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_MCS_S4_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_MCS_M5_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_MCS_S5_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_MCS_M6_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_MCS_S6_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_MCS_M7_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_MCS_S7_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_MCS_M8_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_MCS_S8_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_MCS_M9_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_MCS_S9_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_MCS_M10_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_MCS_S10_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_MCS_M11_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_MCS_S11_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_MCS_M12_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_MCS_S12_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_MCS_M13_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_MCS_S13_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_MCS_M14_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_MCS_S14_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_MCS_M15_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_MCS_S15_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_MCS_M0_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_MCS_S0_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_MCS_M1_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_MCS_S1_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_MCS_M2_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_MCS_S2_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_MCS_M3_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_MCS_S3_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_MCS_M4_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_MCS_S4_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_MCS_M5_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_MCS_S5_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_MCS_M6_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_MCS_S6_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_MCS_M7_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_MCS_S7_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_MCS_M8_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_MCS_S8_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_MCS_M9_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_MCS_S9_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_MCS_M10_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_MCS_S10_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_MCS_M11_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_MCS_S11_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_MCS_M12_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_MCS_S12_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_MCS_M13_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_MCS_S13_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_MCS_M14_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_MCS_S14_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_MCS_M15_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_MCS_S15_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_MCS_ICACHE_BASEADDR 0x00000000
#define XPAR_MICROBLAZE_MCS_ICACHE_HIGHADDR 0x3FFFFFFF
#define XPAR_MICROBLAZE_MCS_USE_ICACHE 0
#define XPAR_MICROBLAZE_MCS_ALLOW_ICACHE_WR 1
#define XPAR_MICROBLAZE_MCS_ADDR_TAG_BITS 0
#define XPAR_MICROBLAZE_MCS_CACHE_BYTE_SIZE 16384
#define XPAR_MICROBLAZE_MCS_ICACHE_USE_FSL 0
#define XPAR_MICROBLAZE_MCS_ICACHE_LINE_LEN 4
#define XPAR_MICROBLAZE_MCS_ICACHE_ALWAYS_USED 0
#define XPAR_MICROBLAZE_MCS_ICACHE_INTERFACE 0
#define XPAR_MICROBLAZE_MCS_ICACHE_VICTIMS 0
#define XPAR_MICROBLAZE_MCS_ICACHE_STREAMS 0
#define XPAR_MICROBLAZE_MCS_ICACHE_FORCE_TAG_LUTRAM 0
#define XPAR_MICROBLAZE_MCS_ICACHE_DATA_WIDTH 0
#define XPAR_MICROBLAZE_MCS_M_AXI_IC_SUPPORTS_THREADS 0
#define XPAR_MICROBLAZE_MCS_M_AXI_IC_THREAD_ID_WIDTH 1
#define XPAR_MICROBLAZE_MCS_M_AXI_IC_SUPPORTS_READ 1
#define XPAR_MICROBLAZE_MCS_M_AXI_IC_SUPPORTS_WRITE 0
#define XPAR_MICROBLAZE_MCS_M_AXI_IC_SUPPORTS_NARROW_BURST 0
#define XPAR_MICROBLAZE_MCS_M_AXI_IC_DATA_WIDTH 32
#define XPAR_MICROBLAZE_MCS_M_AXI_IC_ADDR_WIDTH 32
#define XPAR_MICROBLAZE_MCS_M_AXI_IC_PROTOCOL AXI4
#define XPAR_MICROBLAZE_MCS_M_AXI_IC_USER_VALUE 0b11111
#define XPAR_MICROBLAZE_MCS_M_AXI_IC_SUPPORTS_USER_SIGNALS 1
#define XPAR_MICROBLAZE_MCS_M_AXI_IC_AWUSER_WIDTH 5
#define XPAR_MICROBLAZE_MCS_M_AXI_IC_ARUSER_WIDTH 5
#define XPAR_MICROBLAZE_MCS_M_AXI_IC_WUSER_WIDTH 1
#define XPAR_MICROBLAZE_MCS_M_AXI_IC_RUSER_WIDTH 1
#define XPAR_MICROBLAZE_MCS_M_AXI_IC_BUSER_WIDTH 1
#define XPAR_MICROBLAZE_MCS_INTERCONNECT_M_AXI_IC_READ_ISSUING 2
#define XPAR_MICROBLAZE_MCS_DCACHE_BASEADDR 0x00000000
#define XPAR_MICROBLAZE_MCS_DCACHE_HIGHADDR 0x3FFFFFFF
#define XPAR_MICROBLAZE_MCS_USE_DCACHE 0
#define XPAR_MICROBLAZE_MCS_ALLOW_DCACHE_WR 1
#define XPAR_MICROBLAZE_MCS_DCACHE_ADDR_TAG 0
#define XPAR_MICROBLAZE_MCS_DCACHE_BYTE_SIZE 16384
#define XPAR_MICROBLAZE_MCS_DCACHE_USE_FSL 0
#define XPAR_MICROBLAZE_MCS_DCACHE_LINE_LEN 4
#define XPAR_MICROBLAZE_MCS_DCACHE_ALWAYS_USED 0
#define XPAR_MICROBLAZE_MCS_DCACHE_INTERFACE 0
#define XPAR_MICROBLAZE_MCS_DCACHE_USE_WRITEBACK 0
#define XPAR_MICROBLAZE_MCS_DCACHE_VICTIMS 0
#define XPAR_MICROBLAZE_MCS_DCACHE_FORCE_TAG_LUTRAM 0
#define XPAR_MICROBLAZE_MCS_DCACHE_DATA_WIDTH 0
#define XPAR_MICROBLAZE_MCS_M_AXI_DC_SUPPORTS_THREADS 0
#define XPAR_MICROBLAZE_MCS_M_AXI_DC_THREAD_ID_WIDTH 1
#define XPAR_MICROBLAZE_MCS_M_AXI_DC_SUPPORTS_READ 1
#define XPAR_MICROBLAZE_MCS_M_AXI_DC_SUPPORTS_WRITE 1
#define XPAR_MICROBLAZE_MCS_M_AXI_DC_SUPPORTS_NARROW_BURST 0
#define XPAR_MICROBLAZE_MCS_M_AXI_DC_DATA_WIDTH 32
#define XPAR_MICROBLAZE_MCS_M_AXI_DC_ADDR_WIDTH 32
#define XPAR_MICROBLAZE_MCS_M_AXI_DC_PROTOCOL AXI4
#define XPAR_MICROBLAZE_MCS_M_AXI_DC_EXCLUSIVE_ACCESS 0
#define XPAR_MICROBLAZE_MCS_M_AXI_DC_USER_VALUE 0b11111
#define XPAR_MICROBLAZE_MCS_M_AXI_DC_SUPPORTS_USER_SIGNALS 1
#define XPAR_MICROBLAZE_MCS_M_AXI_DC_AWUSER_WIDTH 5
#define XPAR_MICROBLAZE_MCS_M_AXI_DC_ARUSER_WIDTH 5
#define XPAR_MICROBLAZE_MCS_M_AXI_DC_WUSER_WIDTH 1
#define XPAR_MICROBLAZE_MCS_M_AXI_DC_RUSER_WIDTH 1
#define XPAR_MICROBLAZE_MCS_M_AXI_DC_BUSER_WIDTH 1
#define XPAR_MICROBLAZE_MCS_INTERCONNECT_M_AXI_DC_READ_ISSUING 2
#define XPAR_MICROBLAZE_MCS_INTERCONNECT_M_AXI_DC_WRITE_ISSUING 32
#define XPAR_MICROBLAZE_MCS_USE_MMU 0
#define XPAR_MICROBLAZE_MCS_MMU_DTLB_SIZE 4
#define XPAR_MICROBLAZE_MCS_MMU_ITLB_SIZE 2
#define XPAR_MICROBLAZE_MCS_MMU_TLB_ACCESS 3
#define XPAR_MICROBLAZE_MCS_MMU_ZONES 16
#define XPAR_MICROBLAZE_MCS_MMU_PRIVILEGED_INSTR 0
#define XPAR_MICROBLAZE_MCS_USE_INTERRUPT 2
#define XPAR_MICROBLAZE_MCS_USE_EXT_BRK 0
#define XPAR_MICROBLAZE_MCS_USE_EXT_NM_BRK 0
#define XPAR_MICROBLAZE_MCS_USE_BRANCH_TARGET_CACHE 0
#define XPAR_MICROBLAZE_MCS_BRANCH_TARGET_CACHE_SIZE 0
#define XPAR_MICROBLAZE_MCS_PC_WIDTH 32
/******************************************************************/
#define XPAR_CPU_ID 0
#define XPAR_MICROBLAZE_ID 0
#define XPAR_MICROBLAZE_SCO 0
#define XPAR_MICROBLAZE_FREQ 150000000
#define XPAR_MICROBLAZE_DATA_SIZE 32
#define XPAR_MICROBLAZE_DYNAMIC_BUS_SIZING 1
#define XPAR_MICROBLAZE_AVOID_PRIMITIVES 0
#define XPAR_MICROBLAZE_FAULT_TOLERANT 0
#define XPAR_MICROBLAZE_ECC_USE_CE_EXCEPTION 0
#define XPAR_MICROBLAZE_LOCKSTEP_SLAVE 0
#define XPAR_MICROBLAZE_ENDIANNESS 1
#define XPAR_MICROBLAZE_AREA_OPTIMIZED 1
#define XPAR_MICROBLAZE_OPTIMIZATION 0
#define XPAR_MICROBLAZE_INTERCONNECT 2
#define XPAR_MICROBLAZE_STREAM_INTERCONNECT 0
#define XPAR_MICROBLAZE_DPLB_DWIDTH 32
#define XPAR_MICROBLAZE_DPLB_NATIVE_DWIDTH 32
#define XPAR_MICROBLAZE_DPLB_BURST_EN 0
#define XPAR_MICROBLAZE_DPLB_P2P 0
#define XPAR_MICROBLAZE_IPLB_DWIDTH 32
#define XPAR_MICROBLAZE_IPLB_NATIVE_DWIDTH 32
#define XPAR_MICROBLAZE_IPLB_BURST_EN 0
#define XPAR_MICROBLAZE_IPLB_P2P 0
#define XPAR_MICROBLAZE_M_AXI_DP_SUPPORTS_THREADS 0
#define XPAR_MICROBLAZE_M_AXI_DP_THREAD_ID_WIDTH 1
#define XPAR_MICROBLAZE_M_AXI_DP_SUPPORTS_READ 1
#define XPAR_MICROBLAZE_M_AXI_DP_SUPPORTS_WRITE 1
#define XPAR_MICROBLAZE_M_AXI_DP_SUPPORTS_NARROW_BURST 0
#define XPAR_MICROBLAZE_M_AXI_DP_DATA_WIDTH 32
#define XPAR_MICROBLAZE_M_AXI_DP_ADDR_WIDTH 32
#define XPAR_MICROBLAZE_M_AXI_DP_PROTOCOL AXI4LITE
#define XPAR_MICROBLAZE_M_AXI_DP_EXCLUSIVE_ACCESS 0
#define XPAR_MICROBLAZE_INTERCONNECT_M_AXI_DP_READ_ISSUING 1
#define XPAR_MICROBLAZE_INTERCONNECT_M_AXI_DP_WRITE_ISSUING 1
#define XPAR_MICROBLAZE_M_AXI_IP_SUPPORTS_THREADS 0
#define XPAR_MICROBLAZE_M_AXI_IP_THREAD_ID_WIDTH 1
#define XPAR_MICROBLAZE_M_AXI_IP_SUPPORTS_READ 1
#define XPAR_MICROBLAZE_M_AXI_IP_SUPPORTS_WRITE 0
#define XPAR_MICROBLAZE_M_AXI_IP_SUPPORTS_NARROW_BURST 0
#define XPAR_MICROBLAZE_M_AXI_IP_DATA_WIDTH 32
#define XPAR_MICROBLAZE_M_AXI_IP_ADDR_WIDTH 32
#define XPAR_MICROBLAZE_M_AXI_IP_PROTOCOL AXI4LITE
#define XPAR_MICROBLAZE_INTERCONNECT_M_AXI_IP_READ_ISSUING 1
#define XPAR_MICROBLAZE_D_AXI 0
#define XPAR_MICROBLAZE_D_PLB 0
#define XPAR_MICROBLAZE_D_LMB 1
#define XPAR_MICROBLAZE_I_AXI 0
#define XPAR_MICROBLAZE_I_PLB 0
#define XPAR_MICROBLAZE_I_LMB 1
#define XPAR_MICROBLAZE_USE_MSR_INSTR 0
#define XPAR_MICROBLAZE_USE_PCMP_INSTR 0
#define XPAR_MICROBLAZE_USE_BARREL 0
#define XPAR_MICROBLAZE_USE_DIV 0
#define XPAR_MICROBLAZE_USE_HW_MUL 0
#define XPAR_MICROBLAZE_USE_FPU 0
#define XPAR_MICROBLAZE_USE_REORDER_INSTR 0
#define XPAR_MICROBLAZE_UNALIGNED_EXCEPTIONS 0
#define XPAR_MICROBLAZE_ILL_OPCODE_EXCEPTION 0
#define XPAR_MICROBLAZE_M_AXI_I_BUS_EXCEPTION 0
#define XPAR_MICROBLAZE_M_AXI_D_BUS_EXCEPTION 0
#define XPAR_MICROBLAZE_IPLB_BUS_EXCEPTION 0
#define XPAR_MICROBLAZE_DPLB_BUS_EXCEPTION 0
#define XPAR_MICROBLAZE_DIV_ZERO_EXCEPTION 0
#define XPAR_MICROBLAZE_FPU_EXCEPTION 0
#define XPAR_MICROBLAZE_FSL_EXCEPTION 0
#define XPAR_MICROBLAZE_USE_STACK_PROTECTION 0
#define XPAR_MICROBLAZE_PVR 0
#define XPAR_MICROBLAZE_PVR_USER1 0x00
#define XPAR_MICROBLAZE_PVR_USER2 0x00000000
#define XPAR_MICROBLAZE_DEBUG_ENABLED 0
#define XPAR_MICROBLAZE_NUMBER_OF_PC_BRK 1
#define XPAR_MICROBLAZE_NUMBER_OF_RD_ADDR_BRK 0
#define XPAR_MICROBLAZE_NUMBER_OF_WR_ADDR_BRK 0
#define XPAR_MICROBLAZE_INTERRUPT_IS_EDGE 0
#define XPAR_MICROBLAZE_EDGE_IS_POSITIVE 1
#define XPAR_MICROBLAZE_RESET_MSR 0x00000000
#define XPAR_MICROBLAZE_OPCODE_0X0_ILLEGAL 0
#define XPAR_MICROBLAZE_FSL_LINKS 0
#define XPAR_MICROBLAZE_FSL_DATA_SIZE 32
#define XPAR_MICROBLAZE_USE_EXTENDED_FSL_INSTR 0
#define XPAR_MICROBLAZE_M0_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_S0_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_M1_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_S1_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_M2_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_S2_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_M3_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_S3_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_M4_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_S4_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_M5_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_S5_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_M6_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_S6_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_M7_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_S7_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_M8_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_S8_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_M9_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_S9_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_M10_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_S10_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_M11_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_S11_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_M12_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_S12_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_M13_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_S13_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_M14_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_S14_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_M15_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_S15_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_M0_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_S0_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_M1_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_S1_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_M2_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_S2_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_M3_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_S3_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_M4_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_S4_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_M5_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_S5_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_M6_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_S6_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_M7_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_S7_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_M8_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_S8_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_M9_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_S9_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_M10_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_S10_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_M11_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_S11_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_M12_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_S12_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_M13_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_S13_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_M14_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_S14_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_M15_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_S15_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_ICACHE_BASEADDR 0x00000000
#define XPAR_MICROBLAZE_ICACHE_HIGHADDR 0x3FFFFFFF
#define XPAR_MICROBLAZE_USE_ICACHE 0
#define XPAR_MICROBLAZE_ALLOW_ICACHE_WR 1
#define XPAR_MICROBLAZE_ADDR_TAG_BITS 0
#define XPAR_MICROBLAZE_CACHE_BYTE_SIZE 16384
#define XPAR_MICROBLAZE_ICACHE_USE_FSL 0
#define XPAR_MICROBLAZE_ICACHE_LINE_LEN 4
#define XPAR_MICROBLAZE_ICACHE_ALWAYS_USED 0
#define XPAR_MICROBLAZE_ICACHE_INTERFACE 0
#define XPAR_MICROBLAZE_ICACHE_VICTIMS 0
#define XPAR_MICROBLAZE_ICACHE_STREAMS 0
#define XPAR_MICROBLAZE_ICACHE_FORCE_TAG_LUTRAM 0
#define XPAR_MICROBLAZE_ICACHE_DATA_WIDTH 0
#define XPAR_MICROBLAZE_M_AXI_IC_SUPPORTS_THREADS 0
#define XPAR_MICROBLAZE_M_AXI_IC_THREAD_ID_WIDTH 1
#define XPAR_MICROBLAZE_M_AXI_IC_SUPPORTS_READ 1
#define XPAR_MICROBLAZE_M_AXI_IC_SUPPORTS_WRITE 0
#define XPAR_MICROBLAZE_M_AXI_IC_SUPPORTS_NARROW_BURST 0
#define XPAR_MICROBLAZE_M_AXI_IC_DATA_WIDTH 32
#define XPAR_MICROBLAZE_M_AXI_IC_ADDR_WIDTH 32
#define XPAR_MICROBLAZE_M_AXI_IC_PROTOCOL AXI4
#define XPAR_MICROBLAZE_M_AXI_IC_USER_VALUE 0b11111
#define XPAR_MICROBLAZE_M_AXI_IC_SUPPORTS_USER_SIGNALS 1
#define XPAR_MICROBLAZE_M_AXI_IC_AWUSER_WIDTH 5
#define XPAR_MICROBLAZE_M_AXI_IC_ARUSER_WIDTH 5
#define XPAR_MICROBLAZE_M_AXI_IC_WUSER_WIDTH 1
#define XPAR_MICROBLAZE_M_AXI_IC_RUSER_WIDTH 1
#define XPAR_MICROBLAZE_M_AXI_IC_BUSER_WIDTH 1
#define XPAR_MICROBLAZE_INTERCONNECT_M_AXI_IC_READ_ISSUING 2
#define XPAR_MICROBLAZE_DCACHE_BASEADDR 0x00000000
#define XPAR_MICROBLAZE_DCACHE_HIGHADDR 0x3FFFFFFF
#define XPAR_MICROBLAZE_USE_DCACHE 0
#define XPAR_MICROBLAZE_ALLOW_DCACHE_WR 1
#define XPAR_MICROBLAZE_DCACHE_ADDR_TAG 0
#define XPAR_MICROBLAZE_DCACHE_BYTE_SIZE 16384
#define XPAR_MICROBLAZE_DCACHE_USE_FSL 0
#define XPAR_MICROBLAZE_DCACHE_LINE_LEN 4
#define XPAR_MICROBLAZE_DCACHE_ALWAYS_USED 0
#define XPAR_MICROBLAZE_DCACHE_INTERFACE 0
#define XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK 0
#define XPAR_MICROBLAZE_DCACHE_VICTIMS 0
#define XPAR_MICROBLAZE_DCACHE_FORCE_TAG_LUTRAM 0
#define XPAR_MICROBLAZE_DCACHE_DATA_WIDTH 0
#define XPAR_MICROBLAZE_M_AXI_DC_SUPPORTS_THREADS 0
#define XPAR_MICROBLAZE_M_AXI_DC_THREAD_ID_WIDTH 1
#define XPAR_MICROBLAZE_M_AXI_DC_SUPPORTS_READ 1
#define XPAR_MICROBLAZE_M_AXI_DC_SUPPORTS_WRITE 1
#define XPAR_MICROBLAZE_M_AXI_DC_SUPPORTS_NARROW_BURST 0
#define XPAR_MICROBLAZE_M_AXI_DC_DATA_WIDTH 32
#define XPAR_MICROBLAZE_M_AXI_DC_ADDR_WIDTH 32
#define XPAR_MICROBLAZE_M_AXI_DC_PROTOCOL AXI4
#define XPAR_MICROBLAZE_M_AXI_DC_EXCLUSIVE_ACCESS 0
#define XPAR_MICROBLAZE_M_AXI_DC_USER_VALUE 0b11111
#define XPAR_MICROBLAZE_M_AXI_DC_SUPPORTS_USER_SIGNALS 1
#define XPAR_MICROBLAZE_M_AXI_DC_AWUSER_WIDTH 5
#define XPAR_MICROBLAZE_M_AXI_DC_ARUSER_WIDTH 5
#define XPAR_MICROBLAZE_M_AXI_DC_WUSER_WIDTH 1
#define XPAR_MICROBLAZE_M_AXI_DC_RUSER_WIDTH 1
#define XPAR_MICROBLAZE_M_AXI_DC_BUSER_WIDTH 1
#define XPAR_MICROBLAZE_INTERCONNECT_M_AXI_DC_READ_ISSUING 2
#define XPAR_MICROBLAZE_INTERCONNECT_M_AXI_DC_WRITE_ISSUING 32
#define XPAR_MICROBLAZE_USE_MMU 0
#define XPAR_MICROBLAZE_MMU_DTLB_SIZE 4
#define XPAR_MICROBLAZE_MMU_ITLB_SIZE 2
#define XPAR_MICROBLAZE_MMU_TLB_ACCESS 3
#define XPAR_MICROBLAZE_MMU_ZONES 16
#define XPAR_MICROBLAZE_MMU_PRIVILEGED_INSTR 0
#define XPAR_MICROBLAZE_USE_INTERRUPT 2
#define XPAR_MICROBLAZE_USE_EXT_BRK 0
#define XPAR_MICROBLAZE_USE_EXT_NM_BRK 0
#define XPAR_MICROBLAZE_USE_BRANCH_TARGET_CACHE 0
#define XPAR_MICROBLAZE_BRANCH_TARGET_CACHE_SIZE 0
#define XPAR_MICROBLAZE_PC_WIDTH 32
#define XPAR_MICROBLAZE_HW_VER "8.40.a"
/******************************************************************/

418
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/******************************************************************************
*
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
* AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
* SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE,
* OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
* APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
* THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE.
*
* (c) Copyright 2002-2011 Xilinx Inc.
* All rights reserved.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xstatus.h
*
* This file contains Xilinx software status codes. Status codes have their
* own data type called int. These codes are used throughout the Xilinx
* device drivers.
*
******************************************************************************/
#ifndef XSTATUS_H /* prevent circular inclusions */
#define XSTATUS_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xbasic_types.h"
/************************** Constant Definitions *****************************/
/*********************** Common statuses 0 - 500 *****************************/
#define XST_SUCCESS 0L
#define XST_FAILURE 1L
#define XST_DEVICE_NOT_FOUND 2L
#define XST_DEVICE_BLOCK_NOT_FOUND 3L
#define XST_INVALID_VERSION 4L
#define XST_DEVICE_IS_STARTED 5L
#define XST_DEVICE_IS_STOPPED 6L
#define XST_FIFO_ERROR 7L /* an error occurred during an
operation with a FIFO such as
an underrun or overrun, this
error requires the device to
be reset */
#define XST_RESET_ERROR 8L /* an error occurred which requires
the device to be reset */
#define XST_DMA_ERROR 9L /* a DMA error occurred, this error
typically requires the device
using the DMA to be reset */
#define XST_NOT_POLLED 10L /* the device is not configured for
polled mode operation */
#define XST_FIFO_NO_ROOM 11L /* a FIFO did not have room to put
the specified data into */
#define XST_BUFFER_TOO_SMALL 12L /* the buffer is not large enough
to hold the expected data */
#define XST_NO_DATA 13L /* there was no data available */
#define XST_REGISTER_ERROR 14L /* a register did not contain the
expected value */
#define XST_INVALID_PARAM 15L /* an invalid parameter was passed
into the function */
#define XST_NOT_SGDMA 16L /* the device is not configured for
scatter-gather DMA operation */
#define XST_LOOPBACK_ERROR 17L /* a loopback test failed */
#define XST_NO_CALLBACK 18L /* a callback has not yet been
registered */
#define XST_NO_FEATURE 19L /* device is not configured with
the requested feature */
#define XST_NOT_INTERRUPT 20L /* device is not configured for
interrupt mode operation */
#define XST_DEVICE_BUSY 21L /* device is busy */
#define XST_ERROR_COUNT_MAX 22L /* the error counters of a device
have maxed out */
#define XST_IS_STARTED 23L /* used when part of device is
already started i.e.
sub channel */
#define XST_IS_STOPPED 24L /* used when part of device is
already stopped i.e.
sub channel */
#define XST_DATA_LOST 26L /* driver defined error */
#define XST_RECV_ERROR 27L /* generic receive error */
#define XST_SEND_ERROR 28L /* generic transmit error */
#define XST_NOT_ENABLED 29L /* a requested service is not
available because it has not
been enabled */
/***************** Utility Component statuses 401 - 500 *********************/
#define XST_MEMTEST_FAILED 401L /* memory test failed */
/***************** Common Components statuses 501 - 1000 *********************/
/********************* Packet Fifo statuses 501 - 510 ************************/
#define XST_PFIFO_LACK_OF_DATA 501L /* not enough data in FIFO */
#define XST_PFIFO_NO_ROOM 502L /* not enough room in FIFO */
#define XST_PFIFO_BAD_REG_VALUE 503L /* self test, a register value
was invalid after reset */
#define XST_PFIFO_ERROR 504L /* generic packet FIFO error */
#define XST_PFIFO_DEADLOCK 505L /* packet FIFO is reporting
* empty and full simultaneously
*/
/************************** DMA statuses 511 - 530 ***************************/
#define XST_DMA_TRANSFER_ERROR 511L /* self test, DMA transfer
failed */
#define XST_DMA_RESET_REGISTER_ERROR 512L /* self test, a register value
was invalid after reset */
#define XST_DMA_SG_LIST_EMPTY 513L /* scatter gather list contains
no buffer descriptors ready
to be processed */
#define XST_DMA_SG_IS_STARTED 514L /* scatter gather not stopped */
#define XST_DMA_SG_IS_STOPPED 515L /* scatter gather not running */
#define XST_DMA_SG_LIST_FULL 517L /* all the buffer desciptors of
the scatter gather list are
being used */
#define XST_DMA_SG_BD_LOCKED 518L /* the scatter gather buffer
descriptor which is to be
copied over in the scatter
list is locked */
#define XST_DMA_SG_NOTHING_TO_COMMIT 519L /* no buffer descriptors have been
put into the scatter gather
list to be commited */
#define XST_DMA_SG_COUNT_EXCEEDED 521L /* the packet count threshold
specified was larger than the
total # of buffer descriptors
in the scatter gather list */
#define XST_DMA_SG_LIST_EXISTS 522L /* the scatter gather list has
already been created */
#define XST_DMA_SG_NO_LIST 523L /* no scatter gather list has
been created */
#define XST_DMA_SG_BD_NOT_COMMITTED 524L /* the buffer descriptor which was
being started was not committed
to the list */
#define XST_DMA_SG_NO_DATA 525L /* the buffer descriptor to start
has already been used by the
hardware so it can't be reused
*/
#define XST_DMA_SG_LIST_ERROR 526L /* general purpose list access
error */
#define XST_DMA_BD_ERROR 527L /* general buffer descriptor
error */
/************************** IPIF statuses 531 - 550 ***************************/
#define XST_IPIF_REG_WIDTH_ERROR 531L /* an invalid register width
was passed into the function */
#define XST_IPIF_RESET_REGISTER_ERROR 532L /* the value of a register at
reset was not valid */
#define XST_IPIF_DEVICE_STATUS_ERROR 533L /* a write to the device interrupt
status register did not read
back correctly */
#define XST_IPIF_DEVICE_ACK_ERROR 534L /* the device interrupt status
register did not reset when
acked */
#define XST_IPIF_DEVICE_ENABLE_ERROR 535L /* the device interrupt enable
register was not updated when
other registers changed */
#define XST_IPIF_IP_STATUS_ERROR 536L /* a write to the IP interrupt
status register did not read
back correctly */
#define XST_IPIF_IP_ACK_ERROR 537L /* the IP interrupt status register
did not reset when acked */
#define XST_IPIF_IP_ENABLE_ERROR 538L /* IP interrupt enable register was
not updated correctly when other
registers changed */
#define XST_IPIF_DEVICE_PENDING_ERROR 539L /* The device interrupt pending
register did not indicate the
expected value */
#define XST_IPIF_DEVICE_ID_ERROR 540L /* The device interrupt ID register
did not indicate the expected
value */
#define XST_IPIF_ERROR 541L /* generic ipif error */
/****************** Device specific statuses 1001 - 4095 *********************/
/********************* Ethernet statuses 1001 - 1050 *************************/
#define XST_EMAC_MEMORY_SIZE_ERROR 1001L /* Memory space is not big enough
* to hold the minimum number of
* buffers or descriptors */
#define XST_EMAC_MEMORY_ALLOC_ERROR 1002L /* Memory allocation failed */
#define XST_EMAC_MII_READ_ERROR 1003L /* MII read error */
#define XST_EMAC_MII_BUSY 1004L /* An MII operation is in progress */
#define XST_EMAC_OUT_OF_BUFFERS 1005L /* Driver is out of buffers */
#define XST_EMAC_PARSE_ERROR 1006L /* Invalid driver init string */
#define XST_EMAC_COLLISION_ERROR 1007L /* Excess deferral or late
* collision on polled send */
/*********************** UART statuses 1051 - 1075 ***************************/
#define XST_UART
#define XST_UART_INIT_ERROR 1051L
#define XST_UART_START_ERROR 1052L
#define XST_UART_CONFIG_ERROR 1053L
#define XST_UART_TEST_FAIL 1054L
#define XST_UART_BAUD_ERROR 1055L
#define XST_UART_BAUD_RANGE 1056L
/************************ IIC statuses 1076 - 1100 ***************************/
#define XST_IIC_SELFTEST_FAILED 1076 /* self test failed */
#define XST_IIC_BUS_BUSY 1077 /* bus found busy */
#define XST_IIC_GENERAL_CALL_ADDRESS 1078 /* mastersend attempted with */
/* general call address */
#define XST_IIC_STAND_REG_RESET_ERROR 1079 /* A non parameterizable reg */
/* value after reset not valid */
#define XST_IIC_TX_FIFO_REG_RESET_ERROR 1080 /* Tx fifo included in design */
/* value after reset not valid */
#define XST_IIC_RX_FIFO_REG_RESET_ERROR 1081 /* Rx fifo included in design */
/* value after reset not valid */
#define XST_IIC_TBA_REG_RESET_ERROR 1082 /* 10 bit addr incl in design */
/* value after reset not valid */
#define XST_IIC_CR_READBACK_ERROR 1083 /* Read of the control register */
/* didn't return value written */
#define XST_IIC_DTR_READBACK_ERROR 1084 /* Read of the data Tx reg */
/* didn't return value written */
#define XST_IIC_DRR_READBACK_ERROR 1085 /* Read of the data Receive reg */
/* didn't return value written */
#define XST_IIC_ADR_READBACK_ERROR 1086 /* Read of the data Tx reg */
/* didn't return value written */
#define XST_IIC_TBA_READBACK_ERROR 1087 /* Read of the 10 bit addr reg */
/* didn't return written value */
#define XST_IIC_NOT_SLAVE 1088 /* The device isn't a slave */
/*********************** ATMC statuses 1101 - 1125 ***************************/
#define XST_ATMC_ERROR_COUNT_MAX 1101L /* the error counters in the ATM
controller hit the max value
which requires the statistics
to be cleared */
/*********************** Flash statuses 1126 - 1150 **************************/
#define XST_FLASH_BUSY 1126L /* Flash is erasing or programming
*/
#define XST_FLASH_READY 1127L /* Flash is ready for commands */
#define XST_FLASH_ERROR 1128L /* Flash had detected an internal
error. Use XFlash_DeviceControl
to retrieve device specific codes
*/
#define XST_FLASH_ERASE_SUSPENDED 1129L /* Flash is in suspended erase state
*/
#define XST_FLASH_WRITE_SUSPENDED 1130L /* Flash is in suspended write state
*/
#define XST_FLASH_PART_NOT_SUPPORTED 1131L /* Flash type not supported by
driver */
#define XST_FLASH_NOT_SUPPORTED 1132L /* Operation not supported */
#define XST_FLASH_TOO_MANY_REGIONS 1133L /* Too many erase regions */
#define XST_FLASH_TIMEOUT_ERROR 1134L /* Programming or erase operation
aborted due to a timeout */
#define XST_FLASH_ADDRESS_ERROR 1135L /* Accessed flash outside its
addressible range */
#define XST_FLASH_ALIGNMENT_ERROR 1136L /* Write alignment error */
#define XST_FLASH_BLOCKING_CALL_ERROR 1137L /* Couldn't return immediately from
write/erase function with
XFL_NON_BLOCKING_WRITE/ERASE
option cleared */
#define XST_FLASH_CFI_QUERY_ERROR 1138L /* Failed to query the device */
/*********************** SPI statuses 1151 - 1175 ****************************/
#define XST_SPI_MODE_FAULT 1151 /* master was selected as slave */
#define XST_SPI_TRANSFER_DONE 1152 /* data transfer is complete */
#define XST_SPI_TRANSMIT_UNDERRUN 1153 /* slave underruns transmit register */
#define XST_SPI_RECEIVE_OVERRUN 1154 /* device overruns receive register */
#define XST_SPI_NO_SLAVE 1155 /* no slave has been selected yet */
#define XST_SPI_TOO_MANY_SLAVES 1156 /* more than one slave is being
* selected */
#define XST_SPI_NOT_MASTER 1157 /* operation is valid only as master */
#define XST_SPI_SLAVE_ONLY 1158 /* device is configured as slave-only
*/
#define XST_SPI_SLAVE_MODE_FAULT 1159 /* slave was selected while disabled */
#define XST_SPI_SLAVE_MODE 1160 /* device has been addressed as slave */
#define XST_SPI_RECEIVE_NOT_EMPTY 1161 /* device received data in slave mode */
#define XST_SPI_COMMAND_ERROR 1162 /* unrecognised command - qspi only */
/********************** OPB Arbiter statuses 1176 - 1200 *********************/
#define XST_OPBARB_INVALID_PRIORITY 1176 /* the priority registers have either
* one master assigned to two or more
* priorities, or one master not
* assigned to any priority
*/
#define XST_OPBARB_NOT_SUSPENDED 1177 /* an attempt was made to modify the
* priority levels without first
* suspending the use of priority
* levels
*/
#define XST_OPBARB_PARK_NOT_ENABLED 1178 /* bus parking by id was enabled but
* bus parking was not enabled
*/
#define XST_OPBARB_NOT_FIXED_PRIORITY 1179 /* the arbiter must be in fixed
* priority mode to allow the
* priorities to be changed
*/
/************************ Intc statuses 1201 - 1225 **************************/
#define XST_INTC_FAIL_SELFTEST 1201 /* self test failed */
#define XST_INTC_CONNECT_ERROR 1202 /* interrupt already in use */
/********************** TmrCtr statuses 1226 - 1250 **************************/
#define XST_TMRCTR_TIMER_FAILED 1226 /* self test failed */
/********************** WdtTb statuses 1251 - 1275 ***************************/
#define XST_WDTTB_TIMER_FAILED 1251L
/********************** PlbArb statuses 1276 - 1300 **************************/
#define XST_PLBARB_FAIL_SELFTEST 1276L
/********************** Plb2Opb statuses 1301 - 1325 *************************/
#define XST_PLB2OPB_FAIL_SELFTEST 1301L
/********************** Opb2Plb statuses 1326 - 1350 *************************/
#define XST_OPB2PLB_FAIL_SELFTEST 1326L
/********************** SysAce statuses 1351 - 1360 **************************/
#define XST_SYSACE_NO_LOCK 1351L /* No MPU lock has been granted */
/********************** PCI Bridge statuses 1361 - 1375 **********************/
#define XST_PCI_INVALID_ADDRESS 1361L
/********************** FlexRay constants 1400 - 1409 *************************/
#define XST_FR_TX_ERROR 1400
#define XST_FR_TX_BUSY 1401
#define XST_FR_BUF_LOCKED 1402
#define XST_FR_NO_BUF 1403
/****************** USB constants 1410 - 1420 *******************************/
#define XST_USB_ALREADY_CONFIGURED 1410
#define XST_USB_BUF_ALIGN_ERROR 1411
#define XST_USB_NO_DESC_AVAILABLE 1412
#define XST_USB_BUF_TOO_BIG 1413
#define XST_USB_NO_BUF 1414
/****************** HWICAP constants 1421 - 1429 *****************************/
#define XST_HWICAP_WRITE_DONE 1421
/****************** AXI VDMA constants 1430 - 1440 *****************************/
#define XST_VDMA_MISMATCH_ERROR 1430
/*********************** NAND Flash statuses 1441 - 1459 *********************/
#define XST_NAND_BUSY 1441L /* Flash is erasing or
* programming
*/
#define XST_NAND_READY 1442L /* Flash is ready for commands
*/
#define XST_NAND_ERROR 1443L /* Flash had detected an
* internal error.
*/
#define XST_NAND_PART_NOT_SUPPORTED 1444L /* Flash type not supported by
* driver
*/
#define XST_NAND_OPT_NOT_SUPPORTED 1445L /* Operation not supported
*/
#define XST_NAND_TIMEOUT_ERROR 1446L /* Programming or erase
* operation aborted due to a
* timeout
*/
#define XST_NAND_ADDRESS_ERROR 1447L /* Accessed flash outside its
* addressible range
*/
#define XST_NAND_ALIGNMENT_ERROR 1448L /* Write alignment error
*/
#define XST_NAND_PARAM_PAGE_ERROR 1449L /* Failed to read parameter
* page of the device
*/
#define XST_NAND_CACHE_ERROR 1450L /* Flash page buffer error
*/
#define XST_NAND_WRITE_PROTECTED 1451L /* Flash is write protected
*/
/**************************** Type Definitions *******************************/
typedef int XStatus;
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */

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/* $Id: xutil.h,v 1.8 2007/05/04 21:55:59 wre Exp $ */
/******************************************************************************
*
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
* AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
* SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE,
* OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
* APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
* THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE.
*
* (c) Copyright 2002 Xilinx Inc.
* All rights reserved.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xutil.h
*
* This file contains utility functions such as memory test functions.
*
* <b>Memory test description</b>
*
* A subset of the memory tests can be selected or all of the tests can be run
* in order. If there is an error detected by a subtest, the test stops and the
* failure code is returned. Further tests are not run even if all of the tests
* are selected.
*
* Subtest descriptions:
* <pre>
* XUT_ALLMEMTESTS:
* Runs all of the following tests
*
* XUT_INCREMENT:
* Incrementing Value Test.
* This test starts at 'XUT_MEMTEST_INIT_VALUE' and uses the incrementing
* value as the test value for memory.
*
* XUT_WALKONES:
* Walking Ones Test.
* This test uses a walking '1' as the test value for memory.
* location 1 = 0x00000001
* location 2 = 0x00000002
* ...
*
* XUT_WALKZEROS:
* Walking Zero's Test.
* This test uses the inverse value of the walking ones test
* as the test value for memory.
* location 1 = 0xFFFFFFFE
* location 2 = 0xFFFFFFFD
* ...
*
* XUT_INVERSEADDR:
* Inverse Address Test.
* This test uses the inverse of the address of the location under test
* as the test value for memory.
*
* XUT_FIXEDPATTERN:
* Fixed Pattern Test.
* This test uses the provided patters as the test value for memory.
* If zero is provided as the pattern the test uses '0xDEADBEEF".
* </pre>
*
* <i>WARNING</i>
*
* The tests are <b>DESTRUCTIVE</b>. Run before any initialized memory spaces
* have been set up.
*
* The address, Addr, provided to the memory tests is not checked for
* validity except for the NULL case. It is possible to provide a code-space
* pointer for this test to start with and ultimately destroy executable code
* causing random failures.
*
* @note
*
* Used for spaces where the address range of the region is smaller than
* the data width. If the memory range is greater than 2 ** width,
* the patterns used in XUT_WALKONES and XUT_WALKZEROS will repeat on a
* boundry of a power of two making it more difficult to detect addressing
* errors. The XUT_INCREMENT and XUT_INVERSEADDR tests suffer the same
* problem. Ideally, if large blocks of memory are to be tested, break
* them up into smaller regions of memory to allow the test patterns used
* not to repeat over the region tested.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.00a ecm 11/01/01 First release
* 1.00a xd 11/03/04 Improved support for doxygen.
* </pre>
*
******************************************************************************/
#ifndef XUTIL_H /* prevent circular inclusions */
#define XUTIL_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xbasic_types.h"
#include "xstatus.h"
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/* xutil_memtest defines */
#define XUT_MEMTEST_INIT_VALUE 1
/** @name Memory subtests
* @{
*/
/**
* See the detailed description of the subtests in the file description.
*/
#define XUT_ALLMEMTESTS 0
#define XUT_INCREMENT 1
#define XUT_WALKONES 2
#define XUT_WALKZEROS 3
#define XUT_INVERSEADDR 4
#define XUT_FIXEDPATTERN 5
#define XUT_MAXTEST XUT_FIXEDPATTERN
/* @} */
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
/* xutil_memtest prototypes */
int XUtil_MemoryTest32(u32 *Addr, u32 Words, u32 Pattern, u8 Subtest);
int XUtil_MemoryTest16(u16 *Addr, u32 Words, u16 Pattern, u8 Subtest);
int XUtil_MemoryTest8(u8 *Addr, u32 Words, u8 Pattern, u8 Subtest);
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */

98
software/LED_Controller_bsp/microblaze_mcs/include/xversion.h Executable file
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@@ -0,0 +1,98 @@
/* $Id: xversion.h,v 1.9 2007/05/07 14:29:23 wre Exp $ */
/******************************************************************************
*
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
* AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
* SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE,
* OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
* APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
* THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE.
*
* (c) Copyright 2002 Xilinx Inc.
* All rights reserved.
*
******************************************************************************/
/*****************************************************************************/
/**
* @file xversion.h
*
* This file contains the interface for the XVersion component. This
* component represents a version ID. It is encapsulated within a component
* so that it's type and implementation can change without affecting users of
* it.
*
* The version is formatted as X.YYZ where X = 0 - 9, Y = 00 - 99, Z = a - z
* X is the major revision, YY is the minor revision, and Z is the
* compatability revision.
*
* Packed versions are also utilized for the configuration ROM such that
* memory is minimized. A packed version consumes only 16 bits and is
* formatted as follows.
*
* <pre>
* Revision Range Bit Positions
*
* Major Revision 0 - 9 Bits 15 - 12
* Minor Revision 0 - 99 Bits 11 - 5
* Compatability Revision a - z Bits 4 - 0
*
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00a xd 11/03/04 Improved support for doxygen.
* </pre>
*
******************************************************************************/
#ifndef XVERSION_H /* prevent circular inclusions */
#define XVERSION_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xbasic_types.h"
#include "xstatus.h"
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/* the following data type is used to hold a null terminated version string
* consisting of the following format, "X.YYX"
*/
typedef char XVersion[6];
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
void XVersion_UnPack(XVersion *InstancePtr, u16 PackedVersion);
int XVersion_Pack(XVersion *InstancePtr, u16 *PackedVersion);
int XVersion_IsEqual(XVersion *InstancePtr, XVersion *VersionPtr);
void XVersion_ToString(XVersion *InstancePtr, char *StringPtr);
int XVersion_FromString(XVersion *InstancePtr, char *StringPtr);
void XVersion_Copy(XVersion *InstancePtr, XVersion *VersionPtr);
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */